Lines Matching refs:insn
195 /* normaly, since we updated PC, we need only to add one insn */
971 static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
977 if (!(insn & (1 << 25))) {
979 val = insn & 0xfff;
980 if (!(insn & (1 << 23)))
986 rm = (insn) & 0xf;
987 shift = (insn >> 7) & 0x1f;
988 shiftop = (insn >> 5) & 3;
991 if (!(insn & (1 << 23)))
999 static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn,
1005 if (insn & (1 << 22)) {
1007 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
1008 if (!(insn & (1 << 23)))
1017 rm = (insn) & 0xf;
1019 if (!(insn & (1 << 23)))
1488 static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn)
1493 rd = (insn >> 16) & 0xf;
1496 offset = (insn & 0xff) << ((insn >> 7) & 2);
1497 if (insn & (1 << 24)) {
1499 if (insn & (1 << 23))
1504 if (insn & (1 << 21))
1506 } else if (insn & (1 << 21)) {
1508 if (insn & (1 << 23))
1514 } else if (!(insn & (1 << 23)))
1519 static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask)
1521 int rd = (insn >> 0) & 0xf;
1523 if (insn & (1 << 8))
1538 static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
1544 if ((insn & 0x0e000e00) == 0x0c000000) {
1545 if ((insn & 0x0fe00ff0) == 0x0c400000) {
1546 wrd = insn & 0xf;
1547 rdlo = (insn >> 12) & 0xf;
1548 rdhi = (insn >> 16) & 0xf;
1549 if (insn & ARM_CP_RW_BIT) { /* TMRRC */
1562 wrd = (insn >> 12) & 0xf;
1563 if (gen_iwmmxt_address(s, insn))
1565 if (insn & ARM_CP_RW_BIT) {
1566 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1573 if (insn & (1 << 8)) {
1574 if (insn & (1 << 22)) { /* WLDRD */
1581 if (insn & (1 << 22)) { /* WLDRH */
1594 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1602 if (insn & (1 << 8)) {
1603 if (insn & (1 << 22)) { /* WSTRD */
1611 if (insn & (1 << 22)) { /* WSTRH */
1624 if ((insn & 0x0f000000) != 0x0e000000)
1627 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) {
1629 wrd = (insn >> 12) & 0xf;
1630 rd0 = (insn >> 0) & 0xf;
1631 rd1 = (insn >> 16) & 0xf;
1640 if (insn & 0xf)
1642 rd = (insn >> 12) & 0xf;
1643 wrd = (insn >> 16) & 0xf;
1670 wrd = (insn >> 12) & 0xf;
1671 rd0 = (insn >> 0) & 0xf;
1672 rd1 = (insn >> 16) & 0xf;
1681 if (insn & 0xf)
1683 rd = (insn >> 12) & 0xf;
1684 wrd = (insn >> 16) & 0xf;
1689 wrd = (insn >> 12) & 0xf;
1690 rd0 = (insn >> 0) & 0xf;
1691 rd1 = (insn >> 16) & 0xf;
1701 wrd = (insn >> 12) & 0xf;
1702 rd0 = (insn >> 0) & 0xf;
1703 rd1 = (insn >> 16) & 0xf;
1712 wrd = (insn >> 12) & 0xf;
1713 rd0 = (insn >> 0) & 0xf;
1714 rd1 = (insn >> 16) & 0xf;
1716 if (insn & (1 << 21))
1724 wrd = (insn >> 12) & 0xf;
1725 rd0 = (insn >> 16) & 0xf;
1726 rd1 = (insn >> 0) & 0xf;
1728 switch ((insn >> 22) & 3) {
1746 wrd = (insn >> 12) & 0xf;
1747 rd0 = (insn >> 16) & 0xf;
1748 rd1 = (insn >> 0) & 0xf;
1750 switch ((insn >> 22) & 3) {
1768 wrd = (insn >> 12) & 0xf;
1769 rd0 = (insn >> 16) & 0xf;
1770 rd1 = (insn >> 0) & 0xf;
1772 if (insn & (1 << 22))
1776 if (!(insn & (1 << 20)))
1782 wrd = (insn >> 12) & 0xf;
1783 rd0 = (insn >> 16) & 0xf;
1784 rd1 = (insn >> 0) & 0xf;
1786 if (insn & (1 << 21)) {
1787 if (insn & (1 << 20))
1792 if (insn & (1 << 20))
1801 wrd = (insn >> 12) & 0xf;
1802 rd0 = (insn >> 16) & 0xf;
1803 rd1 = (insn >> 0) & 0xf;
1805 if (insn & (1 << 21))
1809 if (!(insn & (1 << 20))) {
1817 wrd = (insn >> 12) & 0xf;
1818 rd0 = (insn >> 16) & 0xf;
1819 rd1 = (insn >> 0) & 0xf;
1821 switch ((insn >> 22) & 3) {
1839 wrd = (insn >> 12) & 0xf;
1840 rd0 = (insn >> 16) & 0xf;
1841 rd1 = (insn >> 0) & 0xf;
1843 if (insn & (1 << 22)) {
1844 if (insn & (1 << 20))
1849 if (insn & (1 << 20))
1859 wrd = (insn >> 12) & 0xf;
1860 rd0 = (insn >> 16) & 0xf;
1861 rd1 = (insn >> 0) & 0xf;
1863 gen_op_iwmmxt_movl_T0_wCx(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3));
1871 rd = (insn >> 12) & 0xf;
1872 wrd = (insn >> 16) & 0xf;
1875 switch ((insn >> 6) & 3) {
1878 gen_op_iwmmxt_insr_M0_T0_T1((insn & 7) << 3);
1882 gen_op_iwmmxt_insr_M0_T0_T1((insn & 3) << 4);
1886 gen_op_iwmmxt_insr_M0_T0_T1((insn & 1) << 5);
1895 rd = (insn >> 12) & 0xf;
1896 wrd = (insn >> 16) & 0xf;
1900 switch ((insn >> 22) & 3) {
1902 if (insn & 8)
1903 gen_op_iwmmxt_extrsb_T0_M0((insn & 7) << 3);
1905 gen_op_iwmmxt_extru_T0_M0((insn & 7) << 3, 0xff);
1909 if (insn & 8)
1910 gen_op_iwmmxt_extrsw_T0_M0((insn & 3) << 4);
1912 gen_op_iwmmxt_extru_T0_M0((insn & 3) << 4, 0xffff);
1916 gen_op_iwmmxt_extru_T0_M0((insn & 1) << 5, ~0u);
1924 if ((insn & 0x000ff008) != 0x0003f000)
1927 switch ((insn >> 22) & 3) {
1929 gen_op_shrl_T1_im(((insn & 7) << 2) + 0);
1932 gen_op_shrl_T1_im(((insn & 3) << 3) + 4);
1935 gen_op_shrl_T1_im(((insn & 1) << 4) + 12);
1944 rd = (insn >> 12) & 0xf;
1945 wrd = (insn >> 16) & 0xf;
1947 switch ((insn >> 6) & 3) {
1964 if ((insn & 0x000ff00f) != 0x0003f000)
1967 switch ((insn >> 22) & 3) {
1990 wrd = (insn >> 12) & 0xf;
1991 rd0 = (insn >> 16) & 0xf;
1993 switch ((insn >> 22) & 3) {
2010 if ((insn & 0x000ff00f) != 0x0003f000)
2013 switch ((insn >> 22) & 3) {
2036 rd = (insn >> 12) & 0xf;
2037 rd0 = (insn >> 16) & 0xf;
2038 if ((insn & 0xf) != 0)
2041 switch ((insn >> 22) & 3) {
2058 wrd = (insn >> 12) & 0xf;
2059 rd0 = (insn >> 16) & 0xf;
2060 rd1 = (insn >> 0) & 0xf;
2062 switch ((insn >> 22) & 3) {
2064 if (insn & (1 << 21))
2070 if (insn & (1 << 21))
2076 if (insn & (1 << 21))
2090 wrd = (insn >> 12) & 0xf;
2091 rd0 = (insn >> 16) & 0xf;
2093 switch ((insn >> 22) & 3) {
2095 if (insn & (1 << 21))
2101 if (insn & (1 << 21))
2107 if (insn & (1 << 21))
2121 wrd = (insn >> 12) & 0xf;
2122 rd0 = (insn >> 16) & 0xf;
2124 switch ((insn >> 22) & 3) {
2126 if (insn & (1 << 21))
2132 if (insn & (1 << 21))
2138 if (insn & (1 << 21))
2152 wrd = (insn >> 12) & 0xf;
2153 rd0 = (insn >> 16) & 0xf;
2155 if (gen_iwmmxt_shift(insn, 0xff))
2157 switch ((insn >> 22) & 3) {
2176 wrd = (insn >> 12) & 0xf;
2177 rd0 = (insn >> 16) & 0xf;
2179 if (gen_iwmmxt_shift(insn, 0xff))
2181 switch ((insn >> 22) & 3) {
2200 wrd = (insn >> 12) & 0xf;
2201 rd0 = (insn >> 16) & 0xf;
2203 if (gen_iwmmxt_shift(insn, 0xff))
2205 switch ((insn >> 22) & 3) {
2224 wrd = (insn >> 12) & 0xf;
2225 rd0 = (insn >> 16) & 0xf;
2227 switch ((insn >> 22) & 3) {
2231 if (gen_iwmmxt_shift(insn, 0xf))
2236 if (gen_iwmmxt_shift(insn, 0x1f))
2241 if (gen_iwmmxt_shift(insn, 0x3f))
2252 wrd = (insn >> 12) & 0xf;
2253 rd0 = (insn >> 16) & 0xf;
2254 rd1 = (insn >> 0) & 0xf;
2256 switch ((insn >> 22) & 3) {
2258 if (insn & (1 << 21))
2264 if (insn & (1 << 21))
2270 if (insn & (1 << 21))
2283 wrd = (insn >> 12) & 0xf;
2284 rd0 = (insn >> 16) & 0xf;
2285 rd1 = (insn >> 0) & 0xf;
2287 switch ((insn >> 22) & 3) {
2289 if (insn & (1 << 21))
2295 if (insn & (1 << 21))
2301 if (insn & (1 << 21))
2314 wrd = (insn >> 12) & 0xf;
2315 rd0 = (insn >> 16) & 0xf;
2316 rd1 = (insn >> 0) & 0xf;
2318 gen_op_movl_T0_im((insn >> 20) & 3);
2327 wrd = (insn >> 12) & 0xf;
2328 rd0 = (insn >> 16) & 0xf;
2329 rd1 = (insn >> 0) & 0xf;
2331 switch ((insn >> 20) & 0xf) {
2370 wrd = (insn >> 12) & 0xf;
2371 rd0 = (insn >> 16) & 0xf;
2373 gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));
2383 wrd = (insn >> 12) & 0xf;
2384 rd0 = (insn >> 16) & 0xf;
2385 rd1 = (insn >> 0) & 0xf;
2387 switch ((insn >> 20) & 0xf) {
2426 wrd = (insn >> 12) & 0xf;
2427 rd0 = (insn >> 16) & 0xf;
2428 rd1 = (insn >> 0) & 0xf;
2430 if (!(insn & (1 << 20)))
2432 switch ((insn >> 22) & 3) {
2436 if (insn & (1 << 21))
2442 if (insn & (1 << 21))
2448 if (insn & (1 << 21))
2462 wrd = (insn >> 5) & 0xf;
2463 rd0 = (insn >> 12) & 0xf;
2464 rd1 = (insn >> 0) & 0xf;
2468 switch ((insn >> 16) & 0xf) {
2481 if (insn & (1 << 16))
2485 if (insn & (1 << 17))
2504 static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2508 if ((insn & 0x0ff00f10) == 0x0e200010) {
2510 rd0 = (insn >> 12) & 0xf;
2511 rd1 = insn & 0xf;
2512 acc = (insn >> 5) & 7;
2517 switch ((insn >> 16) & 0xf) {
2533 if (insn & (1 << 16))
2537 if (insn & (1 << 17))
2549 if ((insn & 0x0fe00ff8) == 0x0c400000) {
2551 rdhi = (insn >> 16) & 0xf;
2552 rdlo = (insn >> 12) & 0xf;
2553 acc = insn & 7;
2558 if (insn & ARM_CP_RW_BIT) { /* MRA */
2577 static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
2580 uint32_t rd = (insn >> 12) & 0xf;
2581 uint32_t cp = (insn >> 8) & 0xf;
2586 if (insn & ARM_CP_RW_BIT) {
2591 gen_helper_get_cp(tmp, cpu_env, tcg_const_i32(insn));
2598 gen_helper_set_cp(cpu_env, tcg_const_i32(insn), tmp);
2604 static int cp15_user_ok(uint32_t insn)
2606 int cpn = (insn >> 16) & 0xf;
2607 int cpm = insn & 0xf;
2608 int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);
2612 if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))
2626 static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
2635 if ((insn & (1 << 25)) == 0) {
2636 if (insn & (1 << 20)) {
2643 if ((insn & (1 << 4)) == 0) {
2647 if (IS_USER(s) && !cp15_user_ok(insn)) {
2650 if ((insn & 0x0fff0fff) == 0x0e070f90
2651 || (insn & 0x0fff0fff) == 0x0e070f58) {
2657 rd = (insn >> 12) & 0xf;
2658 if (insn & ARM_CP_RW_BIT) {
2660 gen_helper_get_cp15(tmp, cpu_env, tcg_const_i32(insn));
2668 gen_helper_set_cp15(cpu_env, tcg_const_i32(insn), tmp);
2674 (insn & 0x0fff0fff) != 0x0e010f10)
2681 #define VFP_SREG(insn, bigbit, smallbit) \
2682 ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
2683 #define VFP_DREG(reg, insn, bigbit, smallbit) do { \
2685 reg = (((insn) >> (bigbit)) & 0x0f) \
2686 | (((insn) >> ((smallbit) - 4)) & 0x10); \
2688 if (insn & (1 << (smallbit))) \
2690 reg = ((insn) >> (bigbit)) & 0x0f; \
2693 #define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
2694 #define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
2695 #define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
2696 #define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
2697 #define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
2698 #define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
2753 static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
2765 if ((insn & 0x0fe00fff) != 0x0ee00a10)
2767 rn = (insn >> 16) & 0xf;
2772 dp = ((insn & 0xf00) == 0xb00);
2773 switch ((insn >> 24) & 0xf) {
2775 if (insn & (1 << 4)) {
2777 rd = (insn >> 12) & 0xf;
2782 VFP_DREG_N(rn, insn);
2783 if (insn & 0xf)
2785 if (insn & 0x00c00060
2789 pass = (insn >> 21) & 1;
2790 if (insn & (1 << 22)) {
2792 offset = ((insn >> 5) & 3) * 8;
2793 } else if (insn & (1 << 5)) {
2795 offset = (insn & (1 << 6)) ? 16 : 0;
2800 if (insn & ARM_CP_RW_BIT) {
2807 if (insn & (1 << 23))
2813 if (insn & (1 << 23)) {
2834 if (insn & (1 << 23)) {
2867 if ((insn & 0x6f) != 0x00)
2869 rn = VFP_SREG_N(insn);
2870 if (insn & ARM_CP_RW_BIT) {
2872 if (insn & (1 << 21)) {
2932 if (insn & (1 << 21)) {
2968 op = ((insn >> 20) & 8) | ((insn >> 19) & 6) | ((insn >> 6) & 1);
2972 rn = ((insn >> 15) & 0x1e) | ((insn >> 7) & 1);
2975 VFP_DREG_N(rn, insn);
2980 rd = VFP_SREG_D(insn);
2982 VFP_DREG_D(rd, insn);
2987 rm = ((insn << 1) & 0x1e) | ((insn >> 5) & 1);
2989 VFP_DREG_M(rm, insn);
2992 rn = VFP_SREG_N(insn);
2995 VFP_DREG_D(rd, insn);
2997 rd = VFP_SREG_D(insn);
2999 rm = VFP_SREG_M(insn);
3124 n = (insn << 12) & 0x80000000;
3125 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3294 if (dp && (insn & 0x03e00000) == 0x00400000) {
3296 rn = (insn >> 16) & 0xf;
3297 rd = (insn >> 12) & 0xf;
3299 VFP_DREG_M(rm, insn);
3301 rm = VFP_SREG_M(insn);
3304 if (insn & ARM_CP_RW_BIT) {
3341 rn = (insn >> 16) & 0xf;
3343 VFP_DREG_D(rd, insn);
3345 rd = VFP_SREG_D(insn);
3351 if ((insn & 0x01200000) == 0x01000000) {
3353 offset = (insn & 0xff) << 2;
3354 if ((insn & (1 << 23)) == 0)
3357 if (insn & (1 << 20)) {
3367 n = (insn >> 1) & 0x7f;
3369 n = insn & 0xff;
3371 if (insn & (1 << 24)) /* pre-decrement */
3372 gen_op_addl_T1_im(-((insn & 0xff) << 2));
3379 if (insn & ARM_CP_RW_BIT) {
3390 if (insn & (1 << 21)) {
3392 if (insn & (1 << 24))
3394 else if (dp && (insn & 1))
3729 static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
3747 VFP_DREG_D(rd, insn);
3748 rn = (insn >> 16) & 0xf;
3749 rm = insn & 0xf;
3750 load = (insn & (1 << 21)) != 0;
3751 if ((insn & (1 << 23)) == 0) {
3753 op = (insn >> 8) & 0xf;
3754 size = (insn >> 6) & 3;
3831 size = (insn >> 10) & 3;
3836 size = (insn >> 6) & 3;
3837 nregs = ((insn >> 8) & 3) + 1;
3838 stride = (insn & (1 << 5)) ? 2 : 1;
3868 pass = (insn >> 7) & 1;
3871 shift = ((insn >> 5) & 3) * 8;
3875 shift = ((insn >> 6) & 1) * 16;
3876 stride = (insn & (1 << 5)) ? 2 : 1;
3880 stride = (insn & (1 << 6)) ? 2 : 1;
3885 nregs = ((insn >> 8) & 3) + 1;
4108 static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
4128 q = (insn & (1 << 6)) != 0;
4129 u = (insn >> 24) & 1;
4130 VFP_DREG_D(rd, insn);
4131 VFP_DREG_N(rn, insn);
4132 VFP_DREG_M(rm, insn);
4133 size = (insn >> 20) & 3;
4134 if ((insn & (1 << 23)) == 0) {
4136 op = ((insn >> 7) & 0x1e) | ((insn >> 4) & 1);
4502 } else if (insn & (1 << 4)) {
4503 if ((insn & 0x00380080) != 0) {
4505 op = (insn >> 8) & 0xf;
4506 if (insn & (1 << 7)) {
4511 while ((insn & (1 << (size + 19))) == 0)
4514 shift = (insn >> 16) & ((1 << (3 + size)) - 1);
4785 } else { /* (insn & 0x00380080) == 0 */
4788 op = (insn >> 8) & 0xf;
4790 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
4791 invert = (insn & (1 << 5)) != 0;
4861 } else { /* (insn & 0x00800010 == 0x00800000) */
4863 op = (insn >> 8) & 0xf;
4864 if ((insn & (1 << 6)) == 0) {
5166 imm = (insn >> 8) & 0xf;
5215 } else if ((insn & (1 << 11)) == 0) {
5217 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
5218 size = (insn >> 18) & 3;
5550 } else if ((insn & (1 << 10)) == 0) {
5552 n = ((insn >> 5) & 0x18) + 8;
5553 if (insn & (1 << 6)) {
5563 if (insn & (1 << 6)) {
5575 } else if ((insn & 0x380) == 0) {
5577 if (insn & (1 << 19)) {
5582 if (insn & (1 << 16)) {
5583 gen_neon_dup_u8(cpu_T[0], ((insn >> 17) & 3) * 8);
5584 } else if (insn & (1 << 17)) {
5585 if ((insn >> 18) & 1)
5601 static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
5603 int crn = (insn >> 16) & 0xf;
5604 int crm = insn & 0xf;
5605 int op1 = (insn >> 21) & 7;
5606 int op2 = (insn >> 5) & 7;
5607 int rt = (insn >> 12) & 0xf;
5633 static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
5635 int crn = (insn >> 16) & 0xf;
5636 int crm = insn & 0xf;
5637 int op1 = (insn >> 21) & 7;
5638 int op2 = (insn >> 5) & 7;
5639 int rt = (insn >> 12) & 0xf;
5666 static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
5670 cpnum = (insn >> 8) & 0xf;
5679 return disas_iwmmxt_insn(env, s, insn);
5681 return disas_dsp_insn(env, s, insn);
5686 return disas_vfp_insn (env, s, insn);
5692 if (insn & (1 << 20))
5693 return disas_cp14_read(env, s, insn);
5695 return disas_cp14_write(env, s, insn);
5697 return disas_cp15_insn (env, s, insn);
5701 return disas_cp_insn (env, s, insn);
5800 unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
5809 insn = ldl_code(s->pc);
5816 if (is_arm_bl_or_blx(insn)) {
5827 trace_add_insn(insn, 0);
5828 ticks = get_insn_ticks_arm(insn);
5838 cond = insn >> 28;
5846 if (((insn >> 25) & 7) == 1) {
5851 if (disas_neon_data_insn(env, s, insn))
5855 if ((insn & 0x0f100000) == 0x04000000) {
5860 if (disas_neon_ls_insn(env, s, insn))
5864 if ((insn & 0x0d70f000) == 0x0550f000)
5866 else if ((insn & 0x0ffffdff) == 0x01010000) {
5869 if (insn & (1 << 9)) {
5874 } else if ((insn & 0x0fffff00) == 0x057ff000) {
5875 switch ((insn >> 4) & 0xf) {
5889 } else if ((insn & 0x0e5fffe0) == 0x084d0500) {
5895 op1 = (insn & 0x1f);
5902 i = (insn >> 23) & 3;
5918 if (insn & (1 << 21)) {
5937 } else if ((insn & 0x0e5fffe0) == 0x081d0a00) {
5943 rn = (insn >> 16) & 0xf;
5945 i = (insn >> 23) & 3;
5959 if (insn & (1 << 21)) {
5975 } else if ((insn & 0x0e000000) == 0x0a000000) {
5984 offset = (((int32_t)insn) << 8) >> 8;
5986 val += (offset << 2) | ((insn >> 23) & 2) | 1;
5991 } else if ((insn & 0x0e000f00) == 0x0c000100) {
5995 if (!disas_iwmmxt_insn(env, s, insn))
5998 } else if ((insn & 0x0fe00000) == 0x0c400000) {
6000 } else if ((insn & 0x0f000010) == 0x0e000010) {
6002 } else if ((insn & 0x0ff10020) == 0x01000000) {
6009 if (insn & (1 << 19)) {
6010 if (insn & (1 << 8))
6012 if (insn & (1 << 7))
6014 if (insn & (1 << 6))
6016 if (insn & (1 << 18))
6019 if (insn & (1 << 17)) {
6021 val |= (insn & 0x1f);
6051 if ((insn & 0x0f900000) == 0x03000000) {
6052 if ((insn & (1 << 21)) == 0) {
6054 rd = (insn >> 12) & 0xf;
6055 val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
6056 if ((insn & (1 << 22)) == 0) {
6068 if (((insn >> 12) & 0xf) != 0xf)
6070 if (((insn >> 16) & 0xf) == 0) {
6071 gen_nop_hint(s, insn & 0xff);
6074 val = insn & 0xff;
6075 shift = ((insn >> 8) & 0xf) * 2;
6079 i = ((insn & (1 << 22)) != 0);
6080 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
6084 } else if ((insn & 0x0f900000) == 0x01000000
6085 && (insn & 0x00000090) != 0x00000090) {
6087 op1 = (insn >> 21) & 3;
6088 sh = (insn >> 4) & 0xf;
6089 rm = insn & 0xf;
6096 if (gen_set_psr_T0(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i))
6100 rd = (insn >> 12) & 0xf;
6119 rd = (insn >> 12) & 0xf;
6149 rd = (insn >> 12) & 0xf;
6150 rn = (insn >> 16) & 0xf;
6172 rs = (insn >> 8) & 0xf;
6173 rn = (insn >> 12) & 0xf;
6174 rd = (insn >> 16) & 0xf;
6218 } else if (((insn & 0x0e000000) == 0 &&
6219 (insn & 0x00000090) != 0x90) ||
6220 ((insn & 0x0e000000) == (1 << 25))) {
6223 op1 = (insn >> 21) & 0xf;
6224 set_cc = (insn >> 20) & 1;
6228 if (insn & (1 << 25)) {
6230 val = insn & 0xff;
6231 shift = ((insn >> 8) & 0xf) * 2;
6242 rm = (insn) & 0xf;
6244 shiftop = (insn >> 5) & 3;
6245 if (!(insn & (1 << 4))) {
6246 shift = (insn >> 7) & 0x1f;
6249 rs = (insn >> 8) & 0xf;
6255 rn = (insn >> 16) & 0xf;
6260 rd = (insn >> 12) & 0xf;
6401 op1 = (insn >> 24) & 0xf;
6406 sh = (insn >> 5) & 3;
6409 rd = (insn >> 16) & 0xf;
6410 rn = (insn >> 12) & 0xf;
6411 rs = (insn >> 8) & 0xf;
6412 rm = (insn) & 0xf;
6413 op1 = (insn >> 20) & 0xf;
6421 if (insn & (1 << 22)) {
6427 } else if (insn & (1 << 21)) {
6433 if (insn & (1 << 20))
6441 if (insn & (1 << 22))
6445 if (insn & (1 << 21)) /* mult accumulate */
6447 if (!(insn & (1 << 23))) { /* double accumulate */
6452 if (insn & (1 << 20))
6458 rn = (insn >> 16) & 0xf;
6459 rd = (insn >> 12) & 0xf;
6460 if (insn & (1 << 23)) {
6462 op1 = (insn >> 21) & 0x3;
6469 if (insn & (1 << 20)) {
6494 rm = insn & 0xf;
6523 rm = (insn) & 0xf;
6530 if (insn & (1 << 22)) {
6545 rn = (insn >> 16) & 0xf;
6546 rd = (insn >> 12) & 0xf;
6548 if (insn & (1 << 24))
6549 gen_add_datah_offset(s, insn, 0, addr);
6551 if (insn & (1 << 20)) {
6596 if (!(insn & (1 << 24))) {
6597 gen_add_datah_offset(s, insn, address_offset, addr);
6599 } else if (insn & (1 << 21)) {
6617 if (insn & (1 << 4)) {
6620 rm = insn & 0xf;
6621 rn = (insn >> 16) & 0xf;
6622 rd = (insn >> 12) & 0xf;
6623 rs = (insn >> 8) & 0xf;
6624 switch ((insn >> 23) & 3) {
6626 op1 = (insn >> 20) & 7;
6629 sh = (insn >> 5) & 7;
6637 if ((insn & 0x00700020) == 0) {
6641 shift = (insn >> 7) & 0x1f;
6642 if (insn & (1 << 6)) {
6659 } else if ((insn & 0x00200020) == 0x00200000) {
6662 shift = (insn >> 7) & 0x1f;
6663 if (insn & (1 << 6)) {
6670 sh = (insn >> 16) & 0x1f;
6672 if (insn & (1 << 22))
6678 } else if ((insn & 0x00300fe0) == 0x00200f20) {
6681 sh = (insn >> 16) & 0x1f;
6683 if (insn & (1 << 22))
6689 } else if ((insn & 0x00700fe0) == 0x00000fa0) {
6699 } else if ((insn & 0x000003e0) == 0x00000060) {
6701 shift = (insn >> 10) & 3;
6706 op1 = (insn >> 20) & 7;
6726 } else if ((insn & 0x003f0f60) == 0x003f0f20) {
6729 if (insn & (1 << 22)) {
6730 if (insn & (1 << 7)) {
6737 if (insn & (1 << 7))
6750 if (insn & (1 << 20)) {
6753 if (insn & (1 << 5))
6760 if (insn & (1 << 6)) {
6769 if (insn & (1 << 5))
6773 if (insn & (1 << 6)) {
6779 if (insn & (1 << 22)) {
6799 op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7);
6817 shift = (insn >> 7) & 0x1f;
6818 i = (insn >> 16) & 0x1f;
6837 shift = (insn >> 7) & 0x1f;
6838 i = ((insn >> 16) & 0x1f) + 1;
6863 if (op1 == 0x7 && ((insn & sh) == sh))
6868 rn = (insn >> 16) & 0xf;
6869 rd = (insn >> 12) & 0xf;
6871 i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
6872 if (insn & (1 << 24))
6873 gen_add_data_offset(s, insn, tmp2);
6874 if (insn & (1 << 20)) {
6876 if (insn & (1 << 22)) {
6884 if (insn & (1 << 22))
6889 if (!(insn & (1 << 24))) {
6890 gen_add_data_offset(s, insn, tmp2);
6892 } else if (insn & (1 << 21)) {
6897 if (insn & (1 << 20)) {
6913 if (insn & (1 << 22)) {
6917 if ((insn & (1 << 15)) == 0)
6920 rn = (insn >> 16) & 0xf;
6928 if (insn & (1 << i))
6932 if (insn & (1 << 23)) {
6933 if (insn & (1 << 24)) {
6940 if (insn & (1 << 24)) {
6951 if (insn & (1 << i)) {
6952 if (insn & (1 << 20)) {
6987 if (insn & (1 << 21)) {
6989 if (insn & (1 << 23)) {
6990 if (insn & (1 << 24)) {
6997 if (insn & (1 << 24)) {
7013 if ((insn & (1 << 22)) && !user) {
7028 if (insn & (1 << 24)) {
7033 offset = (((int32_t)insn << 8) >> 8);
7042 if (disas_coproc_insn(env, s, insn))
7147 uint32_t insn, imm, shift, offset;
7163 insn = insn_hw1;
7164 if ((insn & (1 << 12)) == 0) {
7166 offset = ((insn & 0x7ff) << 1);
7177 if (insn & (1 << 11)) {
7179 offset = ((insn & 0x7ff) << 1) | 1;
7193 offset = ((int32_t)insn << 21) >> 9;
7201 insn = lduw_code(s->pc);
7204 int ticks = get_insn_ticks_thumb(insn);
7205 trace_add_insn( insn_wrap_thumb(insn), 1 );
7211 insn |= (uint32_t)insn_hw1 << 16;
7215 if ((insn & 0xf800e800) != 0xf000e800) {
7219 rn = (insn >> 16) & 0xf;
7220 rs = (insn >> 12) & 0xf;
7221 rd = (insn >> 8) & 0xf;
7222 rm = insn & 0xf;
7223 switch ((insn >> 25) & 0xf) {
7228 if (insn & (1 << 22)) {
7230 if (insn & 0x01200000) {
7238 offset = (insn & 0xff) * 4;
7239 if ((insn & (1 << 23)) == 0)
7241 if (insn & (1 << 24)) {
7245 if (insn & (1 << 20)) {
7260 if (insn & (1 << 21)) {
7269 } else if ((insn & (1 << 23)) == 0) {
7273 if (insn & (1 << 20)) {
7287 } else if ((insn & (1 << 6)) == 0) {
7297 if (insn & (1 << 4)) {
7315 op = (insn >> 4) & 0x3;
7320 if (insn & (1 << 20)) {
7367 if (((insn >> 23) & 1) == ((insn >> 24) & 1)) {
7371 if (insn & (1 << 20)) {
7374 if ((insn & (1 << 24)) == 0)
7380 if (insn & (1 << 21)) {
7382 if (insn & (1 << 24)) {
7394 op = (insn & 0x1f);
7401 if ((insn & (1 << 24)) == 0) {
7410 if (insn & (1 << 21)) {
7411 if ((insn & (1 << 24)) == 0) {
7432 if (insn & (1 << i))
7435 if (insn & (1 << 24)) {
7440 if ((insn & (1 << i)) == 0)
7442 if (insn & (1 << 20)) {
7457 if (insn & (1 << 21)) {
7459 if (insn & (1 << 24)) {
7463 if (insn & (1 << rn))
7478 op = (insn >> 21) & 0xf;
7479 shiftop = (insn >> 4) & 3;
7480 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7481 conds = (insn & (1 << 20)) != 0;
7490 op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
7491 if (op < 4 && (insn & 0xf000) != 0xf000)
7497 if ((insn & 0x70) != 0)
7499 op = (insn >> 21) & 3;
7500 logic_cc = (insn & (1 << 20)) != 0;
7508 shift = (insn >> 4) & 3;
7513 op = (insn >> 20) & 7;
7535 op = (insn >> 20) & 7;
7536 shift = (insn >> 4) & 7;
7546 op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
7591 op = (insn >> 4) & 0xf;
7594 switch ((insn >> 20) & 7) {
7622 if (insn & (1 << 22)) {
7653 if (insn & (1 << 5)) {
7662 if (insn & (1 << 21)) {
7683 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
7745 if (((insn >> 24) & 3) == 3) {
7747 insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4);
7748 if (disas_neon_data_insn(env, s, insn))
7751 if (insn & (1 << 28))
7753 if (disas_coproc_insn (env, s, insn))
7758 if (insn & (1 << 15)) {
7760 if (insn & 0x5000) {
7763 offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff;
7765 offset |= (insn & 0x7ff) << 1;
7769 offset ^= ((~insn) & (1 << 13)) << 10;
7770 offset ^= ((~insn) & (1 << 11)) << 11;
7772 if (insn & (1 << 14)) {
7779 if (insn & (1 << 12)) {
7787 } else if (((insn >> 23) & 7) == 7) {
7789 if (insn & (1 << 13))
7792 if (insn & (1 << 26)) {
7796 op = (insn >> 20) & 7;
7801 addr = tcg_const_i32(insn & 0xff);
7812 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
7817 if (((insn >> 8) & 7) == 0) {
7818 gen_nop_hint(s, insn & 0xff);
7825 if (insn & (1 << 10)) {
7826 if (insn & (1 << 7))
7828 if (insn & (1 << 6))
7830 if (insn & (1 << 5))
7832 if (insn & (1 << 9))
7835 if (insn & (1 << 8)) {
7837 imm |= (insn & 0x1f);
7845 op = (insn >> 4) & 0xf;
7871 addr = tcg_const_i32(insn & 0xff);
7889 op = (insn >> 22) & 0xf;
7895 /* offset[11:1] = insn[10:0] */
7896 offset = (insn & 0x7ff) << 1;
7897 /* offset[17:12] = insn[21:16]. */
7898 offset |= (insn & 0x003f0000) >> 4;
7899 /* offset[31:20] = insn[26]. */
7900 offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11;
7901 /* offset[18] = insn[13]. */
7902 offset |= (insn & (1 << 13)) << 5;
7903 /* offset[19] = insn[11]. */
7904 offset |= (insn & (1 << 11)) << 8;
7911 if (insn & (1 << 25)) {
7912 if (insn & (1 << 24)) {
7913 if (insn & (1 << 20))
7916 op = (insn >> 21) & 7;
7917 imm = insn & 0x1f;
7918 shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
7977 imm = ((insn & 0x04000000) >> 15)
7978 | ((insn & 0x7000) >> 4) | (insn & 0xff);
7979 if (insn & (1 << 22)) {
7981 imm |= (insn >> 4) & 0xf000;
7982 if (insn & (1 << 23)) {
7996 if (insn & (1 << 23))
8004 if (insn & (1 << 23))
8015 shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12);
8016 imm = (insn & 0xff);
8040 rn = (insn >> 16) & 0xf;
8045 op = (insn >> 21) & 0xf;
8046 if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
8049 rd = (insn >> 8) & 0xf;
8061 if ((insn & 0x01100000) == 0x01000000) {
8062 if (disas_neon_ls_insn(env, s, insn))
8072 if (insn & (1 << 23))
8073 imm += insn & 0xfff;
8075 imm -= insn & 0xfff;
8079 if (insn & (1 << 23)) {
8081 imm = insn & 0xfff;
8084 op = (insn >> 8) & 7;
8085 imm = insn & 0xff;
8088 shift = (insn >> 4) & 0xf;
8123 op = ((insn >> 21) & 3) | ((insn >> 22) & 4);
8124 if (insn & (1 << 20)) {
8176 uint32_t val, insn, op, rm, rn, rd, shift, cond;
8190 insn = lduw_code(s->pc);
8198 if (is_thumb_bl_or_blx(insn, s->pc, &ret_off)) {
8209 int ticks = get_insn_ticks_thumb(insn);
8210 trace_add_insn( insn_wrap_thumb(insn), 1 );
8217 switch (insn >> 12) {
8219 rd = insn & 7;
8220 op = (insn >> 11) & 3;
8223 rn = (insn >> 3) & 7;
8225 if (insn & (1 << 10)) {
8227 gen_op_movl_T1_im((insn >> 6) & 7);
8230 rm = (insn >> 6) & 7;
8233 if (insn & (1 << 9)) {
8247 rm = (insn >> 3) & 7;
8248 shift = (insn >> 6) & 0x1f;
8258 op = (insn >> 11) & 3;
8259 rd = (insn >> 8) & 0x7;
8261 gen_op_movl_T0_im(insn & 0xff);
8264 gen_op_movl_T1_im(insn & 0xff);
8291 if (insn & (1 << 11)) {
8292 rd = (insn >> 8) & 7;
8294 val = s->pc + 2 + ((insn & 0xff) * 4);
8303 if (insn & (1 << 10)) {
8305 rd = (insn & 7) | ((insn >> 4) & 8);
8306 rm = (insn >> 3) & 0xf;
8307 op = (insn >> 8) & 3;
8326 if (insn & (1 << 7)) {
8339 rd = insn & 7;
8340 rm = (insn >> 3) & 7;
8341 op = (insn >> 6) & 0xf;
8465 rd = insn & 7;
8466 rn = (insn >> 3) & 7;
8467 rm = (insn >> 6) & 7;
8468 op = (insn >> 9) & 7;
8510 rd = insn & 7;
8511 rn = (insn >> 3) & 7;
8513 val = (insn >> 4) & 0x7c;
8516 if (insn & (1 << 11)) {
8530 rd = insn & 7;
8531 rn = (insn >> 3) & 7;
8533 val = (insn >> 6) & 0x1f;
8536 if (insn & (1 << 11)) {
8550 rd = insn & 7;
8551 rn = (insn >> 3) & 7;
8553 val = (insn >> 5) & 0x3e;
8556 if (insn & (1 << 11)) {
8570 rd = (insn >> 8) & 7;
8572 val = (insn & 0xff) * 4;
8575 if (insn & (1 << 11)) {
8589 rd = (insn >> 8) & 7;
8590 if (insn & (1 << 11)) {
8598 val = (insn & 0xff) * 4;
8605 op = (insn >> 8) & 0xf;
8610 val = (insn & 0x7f) * 4;
8611 if (insn & (1 << 7))
8619 rd = insn & 7;
8620 rm = (insn >> 3) & 7;
8622 switch ((insn >> 6) & 3) {
8633 if (insn & (1 << 8))
8638 if (insn & (1 << i))
8641 if ((insn & (1 << 11)) == 0) {
8645 if (insn & (1 << i)) {
8646 if (insn & (1 << 11)) {
8660 if (insn & (1 << 8)) {
8661 if (insn & (1 << 11)) {
8673 if ((insn & (1 << 11)) == 0) {
8679 if ((insn & 0x0900) == 0x0900)
8684 rm = insn & 7;
8688 if (insn & (1 << 11))
8693 offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
8700 if ((insn & 0xf) == 0) {
8701 gen_nop_hint(s, (insn >> 4) & 0xf);
8705 s->condexec_cond = (insn >> 4) & 0xe;
8706 s->condexec_mask = insn & 0x1f;
8707 /* No actual code generated for this insn, just setup state. */
8719 rn = (insn >> 3) & 0x7;
8720 rd = insn & 0x7;
8722 switch ((insn >> 6) & 3) {
8736 tmp = tcg_const_i32((insn & (1 << 4)) != 0);
8738 if (insn & 1) {
8743 if (insn & 2) {
8749 if (insn & (1 << 4))
8754 val = ((insn & 7) << 6) & shift;
8767 rn = (insn >> 8) & 0x7;
8770 if (insn & (1 << i)) {
8771 if (insn & (1 << 11)) {
8785 if ((insn & (1 << rn)) == 0) {
8794 cond = (insn >> 8) & 0xf;
8813 offset = ((int32_t)insn << 24) >> 24;
8819 if (insn & (1 << 11)) {
8820 if (disas_thumb2_insn(env, s, insn))
8826 offset = ((int32_t)insn << 21) >> 21;
8832 if (disas_thumb2_insn(env, s, insn))
9048 /* FIXME: Single stepping a WFI insn will not halt