Cross Reference: /external/v8/src/arm/assembler-arm.cc

Lines Matching refs:src1
888 void Assembler::ubfx(Register dst, Register src1, const Operand& src2,
894        dst.code()*B12 | src2.imm32_*B7 | 0x5*B4 | src1.code());
898 void Assembler::and_(Register dst, Register src1, const Operand& src2,
900   addrmod1(cond | 0*B21 | s, src1, dst, src2);
904 void Assembler::eor(Register dst, Register src1, const Operand& src2,
906   addrmod1(cond | 1*B21 | s, src1, dst, src2);
910 void Assembler::sub(Register dst, Register src1, const Operand& src2,
912   addrmod1(cond | 2*B21 | s, src1, dst, src2);
916 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
918   addrmod1(cond | 3*B21 | s, src1, dst, src2);
922 void Assembler::add(Register dst, Register src1, const Operand& src2,
924   addrmod1(cond | 4*B21 | s, src1, dst, src2);
945 void Assembler::adc(Register dst, Register src1, const Operand& src2,
947   addrmod1(cond | 5*B21 | s, src1, dst, src2);
951 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
953   addrmod1(cond | 6*B21 | s, src1, dst, src2);
957 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
959   addrmod1(cond | 7*B21 | s, src1, dst, src2);
963 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
964   addrmod1(cond | 8*B21 | S, src1, r0, src2);
968 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
969   addrmod1(cond | 9*B21 | S, src1, r0, src2);
973 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
974   addrmod1(cond | 10*B21 | S, src1, r0, src2);
978 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
979   addrmod1(cond | 11*B21 | S, src1, r0, src2);
983 void Assembler::orr(Register dst, Register src1, const Operand& src2,
985   addrmod1(cond | 12*B21 | s, src1, dst, src2);
997 void Assembler::bic(Register dst, Register src1, const Operand& src2,
999   addrmod1(cond | 14*B21 | s, src1, dst, src2);
1009 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1011   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1013        src2.code()*B8 | B7 | B4 | src1.code());
1017 void Assembler::mul(Register dst, Register src1, Register src2,
1019   ASSERT(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1021   emit(cond | s | dst.code()*B16 | src2.code()*B8 | B7 | B4 | src1.code());
1027                       Register src1,
1031   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1034        src2.code()*B8 | B7 | B4 | src1.code());
1040                       Register src1,
1044   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1047        src2.code()*B8 | B7 | B4 | src1.code());
1053                       Register src1,
1057   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1060        src2.code()*B8 | B7 | B4 | src1.code());
1066                       Register src1,
1070   ASSERT(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1073        src2.code()*B8 | B7 | B4 | src1.code());
1453                      const Register src1,
1461   ASSERT(!src1.is(pc) && !src2.is(pc));
1463        src1.code()*B12 | 0xB*B8 | B4 | dst.code());
1539                      const DwVfpRegister src1,
1548   emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1554                      const DwVfpRegister src1,
1563   emit(cond | 0xE*B24 | 0x3*B20 | src1.code()*B16 |
1569                      const DwVfpRegister src1,
1578   emit(cond | 0xE*B24 | 0x2*B20 | src1.code()*B16 |
1584                      const DwVfpRegister src1,
1593   emit(cond | 0xE*B24 | B23 | src1.code()*B16 |
1598 void Assembler::vcmp(const DwVfpRegister src1,
1608        src1.code()*B12 | 0x5*B9 | B8 | B6 | src2.code());