Searched defs:rINST (Results 1 - 15 of 15) sorted by relevance

/dalvik/vm/compiler/template/armv5te/
H A Dheader.S65 r7 rINST first 16-bit code unit of current instruction
77 #define rINST r7 define
/dalvik/vm/mterp/x86-atom/
H A Dheader.S46 * %ebx rINST first 16-bit code unit of current instruction
62 #define rINST %ebx define
144 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
148 movzwl (rPC), rINST
162 movzwl (rPC), rINST
173 movzwl (rPC), rINST
271 movzbl 1(rPC), rINST
286 movzbl (\_count*2 + 1)(rPC), rINST
292 movzbl 1(rPC), rINST
310 movzbl 1(rPC), rINST
[all...]
/dalvik/vm/mterp/armv5te/
H A Dheader.S59 r7 rINST first 16-bit code unit of current instruction
71 #define rINST r7 define
103 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
105 #define FETCH_INST() ldrh rINST, [rPC]
119 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
123 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
133 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
138 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
159 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
/dalvik/vm/compiler/template/out/
H A DCompilerTemplateAsm-armv5te-vfp.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv5te.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv7-a-neon.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
H A DCompilerTemplateAsm-armv7-a.S72 r7 rINST first 16-bit code unit of current instruction
84 #define rINST r7 define
/dalvik/vm/mterp/out/
H A DInterpAsm-x86-atom.S53 * %ebx rINST first 16-bit code unit of current instruction
69 #define rINST %ebx define
151 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
155 movzwl (rPC), rINST
169 movzwl (rPC), rINST
180 movzwl (rPC), rINST
278 movzbl 1(rPC), rINST
293 movzbl (\_count*2 + 1)(rPC), rINST
299 movzbl 1(rPC), rINST
317 movzbl 1(rPC), rINST
[all...]
H A DInterpAsm-x86.S65 rINST bx first 16-bit code of current instruction
71 o rPC, rFP, rIBASE, rINST/rOPCODE valid on handler entry and exit
72 o eax and ecx are scratch, rINST/ebx sometimes scratch
82 #define rINST %bx define
152 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
157 * Fetch the nth instruction word from rPC into rINST. Does not advance
169 * Extract the opcode of the instruction in rINST
184 * Note: assumes opcode previously fetched and in rINST, and
254 movw 2(rPC),rINST # rINST <
[all...]
H A DInterpAsm-armv4t.S66 r7 rINST first 16-bit code unit of current instruction
78 #define rINST r7 define
110 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
112 #define FETCH_INST() ldrh rINST, [rPC]
126 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
145 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
166 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv5te-vfp.S66 r7 rINST first 16-bit code unit of current instruction
78 #define rINST r7 define
110 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
112 #define FETCH_INST() ldrh rINST, [rPC]
126 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
145 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
166 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv5te.S66 r7 rINST first 16-bit code unit of current instruction
78 #define rINST r7 define
110 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
112 #define FETCH_INST() ldrh rINST, [rPC]
126 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
145 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
166 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv7-a-neon.S66 r7 rINST first 16-bit code unit of current instruction
78 #define rINST r7 define
110 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
112 #define FETCH_INST() ldrh rINST, [rPC]
126 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
145 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
166 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
H A DInterpAsm-armv7-a.S66 r7 rINST first 16-bit code unit of current instruction
78 #define rINST r7 define
110 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
112 #define FETCH_INST() ldrh rINST, [rPC]
126 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]!
130 * src and dest registers are parameterized (not hard-wired to rPC and rINST).
140 * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the
145 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]!
166 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
329 FETCH_INST() @ load rINST fro
[all...]
/dalvik/vm/mterp/x86/
H A Dheader.S58 rINST bx first 16-bit code of current instruction
64 o rPC, rFP, rIBASE, rINST/rOPCODE valid on handler entry and exit
65 o eax and ecx are scratch, rINST/ebx sometimes scratch
75 #define rINST %bx define
145 * Fetch the next instruction from rPC into rINST. Does not advance rPC.
150 * Fetch the nth instruction word from rPC into rINST. Does not advance
162 * Extract the opcode of the instruction in rINST
177 * Note: assumes opcode previously fetched and in rINST, and

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