| /dalvik/vm/compiler/codegen/arm/ |
| H A D | CodegenFactory.c | 37 int displacement, int rSrc)
39 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
36 storeWordDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc) argument
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| H A D | CodegenDriver.c | 4035 ArmLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
4037 return genRegCopyNoInsert(cUnit, rDest, rSrc);
4041 ArmLIR* dvmCompilerRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
4043 return genRegCopy(cUnit, rDest, rSrc);
4054 int displacement, int rSrc, OpSize size)
4056 storeBaseDisp(cUnit, rBase, displacement, rSrc, size);
4053 dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| H A D | Factory.c | 34 int displacement, int rSrc);
493 int rIndex, int rSrc, int scale, OpSize size)
519 res = newLIR3(cUnit, opCode, rSrc, rBase, rNewIndex);
695 int displacement, int rSrc, int rSrcHi,
756 store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
764 store = newLIR3(cUnit, kThumbStrRRI5, rSrc, rScratch, 0);
768 store = newLIR3(cUnit, opCode, rSrc, rBase, rScratch);
790 int displacement, int rSrc, OpSize size)
792 return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
821 static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
492 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
694 storeBaseDispBody(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, int rSrcHi, OpSize size) argument
789 storeBaseDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
845 genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| H A D | Factory.c | 744 int rIndex, int rSrc, int scale, OpSize size)
746 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
752 if (FPREG(rSrc)) {
753 assert(SINGLEREG(rSrc));
771 store = newLIR3(cUnit, opCode, rSrc, regPtr, 0);
792 store = newLIR3(cUnit, opCode, rSrc, rBase, rIndex);
794 store = newLIR4(cUnit, opCode, rSrc, rBase, rIndex, scale);
944 int displacement, int rSrc, int rSrcHi,
952 bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
958 if (!FPREG(rSrc)) {
743 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
943 storeBaseDispBody(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, int rSrcHi, OpSize size) argument
1040 storeBaseDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
1137 fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
1163 genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
1189 genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
[all...] |