/dalvik/vm/compiler/template/armv5te/ |
H A D | TEMPLATE_SHL_LONG.S | 9 mov r1, r1, asl r2 @ r1<- r1 << r2 11 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 13 movpl r1, r0, asl ip @ if r2 >= 32, r1< [all...] |
H A D | TEMPLATE_SHR_LONG.S | 11 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 13 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 14 mov r1, r1, asr r2 @ r1<- r1 >> r2
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H A D | TEMPLATE_USHR_LONG.S | 11 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 13 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 14 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
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H A D | TEMPLATE_INTERPRET.S | 9 * r1 - the Dalvik PC to begin interpretation. 16 ldrne r1,[lr, #-1] 18 mov r0, r1 @ set Dalvik PC
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/dalvik/vm/mterp/armv5te/ |
H A D | OP_CONST_4.S | 3 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 6 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 9 SET_VREG(r1, r0) @ fp[A]<- r1
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H A D | OP_CONST_WIDE_HIGH16.S | 3 FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 6 mov r1, r1, lsl #16 @ r1<- BBBB0000 10 stmia r3, {r0-r1} @ vAA<- r0/r1
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H A D | OP_RETURN_WIDE.S | 10 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 11 stmia r3, {r0-r1} @ retval<- r0/r1
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H A D | OP_FILL_ARRAY_DATA.S | 4 FETCH(r1, 2) @ r1<- BBBB (hi) 6 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 8 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
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H A D | OP_SHL_LONG.S | 15 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 19 mov r1, r1, asl r2 @ r1<- r1 << r2 21 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r [all...] |
H A D | OP_SHL_LONG_2ADDR.S | 13 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 15 mov r1, r1, asl r2 @ r1<- r1 << r2 17 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r [all...] |
H A D | OP_CONST_WIDE.S | 4 FETCH(r1, 2) @ r1<- BBBB (low middle) 6 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 9 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 13 stmia r9, {r0-r1} @ vAA<- r0/r1
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H A D | OP_MUL_LONG_2ADDR.S | 12 mov r1, rINST, lsr #12 @ r1<- B 14 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 16 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 17 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 18 mul ip, r2, r1 @ ip<- ZxW
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H A D | OP_MOVE_16.S | 4 FETCH(r1, 2) @ r1<- BBBB 7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
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H A D | OP_MOVE_FROM16.S | 4 FETCH(r1, 1) @ r1<- BBBB 7 GET_VREG(r2, r1) @ r2<- fp[BBBB]
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H A D | OP_NEW_INSTANCE.S | 14 FETCH(r1, 1) @ r1<- BBBB 16 ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 21 ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 22 cmp r1, #CLASS_INITIALIZED @ has class been initialized? 25 mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 56 * r1 holds BBBB
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H A D | OP_SHR_LONG.S | 15 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 21 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 23 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 29 mov r1, r1, asr r2 @ r1<- r1 >> r [all...] |
H A D | OP_SHR_LONG_2ADDR.S | 13 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 17 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 20 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 21 mov r1, r1, asr r2 @ r1<- r1 >> r [all...] |
H A D | OP_USHR_LONG.S | 15 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 21 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 23 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 29 mov r1, r1, lsr r2 @ r1<- r1 >>> r [all...] |
H A D | OP_USHR_LONG_2ADDR.S | 13 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 17 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 20 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 21 mov r1, r1, lsr r2 @ r1<- r1 >>> r [all...] |
/dalvik/vm/mterp/armv6t2/ |
H A D | OP_CONST_4.S | 3 mov r1, rINST, lsl #16 @ r1<- Bxxx0000 6 mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 8 SET_VREG(r1, r0) @ fp[A]<- r1
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H A D | OP_IGET_QUICK.S | 6 FETCH(r1, 1) @ r1<- field byte offset 11 ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits)
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H A D | OP_IGET_WIDE_QUICK.S | 5 FETCH(r1, 1) @ r1<- field byte offset 10 ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 14 stmia r3, {r0-r1} @ fp[A]<- r0/r1
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H A D | OP_SHL_LONG_2ADDR.S | 12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 14 mov r1, r1, asl r2 @ r1<- r1 << r2 16 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r [all...] |
H A D | OP_MUL_LONG_2ADDR.S | 11 mov r1, rINST, lsr #12 @ r1<- B 13 add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 15 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 16 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 17 mul ip, r2, r1 @ ip<- ZxW
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H A D | OP_SHR_LONG_2ADDR.S | 12 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 16 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 19 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 20 mov r1, r1, asr r2 @ r1<- r1 >> r [all...] |