/external/v8/test/mjsunit/ |
H A D | uri.js | 46 var s7 = String.fromCharCode(cc7); variable 62 assertEquals('%EA%BB%AE', encodeURI(s7)); 73 assertEquals(cc7, decodeURI(encodeURI(s7)).charCodeAt(0));
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H A D | large-object-allocation.js | 232 this.s7 = i;
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/external/webkit/JavaScriptCore/tests/mozilla/ecma_3/Unicode/ |
H A D | uc-005.js | 99 var s7 = '\u02b6 in Z'; variable 108 var sEval = s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7 + s8 + s9 + s10; 155 expect = s7.charAt(0);
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/external/v8/src/mips/ |
H A D | register-allocator-mips-inl.h | 74 25, // s7 112 s7,
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H A D | simulator-mips.h | 115 s0, s1, s2, s3, s4, s5, s6, s7, enumerator in enum:assembler::mips::Simulator::Register
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H A D | simulator-mips.cc | 220 // t0-t7, s0-s7 1569 int32_t s7_val = get_register(s7); 1584 set_register(s7, callee_saved_value); 1599 CHECK_EQ(callee_saved_value, get_register(s7)); 1611 set_register(s7, s7_val);
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H A D | macro-assembler-mips.h | 44 const Register cp = s7; // JavaScript context pointer
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H A D | assembler-mips.h | 116 extern const Register s7;
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H A D | assembler-mips.cc | 71 const Register s7 = { 23 }; member in namespace:v8::internal 143 23, // s7 164 s0, s1, s2, s3, s4, s5, s6, s7,
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/external/opencore/codecs_v2/audio/sbc/enc/src/ |
H A D | sbc_encoder.cpp | 215 Word16 s7 = *data++; local 221 *ptr-- = s7;
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/external/tremolo/Tremolo/ |
H A D | mdct.c | 113 REG_TYPE s7 = x[6] - x[7]; local 116 x[1] = s7 - s1; 118 x[3] = s7 + s1;
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H A D | mdctLARM.s | 818 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 822 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 823 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 847 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 851 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 852 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 934 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 938 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 939 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 963 SUB r14,r12,r14,LSL #1 @ r14= s7 [all...] |
H A D | mdctARM.s | 825 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 829 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 830 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 854 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 858 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 859 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 940 SUB r14,r12,r14,LSL #1 @ r14= s7 = x[6] - x[7] 944 SUB r3, r14,r7 @ r3 = x[1] = s7 - s1 945 ADD r5, r3, r7, LSL #1 @ r5 = x[3] = s7 + s1 969 SUB r14,r12,r14,LSL #1 @ r14= s7 [all...] |
/external/v8/src/arm/ |
H A D | simulator-arm.h | 108 s0 = 0, s1, s2, s3, s4, s5, s6, s7, enumerator in enum:assembler::arm::Simulator::Register
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H A D | assembler-arm.h | 151 extern SwVfpRegister s7;
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H A D | assembler-thumb2.h | 151 extern SwVfpRegister s7;
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H A D | assembler-arm.cc | 154 SwVfpRegister s7 = { 7 }; member in namespace:v8::internal
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H A D | assembler-thumb2.cc | 134 SwVfpRegister s7 = { 7 }; member in namespace:v8::internal
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/external/webkit/JavaScriptCore/assembler/ |
H A D | ARMv7Assembler.h | 71 s7 = 7, enumerator in enum:JSC::ARMRegisters::__anon5487
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/external/opencore/protocols/rtp_payload_parser/util/output/ |
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