Searched defs:op2 (Results 1 - 18 of 18) sorted by relevance

/external/webkit/JavaScriptCore/assembler/
H A DMacroAssemblerARM.cpp69 ARMWord op2; local
72 op2 = m_assembler.lsl(address.index, static_cast<int>(address.scale));
75 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
79 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
84 m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, op2);
H A DARMAssembler.cpp293 ARMWord op2; local
296 op2 = lsl(index, scale);
299 add_r(ARMRegisters::S0, base, op2);
304 add_r(ARMRegisters::S0, base, op2);
310 add_r(ARMRegisters::S0, ARMRegisters::S0, op2);
H A DMacroAssembler.h103 void branch32(Condition cond, RegisterID op1, RegisterID op2, Label target) argument
105 branch32(cond, op1, op2).linkTo(target, this);
H A DARMAssembler.h230 void emitInst(ARMWord op, int rd, int rn, ARMWord op2) argument
232 ASSERT ( ((op2 & ~OP2_IMM) <= 0xfff) || (((op2 & ~OP2_IMMh) <= 0xfff)) );
233 m_buffer.putInt(op | RN(rn) | RD(rd) | op2);
236 void and_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
238 emitInst(static_cast<ARMWord>(cc) | AND, rd, rn, op2);
241 void ands_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
243 emitInst(static_cast<ARMWord>(cc) | AND | SET_CC, rd, rn, op2); local
246 void eor_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
248 emitInst(static_cast<ARMWord>(cc) | EOR, rd, rn, op2);
251 eors_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
253 emitInst(static_cast<ARMWord>(cc) | EOR | SET_CC, rd, rn, op2); local
256 sub_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
261 subs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
263 emitInst(static_cast<ARMWord>(cc) | SUB | SET_CC, rd, rn, op2); local
266 rsb_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
271 rsbs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
273 emitInst(static_cast<ARMWord>(cc) | RSB | SET_CC, rd, rn, op2); local
276 add_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
281 adds_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
283 emitInst(static_cast<ARMWord>(cc) | ADD | SET_CC, rd, rn, op2); local
286 adc_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
291 adcs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
293 emitInst(static_cast<ARMWord>(cc) | ADC | SET_CC, rd, rn, op2); local
296 sbc_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
301 sbcs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
303 emitInst(static_cast<ARMWord>(cc) | SBC | SET_CC, rd, rn, op2); local
306 rsc_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
311 rscs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
313 emitInst(static_cast<ARMWord>(cc) | RSC | SET_CC, rd, rn, op2); local
316 tst_r(int rn, ARMWord op2, Condition cc = AL) argument
318 emitInst(static_cast<ARMWord>(cc) | TST | SET_CC, 0, rn, op2); local
321 teq_r(int rn, ARMWord op2, Condition cc = AL) argument
323 emitInst(static_cast<ARMWord>(cc) | TEQ | SET_CC, 0, rn, op2); local
326 cmp_r(int rn, ARMWord op2, Condition cc = AL) argument
328 emitInst(static_cast<ARMWord>(cc) | CMP | SET_CC, 0, rn, op2); local
331 orr_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
336 orrs_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
338 emitInst(static_cast<ARMWord>(cc) | ORR | SET_CC, rd, rn, op2); local
341 mov_r(int rd, ARMWord op2, Condition cc = AL) argument
343 emitInst(static_cast<ARMWord>(cc) | MOV, rd, ARMRegisters::r0, op2); local
347 movw_r(int rd, ARMWord op2, Condition cc = AL) argument
353 movt_r(int rd, ARMWord op2, Condition cc = AL) argument
360 movs_r(int rd, ARMWord op2, Condition cc = AL) argument
362 emitInst(static_cast<ARMWord>(cc) | MOV | SET_CC, rd, ARMRegisters::r0, op2); local
365 bic_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
370 bics_r(int rd, int rn, ARMWord op2, Condition cc = AL) argument
372 emitInst(static_cast<ARMWord>(cc) | BIC | SET_CC, rd, rn, op2); local
375 mvn_r(int rd, ARMWord op2, Condition cc = AL) argument
377 emitInst(static_cast<ARMWord>(cc) | MVN, rd, ARMRegisters::r0, op2); local
380 mvns_r(int rd, ARMWord op2, Condition cc = AL) argument
382 emitInst(static_cast<ARMWord>(cc) | MVN | SET_CC, rd, ARMRegisters::r0, op2); local
435 dtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) argument
445 dtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) argument
460 ldrh_d(int rd, int rb, ARMWord op2, Condition cc = AL) argument
462 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_PRE, rd, rb, op2); local
465 ldrh_u(int rd, int rb, ARMWord op2, Condition cc = AL) argument
467 emitInst(static_cast<ARMWord>(cc) | LDRH | HDT_UH | DT_UP | DT_PRE, rd, rb, op2); local
475 fdtr_u(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) argument
481 fdtr_d(bool isLoad, int rd, int rb, ARMWord op2, Condition cc = AL) argument
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H A DARMv7Assembler.h1792 void twoWordOp16Op16(OpcodeID1 op1, OpcodeID2 op2) argument
1795 m_buffer.putShort(op2);
/external/libvpx/vp8/common/
H A Dloopfilter_filters.c161 uc *op2, uc *op1, uc *op0, uc *oq0, uc *oq1, uc *oq2)
165 signed char ps2 = (signed char) * op2 ^ 0x80;
212 *op2 = s ^ 0x80;
160 vp8_mbfilter(signed char mask, signed char hev, uc *op2, uc *op1, uc *op0, uc *oq0, uc *oq1, uc *oq2) argument
/external/webkit/JavaScriptCore/parser/
H A DResultType.h121 static ResultType forAdd(ResultType op1, ResultType op2) argument
123 if (op1.definitelyIsNumber() && op2.definitelyIsNumber())
125 if (op1.definitelyIsString() || op2.definitelyIsString())
/external/webkit/JavaScriptCore/jit/
H A DJITArithmetic.cpp92 unsigned op2 = currentInstruction[2].u.operand; local
100 emitLoad(op2, regT3, regT2);
103 } else if (isOperandConstantImmediateInt(op2)) {
106 addJump(branch32(GreaterThanOrEqual, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
108 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
122 emitBinaryDoubleOp(op_jnless, target, op1, op2, OperandTypes(), notInt32Op1, notInt32Op2, !isOperandConstantImmediateInt(op1), isOperandConstantImmediateInt(op1) || !isOperandConstantImmediateInt(op2));
129 unsigned op2 = currentInstruction[2].u.operand; local
133 if (!isOperandConstantImmediateInt(op1) && !isOperandConstantImmediateInt(op2))
141 if (isOperandConstantImmediateInt(op1) || !isOperandConstantImmediateInt(op2))
155 unsigned op2 = currentInstruction[2].u.operand; local
192 unsigned op2 = currentInstruction[2].u.operand; local
218 unsigned op2 = currentInstruction[2].u.operand; local
255 unsigned op2 = currentInstruction[2].u.operand; local
284 unsigned op2 = currentInstruction[3].u.operand; local
306 unsigned op2 = currentInstruction[3].u.operand; local
324 unsigned op2 = currentInstruction[3].u.operand; local
346 unsigned op2 = currentInstruction[3].u.operand; local
364 unsigned op2 = currentInstruction[3].u.operand; local
387 unsigned op2 = currentInstruction[3].u.operand; local
405 unsigned op2 = currentInstruction[3].u.operand; local
428 unsigned op2 = currentInstruction[3].u.operand; local
446 unsigned op2 = currentInstruction[3].u.operand; local
469 unsigned op2 = currentInstruction[3].u.operand; local
630 unsigned op2 = currentInstruction[3].u.operand; local
702 unsigned op2 = currentInstruction[3].u.operand; local
749 unsigned op2 = currentInstruction[3].u.operand; local
811 unsigned op2 = currentInstruction[3].u.operand; local
842 emitBinaryDoubleOp(OpcodeID opcodeID, unsigned dst, unsigned op1, unsigned op2, OperandTypes types, JumpList& notInt32Op1, JumpList& notInt32Op2, bool op1IsInRegisters, bool op2IsInRegisters) argument
977 unsigned op2 = currentInstruction[3].u.operand; local
1009 unsigned op2 = currentInstruction[3].u.operand; local
1051 unsigned op2 = currentInstruction[3].u.operand; local
1095 unsigned op2 = currentInstruction[3].u.operand; local
1126 unsigned op2 = currentInstruction[3].u.operand; local
1163 unsigned op2 = currentInstruction[3].u.operand; local
1188 unsigned op2 = currentInstruction[3].u.operand; local
1213 unsigned op2 = currentInstruction[3].u.operand; local
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H A DJITInlineMethods.h567 ALWAYS_INLINE bool JIT::getOperandConstantImmediateInt(unsigned op1, unsigned op2, unsigned& op, int32_t& constant) argument
571 op = op2;
575 if (isOperandConstantImmediateInt(op2)) {
576 constant = getConstantOperand(op2).asInt32();
H A DJITOpcodes.cpp422 unsigned op2 = currentInstruction[2].u.operand; local
428 emitLoad(op2, regT1, regT0);
434 if (isOperandConstantImmediateInt(op2)) {
437 addJump(branch32(LessThanOrEqual, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
441 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
450 unsigned op2 = currentInstruction[2].u.operand; local
453 if (!isOperandConstantImmediateInt(op1) && !isOperandConstantImmediateInt(op2))
459 stubCall.addArgument(op2);
931 unsigned op2 = currentInstruction[3].u.operand; local
954 stubCallEq.addArgument(op2);
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/external/skia/src/animator/
H A DSkDisplayable.cpp308 SkOperand op2, SkOperand blankOp2) {
321 if (op.fScalar != blankOp.fScalar || op2.fScalar != blankOp.fScalar) {
323 SkDebugf("%s=\"[%g,%g]\" ", info->fName, SkScalarToFloat(op.fScalar), SkScalarToFloat(op2.fScalar));
325 SkDebugf("%s=\"[%x,%x]\" ", info->fName, op.fScalar, op2.fScalar);
307 dumpValues(const SkMemberInfo* info, SkDisplayTypes type, SkOperand op, SkOperand blankOp, SkOperand op2, SkOperand blankOp2) argument
/external/qemu/target-arm/
H A Dneon_helper.c731 uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2) argument
746 result ^= op2 & mask;
748 op2 = (op2 << 1) & 0xfefefefe;
H A Dhelper.c1335 int op2; local
1339 op2 = (insn >> 5) & 7;
1349 && op1 == 2 && crm == 0 && op2 == 0) {
1356 op2 = 0;
1357 switch (op2) {
1387 switch (op2) {
1398 switch (op2) {
1424 op2 = 0;
1425 switch (op2) {
1457 op2
1625 int op2; local
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H A Dtranslate.c613 switch (op2) { \
621 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b) argument
658 switch (op2) { \
666 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b) argument
5605 int op2 = (insn >> 5) & 7; local
5610 if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
5618 if (op1 == 6 && crn == 1 && crm == 0 && op2 == 0) {
5627 fprintf(stderr, "Unknown cp14 read op1:%d crn:%d crm:%d op2:%d\n",
5628 op1, crn, crm, op2);
5637 int op2 local
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/external/v8/src/ia32/
H A Dassembler-ia32.cc2318 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { argument
2319 ASSERT(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2323 EMIT(op2 | dst.code());
H A Dmacro-assembler-ia32.cc1025 Register op2,
1032 or_(scratch, Operand(op2));
1023 NegativeZeroTest(Register result, Register op1, Register op2, Register scratch, Label* then_label) argument
/external/libxml2/
H A Dxpath.c792 #define PUSH_FULL_EXPR(op, op1, op2, val, val2, val3, val4, val5) \
793 xmlXPathCompExprAdd(ctxt->comp, (op1), (op2), \
11173 int op2 = -1; local
11200 op2 = ctxt->comp->last;
11210 /* PUSH_BINARY_EXPR(XPATH_OP_RANGETO, op2, ctxt->comp->last, 0, 0); */
11291 PUSH_BINARY_EXPR(XPATH_OP_RANGETO, op2, op1, 0, 0);
/external/sqlite/dist/
H A Dsqlite3.c9153 u8 op2; /* If a TK_REGISTER, the original value of Expr.op */ member in struct:Expr
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