| /dalvik/vm/compiler/codegen/arm/ |
| H A D | CodegenFactory.c | 37 int displacement, int rSrc)
39 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
36 storeWordDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc) argument
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| H A D | CodegenDriver.c | 4454 ArmLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
4456 return genRegCopyNoInsert(cUnit, rDest, rSrc);
4460 ArmLIR* dvmCompilerRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
4462 return genRegCopy(cUnit, rDest, rSrc);
4473 int displacement, int rSrc, OpSize size)
4475 storeBaseDisp(cUnit, rBase, displacement, rSrc, size);
4472 dvmCompilerFlushRegImpl(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
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| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| H A D | Factory.c | 33 int displacement, int rSrc);
492 int rIndex, int rSrc, int scale, OpSize size)
518 res = newLIR3(cUnit, opCode, rSrc, rBase, rNewIndex);
693 int displacement, int rSrc, int rSrcHi,
753 store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp);
761 store = newLIR3(cUnit, kThumbStrRRI5, rSrc, rScratch, 0);
765 store = newLIR3(cUnit, opCode, rSrc, rBase, rScratch);
787 int displacement, int rSrc, OpSize size)
789 return storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, size);
818 static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
491 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
692 storeBaseDispBody(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, int rSrcHi, OpSize size) argument
786 storeBaseDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
842 genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| H A D | Factory.c | 741 int rIndex, int rSrc, int scale, OpSize size)
743 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
749 if (FPREG(rSrc)) {
750 assert(SINGLEREG(rSrc));
768 store = newLIR3(cUnit, opCode, rSrc, regPtr, 0);
789 store = newLIR3(cUnit, opCode, rSrc, rBase, rIndex);
791 store = newLIR4(cUnit, opCode, rSrc, rBase, rIndex, scale);
940 int displacement, int rSrc, int rSrcHi,
947 bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
953 if (!FPREG(rSrc)) {
740 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
939 storeBaseDispBody(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, int rSrcHi, OpSize size) argument
1035 storeBaseDisp(CompilationUnit *cUnit, int rBase, int displacement, int rSrc, OpSize size) argument
1124 fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
1150 genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) argument
1176 genRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) argument
[all...] |