1a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 2a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * --> DO NOT EDIT <-- 5a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/header.S */ 8a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 10a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 11a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 13a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 14a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 15a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 17a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 18a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 21a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 22a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 23c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 24a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 25a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ARMv5 definitions and declarations. 26a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 27a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 28a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 29a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenARM EABI general notes: 30a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 31a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 32a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr4-r8 are available for general use 33a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr9 is given special treatment in some situations, but not for us 34a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr10 (sl) seems to be generally available 35a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 36a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr12 (ip) is scratch -- not preserved across method calls 37a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr13 (sp) should be managed carefully in case a signal arrives 38a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr14 (lr) must be preserved 39a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr15 (pc) can be tinkered with directly 40a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 41a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0 holds returns of <= 4 bytes 42a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 43a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 44a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 45a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 46a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 47a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 48a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 49a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 50a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden(i.e. the 5th arg). 51a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 52a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenVFP: single-precision results in s0, double-precision results in d0. 53a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 54a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 55a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 56a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 57a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 58a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 59a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMterp and ARM notes: 60a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 61a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenThe following registers have fixed assignments: 62a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 63a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden reg nick purpose 64a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r4 rPC interpreted program counter, used for fetching instructions 65a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 66a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r6 rGLUE MterpGlue pointer 67a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r7 rINST first 16-bit code unit of current instruction 68a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 69a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 70a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMacros are provided for common operations. Each macro MUST emit only 71a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 72a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenunspecified registers or condition codes. 73a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 74a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 75a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* single-purpose registers, given names for clarity */ 76a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rPC r4 77a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rFP r5 78a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rGLUE r6 79a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rINST r7 80a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rIBASE r8 81a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 82a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* save/restore the PC and/or FP from the glue struct */ 83a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 84a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 85a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 86a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 87a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 88a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 89a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 90a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 91a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 92a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be done *before* something calls dvmThrowException. 93a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 94a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 95a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 96a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 97a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * It's okay to do this more than once. 98a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 99a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define EXPORT_PC() \ 100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Given a frame pointer, find the stack save area. 104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_INST() ldrh rINST, [rPC] 114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from the specified offset. Advances rPC 117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Because of the limited size of immediate constants on ARM, this is only 120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with this). 122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This must come AFTER anything that can throw an exception, or the 124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception catch may miss. (This also implies that it must come after 125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * EXPORT_PC().) 126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * here. 145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch a half-word code unit from an offset past the current PC. The 150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The "_S" variant works the same but treats the value as signed. 153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * byte of the halfword you want (lo/hi). 161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the instruction's opcode field into the specified register. 166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the prefetched instruction's opcode field into the specified register. 171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Get/set the 32-bit value from a Dalvik register. 184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 190d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert a virtual register index into an address. 195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add _reg, rFP, _vreg, lsl #2 198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is a #include, not a %include, because we want the C pre-processor 201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to expand the macros into assembler assignment statements. 202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#include "../common/asm-constants.h" 204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2057b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#if defined(WITH_JIT) 2067b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#include "../common/jit-config.h" 2077b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#endif 208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 209c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv7-a/platform.S */ 210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * CPU-version-specific defines 213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * one-way branch. 219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP. Does not modify LR. 221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC source 223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Jump to subroutine. 229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC_LR source 233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov lr, pc 234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDMFD_PC regs 243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {\regs,pc} 244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 246c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden#if !defined(ANDROID_SMP) 247c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden# error "Must define ANDROID_SMP" 248c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden#endif 249c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 250c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* 251c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Macro for data memory barrier; not meaningful pre-ARMv6K. 252c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * If the argument is nonzero, emit barrier; otherwise, emit nothing. 253c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 2540890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden.macro SMP_DMB 255c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden#if ANDROID_SMP != 0 256c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden dmb 257c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden#else 258c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* not SMP */ 259c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden#endif 260c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.endm 261c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/entry.S */ 263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Interpreter entry point. 280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't have formal stack frames, so gdb scans upward in the code 284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to find the start of the function (a label with the %function type), 285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and then looks at the next few instructions to figure out what 286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * got pushed onto the stack. From this it figures out how to restore 287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the registers, including PC, for the previous stack frame. If gdb 288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sees a non-function label, it stops scanning, so either we need to 289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have nothing but assembler-local labels between the entry point and 290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the break, or we need to fake it out. 291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * When this is defined, we add some stuff to make gdb less confused. 293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define ASSIST_DEBUGGER 1 295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdRun 299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdRun, %function 300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This function returns a boolean "changeInterp" value. The return comes 306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * via a call to dvmMterpStdBail(). 307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdRun: 309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY1 \ 310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .save {r4-r10,fp,lr}; \ 311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY2 \ 313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .pad #4; \ 314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align 64 315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* save stack pointer, add magic word for debuggerd */ 321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up "named" registers, figure out entry point */ 324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rGLUE, r0 @ set rGLUE 32551ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee ldr r1, [r0, #offGlue_entryPoint] @ enum is 4 bytes in aapcs-EABI 326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryInstr @ usual case? 329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lnot_instr @ no, handle it 330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 332d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng.LentryInstr: 3337a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* Entry is always a possible trace start */ 335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 3377a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, #0 @ prepare the value for the new state 3387a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 3397a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ is profiling disabled? 3407a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if !defined(WITH_SELF_VERIFICATION) 3417a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bne common_updateProfile @ profiling is enabled 3427a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#else 3437a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r2, [r10, #offThread_shadowSpace] @ to find out the jit exit state 3447a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ profiling is disabled 3457a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r3, [r2, #offShadowSpace_jitExitState] @ jit exit state 3467a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSTraceSelect @ hot trace following? 3477a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng moveq r2,#kJitTSelectRequestHot @ ask for trace selection 3487a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq common_selectTrace @ go build the trace 3497a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r3, #kSVSNoProfile @ don't profile the next instruction? 3507a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng beq 1f @ intrepret the next instruction 3517a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b common_updateProfile @ collect profiles 3527a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 3537a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng1: 354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* start executing the instruction at rPC */ 358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_instr: 364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_returnFromMethod 366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_return: 368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown 370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_throw: 373d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10,[rGLUE, #offGlue_jitResumeNPC] 374d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumeDPC] 375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lbad_arg 377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp rPC,r2 378d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne .LentryInstr @ must have branched, don't resume 379d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#if defined(WITH_SELF_VERIFICATION) 380d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ glue->entryPoint will be set in dvmSelfVerificationSaveState 381d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunStart @ re-enter the translation after the 382d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ single-stepped instruction 383d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @noreturn 384d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#endif 385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #kInterpEntryInstr 38651ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee str r1, [rGLUE, #offGlue_entryPoint] 387d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bx r10 @ re-enter the translation 388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lbad_arg: 391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strBadEntryPoint 392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r1 holds value of entryPoint 393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAbort 395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdBail 399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdBail, %function 400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Restore the stack pointer and PC from the save point established on entry. 403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * LR to PC. 409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 bool changeInterp 413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdBail: 415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ return the changeInterp value 417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 @ un-align 64 418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references. 423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrBadEntryPoint: 425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrBadEntryPoint 426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionStart 429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmInstructionStart, %function 430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionStart = .L_OP_NOP 431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOP: /* 0x00 */ 436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NOP.S */ 437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_inst, %function 444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_inst: 445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE: /* 0x01 */ 454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE.S */ 455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_16: /* 0x03 */ 482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE_WIDE.S */ 497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide vA, vB */ 498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/from16 vAA, vBBBB */ 514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- BBBB 516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/16 vAAAA, vBBBB */ 530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- BBBB 532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- AAAA 533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-result-wide vAA */ 608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-exception vAA */ 637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ r1<- 0 641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN: /* 0x0f */ 656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 64-bit value. Copies the return value into the "glue" 675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* return-wide vAA */ 678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_4: /* 0x12 */ 706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_CONST_4.S */ 707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/4 vA, #+B */ 708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_16: /* 0x13 */ 719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_16.S */ 720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/16 vAA, #+BBBB */ 721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST: /* 0x14 */ 731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST.S */ 732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const vAA, #+BBBBbbbb */ 733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/high16 vAA, #+BBBB0000 */ 747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/16 vAA, #+BBBB */ 760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0 @ r0<- 00000000 811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING: /* 0x1a */ 821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING.S */ 822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBB */ 823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_resolve 830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBBBBBB */ 840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/class vAA, Class@BBBB */ 859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_CLASS_resolve 866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Synchronize on an object. 877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-enter vAA */ 879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null object, throw an exception 885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLockObject @ call(self, obj) 887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ exception raised, bail out 892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlock an object. 902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exceptions that occur when unlocking a monitor need to appear as 904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if they happened at the following instruction. See the Dalvik 905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction spec. 906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-exit vAA */ 908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ before fetch: export the PC 910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 9126bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq 1f @ yes 913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 9176bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq common_exceptionThrown @ yes, exception is pending 918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9206bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee1: 9216bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee FETCH_ADVANCE_INST(1) @ advance before throw 9226bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee b common_errNullObject 923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if a cast from one class to another is allowed. 930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* check-cast vAA, class@BBBB */ 932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r3) @ r9<- object 935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ is object null? 937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolved: 944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_okay: 947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if an object reference is an instance of a class. 957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Most common situation is a non-null object, being compared against 959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an already-resolved class. 960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* instance-of vA, vB, class@CCCC */ 962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- CCCC 970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ARRAY_LENGTH.S */ 984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return the length of an array. 986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yup, fail 992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ vB<- length 996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 1001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 1002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new instance of a class. 1004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-instance vAA, class@BBBB */ 1006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocObject @ r0<- new object 1020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Allocate an array of objects, specified with the array class 1028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and a count. 1029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The verifier guarantees that this is an array class, so we don't 1031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * check for it here. 1032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-array vA, vB, class@CCCC */ 1034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 1035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- CCCC 1036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ check length 1040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_errNegativeArraySize @ negative length, bail 1042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for resolve, alloc 1044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC(); 1115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ 0 means an exception is thrown 1117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ has exception 1118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW: /* 0x27 */ 1125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW.S */ 1126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception object in the current thread. 1128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* throw vAA */ 1130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 11338ba2708ea118381f2df5ca55b9bad2ae4c050504Andy McFadden EXPORT_PC() @ exception handler can throw 1134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 1135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, throw an NPE instead 1136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ bypass dvmSetException, just store it 1137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 1139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO: /* 0x28 */ 1143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO.S */ 1144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 8-bit offset. 1146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto +AA */ 1151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_16: /* 0x29 */ 1171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_16.S */ 1172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 16-bit offset. 1174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/16 +AAAA */ 1179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_32: /* 0x2a */ 1198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_32.S */ 1199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 32-bit offset. 1201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction doesn't affect the V flag, so we need to clear it 1208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * explicitly. 1209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/32 +AAAAAAAA */ 1211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, ip @ (clear V flag during stall) 1214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13285162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13315162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13335162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13425162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13675162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13705162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13725162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13815162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14065162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14095162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14115162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14205162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14455162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14485162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14505162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14595162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * register based on the results of the comparison. 1469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We load the full values with LDM, but in practice many values could 1471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be resolved by only looking at the high word. This could be made 1472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If we just wanted to set condition flags, we could do this: 1475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subs ip, r0, r2 1476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sbcs ip, r1, r3 1477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subeqs ip, r0, r2 1478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * us a constant 5-cycle path plus a branch at the end to the 1482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction epilogue code. The multi-compare approach below needs 1483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in the worst case (the 64-bit values are equal). 1485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* cmp-long vAA, vBB, vCC */ 1487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 1488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 1491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt .LOP_CMP_LONG_greater 1498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CMP_LONG_less 1501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQ: /* 0x32 */ 1506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_EQ.S */ 1507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NE: /* 0x33 */ 1541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_NE.S */ 1542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LT: /* 0x34 */ 1576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LT.S */ 1577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GE: /* 0x35 */ 1611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GE.S */ 1612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GT: /* 0x36 */ 1646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GT.S */ 1647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LE: /* 0x37 */ 1681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LE.S */ 1682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET: /* 0x44 */ 1980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 1981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 1983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 1986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 1991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 1993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 1994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 1995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 1996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 1997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 1998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aget-wide vAA, vBB, vCC */ 2017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT: /* 0x4b */ 2197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aput-wide vAA, vBB, vCC */ 2234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2267d82097f6b409c5cd48568e54eb701604c3cceb18buzbee GET_VREG(rINST, r2) @ rINST<- vBB (array object) 2268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2269d82097f6b409c5cd48568e54eb701604c3cceb18buzbee cmp rINST, #0 @ null array object? 2270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r9) @ r9<- vAA 2271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2272d82097f6b409c5cd48568e54eb701604c3cceb18buzbee ldr r3, [rINST, #offArrayObject_length] @ r3<- arrayObj->length 2273d82097f6b409c5cd48568e54eb701604c3cceb18buzbee add r10, rINST, r0, lsl #2 @ r10<- arrayObj + index*width 2274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r3 @ compare unsigned index, length 2275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET: /* 0x52 */ 2410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET.S */ 2411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish @ no, already resolved 2425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish 2431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE.S */ 2437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Wide 32-bit instance field get. 2439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide vA, vB, field@CCCC */ 2441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish 2455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish 2482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish 2511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish 2540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish 2569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish 2598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT: /* 0x59 */ 2604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT.S */ 2605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ no, already resolved 2619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ yes, finish up 2625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE.S */ 2631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide vA, vB, field@CCCC */ 2632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2653919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 2654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2655919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 2656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2683919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2712919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2741919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2770919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET: /* 0x60 */ 2793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_finish: @ field ptr in r0 2807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28080890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SGET handler. 2821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sget-wide vAA, field@BBBB */ 2823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_finish: 2830861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2831861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 2832861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 28336e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 2834861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 2835861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2836861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 2837861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2839861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28620890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 28890890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29160890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29430890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 29700890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 2971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT: /* 0x67 */ 2981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 2982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 2984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2985919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 2994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_finish: @ field ptr in r0 2995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 2998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 29990890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SPUT handler. 3009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sput-wide vAA, field@BBBB */ 3011861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 3012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3013861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 3014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3015861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 3016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3017861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 3018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3019861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 3020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3021861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 3022861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 3023861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 3024861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 30256e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 3026861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 3027861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 3028861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 3029861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 3030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3036919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 3037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3038919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 3039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3046919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ no, continue 3047b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3048919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 3049d82097f6b409c5cd48568e54eb701604c3cceb18buzbee ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 3050919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 3051919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 3052919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_finish @ yes, finish 3053919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 3054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3064919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 30780890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3091919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31050890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3118919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31320890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3145919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 31590890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 3160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_finish: 3252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue on 3254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ yes, continue on 3274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue 3280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3308de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodNoRange @ jump to common handler 3309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue on 3413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ yes, continue on 3435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue 3441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3471de75089fb7216d19e9c22cce4dc62a49513477d3Carl Shapiro b common_invokeMethodRange @ jump to common handler 3472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_INT: /* 0x7b */ 3493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_INT.S */ 3494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_INT: /* 0x7c */ 3519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_INT.S */ 3520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_LONG.S */ 3546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_LONG.S */ 3573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ optional op; may set condition codes 3589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_FLOAT.S */ 3600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_DOUBLE.S */ 3626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_LONG.S */ 3653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitos s1, s0 @ s1<- op 3694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitod d0, s0 @ d0<- op 3719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 3731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 3732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 3733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 3738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 3741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopNarrower.S */ 3748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 32-bit quantity in r0. 3752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: long-to-float, double-to-int, double-to-float 3754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (This would work for long-to-int, but that instruction is actually 3756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an exact match for OP_MOVE.) 3757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 3768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizs s1, s0 @ s1<- op 3818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtds d0, s0 @ d0<- op 3871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizd s0, d0 @ s0<- op 3896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtsd s0, d0 @ s0<- op 3950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_BYTE.S */ 3960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxtb r0, r0 @ r0<- op, r0-r3 changed 3976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 3985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_CHAR.S */ 3986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden uxth r0, r0 @ r0<- op, r0-r3 changed 4002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_SHORT.S */ 4012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxth r0, r0 @ r0<- op, r0-r3 changed 4028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT: /* 0x90 */ 4037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT.S */ 4038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT: /* 0x91 */ 4078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_INT.S */ 4079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT: /* 0x92 */ 4119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT.S */ 4120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT: /* 0x93 */ 4161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT.S */ 4162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT: /* 0x94 */ 4202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT.S */ 4203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 4237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT: /* 0x95 */ 4244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT.S */ 4245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT: /* 0x96 */ 4285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT.S */ 4286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT: /* 0x97 */ 4326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT.S */ 4327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT: /* 0x98 */ 4367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT.S */ 4368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT: /* 0x99 */ 4408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT.S */ 4409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT: /* 0x9a */ 4449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT.S */ 4450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply. 4581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WX 4584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * x YZ 4585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * -------- 4586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ZW ZX 4587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * YW YX 4588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The low word of the result holds ZX, the high word holds 4590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * it doesn't fit in the low 64 bits. 4592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most ARM math operations, multiply instructions have 4594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * restrictions on using the same register more than once (Rd and Rm 4595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * cannot be the same). 4596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long vAA, vBB, vCC */ 4598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 4606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_MUL_LONG_finish 4613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG: /* 0x9f */ 4661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_LONG.S */ 4662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_LONG.S */ 4707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 4740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_LONG.S */ 4751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long vAA, vBB, vCC */ 4846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_finish 4863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long vAA, vBB, vCC */ 4875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_finish 4892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long vAA, vBB, vCC */ 4904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_finish 4921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 4942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 4943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 4946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 4949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 4955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 4956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 4972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 4973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 4976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 4979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 4985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 4986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 5006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 5036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 5048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 5051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 5058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 5062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 5069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 5070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 5078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 5082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ s2<- op 5108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ s2<- op 5138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ s2<- op 5168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ s2<- op 5198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 5210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 5222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 5243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 5247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 5437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See OP_MUL_LONG for an explanation. 5757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * again we stuff it into rINST. 5760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long/2addr vA, vB */ 5762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 5769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 5892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 5932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 5933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 5943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 5972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 5973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 5982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 5983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 5986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long/2addr vA, vB */ 5988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 5991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 5993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 5996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 5997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 5999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_2ADDR_finish 6003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 6008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long/2addr vA, vB */ 6013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_2ADDR_finish 6028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long/2addr vA, vB */ 6038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_2ADDR_finish 6053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 6077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 6105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 6133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 6161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 6172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 6190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 6199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ d2<- op 6229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ d2<- op 6258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ d2<- op 6287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ d2<- op 6316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 6356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_RSUB_INT.S */ 6401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_LIT16.S */ 6508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_LIT16.S */ 6544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_LIT16.S */ 6579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 6916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 6917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 6954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 6955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 6982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 6992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 6993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7067c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_VOLATILE: /* 0xe3 */ 7068c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_VOLATILE.S */ 7069c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7070c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7071c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7072c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7073c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7074c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7075c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7076c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7077c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7078c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7079c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7080c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7081c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7082c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7083c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish @ no, already resolved 7084c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7085c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7086c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7087c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7088c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7089c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_VOLATILE_finish 7090c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7095c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_VOLATILE: /* 0xe4 */ 7096c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_VOLATILE.S */ 7097c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT.S */ 7098c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7099c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field put. 7100c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7101919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput, iput-boolean, iput-byte, iput-char, iput-short 7102c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7103c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7104c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7105c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7106c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7107c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7108c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7109c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7110c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7111c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ no, already resolved 7112c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7113c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7114c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7115c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7116c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7117c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_VOLATILE_finish @ yes, finish up 7118c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7123c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_VOLATILE: /* 0xe5 */ 7124c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_VOLATILE.S */ 7125c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7126c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7127c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7128c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7129c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7130c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7131c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7132c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7133c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7134c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7135c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7136c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7137c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_VOLATILE_resolve @ yes, do resolve 7138c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_finish: @ field ptr in r0 7139c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 71400890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7141c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7142c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7143c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7144c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7145c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7150c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_VOLATILE: /* 0xe6 */ 7151c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_VOLATILE.S */ 7152c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT.S */ 7153c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SPUT handler. 7155c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7156919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput, sput-boolean, sput-byte, sput-char, sput-short 7157c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7158c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7159c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7160c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7161c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7162c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7163c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7164c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SPUT_VOLATILE_resolve @ yes, do resolve 7165c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_finish: @ field ptr in r0 7166c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7167c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7168c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 7169c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 71700890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 7171c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 7172c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7177c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IGET_OBJECT_VOLATILE: /* 0xe7 */ 7178c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET_OBJECT_VOLATILE.S */ 7179c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IGET.S */ 7180c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7181c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit instance field get. 7182c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7183c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 7184c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7185c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7186c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7187c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7188c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7189c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7190c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7191c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7192c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7193c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish @ no, already resolved 7194c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7195c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7196c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7197c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7198c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 7199c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IGET_OBJECT_VOLATILE_finish 7200c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72055387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 72065387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 72075387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 72085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Wide 32-bit instance field get. 72105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iget-wide vA, vB, field@CCCC */ 72125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72195387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72205387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72215387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72225387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72235387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72245387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 72255387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish 72265387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 72325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 72335387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 72345387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iput-wide vA, vB, field@CCCC */ 72355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 72485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 72495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72545387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 72555387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 72565387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 72575387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SGET handler. 72595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sget-wide vAA, field@BBBB */ 72615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 72625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 72635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 72645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 72655387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 72675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_finish: 7268861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7269861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7270861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 72716e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 7272861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7273861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7274861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7275861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 72765387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7277861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 72785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 72795387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 72855387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 72865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 72875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SPUT handler. 72895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sput-wide vAA, field@BBBB */ 7291861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 72925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7293861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 72945387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7295861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 72965387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7297861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 72985387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7299861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 73005387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7301861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7302861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 7303861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7304861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 73056e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 7306861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7307861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7308861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7309861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 7310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 731496516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 731596516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a throw-verification-error instruction. This throws an 7326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception for an error discovered during verification. The 7327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op AA, ref@BBBB */ 7330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 7332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ export the PC 7333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowVerificationError @ always throws 7335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ handle exception 7336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Execute a "native inline" instruction. 7343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7344b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7345b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7347b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7348b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7349b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 1) @ r10<- BBBB 7353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ can throw 7355b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [sp] @ push &glue->retval 7358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ pop stack 7360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ test boolean result of inline 7361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ returned false, handle exception 7362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7368b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7369b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7370b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7371b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7372b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7373b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7374b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7375b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7376b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7377b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7378b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7379b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7380b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7381b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7382b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7383b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7384b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7385b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7386b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7387b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7388b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7389b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7390b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7391b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7392b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7393b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7394b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_QUICK.S */ 7419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7439b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher FETCH(ip, 1) @ ip<- field byte offset 7440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7444b48a4d53bc3349b5c99f8b87a396e7374e2d335cDave Butcher ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 7445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_QUICK.S */ 7476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 7496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 7497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ check object for null 7500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- field byte offset 7503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7512919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee /* For: iput-object-quick */ 7513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7522919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 7523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7525919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 7526d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strneb r2, [r2, r3, lsr #GC_CARD_SHIFT] @ mark card based on obj head 7527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7640c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_IPUT_OBJECT_VOLATILE: /* 0xfc */ 7641c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_VOLATILE.S */ 7642919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_IPUT_OBJECT.S */ 7643c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7644919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit instance field put. 7645c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7646919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: iput-object, iput-object-volatile 7647c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7648c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vA, vB, field@CCCC */ 7649c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7650c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 7651c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 7652c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 7653c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 7654c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 7655c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7656c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ no, already resolved 7657c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7658c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw 7659c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 7660c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 7661c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 7662c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_IPUT_OBJECT_VOLATILE_finish @ yes, finish up 7663c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown 7664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7668c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SGET_OBJECT_VOLATILE: /* 0xfd */ 7669c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET_OBJECT_VOLATILE.S */ 7670c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SGET.S */ 7671c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7672c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * General 32-bit SGET handler. 7673c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7674c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 7675c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7676c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7677c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7678c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7679c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7680c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7681c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7682c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq .LOP_SGET_OBJECT_VOLATILE_resolve @ yes, do resolve 7683c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_finish: @ field ptr in r0 7684c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 76850890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 7686c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 7687c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7688c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 7689c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7690c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7695c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.L_OP_SPUT_OBJECT_VOLATILE: /* 0xfe */ 7696c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* File: armv5te/OP_SPUT_OBJECT_VOLATILE.S */ 7697919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee/* File: armv5te/OP_SPUT_OBJECT.S */ 7698c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 7699919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * 32-bit SPUT handler for objects 7700c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * 7701919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee * for: sput-object, sput-object-volatile 7702c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 7703c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* op vAA, field@BBBB */ 7704c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 7705c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7706c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 7707c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 7708c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ is resolved entry null? 7709919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ no, continue 7710b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 7711919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee EXPORT_PC() @ resolve() could throw, so export now 7712d82097f6b409c5cd48568e54eb701604c3cceb18buzbee ldr r0, [r9, #offMethod_clazz] @ r0<- method->clazz 7713919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bl dvmResolveStaticField @ r0<- resolved StaticField ptr 7714919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ success? 7715919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee bne .LOP_SPUT_OBJECT_VOLATILE_finish @ yes, finish 7716919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee b common_exceptionThrown @ no, handle exception 7717919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee 7718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionEnd 7732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionEnd: 7733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 7735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Sister implementations 7737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterStart 7740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmSisterStart, %function 7741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 7742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 4 7743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterStart: 7744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING */ 7746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (String ref) 7750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_resolve: 7753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBBBBBB (String ref) 7769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_CLASS */ 7784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the Class has not yet been resolved. 7787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (Class ref) 7788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_CLASS_resolve: 7791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- Class reference 7796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CHECK_CAST */ 7804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_fullcheck: 7812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ class of the object that failed to be cast. 7818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ about to throw 7819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .LstrClassCastExceptionPtr 7821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowExceptionWithClassMessage 7823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds BBBB 7829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolve: 7832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- BBBB 7835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastExceptionPtr: 7845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrClassCastException 7846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INSTANCE_OF */ 7848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_fullcheck: 7856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_INSTANCE_OF_store 7858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds boolean result 7861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_store: 7864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test succeeded, save and bail. 7871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_trivial: 7874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ indicate success 7875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r3 holds BBBB 7885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolve: 7888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r3 @ r1<- BBBB 7891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 7898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_INSTANCE */ 7903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 32 @ minimize cache lines 7905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 7912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Class initialization required. 7916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class object 7918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_needinit: 7920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0 @ save r0 7921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInitClass @ initialize class 7922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ check boolean result 7923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ restore r0 7924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ failed, deal with init exception 7926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds BBBB 7931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolve: 7933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 7940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationErrorPtr: 7942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInstantiationError 7943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_ARRAY */ 7945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolve class. (This is an uncommon case.) 7949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds class ref CCCC 7952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_resolve: 7954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ r9<- length (save) 7956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- CCCC 7957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ r1<- length (restore) 7962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_NEW_ARRAY_finish 7964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Finish allocation. 7967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class 7969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_finish: 7972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 7979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ vA<- r0 7981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7993919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 7994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7999919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8000919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8001919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 8003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 8004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 8006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8009919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8010919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 8013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 8015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 8017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 8019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 8026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 8027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 8028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 8029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 8030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 8031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 8032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 8042919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8043919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8044919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8045919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8046919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8047d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 8048919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 8052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 8053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 8055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 8056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 8058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 8059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) @ define in one or the other, not both 8061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 8062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 8063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 8064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 8065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 8068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 8072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 8073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8077919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldrb rINST, [r3, #1] @ rINST<- descriptor[1] 8078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 8079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 8080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 8081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8083919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp rINST, #'I' @ array of ints? 8084919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'L' @ array of objects? 8085919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmpne rINST, #'[' @ array of arrays? 8086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 8087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 8090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8093919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8094919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str rINST, [rGLUE, #offGlue_retval+4] @ retval.h <- type 8095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 8097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 8099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 8101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 8103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 8110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 8111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 8112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 8113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 8114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 8115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 8116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 8126919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r0, [rGLUE, #offGlue_retval] @ r0<- object 8127919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r1, [rGLUE, #offGlue_retval+4] @ r1<- type 8128919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8129919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8130919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #'I' @ Is int array? 8131d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strneb r2, [r2, r0, lsr #GC_CARD_SHIFT] @ Mark card based on object head 8132919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ execute it 8133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 8136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 8137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 8140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 8142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 8143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) @ define in one or the other, not both 8145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 8146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 8147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 8148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 8149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_FLOAT */ 8152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_FLOAT_finish: 8153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_FLOAT */ 8157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_FLOAT_finish: 8158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_DOUBLE */ 8162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_DOUBLE_finish: 8163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_DOUBLE */ 8167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_DOUBLE_finish: 8168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMP_LONG */ 8172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_less: 8174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, #0 @ r1<- -1 8175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ instead, we just replicate the tail end. 8177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_greater: 8183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ r1<- 1 8184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to _finish 8185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_finish: 8187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_AGET_WIDE */ 8193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_AGET_WIDE_finish: 8195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_WIDE */ 8203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_WIDE_finish: 8205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_OBJECT */ 8212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8214d82097f6b409c5cd48568e54eb701604c3cceb18buzbee * rINST = vBB (arrayObj) 8215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = vAA (obj) 8216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = offset into array (vBB + vCC * width) 8217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_finish: 8219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ storing null reference? 8220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8222d82097f6b409c5cd48568e54eb701604c3cceb18buzbee ldr r1, [rINST, #offObject_clazz] @ r1<- arrayObj->clazz 8223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ okay? 8225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errArrayStore @ no 8226d82097f6b409c5cd48568e54eb701604c3cceb18buzbee mov r1, rINST @ r1<- arrayObj 8227919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8228919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ get biased CT base 8229919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee add r10, #offArrayObject_contents @ r0<- pointer to slot 8230919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8231919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee str r9, [r10] @ vBB[vCC]<- vAA 8232d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strb r2, [r2, r1, lsr #GC_CARD_SHIFT] @ mark card using object head 8233919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_skip_check: 8235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET */ 8241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_finish: 8248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_WIDE */ 8260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_WIDE_finish: 8267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_OBJECT */ 8279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_OBJECT_finish: 8286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 82910890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BOOLEAN */ 8300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BOOLEAN_finish: 8307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83120890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BYTE */ 8321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BYTE_finish: 8328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83330890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_CHAR */ 8342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_CHAR_finish: 8349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83540890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_SHORT */ 8363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_SHORT_finish: 8370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 83750890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ acquiring load 8376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT */ 8384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_finish: 8391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r1, rINST, #8, #4 @ r1<- A 8394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_WIDE */ 8403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_WIDE_finish: 8410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_OBJECT */ 8422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_OBJECT_finish: 8429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8435919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 84390890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8440d82097f6b409c5cd48568e54eb701604c3cceb18buzbee str r0, [r9, r3] @ obj.field (32 bits)<- r0 8441919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 8442919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 8443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BOOLEAN_finish: 8453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 84620890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BYTE */ 8467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BYTE_finish: 8474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 84830890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_CHAR */ 8488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_CHAR_finish: 8495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85040890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_SHORT */ 8509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_SHORT_finish: 8516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 85250890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden @ no-op @ releasing store 8526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET */ 8530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_resolve: 8536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_finish @ yes, finish 8542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_WIDE */ 8545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8549861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8550861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 8551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_resolve: 8553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_OBJECT */ 8562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_resolve: 8568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BOOLEAN */ 8577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_resolve: 8583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BYTE */ 8592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_resolve: 8598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_CHAR */ 8607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_resolve: 8613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_SHORT */ 8622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_resolve: 8628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT */ 8637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_resolve: 8643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_finish @ yes, finish 8649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_WIDE */ 8652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: &fp[AA] 8657861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8658861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 8659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_resolve: 8661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8666861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 8667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_OBJECT */ 8671b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee.LOP_SPUT_OBJECT_finish: @ field ptr in r0 8672919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 8673919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8674919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 8675919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 8676b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 8677919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 8678919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee @ no-op @ releasing store 8679b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee str r1, [r0, #offStaticField_value] @ field<- vAA 8680919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 8681d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 8682919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 8683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_resolve: 8691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BYTE */ 8700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_resolve: 8706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_CHAR */ 8715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_resolve: 8721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_SHORT */ 8730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_resolve: 8736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_continue: 8752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER */ 8762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_continue: 8769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_resolve: 8780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_nsm: 8792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT */ 8796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_resolve: 8803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the float in r0 to a long in r0/r1. 8883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenf2l_doconv: 8889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, lr} 8890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0x5f000000 @ (float)maxlong 8891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r4, r0 8892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0xdf000000 @ (float)minlong 8900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (80000000) 8903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r4 8908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpeq @ is arg == self? 8909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmeqfd sp!, {r4, pc} 8912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_f2lz @ convert float to long 8915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, pc} 8916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddend2l_doconv: 8926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, r5, lr} @ save regs 89275162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 89285162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 89295162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align for EABI 89315162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r5, r1 @ and r1 8933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 89415162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 89425162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 89435162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (8000000000000000) 8947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r4 @ compare against self 8953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r5 8954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpeq @ is arg == self? 8955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f 8958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_d2lz @ convert double to long 8962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 8964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 8965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, r5, pc} 8966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_MUL_LONG */ 8968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_MUL_LONG_finish: 8970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG */ 8975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_finish: 8977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG */ 8983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_finish: 8985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG */ 8991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_finish: 8993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_2ADDR_finish: 9001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 9006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_2ADDR_finish: 9008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 9013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_2ADDR_finish: 9015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9019c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_VOLATILE */ 9020c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9021c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9022c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9023c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9024c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9025c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9026c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_VOLATILE_finish: 9027c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9028c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9029c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9030c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9031c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 90320890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9033c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9034c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9035c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9036c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9037c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9038c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9039c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9040c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_VOLATILE */ 9041c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9042c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9043c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9044c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9045c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9046c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9047c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_VOLATILE_finish: 9048c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9049c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9050c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9051c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9052c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9053c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9054c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9055c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9056c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 90570890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9058c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 9059c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9060c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9061c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_VOLATILE */ 9062c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9063c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9064c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9065c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9066c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9067c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_VOLATILE_resolve: 9068c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9069c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9070c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9071c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9072c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9073c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_VOLATILE_finish @ yes, finish 9074c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9075c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9076c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_VOLATILE */ 9077c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9078c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9079c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9080c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9081c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9082c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SPUT_VOLATILE_resolve: 9083c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9084c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9085c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9086c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9087c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9088c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SPUT_VOLATILE_finish @ yes, finish 9089c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9090c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9091c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IGET_OBJECT_VOLATILE */ 9092c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9093c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9094c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9095c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9096c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9097c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9098c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IGET_OBJECT_VOLATILE_finish: 9099c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9100c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9101c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9102c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9103c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 91040890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ acquiring load 9105c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 9106c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9107c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r2, r2, #15 @ r2<- A 9108c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9109c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 9110c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9111c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 91125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IGET_WIDE_VOLATILE */ 91135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 91165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 91175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 91185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91195387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IGET_WIDE_VOLATILE_finish: 91205387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 91215387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 91225387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 9123c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9124861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 91256e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicRead64 @ r0/r1<- contents of field 9126861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 91275387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 9128861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9129861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 91305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9131861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 91325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 91335387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 91345387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 91355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 91365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IPUT_WIDE_VOLATILE */ 91385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 91415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 91425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 91435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IPUT_WIDE_VOLATILE_finish: 91455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 91465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 91475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden and r2, r2, #15 @ r2<- A 91485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 91495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 91505387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 91515387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 91525387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 9153861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 9154c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden .if 1 9155861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 91566e10b9aaa72425a4825a25f0043533d0c6fdbba4Andy McFadden bl dvmQuasiAtomicSwap64 @ stores r0/r1 into addr r2 9157861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 9158861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 9159861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9160861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 91615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SGET_WIDE_VOLATILE */ 91635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91655387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 91665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 9167861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9168861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 91695387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91705387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_resolve: 91715387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 91725387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 91735387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 91745387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 91755387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 91765387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 91775387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 91785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91795387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SPUT_WIDE_VOLATILE */ 91805387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 91815387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 91825387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 91835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 91845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9: &fp[AA] 9185861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9186861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 91875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 91885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SPUT_WIDE_VOLATILE_resolve: 91895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 91905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 91915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 91925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 91935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 9194861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 91955387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 91965387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 91975387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 9198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_EXECUTE_INLINE */ 9199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Extract args, call function. 9202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = #of args (0-4) 9203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = call index 9204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Other ideas: 9207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Use a jump table from the main piece to jump directly into the 9208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 9209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Have five separate pieces that do the loading, so we can work the 9210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interleave a little better. Increases code size. 9211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_continue: 9213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r9, 2) @ r9<- FEDC 9215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r9, #0xf000 @ isolate F 9218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 9219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r9, #0x0f00 @ isolate E 9220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 9221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r9, #0x00f0 @ isolate D 9222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r9, #0x000f @ isolate C 9224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: 9226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (not reached) 9229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_table: 9231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word gDvmInlineOpsTable 9232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9233b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9234b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9235b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9236b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9237b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9238b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9239b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9240b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9241b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9242b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9243b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9244b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9245b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9246b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9247b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9248b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9249b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9250b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9251b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9252b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9253b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9254b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9255b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9256b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9257b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9258b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9259b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9260b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9261b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9262c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_IPUT_OBJECT_VOLATILE */ 9263c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9264c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9265c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Currently: 9266c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r0 holds resolved field 9267c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r9 holds object 9268c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9269c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_IPUT_OBJECT_VOLATILE_finish: 9270c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden @bl common_squeak0 9271c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 9272c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 9273c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden and r1, r1, #15 @ r1<- A 9274c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r9, #0 @ check object for null 9275c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 9276919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9277c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden beq common_errNullObject @ object was null 9278c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9279c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 92800890e5bf0b2a502ca1030e9773fabc16ef1b5981Andy McFadden SMP_DMB @ releasing store 9281d82097f6b409c5cd48568e54eb701604c3cceb18buzbee str r0, [r9, r3] @ obj.field (32 bits)<- r0 9282919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r0, #0 @ stored a null reference? 9283919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card if not 9284c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9285c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9286c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SGET_OBJECT_VOLATILE */ 9287c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9288c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden /* 9289c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * Continuation if the field has not yet been resolved. 9290c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden * r1: BBBB field ref 9291c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden */ 9292c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden.LOP_SGET_OBJECT_VOLATILE_resolve: 9293c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 9294c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 9295c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 9296c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 9297c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden cmp r0, #0 @ success? 9298c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden bne .LOP_SGET_OBJECT_VOLATILE_finish @ yes, finish 9299c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden b common_exceptionThrown @ no, handle exception 9300c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9301c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden/* continuation for OP_SPUT_OBJECT_VOLATILE */ 9302b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee.LOP_SPUT_OBJECT_VOLATILE_finish: @ field ptr in r0 9303919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee mov r2, rINST, lsr #8 @ r2<- AA 9304919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9305919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_VREG(r1, r2) @ r1<- fp[AA] 9306919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee ldr r2, [rGLUE, #offGlue_cardTable] @ r2<- card table base 9307b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee ldr r9, [r0, #offField_clazz] @ r9<- field->clazz 9308919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GET_INST_OPCODE(ip) @ extract opcode from rINST 9309919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee SMP_DMB @ releasing store 9310b78c76f88ea42e7a3b295c210ca9ee86e7290043buzbee str r1, [r0, #offStaticField_value] @ field<- vAA 9311919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee cmp r1, #0 @ stored a null object? 9312d82097f6b409c5cd48568e54eb701604c3cceb18buzbee strneb r2, [r2, r9, lsr #GC_CARD_SHIFT] @ mark card based on obj head 9313919eb063ce4542d3698e10e20aba9a2dfbdd0f82buzbee GOTO_OPCODE(ip) @ jump to next instruction 9314c35a2ef53d0cccd6f924eeba36633220ec67c32eAndy McFadden 9315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterEnd 9317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterEnd: 9318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/footer.S */ 9320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 9323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common subroutines and data 9324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 9325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 9330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 9331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 933397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 933497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 933597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 9336d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 933797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 9338d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9339d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9340d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 934197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 934297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 934397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 9344d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9345d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 934697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 9347d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 934897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 93497a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 93507a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 93517a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93527a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC @ pass our target PC 93537a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSNoProfile @ r2<- interpreter entry point 93547a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 93557a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r3, [r10, #offThread_inJitCodeCache] @ back to the interp land 93567a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b jitSVShadowRunEnd @ doesn't return 93577a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 935840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 935940094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9360d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 936140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC @ pass our target PC 93627a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 93637a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9364d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9365d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 936640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng 936740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 936840094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 9369d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93709a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 937197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 93727a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9373d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9374d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 937597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 937640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpBackwardBranch 937740094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpBackwardBranch: 9378d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93799a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 938097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 93817a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9382d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9383d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 938497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 938597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 938697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 9387d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93889a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 938997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 93907a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9391d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9392d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 939397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 939497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 939597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 9396d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 939797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 939897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 93997a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r3, #0 @ 0 means !inJitCodeCache 9400d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9401d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 940297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter when the compiler is 9405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * having issues translating/executing a Dalvik instruction. We have to skip 9406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the code cache lookup otherwise it is possible to indefinitely bouce 9407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * between the interpreter and the code cache if the instruction that fails 9408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to be compiled happens to be at a trace start. 9409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpPunt 9411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpPunt: 94127a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r0 9414978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,lr 9416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpPunt; 9417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 94197a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 94207a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return to the interpreter to handle a single instruction. 9428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 <= PC 9430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 <= PC of resume instruction 9431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr <= resume point in translation 9432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpSingleStep 9434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpSingleStep: 9435d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9436d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 9437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#kInterpEntryInstr 9438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ enum is 4 byte in aapcs-EABI 9439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_entryPoint] 9440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC,r0 9441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 94427a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitSingleStep @ Ask for single step and then revert 9445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp to bail to debug interp 9447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 944940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 945040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * Return from the translation cache and immediately request 945140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * a translation for the exit target. Commonly used for callees. 945240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 945340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 945440094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9455978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 945640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmBumpNoChain 945740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng#endif 945840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 945940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC 946040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 946140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 946240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r1, rPC @ arg1 of translation may need this 946340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 94647a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 @ !0 means translation exists 946540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bxne r0 @ continue native execution if so 94667a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng b 2f @ branch over to use the interpreter 9467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache and immediately request 9470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a translation for the exit target. Commonly used following 9471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invokes. 9472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 947340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 947440094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 94759a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 94767a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94779a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9478bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST, #-4 @ .. which is 9 bytes back 9479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 94807a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 94817a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 2f 9484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 94869a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 94879a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* No translation, so request one if profiling isn't disabled*/ 9493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 9494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 949840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng movne r2,#kJitTSelectRequestHot @ ask for trace selection 9499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_selectTrace 9500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter. 9505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The return was done with a BLX from thumb mode, and 9506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the following 32-bit word contains the target rPC value. 9507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note that lr (r14) will have its low-order bit set to denote 9508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * its thumb-mode origin. 9509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We'll need to stash our lr origin away, recover the new 9511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * target and then check to see if there is a translation available 9512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for our new target. If so, we do a translation chain and 9513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * go back to native execution. Otherwise, it's back to the 9514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter (after treating this entry as a potential 9515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace start). 9516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNormal 9518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNormal: 95199a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 95207a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95219a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9522bd0472480c6e876198fe19c4ffa22350c0ce57daBill Buzbee add rINST,#-4 @ .. which is 9 bytes back 9523978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNormal 9525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 95287a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq toInterpreter @ go if not, otherwise do chain 9531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 95339a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 95349a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter to do method invocation. 9541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check if translation exists for the callee, but don't chain to it. 9542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 95437a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng .global dvmJitToInterpNoChainNoProfile 95447a2697d327936e20ef5484f7819e2e4bf91c891fBen ChengdvmJitToInterpNoChainNoProfile: 95457a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#if defined(WITH_JIT_TUNING) 95467a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmBumpNoChain 95477a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng#endif 95487a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 95497a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r0,rPC 95507a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bl dvmJitGetCodeAddr @ Is there a translation? 95517a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 95527a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov r1, rPC @ arg1 of translation may need this 95537a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 95547a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng cmp r0,#0 95557a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng bxne r0 @ continue native execution if so 95567a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng EXPORT_PC() 95577a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng adrl rIBASE, dvmAsmInstructionStart 95587a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng FETCH_INST() 95597a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GET_INST_OPCODE(ip) @ extract opcode from rINST 95607a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng GOTO_OPCODE(ip) @ jump to next instruction 95617a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 95627a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng/* 95637a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Return from the translation cache to the interpreter to do method invocation. 95647a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng * Check if translation exists for the callee, but don't chain to it. 95657a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng */ 9566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNoChain 9567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNoChain: 9568978738d2cbf9d08fa78c65762eaac3351ab76b9aBen Cheng#if defined(WITH_JIT_TUNING) 9569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNoChain 9570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 95717a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 95747a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 95759a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 95769a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution if so 957997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * No translation, restore interpreter regs and start interpreting. 9583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rGLUE & rFP were preserved in the translated code, and rPC has 9584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * already been restored by the time we get here. We'll need to set 9585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * up rIBASE & rINST, and load the address of the JitTable into r0. 9586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddentoInterpreter: 9588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ NOTE: intended fallthrough 95937a2697d327936e20ef5484f7819e2e4bf91c891fBen Cheng 9594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code to update potential trace start counter, and initiate 9596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a trace-build if appropriate. On entry, rPC should point to the 9597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * next instruction to execute, and rINST should be already loaded with 9598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the next opcode word, and r0 holds a pointer to the jit profile 9599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * table (pJitProfTable). 9600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_testUpdateProfile: 9602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_updateProfile: 9607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 96087b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 96097b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 9610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1,r1,#1 @ decrement counter 96127b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 9613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Here, we switch to the debug interpreter to request 9617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace selection. First, though, check to see if there 9618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * is already a native translation in place (and, if so, 9619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * jump to it now). 9620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9621d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 96227a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 96237b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 9624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 96277a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 96287a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 96297a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 963197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ jump to the translation 963340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 963440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng @ fall-through to common_selectTrace 963597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 963640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng moveq r2,#kJitTSelectRequest @ ask for trace selection 96379a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 96389a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 96399a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 96409a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 96419a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 96429a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 9643d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r10, r0 @ save target 96449a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 9645d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng cmp r0, r10 @ special case? 9646d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne jitSVShadowRunStart @ set up self verification shadow space 96474934b377d9cf5df6f80da7caab4f2178c6cec307Ben Cheng @ Need to clear the inJitCodeCache flag 96484934b377d9cf5df6f80da7caab4f2178c6cec307Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ r10 <- glue->self 96494934b377d9cf5df6f80da7caab4f2178c6cec307Ben Cheng mov r3, #0 @ 0 means not in the JIT code cache 96504934b377d9cf5df6f80da7caab4f2178c6cec307Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ back to the interp land 96519a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 96529a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 96539a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 965497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 96559a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 965640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 965740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * On entry: 965840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 965940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 9660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_selectTrace: 9661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 96629c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 96639c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp 9665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 966797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 966897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 966997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 967097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 9671d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * On entry: 9672d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * rPC, rFP, rGLUE: the values that they should contain 9673d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * r10: the address of the target translation. 967497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9675d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunStart: 967697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 967797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 967897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 96799a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 968097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9681ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9682ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9683ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 968497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 968597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 968697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 968797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 968897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9689d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunEnd: 969097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 969197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9692ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9693ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9694ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9695ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 969697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 969797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 969897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 969997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 970030f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 970130f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 970297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 970397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 970497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 970597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 970697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 970797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 970897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 970997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 971097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 971197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 971297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code when a backward branch is taken. 9717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9718c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * TODO: we could avoid a branch by just setting r0 and falling through 9719c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * into the common_periodicChecks code, and having a test on r0 at the 9720c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * end determine if we should return to the caller or update & branch to 9721c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the next instr. 9722c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is PC adjustment *in bytes* 9725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_backwardBranch: 9727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryInstr 9728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9745c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * activity has begun. If so, we suspend the thread or side-exit to 9746c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * the debug interpreter as appropriate. 9747c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9748c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * The common case is no activity on any of these, so we want to figure 9749c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * that out quickly. If something is up, we can then sort out what. 9750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9751c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * We want to be fast if the VM was built without debugger or profiler 9752c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * support, but we also need to recognize that the system is usually 9753c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * shipped with both of these enabled. 9754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: reduce this so we're just checking a single location. 9756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9758c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 is reentry type, e.g. kInterpEntryInstr (for debugger/profiling) 9759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is trampoline PC adjustment *in bytes* 9760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_periodicChecks: 9762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9767c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9769c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9770c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9772c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrne ip, ip, r1 @ ip<- suspendCount | debuggerActive 9773c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs ip, ip, r2 @ ip<- suspend|debugger|profiler; set Z 9774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9775c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bxeq lr @ all zero, return 9776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9777c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9778c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * One or more interesting events have happened. Figure out what. 9779c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9780c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * If debugging or profiling are compiled in, we need to disambiguate. 9781c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9782c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * r0 still holds the reentry type. 9783c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9784c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr ip, [r3] @ ip<- suspendCount (int) 9785c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp ip, #0 @ want suspend? 9786c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 1f @ no, must be debugger/profiler 9787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9788c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden stmfd sp!, {r0, lr} @ preserve r0 and lr 9789964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9790964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9791964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9792964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9793964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9794d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 9795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9796d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [r3] @ r3 <- pJitProfTable 9797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC 9798964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9799964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9800964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9801964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9802964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9803c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bl dvmCheckSuspendPending @ do full check, suspend if necessary 9804c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldmfd sp!, {r0, lr} @ restore r0 and lr 9805c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9806c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden /* 9807c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * Reload the debugger/profiler enable flags. We're checking to see 9808c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * if either of these got set while we were suspended. 9809c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * 9810c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * We can't really avoid the #ifdefs here, because the fields don't 9811c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden * exist when the feature is disabled. 9812c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden */ 9813c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9814c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden cmp r1, #0 @ debugger enabled? 9815c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldrneb r1, [r1] @ yes, r1<- debuggerActive (boolean) 9816c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9817c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9819c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden orrs r1, r1, r2 9820c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden beq 2f 9821c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9822c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden1: @ debugger/profiler enabled, bail out; glue->entryPoint was set above 9823c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden str r0, [rGLUE, #offGlue_entryPoint] @ store r0, need for debug/prof 9824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, rPC, r9 @ update rPC 9825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ "want switch" = true 9826c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden b common_gotoBail @ side exit 9827c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden 9828c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden2: 9829c95e0fbce4f77b2b08eb48205e405793de0d4248Andy McFadden bx lr @ nothing to do, return 9830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * State registers will be saved to the "glue" area before bailing. 9836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * other interpreter or just bail all the way out 9840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_gotoBail: 9842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ r0<- glue ptr 9844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r1, r1, #1 @ using (boolean+1) 9847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl _longjmp @ does not return 9849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_abort 9850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation with range. 9854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodRange: 9859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewRange: 9860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- CCCC 9865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r2, r2, #1 @ count-- 9873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r10], #4 @ *outs++ = val 9874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1b @ ...while count != 0 9875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LinvokeArgsDone 9877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation without range. 9880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodNoRange: 9885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewNoRange: 9886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone 9893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNonRange: 9896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vA 9903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r1, #0xf000 @ isolate G 9904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vG 9907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r1, #0x0f00 @ isolate F 9908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vF 9911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r1, #0x00f0 @ isolate E 9912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vE 9915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r1, #0x000f @ isolate D 9916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vD 9919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: @ fall through to .LinvokeArgsDone 9920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ find space for the new stack frame, check for overflow 9925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@ bl common_dumpRegs 9929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 99337a44e4ee0782d24b4c6090be1f0a3c66f971f2c1Andy McFadden blo .LstackOverflow @ yes, this frame will overflow stack 9934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ set up newSaveArea 9936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EASY_GDB 9937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offStackSaveArea_returnAddr] 9945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r10, #offStackSaveArea_method] 9947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden tst r3, #ACC_NATIVE 9948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LinvokeNative 9949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP 9954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 9959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 9960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r2 @ publish new rPC 9968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Update "glue" values for the new method 9971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNative: 9992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Prep for the native call 9993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9995d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9997d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ r2<- methodToCall 10001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ r0<- newFp (points to args) 10002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 10003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 10005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 10006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .Lskip 10007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_mterp, %function 10008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_mterp: 10009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 10010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 10011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 10012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lskip: 10013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @mov lr, pc @ set return addr 10016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 10017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 10018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10019964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10020964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 10021964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10022964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 10023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ native return; r9=self, r10=newSaveArea 10024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ equivalent to dvmPopJniLocals 10025d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 10026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 10027964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10028964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 10029964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 10031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null? 10032d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 10033964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 10034964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 10035964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 10036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ no, handle exception 10037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 10039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 100426ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 100436ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 10044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 10045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmHandleStackOverflow 10046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 10048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 10049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation, calling through "glue code". 10054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: now that we have range and non-range invoke handlers, this 10056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * needs to be split into two. Maybe just create entry points 10057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that set r9 and jump here? 10058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 10060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 10061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 10062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeOld: 10065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #8 @ space for args + pad 10066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 10067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ A2<- methodToCall 10068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ A0<- glue 10069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 10070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ A1<- methodCallRange 10071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ A3<- AA 10072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #0] @ A4<- ip 10073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 10074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ remove arg area 10075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall @ continue to next instruction 10076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for handling a return instruction. 10082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 10084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_returnFromMethod: 10086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnNew: 10087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryReturn 10088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 10089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 10090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 10092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 10093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 10094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 10095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r2<- method we're returning to 10096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 10097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is this a break frame? 10098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 10099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 10100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_gotoBail @ break frame, bail out completely 10101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 10103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 10104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 10105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 10106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 101077a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 10108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 10109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 101107a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 101117a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 101127a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 10113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 10116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 10118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 10119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return handling, calls through "glue code". 10124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnOld: 10127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 10129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_returnFromMethod 10130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 10131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Somebody has thrown an exception. Handle it. 10136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If the exception processing code returns to us (instead of falling 10138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out of the interpreter), continue with whatever the next instruction 10139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * now happens to be. 10140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 10142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpCommonExceptionThrown 10144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpCommonExceptionThrown: 10145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_exceptionThrown: 10146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionNew: 10147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryThrow 10148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 10149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 10150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 10152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 10153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 10154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 10155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 10156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- NULL 10157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 10158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up args and a local for "&fp" */ 10160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 10161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [sp, #-4]! @ *--sp = fp 10162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov ip, sp @ ip<- &fp 10163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- false 10164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #-4]! @ *--sp = &fp 10165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 10166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 10167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 10168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r9 @ r2<- exception 10169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 10170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 10171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 10173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 10174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 10176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 10178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ no, skip ahead 10179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r0 @ save relPc result in rFP 10180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 101814fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 10182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCleanupStackOverflow @ call(self) 10183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP @ restore result 10184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 10185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 10187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 10188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is catchRelPc < 0? 10189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ restore stack 10190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi .LnotCaughtLocally 10191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* adjust locals to match self->curFrame and updated PC */ 10193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 10194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 10195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 10196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 10197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 10198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 10199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 10200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 10201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* release the tracked alloc on the exception */ 10203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 10204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 10205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* restore the exception if the handler wants it */ 10208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 10209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 10211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 10212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 10215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix stack overflow if necessary */ 10216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 10218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, r10 @ if yes: r0<- self 102194fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 10220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 10221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ may want to show "not caught locally" debug messages here 10223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if DVM_SHOW_EXCEPTION >= 2 10224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call __android_log_print(prio, tag, format, ...) */ 10225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* "Exception %s from %s:%d not caught locally" */ 10226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 10227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 10228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_insns] 10229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 10230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden asr r1, r1, #1 10231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLineNumFromPC 10232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 10233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmGetMethodSourceFile(method) 10234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 10235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmGetMethodSourceFile 10236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 10237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ exception->clazz->descriptor 10238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] 10239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_descriptor] 10240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ 10241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, strExceptionNotCaughtLocally 10242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strLogTag 10243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #3 @ LOG_DEBUG 10244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __android_log_print 10245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offThread_exception] @ restore exception 10247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 10248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 10249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 10251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail @ bail out 10252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exception handling, calls through "glue code". 10256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionOld: 10259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 10261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_exceptionThrown 10262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 10263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * After returning from a "glued" function, pull out the updated 10268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * values and start executing at the next instruction. 10269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_resumeAfterGlueCall: 10271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 10272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 10273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array index. 10278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayIndex: 10280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayIndexException 10282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array value. 10288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayStore: 10290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayStoreException 10292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Integer divide or mod by zero. 10298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errDivideByZero: 10300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArithmeticException 10302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strDivideByZero 10303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Attempt to allocate an array with a negative size. 10308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNegativeArraySize: 10310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNegativeArraySizeException 10312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invocation of a non-existent method. 10318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNoSuchMethod: 10320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNoSuchMethodError 10322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We encountered a null object when we weren't expecting one. We 10328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * export the PC, throw a NullPointerException, and goto the exception 10329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * processing code. 10330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNullObject: 10332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNullPointerException 10334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For debugging, cause an immediate fault. The source address will 10340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be in lr (use a bl instruction to jump here). 10341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_abort: 10343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, .LdeadFood 10344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdeadFood: 10345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word 0xdeadf00d 10346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out a "we were here", preserving all registers. (The attempt 10349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to save ip won't work, but we need to save an even number of 10350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * registers for EABI 64-bit stack alignment.) 10351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .macro SQUEAK num 10353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_squeak\num: 10354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 10356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #\num 10357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endm 10361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 0 10363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 1 10364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 2 10365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 3 10366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 4 10367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 5 10368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out the number in r0, preserving registers. 10371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNum: 10373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 10375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 10376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print a newline, preserving registers. 10382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNewline: 10384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNewline 10386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printHex: 10394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 10396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintHex 10397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printLong: 10405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r1 10407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 10408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintLong 10409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printMethod: 10417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpPrintMethod 10419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Call a C helper function that dumps regs and possibly some 10424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * additional info. Requires the C function to be compiled in. 10425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_dumpRegs: 10428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpDumpArmRegs 10430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if 0 10435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Experiment on VFP mode. 10437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddensetFPSCR: 10443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ make sure no stray bits are set 10444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmrx r2, fpscr @ get VFP reg 10445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ bit-invert mask 10446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, r1 @ clear masked bits 10447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r2, r2, r0 @ set specified bits 10448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmxr fpscr, r2 @ set VFP reg 10449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r2 @ return new value 10450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmConfigureFP 10454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmConfigureFP, %function 10455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmConfigureFP: 10456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {ip, lr} 10457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x03000000 sets DN/FZ */ 10458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x00009f00 clears the six exception enable flags */ 10459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_squeak0 10460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl setFPSCR 10463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {ip, pc} 10464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references, must be close to the code that uses them. 10469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArithmeticException: 10472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArithmeticException 10473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayIndexException: 10474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayIndexException 10475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayStoreException: 10476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayStoreException 10477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrDivideByZero: 10478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrDivideByZero 10479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNegativeArraySizeException: 10480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNegativeArraySizeException 10481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNoSuchMethodError: 10482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNoSuchMethodError 10483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNullPointerException: 10484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNullPointerException 10485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrLogTag: 10487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrLogTag 10488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrExceptionNotCaughtLocally: 10489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrExceptionNotCaughtLocally 10490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNewline: 10492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNewline 10493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrSqueak: 10494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrSqueak 10495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintHex: 10496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintHex 10497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintLong: 10498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintLong 10499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Zero-terminated ASCII string data. 10502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with the address, or use an ADR pseudo-op to get the address 10505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * PC-relative addressing mode and hence has a limited range, which 10507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * makes it not work well with mergeable string sections. 10508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrBadEntryPoint: 10512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Bad entry point %d\n" 10513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArithmeticException: 10514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArithmeticException;" 10515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayIndexException: 10516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayStoreException: 10518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastException: 10520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ClassCastException;" 10521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrDivideByZero: 10522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "divide by zero" 10523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrFilledNewArrayNotImpl: 10524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInternalError: 10526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InternalError;" 10527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationError: 10528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InstantiationError;" 10529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNegativeArraySizeException: 10530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNoSuchMethodError: 10532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNullPointerException: 10534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NullPointerException;" 10535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrLogTag: 10537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "mterp" 10538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrExceptionNotCaughtLocally: 10539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNewline: 10542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "\n" 10543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrSqueak: 10544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%d>" 10545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintHex: 10546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<0x%x>" 10547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintLong: 10548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%lld>" 10549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10550