InterpAsm-armv7-a.S revision 30f1f463b132c7b6daf2de825c5fa44ce356ca13
1a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 2a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * --> DO NOT EDIT <-- 5a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/header.S */ 8a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 10a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 11a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 13a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 14a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 15a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 17a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 18a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 21a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 22a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 23a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 24a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ARMv5 definitions and declarations. 25a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 26a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 27a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 28a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenARM EABI general notes: 29a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 30a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr4-r8 are available for general use 32a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr9 is given special treatment in some situations, but not for us 33a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr10 (sl) seems to be generally available 34a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr14 (lr) must be preserved 38a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr15 (pc) can be tinkered with directly 39a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 40a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0 holds returns of <= 4 bytes 41a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 43a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 47a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden(i.e. the 5th arg). 50a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 51a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 53a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 56a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 57a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 58a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMterp and ARM notes: 59a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 60a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenThe following registers have fixed assignments: 61a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 62a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden reg nick purpose 63a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r6 rGLUE MterpGlue pointer 66a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r7 rINST first 16-bit code unit of current instruction 67a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 69a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenunspecified registers or condition codes. 72a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 73a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 74a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* single-purpose registers, given names for clarity */ 75a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rPC r4 76a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rFP r5 77a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rGLUE r6 78a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rINST r7 79a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rIBASE r8 80a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 81a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 89a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 90a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be done *before* something calls dvmThrowException. 92a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 93a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 96a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * It's okay to do this more than once. 97a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 98a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define EXPORT_PC() \ 99a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Given a frame pointer, find the stack save area. 103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with this). 121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This must come AFTER anything that can throw an exception, or the 123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception catch may miss. (This also implies that it must come after 124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * EXPORT_PC().) 125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * here. 144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The "_S" variant works the same but treats the value as signed. 152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * byte of the halfword you want (lo/hi). 160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the instruction's opcode field into the specified register. 165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Get/set the 32-bit value from a Dalvik register. 183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_JIT_ENABLED(_reg) ldr _reg,[rGLUE,#offGlue_jitEnabled] 189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert a virtual register index into an address. 194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add _reg, rFP, _vreg, lsl #2 197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to expand the macros into assembler assignment statements. 201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#include "../common/asm-constants.h" 203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/platform.S */ 206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * CPU-version-specific defines 209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * one-way branch. 215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP. Does not modify LR. 217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC source 219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Jump to subroutine. 225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC_LR source 229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov lr, pc 230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDMFD_PC regs 239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {\regs,pc} 240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/entry.S */ 244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Interpreter entry point. 261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't have formal stack frames, so gdb scans upward in the code 265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to find the start of the function (a label with the %function type), 266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and then looks at the next few instructions to figure out what 267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * got pushed onto the stack. From this it figures out how to restore 268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the registers, including PC, for the previous stack frame. If gdb 269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sees a non-function label, it stops scanning, so either we need to 270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have nothing but assembler-local labels between the entry point and 271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the break, or we need to fake it out. 272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * When this is defined, we add some stuff to make gdb less confused. 274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define ASSIST_DEBUGGER 1 276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdRun 280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdRun, %function 281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This function returns a boolean "changeInterp" value. The return comes 287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * via a call to dvmMterpStdBail(). 288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdRun: 290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY1 \ 291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .save {r4-r10,fp,lr}; \ 292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY2 \ 294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .pad #4; \ 295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align 64 296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* save stack pointer, add magic word for debuggerd */ 302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up "named" registers, figure out entry point */ 305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rGLUE, r0 @ set rGLUE 306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offGlue_entryPoint] @ InterpEntry enum is char 307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryInstr @ usual case? 310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lnot_instr @ no, handle it 311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lno_singleStep: 314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* Entry is always a possible trace start */ 315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* start executing the instruction at rPC */ 323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_instr: 329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_returnFromMethod 331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_return: 333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown 335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_throw: 338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0,[rGLUE, #offGlue_jitResume] 339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2,[rGLUE, #offGlue_jitResumePC] 340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lbad_arg 342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp rPC,r2 343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lno_singleStep @ must have branched, don't resume 344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #kInterpEntryInstr 345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r1, [rGLUE, #offGlue_entryPoint] 346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, .LdvmCompilerTemplate 347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx r0 @ re-enter the translation 348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdvmCompilerTemplate: 349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word dvmCompilerTemplateStart 350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lbad_arg: 353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strBadEntryPoint 354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r1 holds value of entryPoint 355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAbort 357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdBail 361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdBail, %function 362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Restore the stack pointer and PC from the save point established on entry. 365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * LR to PC. 371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 bool changeInterp 375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdBail: 377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ return the changeInterp value 379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 @ un-align 64 380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references. 385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrBadEntryPoint: 387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrBadEntryPoint 388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionStart 392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmInstructionStart, %function 393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionStart = .L_OP_NOP 394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOP: /* 0x00 */ 399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NOP.S */ 400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_inst, %function 407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_inst: 408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE: /* 0x01 */ 418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE.S */ 419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_16: /* 0x03 */ 448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE_WIDE.S */ 464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide vA, vB */ 465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/from16 vAA, vBBBB */ 482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- BBBB 484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/16 vAAAA, vBBBB */ 499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- BBBB 501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- AAAA 502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-result-wide vAA */ 582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-exception vAA */ 613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ r1<- 0 617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN: /* 0x0f */ 634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 64-bit value. Copies the return value into the "glue" 654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* return-wide vAA */ 657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_4: /* 0x12 */ 687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_CONST_4.S */ 688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/4 vA, #+B */ 689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_16: /* 0x13 */ 701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_16.S */ 702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/16 vAA, #+BBBB */ 703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST: /* 0x14 */ 714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST.S */ 715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const vAA, #+BBBBbbbb */ 716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/high16 vAA, #+BBBB0000 */ 731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/16 vAA, #+BBBB */ 745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0 @ r0<- 00000000 799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING: /* 0x1a */ 810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING.S */ 811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBB */ 812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_resolve 819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBBBBBB */ 829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/class vAA, Class@BBBB */ 848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_CLASS_resolve 855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Synchronize on an object. 866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-enter vAA */ 868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null object, throw an exception 874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLockObject @ call(self, obj) 876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ exception raised, bail out 881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlock an object. 892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exceptions that occur when unlocking a monitor need to appear as 894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if they happened at the following instruction. See the Dalvik 895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction spec. 896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-exit vAA */ 898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ before fetch: export the PC 900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes 903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, exception is pending 907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if a cast from one class to another is allowed. 918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* check-cast vAA, class@BBBB */ 920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r3) @ r9<- object 923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ is object null? 925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolved: 932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_okay: 935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if an object reference is an instance of a class. 945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Most common situation is a non-null object, being compared against 947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an already-resolved class. 948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* instance-of vA, vB, class@CCCC */ 950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- CCCC 958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ARRAY_LENGTH.S */ 972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return the length of an array. 974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yup, fail 980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ vB<- length 984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new instance of a class. 993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-instance vAA, class@BBBB */ 995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocObject @ r0<- new object 1009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Allocate an array of objects, specified with the array class 1017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and a count. 1018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The verifier guarantees that this is an array class, so we don't 1020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * check for it here. 1021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-array vA, vB, class@CCCC */ 1023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 1024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- CCCC 1025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ check length 1029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_errNegativeArraySize @ negative length, bail 1031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for resolve, alloc 1033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC(); 1104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ 0 means an exception is thrown 1106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ has exception 1107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW: /* 0x27 */ 1114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW.S */ 1115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception object in the current thread. 1117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* throw vAA */ 1119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 1123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, throw an NPE instead 1124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ bypass dvmSetException, just store it 1125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 1127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO: /* 0x28 */ 1132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO.S */ 1133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 8-bit offset. 1135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto +AA */ 1140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_16: /* 0x29 */ 1160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_16.S */ 1161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 16-bit offset. 1163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/16 +AAAA */ 1168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_32: /* 0x2a */ 1188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_32.S */ 1189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 32-bit offset. 1191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction doesn't affect the V flag, so we need to clear it 1198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * explicitly. 1199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/32 +AAAAAAAA */ 1201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, ip @ (clear V flag during stall) 1204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13205162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13235162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13255162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13345162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13595162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13625162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13645162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13735162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13985162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14015162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14035162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14125162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14375162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14405162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14425162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14515162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * register based on the results of the comparison. 1461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We load the full values with LDM, but in practice many values could 1463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be resolved by only looking at the high word. This could be made 1464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If we just wanted to set condition flags, we could do this: 1467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subs ip, r0, r2 1468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sbcs ip, r1, r3 1469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subeqs ip, r0, r2 1470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * us a constant 5-cycle path plus a branch at the end to the 1474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction epilogue code. The multi-compare approach below needs 1475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in the worst case (the 64-bit values are equal). 1477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* cmp-long vAA, vBB, vCC */ 1479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 1480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 1483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt .LOP_CMP_LONG_greater 1490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CMP_LONG_less 1493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQ: /* 0x32 */ 1498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_EQ.S */ 1499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NE: /* 0x33 */ 1534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_NE.S */ 1535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LT: /* 0x34 */ 1570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LT.S */ 1571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GE: /* 0x35 */ 1606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GE.S */ 1607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GT: /* 0x36 */ 1642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GT.S */ 1643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LE: /* 0x37 */ 1678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LE.S */ 1679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET: /* 0x44 */ 1990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 1991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 1993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 1996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 1998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aget-wide vAA, vBB, vCC */ 2028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT: /* 0x4b */ 2213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aput-wide vAA, vBB, vCC */ 2251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null array object? 2287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r9) @ r9<- vAA 2288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r3 @ compare unsigned index, length 2292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET: /* 0x52 */ 2431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET.S */ 2432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish @ no, already resolved 2446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish 2452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE.S */ 2458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Wide 32-bit instance field get. 2460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide vA, vB, field@CCCC */ 2462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish 2476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish 2503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish 2532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish 2561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish 2590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish 2619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT: /* 0x59 */ 2625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT.S */ 2626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ no, already resolved 2640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ yes, finish up 2646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE.S */ 2652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide vA, vB, field@CCCC */ 2653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET: /* 0x60 */ 2816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_finish: @ field ptr in r0 2830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SGET handler. 2843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sget-wide vAA, field@BBBB */ 2845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_finish: 2852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 2853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offStaticField_value] @ r2/r3<- field value (aligned) 2854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[AA] 2855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r1, {r2-r3} @ vAA/vAA+1<- r2/r3 2857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT: /* 0x67 */ 2993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 2994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 2996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 2998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_finish: @ field ptr in r0 3007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SPUT handler. 3020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sput-wide vAA, field@BBBB */ 3022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r0, AA in r9 3031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 3033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offStaticField_value] @ field<- vAA/vAA+1 3035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_finish: 3255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue on 3257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ yes, continue on 3277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue 3283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodNoRange @ jump to common handler 3313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue on 3419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ yes, continue on 3441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue 3447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodRange @ jump to common handler 3479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_INT: /* 0x7b */ 3503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_INT.S */ 3504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_INT: /* 0x7c */ 3529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_INT.S */ 3530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_LONG.S */ 3556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_LONG.S */ 3584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ optional op; may set condition codes 3600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_FLOAT.S */ 3612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_DOUBLE.S */ 3638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_LONG.S */ 3666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitos s1, s0 @ s1<- op 3707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitod d0, s0 @ d0<- op 3732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 3744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 3745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 3746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 3751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 3754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopNarrower.S */ 3762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 32-bit quantity in r0. 3766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: long-to-float, double-to-int, double-to-float 3768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (This would work for long-to-int, but that instruction is actually 3770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an exact match for OP_MOVE.) 3771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 3782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizs s1, s0 @ s1<- op 3833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtds d0, s0 @ d0<- op 3886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizd s0, d0 @ s0<- op 3911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtsd s0, d0 @ s0<- op 3966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_BYTE.S */ 3976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxtb r0, r0 @ r0<- op, r0-r3 changed 3992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_CHAR.S */ 4002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden uxth r0, r0 @ r0<- op, r0-r3 changed 4018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_SHORT.S */ 4028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxth r0, r0 @ r0<- op, r0-r3 changed 4044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT: /* 0x90 */ 4053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT.S */ 4054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT: /* 0x91 */ 4095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_INT.S */ 4096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT: /* 0x92 */ 4137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT.S */ 4138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT: /* 0x93 */ 4180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT.S */ 4181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT: /* 0x94 */ 4222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT.S */ 4223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 4257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT: /* 0x95 */ 4265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT.S */ 4266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT: /* 0x96 */ 4307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT.S */ 4308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT: /* 0x97 */ 4349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT.S */ 4350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT: /* 0x98 */ 4391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT.S */ 4392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT: /* 0x99 */ 4433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT.S */ 4434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT: /* 0x9a */ 4475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT.S */ 4476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply. 4610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WX 4613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * x YZ 4614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * -------- 4615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ZW ZX 4616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * YW YX 4617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The low word of the result holds ZX, the high word holds 4619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * it doesn't fit in the low 64 bits. 4621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most ARM math operations, multiply instructions have 4623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * restrictions on using the same register more than once (Rd and Rm 4624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * cannot be the same). 4625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long vAA, vBB, vCC */ 4627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 4635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_MUL_LONG_finish 4642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG: /* 0x9f */ 4691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_LONG.S */ 4692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_LONG.S */ 4738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 4771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_LONG.S */ 4783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long vAA, vBB, vCC */ 4880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_finish 4897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long vAA, vBB, vCC */ 4909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_finish 4926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long vAA, vBB, vCC */ 4938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_finish 4955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 4976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 4977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 4980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 4983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 4989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 4990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 5010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 5040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 5070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 5082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 5085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 5092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 5096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 5103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 5104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 5112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 5116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ s2<- op 5143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ s2<- op 5173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ s2<- op 5203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ s2<- op 5233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 5245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 5257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 5278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 5282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 5477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See OP_MUL_LONG for an explanation. 5806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * again we stuff it into rINST. 5809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long/2addr vA, vB */ 5811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 5818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 5944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 5985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 5986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 5997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 6038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long/2addr vA, vB */ 6043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_2ADDR_finish 6058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 6063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long/2addr vA, vB */ 6068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_2ADDR_finish 6083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long/2addr vA, vB */ 6093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_2ADDR_finish 6108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 6132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 6160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 6188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 6216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 6227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 6245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 6254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ d2<- op 6285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ d2<- op 6314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ d2<- op 6343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ d2<- op 6372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 6412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_RSUB_INT.S */ 6459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_LIT16.S */ 6569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_LIT16.S */ 6606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_LIT16.S */ 6642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 6988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 6989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 7016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E8: /* 0xe8 */ 7189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E8.S */ 7190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E9: /* 0xe9 */ 7198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E9.S */ 7199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EA: /* 0xea */ 7207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EA.S */ 7208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EB: /* 0xeb */ 7216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EB.S */ 7217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EC: /* 0xec */ 7225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EC.S */ 7226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a throw-verification-error instruction. This throws an 7237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception for an error discovered during verification. The 7238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op AA, ref@BBBB */ 7241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 7243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ export the PC 7244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowVerificationError @ always throws 7246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ handle exception 7247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Execute a "native inline" instruction. 7255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We need to call: 7257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * dvmPerformInlineOp4Std(arg0, arg1, arg2, arg3, &retval, ref) 7258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The first four args are in r0-r3, but the last two must be pushed 7260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * onto the stack. 7261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 1) @ r10<- BBBB 7264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ can throw 7266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #8 @ make room for arg(s) 7267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [sp] @ push &glue->retval 7269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ pop stack 7271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ test boolean result of inline 7272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ returned false, handle exception 7273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EF: /* 0xef */ 7280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EF.S */ 7281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_QUICK.S */ 7310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_QUICK.S */ 7370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 7391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 7392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ check object for null 7395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- field byte offset 7398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionEnd 7576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionEnd: 7577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 7579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Sister implementations 7581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterStart 7584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmSisterStart, %function 7585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 7586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 4 7587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterStart: 7588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING */ 7590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (String ref) 7594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_resolve: 7597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBBBBBB (String ref) 7614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_CLASS */ 7630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the Class has not yet been resolved. 7633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (Class ref) 7634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_CLASS_resolve: 7637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- Class reference 7642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CHECK_CAST */ 7651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_fullcheck: 7659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ class of the object that failed to be cast. 7665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ about to throw 7666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .LstrClassCastExceptionPtr 7668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowExceptionWithClassMessage 7670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds BBBB 7676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolve: 7679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- BBBB 7682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastExceptionPtr: 7692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrClassCastException 7693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INSTANCE_OF */ 7696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_fullcheck: 7704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_INSTANCE_OF_store 7706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds boolean result 7709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_store: 7712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test succeeded, save and bail. 7719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_trivial: 7722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ indicate success 7723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r3 holds BBBB 7733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolve: 7736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r3 @ r1<- BBBB 7739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 7746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_INSTANCE */ 7752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 32 @ minimize cache lines 7754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 7761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Class initialization required. 7765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class object 7767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_needinit: 7769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0 @ save r0 7770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInitClass @ initialize class 7771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ check boolean result 7772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ restore r0 7773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ failed, deal with init exception 7775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds BBBB 7780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolve: 7782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 7789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationErrorPtr: 7791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInstantiationError 7792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_ARRAY */ 7795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolve class. (This is an uncommon case.) 7799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds class ref CCCC 7802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_resolve: 7804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ r9<- length (save) 7806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- CCCC 7807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ r1<- length (restore) 7812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_NEW_ARRAY_finish 7814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Finish allocation. 7817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class 7819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_finish: 7822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 7829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ vA<- r0 7831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 7851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 7852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 7853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 7854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 7857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 7863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 7865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 7867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 7877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 7878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 7879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 7880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 7881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 7882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 7892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 7897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 7898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 7900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 7901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 7903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) @ define in one or the other, not both 7906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 7907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 7908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 7909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 7910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 7914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 7921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 7925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 7930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 7931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 7932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 7933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 7934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 7936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 7942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 7944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 7946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 7948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 7956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 7957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 7958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 7959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 7960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 7961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 7971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 7976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 7977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 7979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 7980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 7982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) @ define in one or the other, not both 7985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 7986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 7987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 7988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 7989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_FLOAT */ 7993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_FLOAT_finish: 7994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_FLOAT */ 7999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_FLOAT_finish: 8000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_DOUBLE */ 8005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_DOUBLE_finish: 8006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_DOUBLE */ 8011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_DOUBLE_finish: 8012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMP_LONG */ 8017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_less: 8019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, #0 @ r1<- -1 8020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ instead, we just replicate the tail end. 8022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_greater: 8028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ r1<- 1 8029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to _finish 8030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_finish: 8032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_AGET_WIDE */ 8039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_AGET_WIDE_finish: 8041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_WIDE */ 8050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_WIDE_finish: 8052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_OBJECT */ 8060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = vBB (arrayObj) 8063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = vAA (obj) 8064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = offset into array (vBB + vCC * width) 8065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_finish: 8067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ storing null reference? 8068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ okay? 8073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errArrayStore @ no 8074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_skip_check: 8075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET */ 8082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_finish: 8089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_WIDE */ 8102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_WIDE_finish: 8109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_OBJECT */ 8122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_OBJECT_finish: 8129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BOOLEAN */ 8143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BOOLEAN_finish: 8150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BYTE */ 8164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BYTE_finish: 8171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_CHAR */ 8185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_CHAR_finish: 8192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_SHORT */ 8206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_SHORT_finish: 8213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT */ 8227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_finish: 8234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r1, rINST, #8, #4 @ r1<- A 8237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_WIDE */ 8247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_WIDE_finish: 8254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_OBJECT */ 8267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_OBJECT_finish: 8274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BOOLEAN_finish: 8295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BYTE */ 8309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BYTE_finish: 8316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_CHAR */ 8330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_CHAR_finish: 8337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_SHORT */ 8351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_SHORT_finish: 8358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET */ 8372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_resolve: 8378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_finish @ yes, finish 8384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_WIDE */ 8388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_resolve: 8394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_OBJECT */ 8404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_resolve: 8410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BOOLEAN */ 8420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_resolve: 8426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BYTE */ 8436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_resolve: 8442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_CHAR */ 8452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_resolve: 8458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_SHORT */ 8468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_resolve: 8474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT */ 8484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_resolve: 8490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_finish @ yes, finish 8496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_WIDE */ 8500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: &fp[AA] 8505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_resolve: 8507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_OBJECT */ 8517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_resolve: 8523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_resolve: 8539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BYTE */ 8549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_resolve: 8555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_CHAR */ 8565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_resolve: 8571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_SHORT */ 8581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_resolve: 8587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_continue: 8604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER */ 8615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_continue: 8622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_resolve: 8633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_nsm: 8645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT */ 8650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_resolve: 8657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the float in r0 to a long in r0/r1. 8741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenf2l_doconv: 8747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, lr} 8748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0x5f000000 @ (float)maxlong 8749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r4, r0 8750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0xdf000000 @ (float)minlong 8758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (80000000) 8761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r4 8766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpeq @ is arg == self? 8767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmeqfd sp!, {r4, pc} 8770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_f2lz @ convert float to long 8773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, pc} 8774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddend2l_doconv: 8785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, r5, lr} @ save regs 87865162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 87875162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 87885162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align for EABI 87905162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r5, r1 @ and r1 8792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 88005162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 88015162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 88025162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (8000000000000000) 8806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r4 @ compare against self 8812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r5 8813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpeq @ is arg == self? 8814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f 8817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_d2lz @ convert double to long 8821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 8823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 8824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, r5, pc} 8825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_MUL_LONG */ 8828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_MUL_LONG_finish: 8830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG */ 8836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_finish: 8838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG */ 8845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_finish: 8847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG */ 8854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_finish: 8856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_2ADDR_finish: 8865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_2ADDR_finish: 8873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 8879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_2ADDR_finish: 8881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_EXECUTE_INLINE */ 8887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Extract args, call function. 8890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = #of args (0-4) 8891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = call index 8892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Other ideas: 8895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Use a jump table from the main piece to jump directly into the 8896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 8897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Have five separate pieces that do the loading, so we can work the 8898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interleave a little better. Increases code size. 8899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_continue: 8901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r9, 2) @ r9<- FEDC 8903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 8905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r9, #0xf000 @ isolate F 8906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 8907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r9, #0x0f00 @ isolate E 8908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 8909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r9, #0x00f0 @ isolate D 8910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 8911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r9, #0x000f @ isolate C 8912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 8913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: 8914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 8915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 8916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (not reached) 8917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_table: 8919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word gDvmInlineOpsTable 8920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 8923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterEnd 8924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterEnd: 8925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/footer.S */ 8927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 8930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common subroutines and data 8931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 8932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 8937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 8938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 894097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 894197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 894297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 894397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 894497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 894597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 894697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 894797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 894897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 894997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 895097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 895197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToTraceSelect 895297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToTraceSelect: 895397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr r0,[r14, #-1] @ pass our target PC 895497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 895597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 895697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 895797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToBackwardBranch 895897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToBackwardBranch: 895997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr r0,[r14, #-1] @ pass our target PC 896097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 896197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 896297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 896397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 896497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 896597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr r0,[r14, #-1] @ pass our target PC 896697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 896797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 896897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 896997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 897097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 897197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 897297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 897397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 897497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 8975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter when the compiler is 8977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * having issues translating/executing a Dalvik instruction. We have to skip 8978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the code cache lookup otherwise it is possible to indefinitely bouce 8979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * between the interpreter and the code cache if the instruction that fails 8980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to be compiled happens to be at a trace start. 8981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpPunt 8983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpPunt: 8984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r0 8985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 8986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,lr 8987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpPunt; 8988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 8989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 8990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 8991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 8992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 8993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 8994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return to the interpreter to handle a single instruction. 8997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 <= PC 8999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 <= PC of resume instruction 9000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr <= resume point in translation 9001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpSingleStep 9003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpSingleStep: 9004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str lr,[rGLUE,#offGlue_jitResume] 9005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1,[rGLUE,#offGlue_jitResumePC] 9006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#kInterpEntryInstr 9007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ enum is 4 byte in aapcs-EABI 9008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_entryPoint] 9009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC,r0 9010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitSingleStep @ Ask for single step and then revert 9013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp to bail to debug interp 9015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache and immediately request 9020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a translation for the exit target. Commonly used following 9021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invokes. 9022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToTraceSelect 9024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToTraceSelect: 9025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rPC,[r14, #-1] @ get our target PC 9026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST,r14,#-5 @ save start of chain branch 9027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 9029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 2f 9031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 9033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* No translation, so request one if profiling isn't disabled*/ 9038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 9039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 9043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_selectTrace 9044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter. 9049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The return was done with a BLX from thumb mode, and 9050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the following 32-bit word contains the target rPC value. 9051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note that lr (r14) will have its low-order bit set to denote 9052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * its thumb-mode origin. 9053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We'll need to stash our lr origin away, recover the new 9055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * target and then check to see if there is a translation available 9056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for our new target. If so, we do a translation chain and 9057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * go back to native execution. Otherwise, it's back to the 9058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter (after treating this entry as a potential 9059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace start). 9060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNormal 9062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNormal: 9063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rPC,[r14, #-1] @ get our target PC 9064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST,r14,#-5 @ save start of chain branch 9065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 9066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNormal 9067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 9070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq toInterpreter @ go if not, otherwise do chain 9072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 9074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter to do method invocation. 9080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check if translation exists for the callee, but don't chain to it. 9081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNoChain 9083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNoChain: 9084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 9085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNoChain 9086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 9089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution if so 909197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * No translation, restore interpreter regs and start interpreting. 9095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rGLUE & rFP were preserved in the translated code, and rPC has 9096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * already been restored by the time we get here. We'll need to set 9097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * up rIBASE & rINST, and load the address of the JitTable into r0. 9098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddentoInterpreter: 9100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ NOTE: intended fallthrough 9105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code to update potential trace start counter, and initiate 9107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a trace-build if appropriate. On entry, rPC should point to the 9108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * next instruction to execute, and rINST should be already loaded with 9109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the next opcode word, and r0 holds a pointer to the jit profile 9110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * table (pJitProfTable). 9111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_testUpdateProfile: 9113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_updateProfile: 9118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 911938329f5678fd7a4879528b02a0ab60322d38a897Ben Cheng lsl r3,r3,#23 @ shift out excess 511 912038329f5678fd7a4879528b02a0ab60322d38a897Ben Cheng ldrb r1,[r0,r3,lsr #23] @ get counter 9121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1,r1,#1 @ decrement counter 912338329f5678fd7a4879528b02a0ab60322d38a897Ben Cheng strb r1,[r0,r3,lsr #23] @ and store it 9124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Here, we switch to the debug interpreter to request 9128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace selection. First, though, check to see if there 9129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * is already a native translation in place (and, if so, 9130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * jump to it now). 9131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#255 913338329f5678fd7a4879528b02a0ab60322d38a897Ben Cheng strb r1,[r0,r3,lsr #23] @ reset counter 9134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 9137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_selectTrace 913997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ jump to the translation 914197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 914297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bne dvmJitSelfVerificationStart @ set up self verification 914397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_selectTrace: 9145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitTSelectRequest @ ask for trace selection 9146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 91479c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 91489c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp 9150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 915297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 915397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 915497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 915597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 915697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 915797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationStart: 915897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao sub sp,sp,#4 @ allocate stack space 915997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r0,[sp,#0] @ save out dvmJitGetCodeAddr(rPC) 916097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 916197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 916297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 916397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 916497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr rFP,[r0,#20] @ rFP<- fp in shadow space 916597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao add rGLUE,r0,#24 @ rGLUE<- pointer in shadow space 916697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr r0,[sp,#0] @ r0<- dvmJitGetCodeAddr(rPC) 916797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao add sp,sp,#4 @ restore stack 916897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bx r0 @ jump to the translation 916997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 917097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 917197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 917297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 917397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 917497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationEnd: 917597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 917697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 917797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr rPC,[r0,#0] @ restore PC 917897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr rFP,[r0,#4] @ restore FP 917997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr rGLUE,[r0,#8] @ restore InterpState 918097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao ldr r1,[r0,#12] @ get exitPoint 918197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 918297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 918397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 918497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 918530f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 918630f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 918797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 918897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 918997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 919097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 919197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 919297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 919397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 919497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 919597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 919697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 919797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code when a backward branch is taken. 9202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is PC adjustment *in bytes* 9205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_backwardBranch: 9207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryInstr 9208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * activity has begun. 9226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have to do the second ldr. 9229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: reduce this so we're just checking a single location. 9231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is trampoline PC adjustment *in bytes* 9235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_periodicChecks: 9237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 92399c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 92409c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 92419c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_PROFILER) 9246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined (WITH_PROFILER) 9255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ suspend pending? 9259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 2f @ yes, do full suspension check 9260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached or profiler started? 9265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_DEBUGGER) 9266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached? 9267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_PROFILER) 9268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ profiler started? 9269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# endif 9270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 3f @ debugger/profiler, switch interp 9271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr @ nothing to do, return 9274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: @ check suspend 9276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC 9278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: @ debugger/profiler enabled, bail out 9281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, rPC, r9 @ update rPC 9282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ "want switch" = true 9283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * State registers will be saved to the "glue" area before bailing. 9290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * other interpreter or just bail all the way out 9294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_gotoBail: 9296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ r0<- glue ptr 9298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r1, r1, #1 @ using (boolean+1) 9301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl _longjmp @ does not return 9303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_abort 9304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation with range. 9308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodRange: 9313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewRange: 9314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- CCCC 9319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r2, r2, #1 @ count-- 9327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r10], #4 @ *outs++ = val 9328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1b @ ...while count != 0 9329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LinvokeArgsDone 9331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation without range. 9334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodNoRange: 9339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewNoRange: 9340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone 9347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNonRange: 9350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vA 9357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r1, #0xf000 @ isolate G 9358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vG 9361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r1, #0x0f00 @ isolate F 9362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vF 9365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r1, #0x00f0 @ isolate E 9366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vE 9369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r1, #0x000f @ isolate D 9370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vD 9373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: @ fall through to .LinvokeArgsDone 9374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ find space for the new stack frame, check for overflow 9379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@ bl common_dumpRegs 9383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 9387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LstackOverflow @ yes, this frame will overflow stack 9388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ set up newSaveArea 9390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EASY_GDB 9391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offStackSaveArea_returnAddr] 9399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r10, #offStackSaveArea_method] 9401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden tst r3, #ACC_NATIVE 9402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LinvokeNative 9403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP 9408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 9413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 9414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r2 @ publish new rPC 9422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Update "glue" values for the new method 9425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNative: 9446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Prep for the native call 9447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9449d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9451d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ r2<- methodToCall 9455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ r0<- newFp (points to args) 9456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 9460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .Lskip 9461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_mterp, %function 9462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_mterp: 9463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 9464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 9465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 9466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lskip: 9467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @mov lr, pc @ set return addr 9470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ native return; r9=self, r10=newSaveArea 9474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ equivalent to dvmPopJniLocals 9475d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null? 9479d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ no, handle exception 9481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 94866ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 94876ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmHandleStackOverflow 9490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 9493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation, calling through "glue code". 9498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: now that we have range and non-range invoke handlers, this 9500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * needs to be split into two. Maybe just create entry points 9501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that set r9 and jump here? 9502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeOld: 9509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #8 @ space for args + pad 9510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ A2<- methodToCall 9512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ A0<- glue 9513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ A1<- methodCallRange 9515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #0] @ A4<- ip 9517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ remove arg area 9519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for handling a return instruction. 9526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_returnFromMethod: 9530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnNew: 9531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryReturn 9532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r2<- method we're returning to 9540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is this a break frame? 9542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 9544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_gotoBail @ break frame, bail out completely 9545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offStackSaveArea_returnAddr] @ r3 = saveArea->returnAddr 9552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ caller is compiled code 9556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blxne r3 9557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return handling, calls through "glue code". 9570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnOld: 9573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 9575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_returnFromMethod 9576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 9577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Somebody has thrown an exception. Handle it. 9582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If the exception processing code returns to us (instead of falling 9584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out of the interpreter), continue with whatever the next instruction 9585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * now happens to be. 9586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpCommonExceptionThrown 9590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpCommonExceptionThrown: 9591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_exceptionThrown: 9592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionNew: 9593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryThrow 9594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitTSelectAbort @ abandon trace selection in progress 9599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- NULL 9608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up args and a local for "&fp" */ 9611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov ip, sp @ ip<- &fp 9614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- false 9615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 9618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r9 @ r2<- exception 9620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 9629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ no, skip ahead 9630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r0 @ save relPc result in rFP 9631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 9632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCleanupStackOverflow @ call(self) 9633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP @ restore result 9634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 9635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is catchRelPc < 0? 9639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ restore stack 9640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi .LnotCaughtLocally 9641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* adjust locals to match self->curFrame and updated PC */ 9643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* release the tracked alloc on the exception */ 9653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* restore the exception if the handler wants it */ 9658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 9659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 9661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 9662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 9665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix stack overflow if necessary */ 9666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 9668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, r10 @ if yes: r0<- self 9669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 9670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ may want to show "not caught locally" debug messages here 9672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if DVM_SHOW_EXCEPTION >= 2 9673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call __android_log_print(prio, tag, format, ...) */ 9674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* "Exception %s from %s:%d not caught locally" */ 9675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 9676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 9677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_insns] 9678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 9679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden asr r1, r1, #1 9680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLineNumFromPC 9681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 9682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmGetMethodSourceFile(method) 9683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 9684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmGetMethodSourceFile 9685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 9686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ exception->clazz->descriptor 9687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] 9688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_descriptor] 9689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ 9690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, strExceptionNotCaughtLocally 9691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strLogTag 9692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #3 @ LOG_DEBUG 9693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __android_log_print 9694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offThread_exception] @ restore exception 9696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 9700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail @ bail out 9701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exception handling, calls through "glue code". 9705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionOld: 9708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 9710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_exceptionThrown 9711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 9712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * After returning from a "glued" function, pull out the updated 9717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * values and start executing at the next instruction. 9718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_resumeAfterGlueCall: 9720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 9721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 9722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array index. 9727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayIndex: 9729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayIndexException 9731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array value. 9737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayStore: 9739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayStoreException 9741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Integer divide or mod by zero. 9747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errDivideByZero: 9749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArithmeticException 9751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strDivideByZero 9752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Attempt to allocate an array with a negative size. 9757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNegativeArraySize: 9759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNegativeArraySizeException 9761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invocation of a non-existent method. 9767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNoSuchMethod: 9769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNoSuchMethodError 9771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We encountered a null object when we weren't expecting one. We 9777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * export the PC, throw a NullPointerException, and goto the exception 9778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * processing code. 9779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNullObject: 9781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNullPointerException 9783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For debugging, cause an immediate fault. The source address will 9789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be in lr (use a bl instruction to jump here). 9790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_abort: 9792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, .LdeadFood 9793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdeadFood: 9794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word 0xdeadf00d 9795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out a "we were here", preserving all registers. (The attempt 9798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to save ip won't work, but we need to save an even number of 9799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * registers for EABI 64-bit stack alignment.) 9800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .macro SQUEAK num 9802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_squeak\num: 9803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 9805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #\num 9806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endm 9810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 0 9812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 1 9813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 2 9814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 3 9815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 4 9816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 5 9817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out the number in r0, preserving registers. 9820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNum: 9822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 9824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 9825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print a newline, preserving registers. 9831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNewline: 9833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNewline 9835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 9841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printHex: 9843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 9845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintHex 9846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 9852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printLong: 9854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r1 9856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 9857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintLong 9858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 9864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printMethod: 9866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpPrintMethod 9868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Call a C helper function that dumps regs and possibly some 9873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * additional info. Requires the C function to be compiled in. 9874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_dumpRegs: 9877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpDumpArmRegs 9879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if 0 9884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Experiment on VFP mode. 9886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 9888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 9890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddensetFPSCR: 9892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ make sure no stray bits are set 9893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmrx r2, fpscr @ get VFP reg 9894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ bit-invert mask 9895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, r1 @ clear masked bits 9896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r2, r2, r0 @ set specified bits 9897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmxr fpscr, r2 @ set VFP reg 9898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r2 @ return new value 9899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 9902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmConfigureFP 9903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmConfigureFP, %function 9904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmConfigureFP: 9905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {ip, lr} 9906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x03000000 sets DN/FZ */ 9907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x00009f00 clears the six exception enable flags */ 9908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_squeak0 9909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 9910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 9911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl setFPSCR 9912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {ip, pc} 9913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references, must be close to the code that uses them. 9918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 9920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArithmeticException: 9921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArithmeticException 9922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayIndexException: 9923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayIndexException 9924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayStoreException: 9925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayStoreException 9926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrDivideByZero: 9927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrDivideByZero 9928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNegativeArraySizeException: 9929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNegativeArraySizeException 9930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNoSuchMethodError: 9931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNoSuchMethodError 9932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNullPointerException: 9933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNullPointerException 9934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrLogTag: 9936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrLogTag 9937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrExceptionNotCaughtLocally: 9938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrExceptionNotCaughtLocally 9939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNewline: 9941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNewline 9942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrSqueak: 9943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrSqueak 9944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintHex: 9945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintHex 9946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintLong: 9947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintLong 9948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Zero-terminated ASCII string data. 9951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 9953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with the address, or use an ADR pseudo-op to get the address 9954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * directly. 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