InterpAsm-armv7-a.S revision 7a44e4ee0782d24b4c6090be1f0a3c66f971f2c1
1a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 2a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * --> DO NOT EDIT <-- 5a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/header.S */ 8a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 10a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 11a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 13a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 14a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 15a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 17a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 18a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 21a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 22a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 23a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 24a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ARMv5 definitions and declarations. 25a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 26a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 27a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 28a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenARM EABI general notes: 29a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 30a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr4-r8 are available for general use 32a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr9 is given special treatment in some situations, but not for us 33a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr10 (sl) seems to be generally available 34a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr14 (lr) must be preserved 38a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr15 (pc) can be tinkered with directly 39a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 40a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0 holds returns of <= 4 bytes 41a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 43a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 47a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden(i.e. the 5th arg). 50a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 51a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 53a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 56a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 57a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 58a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMterp and ARM notes: 59a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 60a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenThe following registers have fixed assignments: 61a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 62a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden reg nick purpose 63a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r6 rGLUE MterpGlue pointer 66a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r7 rINST first 16-bit code unit of current instruction 67a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 69a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenunspecified registers or condition codes. 72a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 73a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 74a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* single-purpose registers, given names for clarity */ 75a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rPC r4 76a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rFP r5 77a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rGLUE r6 78a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rINST r7 79a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rIBASE r8 80a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 81a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 89a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 90a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be done *before* something calls dvmThrowException. 92a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 93a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 96a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * It's okay to do this more than once. 97a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 98a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define EXPORT_PC() \ 99a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Given a frame pointer, find the stack save area. 103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with this). 121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This must come AFTER anything that can throw an exception, or the 123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception catch may miss. (This also implies that it must come after 124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * EXPORT_PC().) 125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * here. 144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The "_S" variant works the same but treats the value as signed. 152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * byte of the halfword you want (lo/hi). 160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the instruction's opcode field into the specified register. 165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Get/set the 32-bit value from a Dalvik register. 183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 189d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert a virtual register index into an address. 194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add _reg, rFP, _vreg, lsl #2 197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to expand the macros into assembler assignment statements. 201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#include "../common/asm-constants.h" 203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2047b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#if defined(WITH_JIT) 2057b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#include "../common/jit-config.h" 2067b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng#endif 207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/platform.S */ 209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * CPU-version-specific defines 212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * one-way branch. 218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP. Does not modify LR. 220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC source 222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Jump to subroutine. 228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC_LR source 232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov lr, pc 233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDMFD_PC regs 242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {\regs,pc} 243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/entry.S */ 247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Interpreter entry point. 264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't have formal stack frames, so gdb scans upward in the code 268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to find the start of the function (a label with the %function type), 269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and then looks at the next few instructions to figure out what 270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * got pushed onto the stack. From this it figures out how to restore 271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the registers, including PC, for the previous stack frame. If gdb 272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sees a non-function label, it stops scanning, so either we need to 273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have nothing but assembler-local labels between the entry point and 274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the break, or we need to fake it out. 275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * When this is defined, we add some stuff to make gdb less confused. 277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define ASSIST_DEBUGGER 1 279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdRun 283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdRun, %function 284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This function returns a boolean "changeInterp" value. The return comes 290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * via a call to dvmMterpStdBail(). 291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdRun: 293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY1 \ 294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .save {r4-r10,fp,lr}; \ 295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY2 \ 297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .pad #4; \ 298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align 64 299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* save stack pointer, add magic word for debuggerd */ 305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up "named" registers, figure out entry point */ 308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rGLUE, r0 @ set rGLUE 30951ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee ldr r1, [r0, #offGlue_entryPoint] @ enum is 4 bytes in aapcs-EABI 310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryInstr @ usual case? 313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lnot_instr @ no, handle it 314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 316d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng.LentryInstr: 3177a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* Entry is always a possible trace start */ 319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 3217a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, #0 @ prepare the value for the new state 3227a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* start executing the instruction at rPC */ 329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_instr: 335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_returnFromMethod 337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_return: 339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown 341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_throw: 344d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10,[rGLUE, #offGlue_jitResumeNPC] 345d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r2,[rGLUE, #offGlue_jitResumeDPC] 346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lbad_arg 348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp rPC,r2 349d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne .LentryInstr @ must have branched, don't resume 350d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#if defined(WITH_SELF_VERIFICATION) 351d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ glue->entryPoint will be set in dvmSelfVerificationSaveState 352d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunStart @ re-enter the translation after the 353d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @ single-stepped instruction 354d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng @noreturn 355d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng#endif 356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #kInterpEntryInstr 35751ae442fa9ed49e081e58e5127d1805789dbb196Bill Buzbee str r1, [rGLUE, #offGlue_entryPoint] 358d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bx r10 @ re-enter the translation 359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lbad_arg: 362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strBadEntryPoint 363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r1 holds value of entryPoint 364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAbort 366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdBail 370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdBail, %function 371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Restore the stack pointer and PC from the save point established on entry. 374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * LR to PC. 380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 bool changeInterp 384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdBail: 386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ return the changeInterp value 388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 @ un-align 64 389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references. 394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrBadEntryPoint: 396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrBadEntryPoint 397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionStart 401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmInstructionStart, %function 402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionStart = .L_OP_NOP 403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOP: /* 0x00 */ 408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NOP.S */ 409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_inst, %function 416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_inst: 417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE: /* 0x01 */ 427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE.S */ 428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_16: /* 0x03 */ 457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE_WIDE.S */ 473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide vA, vB */ 474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/from16 vAA, vBBBB */ 491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- BBBB 493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/16 vAAAA, vBBBB */ 508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- BBBB 510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- AAAA 511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-result-wide vAA */ 591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-exception vAA */ 622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ r1<- 0 626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN: /* 0x0f */ 643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 64-bit value. Copies the return value into the "glue" 663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* return-wide vAA */ 666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_4: /* 0x12 */ 696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_CONST_4.S */ 697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/4 vA, #+B */ 698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_16: /* 0x13 */ 710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_16.S */ 711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/16 vAA, #+BBBB */ 712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST: /* 0x14 */ 723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST.S */ 724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const vAA, #+BBBBbbbb */ 725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/high16 vAA, #+BBBB0000 */ 740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/16 vAA, #+BBBB */ 754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0 @ r0<- 00000000 808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING: /* 0x1a */ 819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING.S */ 820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBB */ 821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_resolve 828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBBBBBB */ 838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/class vAA, Class@BBBB */ 857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_CLASS_resolve 864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Synchronize on an object. 875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-enter vAA */ 877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null object, throw an exception 883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLockObject @ call(self, obj) 885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ exception raised, bail out 890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlock an object. 901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exceptions that occur when unlocking a monitor need to appear as 903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if they happened at the following instruction. See the Dalvik 904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction spec. 905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-exit vAA */ 907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ before fetch: export the PC 909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 9116bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq 1f @ yes 912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 9166bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee beq common_exceptionThrown @ yes, exception is pending 917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9196bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee1: 9206bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee FETCH_ADVANCE_INST(1) @ advance before throw 9216bbdd6b005ec5cb567ec9576190a7cd784248c5cBill Buzbee b common_errNullObject 922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if a cast from one class to another is allowed. 930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* check-cast vAA, class@BBBB */ 932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r3) @ r9<- object 935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ is object null? 937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolved: 944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_okay: 947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if an object reference is an instance of a class. 957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Most common situation is a non-null object, being compared against 959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an already-resolved class. 960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* instance-of vA, vB, class@CCCC */ 962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- CCCC 970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ARRAY_LENGTH.S */ 984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return the length of an array. 986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yup, fail 992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ vB<- length 996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 1002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 1003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new instance of a class. 1005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-instance vAA, class@BBBB */ 1007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocObject @ r0<- new object 1021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Allocate an array of objects, specified with the array class 1029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and a count. 1030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The verifier guarantees that this is an array class, so we don't 1032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * check for it here. 1033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-array vA, vB, class@CCCC */ 1035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 1036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- CCCC 1037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ check length 1041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_errNegativeArraySize @ negative length, bail 1043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for resolve, alloc 1045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC(); 1116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ 0 means an exception is thrown 1118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ has exception 1119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW: /* 0x27 */ 1126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW.S */ 1127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception object in the current thread. 1129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* throw vAA */ 1131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 1135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, throw an NPE instead 1136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ bypass dvmSetException, just store it 1137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 1139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO: /* 0x28 */ 1144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO.S */ 1145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 8-bit offset. 1147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto +AA */ 1152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_16: /* 0x29 */ 1172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_16.S */ 1173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 16-bit offset. 1175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/16 +AAAA */ 1180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_32: /* 0x2a */ 1200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_32.S */ 1201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 32-bit offset. 1203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction doesn't affect the V flag, so we need to clear it 1210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * explicitly. 1211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/32 +AAAAAAAA */ 1213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, ip @ (clear V flag during stall) 1216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13325162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13355162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13375162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13465162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13715162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13745162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13765162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13855162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14105162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14135162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14155162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14245162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14495162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14525162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14545162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14635162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * register based on the results of the comparison. 1473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We load the full values with LDM, but in practice many values could 1475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be resolved by only looking at the high word. This could be made 1476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If we just wanted to set condition flags, we could do this: 1479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subs ip, r0, r2 1480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sbcs ip, r1, r3 1481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subeqs ip, r0, r2 1482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * us a constant 5-cycle path plus a branch at the end to the 1486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction epilogue code. The multi-compare approach below needs 1487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in the worst case (the 64-bit values are equal). 1489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* cmp-long vAA, vBB, vCC */ 1491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 1492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 1495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt .LOP_CMP_LONG_greater 1502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CMP_LONG_less 1505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQ: /* 0x32 */ 1510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_EQ.S */ 1511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NE: /* 0x33 */ 1546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_NE.S */ 1547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LT: /* 0x34 */ 1582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LT.S */ 1583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GE: /* 0x35 */ 1618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GE.S */ 1619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GT: /* 0x36 */ 1654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GT.S */ 1655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LE: /* 0x37 */ 1690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LE.S */ 1691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET: /* 0x44 */ 2002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aget-wide vAA, vBB, vCC */ 2040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT: /* 0x4b */ 2225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aput-wide vAA, vBB, vCC */ 2263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null array object? 2299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r9) @ r9<- vAA 2300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r3 @ compare unsigned index, length 2304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET: /* 0x52 */ 2443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET.S */ 2444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish @ no, already resolved 2458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish 2464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE.S */ 2470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Wide 32-bit instance field get. 2472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide vA, vB, field@CCCC */ 2474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish 2488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish 2515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish 2544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish 2573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish 2602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish 2631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT: /* 0x59 */ 2637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT.S */ 2638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ no, already resolved 2652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ yes, finish up 2658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE.S */ 2664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide vA, vB, field@CCCC */ 2665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET: /* 0x60 */ 2828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_finish: @ field ptr in r0 2842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SGET handler. 2855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sget-wide vAA, field@BBBB */ 2857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_finish: 2864861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2865861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 2866861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 2867861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_read_64 @ r0/r1<- contents of field 2868861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 2869861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 2870861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 2871861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2873861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 2874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 3000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 3003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT: /* 0x67 */ 3010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_finish: @ field ptr in r0 3024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SPUT handler. 3037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sput-wide vAA, field@BBBB */ 3039861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 3040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3041861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 3042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3043861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 3044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3045861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 3046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3047861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r2, AA in r9 3048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3049861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 3050861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 3051861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 0 3052861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 3053861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2 3054861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 3055861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 3056861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 3057861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 3058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_finish: 3277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue on 3279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ yes, continue on 3299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue 3305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodNoRange @ jump to common handler 3335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue on 3441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ yes, continue on 3463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue 3469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodRange @ jump to common handler 3501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_INT: /* 0x7b */ 3525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_INT.S */ 3526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_INT: /* 0x7c */ 3551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_INT.S */ 3552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_LONG.S */ 3578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_LONG.S */ 3606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ optional op; may set condition codes 3622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_FLOAT.S */ 3634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_DOUBLE.S */ 3660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_LONG.S */ 3688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitos s1, s0 @ s1<- op 3729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitod d0, s0 @ d0<- op 3754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 3766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 3767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 3768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 3773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 3776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopNarrower.S */ 3784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 32-bit quantity in r0. 3788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: long-to-float, double-to-int, double-to-float 3790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (This would work for long-to-int, but that instruction is actually 3792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an exact match for OP_MOVE.) 3793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 3804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizs s1, s0 @ s1<- op 3855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtds d0, s0 @ d0<- op 3908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizd s0, d0 @ s0<- op 3933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtsd s0, d0 @ s0<- op 3988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_BYTE.S */ 3998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxtb r0, r0 @ r0<- op, r0-r3 changed 4014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_CHAR.S */ 4024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden uxth r0, r0 @ r0<- op, r0-r3 changed 4040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_SHORT.S */ 4050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxth r0, r0 @ r0<- op, r0-r3 changed 4066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT: /* 0x90 */ 4075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT.S */ 4076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT: /* 0x91 */ 4117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_INT.S */ 4118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT: /* 0x92 */ 4159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT.S */ 4160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT: /* 0x93 */ 4202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT.S */ 4203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT: /* 0x94 */ 4244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT.S */ 4245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 4279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT: /* 0x95 */ 4287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT.S */ 4288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT: /* 0x96 */ 4329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT.S */ 4330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT: /* 0x97 */ 4371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT.S */ 4372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT: /* 0x98 */ 4413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT.S */ 4414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT: /* 0x99 */ 4455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT.S */ 4456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT: /* 0x9a */ 4497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT.S */ 4498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply. 4632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WX 4635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * x YZ 4636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * -------- 4637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ZW ZX 4638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * YW YX 4639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The low word of the result holds ZX, the high word holds 4641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * it doesn't fit in the low 64 bits. 4643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most ARM math operations, multiply instructions have 4645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * restrictions on using the same register more than once (Rd and Rm 4646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * cannot be the same). 4647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long vAA, vBB, vCC */ 4649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 4657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_MUL_LONG_finish 4664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG: /* 0x9f */ 4713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_LONG.S */ 4714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_LONG.S */ 4760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 4793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_LONG.S */ 4805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long vAA, vBB, vCC */ 4902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_finish 4919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long vAA, vBB, vCC */ 4931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_finish 4948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long vAA, vBB, vCC */ 4960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_finish 4977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 4998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 4999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 5002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 5011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 5012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 5032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 5062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 5092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 5104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 5107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 5114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 5118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 5125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 5126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 5134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 5138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ s2<- op 5165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ s2<- op 5195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ s2<- op 5225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ s2<- op 5255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 5267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 5279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 5300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 5304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 5499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See OP_MUL_LONG for an explanation. 5828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * again we stuff it into rINST. 5831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long/2addr vA, vB */ 5833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 5840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 5966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 6007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 6008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 6018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 6019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 6060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long/2addr vA, vB */ 6065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_2ADDR_finish 6080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 6085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long/2addr vA, vB */ 6090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_2ADDR_finish 6105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long/2addr vA, vB */ 6115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_2ADDR_finish 6130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 6154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 6182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 6210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 6238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 6249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 6267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 6276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ d2<- op 6307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ d2<- op 6336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ d2<- op 6365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ d2<- op 6394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 6434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_RSUB_INT.S */ 6481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_LIT16.S */ 6591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_LIT16.S */ 6628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_LIT16.S */ 6664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 7000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 7010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 7011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 7038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IGET_WIDE_VOLATILE: /* 0xe8 */ 72115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE_VOLATILE.S */ 72125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IGET_WIDE.S */ 72135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Wide 32-bit instance field get. 72155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iget-wide vA, vB, field@CCCC */ 72175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72195387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72205387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72215387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72225387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72235387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72245387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish @ no, already resolved 72255387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72265387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72275387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72285387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72295387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 72305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IGET_WIDE_VOLATILE_finish 72315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_IPUT_WIDE_VOLATILE: /* 0xe9 */ 72375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE_VOLATILE.S */ 72385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_IPUT_WIDE.S */ 72395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* iput-wide vA, vB, field@CCCC */ 72405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 72415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 72425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 72435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 72445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 72455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 72465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ no, already resolved 72485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 72495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw 72505387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 72515387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 72525387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 72535387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_IPUT_WIDE_VOLATILE_finish @ yes, finish up 72545387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown 7255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SGET_WIDE_VOLATILE: /* 0xea */ 72605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE_VOLATILE.S */ 72615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 72625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SGET handler. 72645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72655387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sget-wide vAA, field@BBBB */ 72665387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 72675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 72685387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 72695387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 72705387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ is resolved entry null? 72715387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SGET_WIDE_VOLATILE_resolve @ yes, do resolve 72725387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_finish: 7273861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7274861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7275861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r0, #offStaticField_value @ r0<- pointer to data 7276861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_read_64 @ r0/r1<- contents of field 7277861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7278861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldrd r0, [r0, #offStaticField_value] @ r0/r1<- field value (aligned) 7279861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7280861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 72815387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7282861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 72835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 72845387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 72895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.L_OP_SPUT_WIDE_VOLATILE: /* 0xeb */ 72905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE_VOLATILE.S */ 72915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 72925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 72935387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * 64-bit SPUT handler. 72945387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 72955387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* sput-wide vAA, field@BBBB */ 7296861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- DvmDex 72975387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 7298861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r0, [r0, #offDvmDex_pResFields] @ r0<- dvmDex->pResFields 72995387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7300861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldr r2, [r0, r1, lsl #2] @ r2<- resolved StaticField ptr 73015387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 7302861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden cmp r2, #0 @ is resolved entry null? 73035387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq .LOP_SPUT_WIDE_VOLATILE_resolve @ yes, do resolve 7304861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden.LOP_SPUT_WIDE_VOLATILE_finish: @ field ptr in r2, AA in r9 73055387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7306861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 7307861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 7308861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 7309861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r2, #offStaticField_value @ r2<- pointer to data 7310861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2 7311861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 7312861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r2, #offStaticField_value] @ field<- vAA/vAA+1 7313861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 7314861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 7315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 731996516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 732096516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a throw-verification-error instruction. This throws an 7332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception for an error discovered during verification. The 7333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op AA, ref@BBBB */ 7336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 7338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ export the PC 7339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowVerificationError @ always throws 7341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ handle exception 7342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Execute a "native inline" instruction. 7350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7351b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7352b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7354b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7355b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7356b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 1) @ r10<- BBBB 7360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ can throw 7362b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [sp] @ push &glue->retval 7365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ pop stack 7367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ test boolean result of inline 7368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ returned false, handle exception 7369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7375b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7376b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7377b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7378b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7379b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7380b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7381b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7382b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7383b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7384b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7385b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7386b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7387b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7388b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7389b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7390b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7391b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7392b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7393b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7394b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7395b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7396b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7397b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7398b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7399b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7400b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7401b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_QUICK.S */ 7427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_QUICK.S */ 7487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 7508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 7509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ check object for null 7512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- field byte offset 7515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionEnd 7693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionEnd: 7694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 7696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Sister implementations 7698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterStart 7701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmSisterStart, %function 7702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 7703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 4 7704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterStart: 7705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING */ 7707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (String ref) 7711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_resolve: 7714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBBBBBB (String ref) 7731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_CLASS */ 7747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the Class has not yet been resolved. 7750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (Class ref) 7751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_CLASS_resolve: 7754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- Class reference 7759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CHECK_CAST */ 7768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_fullcheck: 7776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ class of the object that failed to be cast. 7782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ about to throw 7783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .LstrClassCastExceptionPtr 7785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowExceptionWithClassMessage 7787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds BBBB 7793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolve: 7796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- BBBB 7799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastExceptionPtr: 7809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrClassCastException 7810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INSTANCE_OF */ 7813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_fullcheck: 7821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_INSTANCE_OF_store 7823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds boolean result 7826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_store: 7829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test succeeded, save and bail. 7836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_trivial: 7839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ indicate success 7840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r3 holds BBBB 7850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolve: 7853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r3 @ r1<- BBBB 7856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 7863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_INSTANCE */ 7869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 32 @ minimize cache lines 7871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 7878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Class initialization required. 7882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class object 7884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_needinit: 7886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0 @ save r0 7887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInitClass @ initialize class 7888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ check boolean result 7889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ restore r0 7890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ failed, deal with init exception 7892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds BBBB 7897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolve: 7899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 7906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationErrorPtr: 7908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInstantiationError 7909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_ARRAY */ 7912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolve class. (This is an uncommon case.) 7916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds class ref CCCC 7919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_resolve: 7921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ r9<- length (save) 7923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- CCCC 7924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ r1<- length (restore) 7929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_NEW_ARRAY_finish 7931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Finish allocation. 7934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class 7936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_finish: 7939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 7946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ vA<- r0 7948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 7968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 7969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 7970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 7971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 7974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 7980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 7982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 7984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 7994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 7995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 7996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 7997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 7998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 7999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 8009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 8011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 8014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 8015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 8017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 8018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 8020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 8021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) @ define in one or the other, not both 8023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 8024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 8025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 8026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 8027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 8031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 8035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 8036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 8038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 8039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 8040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 8041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 8042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 8043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 8044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 8045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 8047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 8048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 8049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 8050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 8051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 8052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 8053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 8054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 8056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 8057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 8058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 8059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 8060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 8061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 8063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 8064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 8065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 8066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 8067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 8072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 8073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 8074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 8075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 8076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 8077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 8078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 8079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 8080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 8081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 8082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 8083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 8084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 8085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 8088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 8089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 8090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 8093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 8094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 8097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 8099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 8100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) @ define in one or the other, not both 8102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 8103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 8104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 8105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 8106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_FLOAT */ 8110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_FLOAT_finish: 8111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_FLOAT */ 8116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_FLOAT_finish: 8117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_DOUBLE */ 8122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_DOUBLE_finish: 8123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_DOUBLE */ 8128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_DOUBLE_finish: 8129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMP_LONG */ 8134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_less: 8136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, #0 @ r1<- -1 8137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ instead, we just replicate the tail end. 8139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_greater: 8145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ r1<- 1 8146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to _finish 8147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_finish: 8149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_AGET_WIDE */ 8156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_AGET_WIDE_finish: 8158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_WIDE */ 8167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_WIDE_finish: 8169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_OBJECT */ 8177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = vBB (arrayObj) 8180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = vAA (obj) 8181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = offset into array (vBB + vCC * width) 8182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_finish: 8184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ storing null reference? 8185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ okay? 8190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errArrayStore @ no 8191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_skip_check: 8192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET */ 8199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_finish: 8206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_WIDE */ 8219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_WIDE_finish: 8226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_OBJECT */ 8239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_OBJECT_finish: 8246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BOOLEAN */ 8260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BOOLEAN_finish: 8267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BYTE */ 8281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BYTE_finish: 8288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_CHAR */ 8302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_CHAR_finish: 8309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_SHORT */ 8323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_SHORT_finish: 8330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT */ 8344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_finish: 8351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r1, rINST, #8, #4 @ r1<- A 8354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_WIDE */ 8364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_WIDE_finish: 8371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_OBJECT */ 8384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_OBJECT_finish: 8391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BOOLEAN_finish: 8412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BYTE */ 8426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BYTE_finish: 8433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_CHAR */ 8447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_CHAR_finish: 8454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_SHORT */ 8468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_SHORT_finish: 8475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET */ 8489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_resolve: 8495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_finish @ yes, finish 8501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_WIDE */ 8505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8509861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8510861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 8511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_resolve: 8513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_OBJECT */ 8523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_resolve: 8529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BOOLEAN */ 8539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_resolve: 8545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BYTE */ 8555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_resolve: 8561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_CHAR */ 8571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_resolve: 8577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_SHORT */ 8587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_resolve: 8593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT */ 8603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_resolve: 8609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_finish @ yes, finish 8615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_WIDE */ 8619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: &fp[AA] 8624861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 8625861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 8626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_resolve: 8628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8633861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 8634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_OBJECT */ 8639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_resolve: 8645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_resolve: 8661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BYTE */ 8671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_resolve: 8677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_CHAR */ 8687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_resolve: 8693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_SHORT */ 8703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_resolve: 8709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_continue: 8726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER */ 8737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_continue: 8744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_resolve: 8755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_nsm: 8767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT */ 8772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_resolve: 8779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the float in r0 to a long in r0/r1. 8863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenf2l_doconv: 8869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, lr} 8870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0x5f000000 @ (float)maxlong 8871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r4, r0 8872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0xdf000000 @ (float)minlong 8880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (80000000) 8883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r4 8888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpeq @ is arg == self? 8889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmeqfd sp!, {r4, pc} 8892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_f2lz @ convert float to long 8895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, pc} 8896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddend2l_doconv: 8907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, r5, lr} @ save regs 89085162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 89095162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 89105162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align for EABI 89125162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r5, r1 @ and r1 8914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 89225162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 89235162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 89245162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (8000000000000000) 8928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r4 @ compare against self 8934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r5 8935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpeq @ is arg == self? 8936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f 8939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_d2lz @ convert double to long 8943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 8945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 8946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, r5, pc} 8947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_MUL_LONG */ 8950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_MUL_LONG_finish: 8952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG */ 8958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_finish: 8960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG */ 8967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_finish: 8969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG */ 8976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_finish: 8978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_2ADDR_finish: 8987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_2ADDR_finish: 8995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 9001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_2ADDR_finish: 9003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 9005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 90085387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IGET_WIDE_VOLATILE */ 90095387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90105387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 90115387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 90125387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 90135387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 90145387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 90155387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IGET_WIDE_VOLATILE_finish: 90165387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 90175387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 90185387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 9019861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 9020861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r0, r9, r3 @ r0<- address of field 9021861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_read_64 @ r0/r1<- contents of field 9022861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 90235387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 9024861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9025861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 90265387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 9027861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden and r2, r2, #15 @ r2<- A 90285387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 90295387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 90305387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 90315387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 90325387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90335387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90345387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_IPUT_WIDE_VOLATILE */ 90355387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90365387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 90375387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Currently: 90385387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r0 holds resolved field 90395387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9 holds object 90405387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 90415387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_IPUT_WIDE_VOLATILE_finish: 90425387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 90435387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r9, #0 @ check object for null 90445387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden and r2, r2, #15 @ r2<- A 90455387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 90465387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 90475387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden beq common_errNullObject @ object was null 90485387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 90495387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 9050861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GET_INST_OPCODE(r10) @ extract opcode from rINST 9051861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .if 1 9052861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden add r2, r9, r3 @ r2<- target address 9053861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden bl android_quasiatomic_swap_64 @ stores r0/r1 into addr r2 9054861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .else 9055861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0/r1 9056861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden .endif 9057861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden GOTO_OPCODE(r10) @ jump to next instruction 90585387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90595387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90605387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SGET_WIDE_VOLATILE */ 90615387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90625387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 90635387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 90645387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 9065861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9066861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r0. 90675387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 90685387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SGET_WIDE_VOLATILE_resolve: 90695387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 90705387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 90715387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 90725387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 90735387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 90745387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SGET_WIDE_VOLATILE_finish @ yes, finish 90755387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 90765387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90775387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90785387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden/* continuation for OP_SPUT_WIDE_VOLATILE */ 90795387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90805387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden /* 90815387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * Continuation if the field has not yet been resolved. 90825387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r1: BBBB field ref 90835387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden * r9: &fp[AA] 9084861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * 9085861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden * Returns StaticField pointer in r2. 90865387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden */ 90875387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden.LOP_SPUT_WIDE_VOLATILE_resolve: 90885387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 90895387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 90905387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 90915387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 90925387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden cmp r0, #0 @ success? 9093861b33855aff080278ea5125e4372a2d4bf8aef5Andy McFadden mov r2, r0 @ copy to r2 90945387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden bne .LOP_SPUT_WIDE_VOLATILE_finish @ yes, finish 90955387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden b common_exceptionThrown @ no, handle exception 90965387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 90975387824f19033ed51a945fbc8c2b574998404b3dAndy McFadden 9098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_EXECUTE_INLINE */ 9099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Extract args, call function. 9102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = #of args (0-4) 9103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = call index 9104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Other ideas: 9107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Use a jump table from the main piece to jump directly into the 9108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 9109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Have five separate pieces that do the loading, so we can work the 9110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interleave a little better. Increases code size. 9111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_continue: 9113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r9, 2) @ r9<- FEDC 9115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r9, #0xf000 @ isolate F 9118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 9119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r9, #0x0f00 @ isolate E 9120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 9121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r9, #0x00f0 @ isolate D 9122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 9123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r9, #0x000f @ isolate C 9124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 9125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: 9126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 9127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (not reached) 9129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_table: 9131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word gDvmInlineOpsTable 9132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9134b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 9135b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9136b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 9137b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 9138b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 9139b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 9140b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 9141b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 9142b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 9143b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 9144b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 9145b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 9146b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 9147b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 9148b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 9149b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 9150b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 9151b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 9152b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 9153b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 9154b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 9155b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 9156b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 9157b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 9158b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 9159b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9160b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 9161b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 9162b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9163b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 9164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 9165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterEnd 9166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterEnd: 9167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/footer.S */ 9169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 9172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common subroutines and data 9173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 9174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 9179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 9180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 918297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 918397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 918497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 9185d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 918697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 9187d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9188d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9189d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 919097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 919197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 919297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 9193d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9194d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 919597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 9196d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 919797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 919840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 919940094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 9200d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 920140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC @ pass our target PC 920240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r2,#kSVSTraceSelectNoChain @ r2<- interpreter entry point 9203d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9204d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9205d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 920640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng 920740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 920840094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 9209d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92109a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 921197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 9212d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9213d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9214d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 921597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 921640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpBackwardBranch 921740094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpBackwardBranch: 9218d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92199a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 922097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 9221d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9222d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9223d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 922497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 922597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 922697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 9227d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92289a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 922997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 9230d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9231d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9232d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 923397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 923497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 923597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 9236d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 923797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 923897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 9239d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r3, #0 9240d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r3, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9241d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng b jitSVShadowRunEnd @ doesn't return 924297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter when the compiler is 9245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * having issues translating/executing a Dalvik instruction. We have to skip 9246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the code cache lookup otherwise it is possible to indefinitely bouce 9247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * between the interpreter and the code cache if the instruction that fails 9248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to be compiled happens to be at a trace start. 9249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpPunt 9251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpPunt: 92527a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r0 925486717f79d9b018f4d69cc991075fa36611f234e5Ben Cheng#ifdef JIT_STATS 9255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,lr 9256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpPunt; 9257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 92597a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 92607a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return to the interpreter to handle a single instruction. 9268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 <= PC 9270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 <= PC of resume instruction 9271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr <= resume point in translation 9272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpSingleStep 9274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpSingleStep: 9275d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str lr,[rGLUE,#offGlue_jitResumeNPC] 9276d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng str r1,[rGLUE,#offGlue_jitResumeDPC] 9277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#kInterpEntryInstr 9278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ enum is 4 byte in aapcs-EABI 9279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_entryPoint] 9280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC,r0 9281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 92827a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitSingleStep @ Ask for single step and then revert 9285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp to bail to debug interp 9287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 928940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 929040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * Return from the translation cache and immediately request 929140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * a translation for the exit target. Commonly used for callees. 929240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 929340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelectNoChain 929440094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelectNoChain: 929586717f79d9b018f4d69cc991075fa36611f234e5Ben Cheng#ifdef JIT_STATS 929640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmBumpNoChain 929740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng#endif 929840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 929940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r0,rPC 930040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 930140094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 930240094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r1, rPC @ arg1 of translation may need this 930340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 930440094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng cmp r0,#0 930540094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng bxne r0 @ continue native execution if so 930640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng b 2f 9307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache and immediately request 9310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a translation for the exit target. Commonly used following 9311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invokes. 9312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 931340094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng .global dvmJitToInterpTraceSelect 931440094c16d9727cc1e047a7d4bddffe04dd566211Ben ChengdvmJitToInterpTraceSelect: 93159a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 93167a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93179a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 93197a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 93207a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 2f 9323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 93259a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 93269a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* No translation, so request one if profiling isn't disabled*/ 9332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 9333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 933740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng movne r2,#kJitTSelectRequestHot @ ask for trace selection 9338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_selectTrace 9339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter. 9344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The return was done with a BLX from thumb mode, and 9345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the following 32-bit word contains the target rPC value. 9346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note that lr (r14) will have its low-order bit set to denote 9347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * its thumb-mode origin. 9348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We'll need to stash our lr origin away, recover the new 9350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * target and then check to see if there is a translation available 9351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for our new target. If so, we do a translation chain and 9352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * go back to native execution. Otherwise, it's back to the 9353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter (after treating this entry as a potential 9354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace start). 9355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNormal 9357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNormal: 93589a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 93597a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 93609a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 936186717f79d9b018f4d69cc991075fa36611f234e5Ben Cheng#ifdef JIT_STATS 9362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNormal 9363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 93667a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq toInterpreter @ go if not, otherwise do chain 9369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 93719a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 93729a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter to do method invocation. 9379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check if translation exists for the callee, but don't chain to it. 9380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNoChain 9382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNoChain: 938386717f79d9b018f4d69cc991075fa36611f234e5Ben Cheng#ifdef JIT_STATS 9384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNoChain 9385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 93867a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 93897a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 93909a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 93919a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution if so 939497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * No translation, restore interpreter regs and start interpreting. 9398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rGLUE & rFP were preserved in the translated code, and rPC has 9399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * already been restored by the time we get here. We'll need to set 9400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * up rIBASE & rINST, and load the address of the JitTable into r0. 9401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddentoInterpreter: 9403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ NOTE: intended fallthrough 9408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code to update potential trace start counter, and initiate 9410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a trace-build if appropriate. On entry, rPC should point to the 9411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * next instruction to execute, and rINST should be already loaded with 9412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the next opcode word, and r0 holds a pointer to the jit profile 9413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * table (pJitProfTable). 9414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_testUpdateProfile: 9416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_updateProfile: 9421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 94227b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng lsl r3,r3,#(32 - JIT_PROF_SIZE_LOG_2) @ shift out excess bits 94237b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng ldrb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ get counter 9424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1,r1,#1 @ decrement counter 94267b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ and store it 9427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Here, we switch to the debug interpreter to request 9431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace selection. First, though, check to see if there 9432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * is already a native translation in place (and, if so, 9433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * jump to it now). 9434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9435d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 94367a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 94377b133ef7c84e68c3c4042176d830ea5b52e84139Ben Cheng strb r1,[r0,r3,lsr #(32 - JIT_PROF_SIZE_LOG_2)] @ reset counter 9438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 94417a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 94427a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 94437a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 944597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ jump to the translation 944740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng mov r2,#kJitTSelectRequest @ ask for trace selection 944840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng @ fall-through to common_selectTrace 944997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 945040094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng moveq r2,#kJitTSelectRequest @ ask for trace selection 94519a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 94529a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 94539a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 94549a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 94559a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 94569a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 9457d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng mov r10, r0 @ save target 94589a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 9459d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng cmp r0, r10 @ special case? 9460d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng bne jitSVShadowRunStart @ set up self verification shadow space 94619a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 94629a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 94639a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 946497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 94659a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 946640094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng/* 946740094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * On entry: 946840094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng * r2 is jit state, e.g. kJitTSelectRequest or kJitTSelectRequestHot 946940094c16d9727cc1e047a7d4bddffe04dd566211Ben Cheng */ 9470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_selectTrace: 9471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 94729c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 94739c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp 9475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 947797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 947897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 947997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 948097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 9481d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * On entry: 9482d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * rPC, rFP, rGLUE: the values that they should contain 9483d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng * r10: the address of the target translation. 948497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9485d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunStart: 948697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 948797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 948897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 94899a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 949097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9491ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9492ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9493ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 949497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 949597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 949697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 949797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 949897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 9499d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben ChengjitSVShadowRunEnd: 950097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 950197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9502ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9503ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9504ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9505ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 950697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 950797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 950897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 950997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 951030f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 951130f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 951297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 951397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 951497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 951597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 951697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 951797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 951897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 951997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 952097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 952197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 952297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code when a backward branch is taken. 9527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is PC adjustment *in bytes* 9530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_backwardBranch: 9532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryInstr 9533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * activity has begun. 9551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have to do the second ldr. 9554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: reduce this so we're just checking a single location. 9556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is trampoline PC adjustment *in bytes* 9560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_periodicChecks: 9562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 95649c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 95659c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 95669c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_PROFILER) 9571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined (WITH_PROFILER) 9580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ suspend pending? 9584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 2f @ yes, do full suspension check 9585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached or profiler started? 9590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_DEBUGGER) 9591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached? 9592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_PROFILER) 9593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ profiler started? 9594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# endif 9595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 3f @ debugger/profiler, switch interp 9596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr @ nothing to do, return 9599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: @ check suspend 9601964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9602964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9603964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9604964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9605964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9606d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r3<-&gDvmJit.pJitProfTable 9607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9608d5adae17d71e86a1a5f3ae7825054e3249fb7879Ben Cheng ldr r3, [r3] @ r3 <- pJitProfTable 9609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC 9610964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9611964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9612964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9613964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9614964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: @ debugger/profiler enabled, bail out 9618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, rPC, r9 @ update rPC 9619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ "want switch" = true 9620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * State registers will be saved to the "glue" area before bailing. 9627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * other interpreter or just bail all the way out 9631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_gotoBail: 9633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ r0<- glue ptr 9635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r1, r1, #1 @ using (boolean+1) 9638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl _longjmp @ does not return 9640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_abort 9641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation with range. 9645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodRange: 9650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewRange: 9651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- CCCC 9656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r2, r2, #1 @ count-- 9664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r10], #4 @ *outs++ = val 9665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1b @ ...while count != 0 9666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LinvokeArgsDone 9668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation without range. 9671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodNoRange: 9676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewNoRange: 9677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone 9684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNonRange: 9687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vA 9694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r1, #0xf000 @ isolate G 9695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vG 9698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r1, #0x0f00 @ isolate F 9699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vF 9702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r1, #0x00f0 @ isolate E 9703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vE 9706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r1, #0x000f @ isolate D 9707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vD 9710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: @ fall through to .LinvokeArgsDone 9711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ find space for the new stack frame, check for overflow 9716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@ bl common_dumpRegs 9720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 97247a44e4ee0782d24b4c6090be1f0a3c66f971f2c1Andy McFadden blo .LstackOverflow @ yes, this frame will overflow stack 9725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ set up newSaveArea 9727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EASY_GDB 9728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offStackSaveArea_returnAddr] 9736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r10, #offStackSaveArea_method] 9738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden tst r3, #ACC_NATIVE 9739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LinvokeNative 9740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP 9745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 9750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 9751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r2 @ publish new rPC 9759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Update "glue" values for the new method 9762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNative: 9783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Prep for the native call 9784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9786d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9788d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ r2<- methodToCall 9792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ r0<- newFp (points to args) 9793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 9797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .Lskip 9798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_mterp, %function 9799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_mterp: 9800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 9801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 9802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 9803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lskip: 9804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @mov lr, pc @ set return addr 9807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9810964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9811964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 9812964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9813964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 9814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ native return; r9=self, r10=newSaveArea 9815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ equivalent to dvmPopJniLocals 9816d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9818964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9819964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 9820964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null? 9823d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9824964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9825964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 9826964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ no, handle exception 9828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 98336ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 98346ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmHandleStackOverflow 9837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 9840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation, calling through "glue code". 9845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: now that we have range and non-range invoke handlers, this 9847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * needs to be split into two. Maybe just create entry points 9848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that set r9 and jump here? 9849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeOld: 9856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #8 @ space for args + pad 9857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ A2<- methodToCall 9859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ A0<- glue 9860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ A1<- methodCallRange 9862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #0] @ A4<- ip 9864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ remove arg area 9866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for handling a return instruction. 9873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_returnFromMethod: 9877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnNew: 9878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryReturn 9879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r2<- method we're returning to 9887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is this a break frame? 9889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 9891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_gotoBail @ break frame, bail out completely 9892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 98987a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 9899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 99027a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 99037a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 99047a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 9905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return handling, calls through "glue code". 9918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnOld: 9921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 9923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_returnFromMethod 9924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 9925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Somebody has thrown an exception. Handle it. 9930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If the exception processing code returns to us (instead of falling 9932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out of the interpreter), continue with whatever the next instruction 9933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * now happens to be. 9934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpCommonExceptionThrown 9938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpCommonExceptionThrown: 9939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_exceptionThrown: 9940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionNew: 9941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryThrow 9942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- NULL 9951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up args and a local for "&fp" */ 9954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov ip, sp @ ip<- &fp 9957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- false 9958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 9961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r9 @ r2<- exception 9963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 9972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ no, skip ahead 9973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r0 @ save relPc result in rFP 9974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 99754fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden mov r1, r9 @ r1<- exception 9976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCleanupStackOverflow @ call(self) 9977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP @ restore result 9978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 9979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is catchRelPc < 0? 9983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ restore stack 9984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi .LnotCaughtLocally 9985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* adjust locals to match self->curFrame and updated PC */ 9987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* release the tracked alloc on the exception */ 9997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* restore the exception if the handler wants it */ 10002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 10003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 10005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 10006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 10009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix stack overflow if necessary */ 10010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 10011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 10012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, r10 @ if yes: r0<- self 100134fbba1f95b3e27bdc5f5572bb0420b5f928aa54eAndy McFadden movne r1, r9 @ if yes: r1<- exception 10014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 10015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ may want to show "not caught locally" debug messages here 10017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if DVM_SHOW_EXCEPTION >= 2 10018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call __android_log_print(prio, tag, format, ...) */ 10019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* "Exception %s from %s:%d not caught locally" */ 10020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 10021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 10022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_insns] 10023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 10024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden asr r1, r1, #1 10025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLineNumFromPC 10026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 10027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmGetMethodSourceFile(method) 10028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 10029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmGetMethodSourceFile 10030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 10031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ exception->clazz->descriptor 10032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] 10033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_descriptor] 10034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ 10035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, strExceptionNotCaughtLocally 10036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strLogTag 10037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #3 @ LOG_DEBUG 10038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __android_log_print 10039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offThread_exception] @ restore exception 10041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 10042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 10043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 10044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 10045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail @ bail out 10046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exception handling, calls through "glue code". 10050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionOld: 10053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 10054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 10055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_exceptionThrown 10056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 10057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * After returning from a "glued" function, pull out the updated 10062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * values and start executing at the next instruction. 10063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_resumeAfterGlueCall: 10065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 10066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 10067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 10068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 10069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array index. 10072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayIndex: 10074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayIndexException 10076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array value. 10082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayStore: 10084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayStoreException 10086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Integer divide or mod by zero. 10092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errDivideByZero: 10094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArithmeticException 10096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strDivideByZero 10097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Attempt to allocate an array with a negative size. 10102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNegativeArraySize: 10104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNegativeArraySizeException 10106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invocation of a non-existent method. 10112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNoSuchMethod: 10114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNoSuchMethodError 10116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We encountered a null object when we weren't expecting one. We 10122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * export the PC, throw a NullPointerException, and goto the exception 10123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * processing code. 10124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNullObject: 10126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 10127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNullPointerException 10128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 10129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 10130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 10131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For debugging, cause an immediate fault. The source address will 10134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be in lr (use a bl instruction to jump here). 10135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_abort: 10137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, .LdeadFood 10138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdeadFood: 10139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word 0xdeadf00d 10140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out a "we were here", preserving all registers. (The attempt 10143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to save ip won't work, but we need to save an even number of 10144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * registers for EABI 64-bit stack alignment.) 10145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .macro SQUEAK num 10147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_squeak\num: 10148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 10150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #\num 10151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endm 10155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 0 10157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 1 10158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 2 10159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 3 10160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 4 10161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 5 10162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out the number in r0, preserving registers. 10165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNum: 10167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 10169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 10170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print a newline, preserving registers. 10176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNewline: 10178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNewline 10180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 10186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printHex: 10188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 10190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintHex 10191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 10197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printLong: 10199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r1 10201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 10202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintLong 10203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 10204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 10209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printMethod: 10211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpPrintMethod 10213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Call a C helper function that dumps regs and possibly some 10218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * additional info. Requires the C function to be compiled in. 10219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 10221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_dumpRegs: 10222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 10223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpDumpArmRegs 10224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 10225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 10227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if 0 10229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Experiment on VFP mode. 10231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 10233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 10235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddensetFPSCR: 10237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ make sure no stray bits are set 10238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmrx r2, fpscr @ get VFP reg 10239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ bit-invert mask 10240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, r1 @ clear masked bits 10241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r2, r2, r0 @ set specified bits 10242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmxr fpscr, r2 @ set VFP reg 10243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r2 @ return new value 10244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmConfigureFP 10248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmConfigureFP, %function 10249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmConfigureFP: 10250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {ip, lr} 10251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x03000000 sets DN/FZ */ 10252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x00009f00 clears the six exception enable flags */ 10253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_squeak0 10254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl setFPSCR 10257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {ip, pc} 10258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references, must be close to the code that uses them. 10263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArithmeticException: 10266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArithmeticException 10267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayIndexException: 10268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayIndexException 10269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayStoreException: 10270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayStoreException 10271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrDivideByZero: 10272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrDivideByZero 10273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNegativeArraySizeException: 10274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNegativeArraySizeException 10275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNoSuchMethodError: 10276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNoSuchMethodError 10277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNullPointerException: 10278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNullPointerException 10279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrLogTag: 10281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrLogTag 10282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrExceptionNotCaughtLocally: 10283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrExceptionNotCaughtLocally 10284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNewline: 10286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNewline 10287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrSqueak: 10288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrSqueak 10289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintHex: 10290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintHex 10291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintLong: 10292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintLong 10293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Zero-terminated ASCII string data. 10296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with the address, or use an ADR pseudo-op to get the address 10299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * PC-relative addressing mode and hence has a limited range, which 10301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * makes it not work well with mergeable string sections. 10302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrBadEntryPoint: 10306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Bad entry point %d\n" 10307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArithmeticException: 10308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArithmeticException;" 10309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayIndexException: 10310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayStoreException: 10312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastException: 10314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ClassCastException;" 10315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrDivideByZero: 10316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "divide by zero" 10317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrFilledNewArrayNotImpl: 10318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInternalError: 10320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InternalError;" 10321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationError: 10322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InstantiationError;" 10323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNegativeArraySizeException: 10324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNoSuchMethodError: 10326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNullPointerException: 10328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NullPointerException;" 10329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrLogTag: 10331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "mterp" 10332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrExceptionNotCaughtLocally: 10333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNewline: 10336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "\n" 10337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrSqueak: 10338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%d>" 10339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintHex: 10340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<0x%x>" 10341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintLong: 10342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%lld>" 10343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10345