InterpAsm-armv7-a.S revision 964a7b06a9134947b5985c7f712d18d57ed665d2
1a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 2a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This file was generated automatically by gen-mterp.py for 'armv7-a'. 3a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * --> DO NOT EDIT <-- 5a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/header.S */ 8a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 10a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 11a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 12a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 13a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 14a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 15a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 16a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 17a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 18a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 19a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 21a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 22a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 23a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 24a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ARMv5 definitions and declarations. 25a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 26a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 27a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 28a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenARM EABI general notes: 29a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 30a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r3 hold first 4 args to a method; they are not preserved across method calls 31a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr4-r8 are available for general use 32a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr9 is given special treatment in some situations, but not for us 33a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr10 (sl) seems to be generally available 34a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 35a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr12 (ip) is scratch -- not preserved across method calls 36a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr13 (sp) should be managed carefully in case a signal arrives 37a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr14 (lr) must be preserved 38a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr15 (pc) can be tinkered with directly 39a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 40a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0 holds returns of <= 4 bytes 41a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenr0-r1 hold returns of 8 bytes, low word in r0 42a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 43a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenCallee must save/restore r4+ (except r12) if it modifies them. If VFP 44a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenis present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 45a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddens0-s15 (d0-d7, q0-a3) do not need to be. 46a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 47a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenStack is "full descending". Only the arguments that don't fit in the first 4 48a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenregisters are placed on the stack. "sp" points at the first stacked argument 49a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden(i.e. the 5th arg). 50a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 51a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenVFP: single-precision results in s0, double-precision results in d0. 52a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 53a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenIn the EABI, "sp" must be 64-bit aligned on entry to a function, and any 54a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden64-bit quantities (long long, double) must be 64-bit aligned. 55a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 56a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 57a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 58a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMterp and ARM notes: 59a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 60a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenThe following registers have fixed assignments: 61a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 62a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden reg nick purpose 63a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r4 rPC interpreted program counter, used for fetching instructions 64a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r5 rFP interpreted frame pointer, used for accessing locals and args 65a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r6 rGLUE MterpGlue pointer 66a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r7 rINST first 16-bit code unit of current instruction 67a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden r8 rIBASE interpreted instruction base pointer, used for computed goto 68a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 69a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenMacros are provided for common operations. Each macro MUST emit only 70a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenone instruction to make instruction-counting easier. They MUST NOT alter 71a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenunspecified registers or condition codes. 72a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden*/ 73a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 74a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* single-purpose registers, given names for clarity */ 75a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rPC r4 76a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rFP r5 77a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rGLUE r6 78a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rINST r7 79a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define rIBASE r8 80a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 81a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* save/restore the PC and/or FP from the glue struct */ 82a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FROM_GLUE() ldr rPC, [rGLUE, #offGlue_pc] 83a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_TO_GLUE() str rPC, [rGLUE, #offGlue_pc] 84a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_FP_FROM_GLUE() ldr rFP, [rGLUE, #offGlue_fp] 85a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_FP_TO_GLUE() str rFP, [rGLUE, #offGlue_fp] 86a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define LOAD_PC_FP_FROM_GLUE() ldmia rGLUE, {rPC, rFP} 87a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVE_PC_FP_TO_GLUE() stmia rGLUE, {rPC, rFP} 88a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 89a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 90a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "export" the PC to the stack frame, f/b/o future exception objects. Must 91a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be done *before* something calls dvmThrowException. 92a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 93a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "SAVEAREA_FROM_FP(fp)->xtra.currentPc = pc", i.e. 94a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fp - sizeof(StackSaveArea) + offsetof(SaveArea, xtra.currentPc) 95a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 96a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * It's okay to do this more than once. 97a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 98a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define EXPORT_PC() \ 99a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [rFP, #(-sizeofStackSaveArea + offStackSaveArea_currentPc)] 100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Given a frame pointer, find the stack save area. 103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In C this is "((StackSaveArea*)(_fp) -1)". 105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SAVEAREA_FROM_FP(_reg, _fpreg) \ 107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub _reg, _fpreg, #sizeofStackSaveArea 108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from rPC into rINST. Does not advance rPC. 111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_INST() ldrh rINST, [rPC] 113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from the specified offset. Advances rPC 116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to point to the next instruction. "_count" is in 16-bit code units. 117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Because of the limited size of immediate constants on ARM, this is only 119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * suitable for small forward movements (i.e. don't try to implement "goto" 120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with this). 121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This must come AFTER anything that can throw an exception, or the 123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception catch may miss. (This also implies that it must come after 124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * EXPORT_PC().) 125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #(_count*2)]! 127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The operation performed here is similar to FETCH_ADVANCE_INST, except the 130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * src and dest registers are parameterized (not hard-wired to rPC and rINST). 131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define PREFETCH_ADVANCE_INST(_dreg, _sreg, _count) \ 133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh _dreg, [_sreg, #(_count*2)]! 134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch the next instruction from an offset specified by _reg. Updates 137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rPC to point to the next instruction. "_reg" must specify the distance 138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in bytes, *not* 16-bit code units, and may be a signed value. 139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We want to write "ldrh rINST, [rPC, _reg, lsl #2]!", but some of the 141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * bits that hold the shift distance are used for the half/byte/sign flags. 142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * In some cases we can pre-double _reg for free, so we require a byte offset 143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * here. 144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch a half-word code unit from an offset past the current PC. The 149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" value is in 16-bit code units. Does not advance rPC. 150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The "_S" variant works the same but treats the value as signed. 152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH(_reg, _count) ldrh _reg, [rPC, #(_count*2)] 154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_S(_reg, _count) ldrsh _reg, [rPC, #(_count*2)] 155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Fetch one byte from an offset past the current PC. Pass in the same 158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "_count" as you would for FETCH, and an additional 0/1 indicating which 159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * byte of the halfword you want (lo/hi). 160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define FETCH_B(_reg, _count, _byte) ldrb _reg, [rPC, #(_count*2+_byte)] 162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the instruction's opcode field into the specified register. 165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_INST_OPCODE(_reg) and _reg, rINST, #255 167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Put the prefetched instruction's opcode field into the specified register. 170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_PREFETCHED_OPCODE(_oreg, _ireg) and _oreg, _ireg, #255 172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Begin executing the opcode in _reg. Because this only jumps within the 175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE(_reg) add pc, rIBASE, _reg, lsl #6 178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFEQ(_reg) addeq pc, rIBASE, _reg, lsl #6 179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GOTO_OPCODE_IFNE(_reg) addne pc, rIBASE, _reg, lsl #6 180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Get/set the 32-bit value from a Dalvik register. 183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_VREG(_reg, _vreg) ldr _reg, [rFP, _vreg, lsl #2] 185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define SET_VREG(_reg, _vreg) str _reg, [rFP, _vreg, lsl #2] 186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define GET_JIT_PROF_TABLE(_reg) ldr _reg,[rGLUE,#offGlue_pJitProfTable] 189d726991ba52466cde88e37aba4de2395b62477faBill Buzbee#define GET_JIT_THRESHOLD(_reg) ldr _reg,[rGLUE,#offGlue_jitThreshold] 190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert a virtual register index into an address. 194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define VREG_INDEX_TO_ADDR(_reg, _vreg) \ 196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add _reg, rFP, _vreg, lsl #2 197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is a #include, not a %include, because we want the C pre-processor 200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to expand the macros into assembler assignment statements. 201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#include "../common/asm-constants.h" 203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/platform.S */ 206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * CPU-version-specific defines 209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDR PC,xxx", which is not allowed pre-ARMv5. Essentially a 214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * one-way branch. 215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP. Does not modify LR. 217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC source 219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "MOV LR,PC / LDR PC,xxx", which is not allowed pre-ARMv5. 224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Jump to subroutine. 225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDR_PC_LR source 229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov lr, pc 230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, \source 231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Macro for "LDMFD SP!, {...regs...,PC}". 235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * May modify IP and LR. 237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.macro LDMFD_PC regs 239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {\regs,pc} 240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.endm 241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/entry.S */ 244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Copyright (C) 2008 The Android Open Source Project 246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Licensed under the Apache License, Version 2.0 (the "License"); 248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * you may not use this file except in compliance with the License. 249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * You may obtain a copy of the License at 250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * http://www.apache.org/licenses/LICENSE-2.0 252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unless required by applicable law or agreed to in writing, software 254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distributed under the License is distributed on an "AS IS" BASIS, 255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See the License for the specific language governing permissions and 257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * limitations under the License. 258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Interpreter entry point. 261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't have formal stack frames, so gdb scans upward in the code 265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to find the start of the function (a label with the %function type), 266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and then looks at the next few instructions to figure out what 267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * got pushed onto the stack. From this it figures out how to restore 268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the registers, including PC, for the previous stack frame. If gdb 269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sees a non-function label, it stops scanning, so either we need to 270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have nothing but assembler-local labels between the entry point and 271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the break, or we need to fake it out. 272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * When this is defined, we add some stuff to make gdb less confused. 274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define ASSIST_DEBUGGER 1 276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdRun 280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdRun, %function 281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This function returns a boolean "changeInterp" value. The return comes 287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * via a call to dvmMterpStdBail(). 288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdRun: 290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY1 \ 291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .save {r4-r10,fp,lr}; \ 292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4-r10,fp,lr} @ save 9 regs 293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#define MTERP_ENTRY2 \ 294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .pad #4; \ 295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align 64 296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* save stack pointer, add magic word for debuggerd */ 302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str sp, [r0, #offGlue_bailPtr] @ save SP for eventual return 303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up "named" registers, figure out entry point */ 305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rGLUE, r0 @ set rGLUE 306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offGlue_entryPoint] @ InterpEntry enum is char 307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ load rPC and rFP from "glue" 308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adr rIBASE, dvmAsmInstructionStart @ set rIBASE 309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryInstr @ usual case? 310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lnot_instr @ no, handle it 311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lno_singleStep: 3147a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* Entry is always a possible trace start */ 316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 3187a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, #0 @ prepare the value for the new state 3197a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r1, [r10, #offThread_inJitCodeCache] @ back to the interp land 320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* start executing the instruction at rPC */ 326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_instr: 332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryReturn @ were we returning from a method? 333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_returnFromMethod 334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_return: 336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryThrow @ were we throwing an exception? 337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown 338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lnot_throw: 341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0,[rGLUE, #offGlue_jitResume] 342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2,[rGLUE, #offGlue_jitResumePC] 343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #kInterpEntryResume @ resuming after Jit single-step? 344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lbad_arg 345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp rPC,r2 346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .Lno_singleStep @ must have branched, don't resume 347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #kInterpEntryInstr 348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r1, [rGLUE, #offGlue_entryPoint] 349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, .LdvmCompilerTemplate 350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx r0 @ re-enter the translation 351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdvmCompilerTemplate: 352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word dvmCompilerTemplateStart 353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lbad_arg: 356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strBadEntryPoint 357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r1 holds value of entryPoint 358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAbort 360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpStdBail 364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmMterpStdBail, %function 365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Restore the stack pointer and PC from the save point established on entry. 368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This is essentially the same as a longjmp, but should be cheaper. The 369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * last instruction causes us to return to whoever called dvmMterpStdRun. 370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We pushed some registers on the stack in dvmMterpStdRun, then saved 372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * SP and LR. Here we restore SP, restore the registers, and then restore 373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * LR to PC. 374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 MterpGlue* glue 377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 bool changeInterp 378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpStdBail: 380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr sp, [r0, #offGlue_bailPtr] @ sp<- saved SP 381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ return the changeInterp value 382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 @ un-align 64 383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDMFD_PC "r4-r10,fp" @ restore 9 regs and return 384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references. 388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrBadEntryPoint: 390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrBadEntryPoint 391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionStart 395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmInstructionStart, %function 396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionStart = .L_OP_NOP 397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOP: /* 0x00 */ 402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NOP.S */ 403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance to next instr, load rINST 404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_inst, %function 410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_inst: 411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE: /* 0x01 */ 421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE.S */ 422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_FROM16: /* 0x02 */ 436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_16: /* 0x03 */ 451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE: /* 0x04 */ 466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MOVE_WIDE.S */ 467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide vA, vB */ 468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[A] 473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[B] 474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[A]<- r0/r1 477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_FROM16: /* 0x05 */ 483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_FROM16.S */ 484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/from16 vAA, vBBBB */ 485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- BBBB 487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_WIDE_16: /* 0x06 */ 500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_WIDE_16.S */ 501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-wide/16 vAAAA, vBBBB */ 502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- BBBB 504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- AAAA 505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] 506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] 507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT: /* 0x07 */ 517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT.S */ 518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_FROM16: /* 0x08 */ 535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_FROM16.S */ 536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_FROM16.S */ 537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/from16, move-object/from16 */ 538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBBBB */ 539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AA]<- r2 545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_OBJECT_16: /* 0x09 */ 552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_OBJECT_16.S */ 553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_16.S */ 554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move/16, move-object/16 */ 555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAAAA, vBBBB */ 556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB 557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- AAAA 558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[BBBB] 560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[AAAA]<- r2 562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT: /* 0x0a */ 569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_WIDE: /* 0x0b */ 583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_WIDE.S */ 584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-result-wide vAA */ 585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- retval.j 589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r2, {r0-r1} @ fp[AA]<- r0/r1 592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_RESULT_OBJECT: /* 0x0c */ 598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT_OBJECT.S */ 599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_RESULT.S */ 600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for: move-result, move-result-object */ 601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_retval] @ r0<- glue->retval.i 605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[AA]<- r0 607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MOVE_EXCEPTION: /* 0x0d */ 614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE_EXCEPTION.S */ 615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* move-exception vAA */ 616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offThread_exception] @ r3<- dvmGetException bypass 619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ r1<- 0 620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ fp[AA]<- exception obj 622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ dvmClearException bypass 624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_VOID: /* 0x0e */ 630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_VOID.S */ 631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN: /* 0x0f */ 637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_WIDE: /* 0x10 */ 654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_WIDE.S */ 655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 64-bit value. Copies the return value into the "glue" 657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* return-wide vAA */ 660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] 662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rGLUE, #offGlue_retval @ r3<- &glue->retval 663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ retval<- r0/r1 665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RETURN_OBJECT: /* 0x11 */ 671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN_OBJECT.S */ 672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RETURN.S */ 673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return a 32-bit value. Copies the return value into the "glue" 675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * structure, then jumps to the return handler. 676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: return, return-object 678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA */ 680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vAA 682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.i <- vAA 683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_returnFromMethod 684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_4: /* 0x12 */ 690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_CONST_4.S */ 691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/4 vA, #+B */ 692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsl #16 @ r1<- Bxxx0000 693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #28 @ r1<- sssssssB (sign-extended) 696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r0) @ fp[A]<- r1 698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_16: /* 0x13 */ 704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_16.S */ 705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/16 vAA, #+BBBB */ 706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST: /* 0x14 */ 717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST.S */ 718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const vAA, #+BBBBbbbb */ 719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_HIGH16: /* 0x15 */ 732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_HIGH16.S */ 733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/high16 vAA, #+BBBB0000 */ 734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000BBBB (zero-extended) 735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsl #16 @ r0<- BBBB0000 737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_16: /* 0x16 */ 746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_16.S */ 747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/16 vAA, #+BBBB */ 748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssBBBB (sign-extended) 749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_32: /* 0x17 */ 761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_32.S */ 762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/32 vAA, #+BBBBbbbb */ 763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- 0000bbbb (low) 764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r2, 2) @ r2<- ssssBBBB (high) 766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r1<- ssssssss 770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE: /* 0x18 */ 778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE.S */ 779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (low middle) 782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 3) @ r2<- hhhh (high middle) 783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 4) @ r3<- HHHH (high) 785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(5) @ advance rPC, load rINST 788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_WIDE_HIGH16: /* 0x19 */ 797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_WIDE_HIGH16.S */ 798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const-wide/high16 vAA, #+BBBB000000000000 */ 799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- 0000BBBB (zero-extended) 800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0 @ r0<- 00000000 802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsl #16 @ r1<- BBBB0000 803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] 805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ vAA<- r0/r1 807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING: /* 0x1a */ 813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING.S */ 814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBB */ 815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_resolve 822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_STRING_JUMBO: /* 0x1b */ 830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_STRING_JUMBO.S */ 831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/string vAA, String@BBBBBBBB */ 832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (low) 833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (high) 834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResStrings] @ r2<- dvmDex->pResStrings 837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResStrings[BBBB] 839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_STRING_JUMBO_resolve 841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CONST_CLASS: /* 0x1c */ 849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CONST_CLASS.S */ 850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* const/class vAA, Class@BBBB */ 851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- glue->methodClassDex 853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- dvmDex->pResClasses 855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- pResClasses[BBBB] 856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ not yet resolved? 857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CONST_CLASS_resolve 858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_ENTER: /* 0x1d */ 866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_ENTER.S */ 867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Synchronize on an object. 869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-enter vAA */ 871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC, MONITOR_TRACKING 876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null object, throw an exception 877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLockObject @ call(self, obj) 879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef WITH_DEADLOCK_PREDICTION /* implies WITH_MONITOR_TRACKING */ 880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offThread_exception] @ check for exception 882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ exception raised, bail out 884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MONITOR_EXIT: /* 0x1e */ 892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MONITOR_EXIT.S */ 893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlock an object. 895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exceptions that occur when unlocking a monitor need to appear as 897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if they happened at the following instruction. See the Dalvik 898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction spec. 899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* monitor-exit vAA */ 901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ before fetch: export the PC 903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (object) 904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes 906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmUnlockObject @ r0<- success for unlock(self, obj) 908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, exception is pending 910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ before throw: advance rPC, load rINST 911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CHECK_CAST: /* 0x1f */ 918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CHECK_CAST.S */ 919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if a cast from one class to another is allowed. 921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* check-cast vAA, class@BBBB */ 923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r3) @ r9<- object 926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_methodClassDex] @ r0<- pDvmDex 927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ is object null? 928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offDvmDex_pResClasses] @ r0<- pDvmDex->pResClasses 929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_okay @ null obj, cast always succeeds 930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, r2, lsl #2] @ r1<- resolved class 931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_CHECK_CAST_resolve @ not resolved, do it now 934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolved: 935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_fullcheck @ no, do full check 937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_okay: 938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INSTANCE_OF: /* 0x20 */ 945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INSTANCE_OF.S */ 946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check to see if an object reference is an instance of a class. 948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Most common situation is a non-null object, being compared against 950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an already-resolved class. 951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* instance-of vA, vB, class@CCCC */ 953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- pDvmDex 959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_store @ null obj, not an instance, store r0 960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- CCCC 961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResClasses] @ r2<- pDvmDex->pResClasses 962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r2, r3, lsl #2] @ r1<- resolved class 963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ have we resolved this before? 965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_resolve @ not resolved, do it now 966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolved: @ r0=obj->clazz, r1=resolved class 967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r1 @ same class (trivial success)? 968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INSTANCE_OF_trivial @ yes, trivial finish 969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_fullcheck @ no, do full check 970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ARRAY_LENGTH: /* 0x21 */ 974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ARRAY_LENGTH.S */ 975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return the length of an array. 977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- vB (object ref) 981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is object null? 982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yup, fail 983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- array length 985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r3, r2) @ vB<- length 987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_INSTANCE: /* 0x22 */ 993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_INSTANCE.S */ 994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new instance of a class. 996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-instance vAA, class@BBBB */ 998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for init, resolve, alloc 1003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_NEW_INSTANCE_resolve @ no, resolve it now 1005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolved: @ r0=class 1006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r0, #offClassObject_status] @ r1<- ClassStatus enum 1007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #CLASS_INITIALIZED @ has class been initialized? 1008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_needinit @ no, init class now 1009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_initialized: @ r0=class 1010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #ALLOC_DONT_TRACK @ flags for alloc call 1011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocObject @ r0<- new object 1012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_INSTANCE_finish @ continue 1013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEW_ARRAY: /* 0x23 */ 1017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_NEW_ARRAY.S */ 1018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Allocate an array of objects, specified with the array class 1020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and a count. 1021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The verifier guarantees that this is an array class, so we don't 1023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * check for it here. 1024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* new-array vA, vB, class@CCCC */ 1026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 1027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- CCCC 1028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r0) @ r1<- vB (array length) 1030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ check length 1032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r0<- resolved class 1033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_errNegativeArraySize @ negative length, bail 1034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ req'd for resolve, alloc 1036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_ARRAY_finish @ resolved, continue 1037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_NEW_ARRAY_resolve @ do resolve now 1038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY: /* 0x24 */ 1042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_continue @ yes, continue on 1058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_continue 1065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILLED_NEW_ARRAY_RANGE: /* 0x25 */ 1069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY_RANGE.S */ 1070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILLED_NEW_ARRAY.S */ 1071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Create a new array with elements filled from registers. 1073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: filled-new-array, filled-new-array/range 1075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 1079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 1080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResClasses] @ r3<- pDvmDex->pResClasses 1081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for resolve and alloc 1082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved class 1083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r10, rINST, lsr #8 @ r10<- AA or BA 1084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 1085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_continue @ yes, continue on 1086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 1087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 1088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 1089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 1090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 1091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 1092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_FILLED_NEW_ARRAY_RANGE_continue 1093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FILL_ARRAY_DATA: /* 0x26 */ 1098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_FILL_ARRAY_DATA.S */ 1099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fill-array-data vAA, +BBBBBBBB */ 1100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vAA (array object) 1105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC(); 1107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleFillArrayData@ fill the array with predefined data 1108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ 0 means an exception is thrown 1109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ has exception 1110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 1111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW: /* 0x27 */ 1117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW.S */ 1118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception object in the current thread. 1120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* throw vAA */ 1122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 1123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vAA (exception object) 1124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 1125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null object? 1126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, throw an NPE instead 1127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ bypass dvmSetException, just store it 1128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offThread_exception] @ thread->exception<- obj 1129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 1130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO: /* 0x28 */ 1135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO.S */ 1136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 8-bit offset. 1138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto +AA */ 1143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsl #16 @ r0<- AAxx0000 1144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asr #24 @ r9<- ssssssAA (sign-extended) 1145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r9, lsl #1 @ r9<- byte offset 1146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_16: /* 0x29 */ 1163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_16.S */ 1164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 16-bit offset. 1166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/16 +AAAA */ 1171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r0, 1) @ r0<- ssssAAAA (sign-extended) 1172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- byte offset, check sign 1173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_GOTO_32: /* 0x2a */ 1191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_GOTO_32.S */ 1192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unconditional branch, 32-bit offset. 1194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The branch distance is a signed code-unit offset, which we need to 1196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * double to get a byte offset. 1197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most opcodes, this one is allowed to branch to itself, so 1199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * our "backward branch" test must be "<=0" instead of "<0". The ORRS 1200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction doesn't affect the V flag, so we need to clear it 1201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * explicitly. 1202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* goto/32 +AAAAAAAA */ 1204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- aaaa (lo) 1205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- AAAA (hi) 1206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, ip @ (clear V flag during stall) 1207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r0, r0, r1, lsl #16 @ r0<- AAAAaaaa, check sign 1208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0, asl #1 @ r9<- byte offset 1209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble common_backwardBranch @ backward branch, do periodic checks 1210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_PACKED_SWITCH: /* 0x2b */ 1226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandlePackedSwitch @ r0<- code-unit branch offset 1244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPARSE_SWITCH: /* 0x2c */ 1264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPARSE_SWITCH.S */ 1265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_PACKED_SWITCH.S */ 1266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a packed-switch or sparse-switch instruction. In both cases 1268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * we decode it and hand it off to a helper function. 1269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We don't really expect backward branches in a switch statement, but 1271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * they're perfectly legal, so we check for them here. 1272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: packed-switch, sparse-switch 1274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, +BBBB */ 1276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- bbbb (lo) 1277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- BBBB (hi) 1278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 1279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vAA 1281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInterpHandleSparseSwitch @ r0<- code-unit branch offset 1283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r0, asl #1 @ r9<- branch byte offset, check sign 1284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_backwardBranch @ (want to use BLE but V is unknown) 1286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_FLOAT: /* 0x2d */ 1304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_FLOAT.S */ 1305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13235162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13265162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13285162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13375162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_FLOAT_finish @ argh 1338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_FLOAT: /* 0x2e */ 1343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_FLOAT.S */ 1344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 13625162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 13655162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 13675162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden flds s0, [r2] @ s0<- vBB 1368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 1369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmpes s0, s1 @ compare (vBB, vCC) 1370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 13765162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_FLOAT_finish @ argh 1377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPL_DOUBLE: /* 0x2f */ 1382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPL_DOUBLE.S */ 1383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14015162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14045162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14065162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, #0 @ r0<- -1 (default) 1411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movgt r0, #1 @ (greater than) r1<- 1 1414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14155162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPL_DOUBLE_finish @ argh 1416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMPG_DOUBLE: /* 0x30 */ 1421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_CMPG_DOUBLE.S */ 1422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two floating-point values. Puts 0, 1, or -1 into the 1424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * destination register based on the results of the comparison. 1425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int compare(x, y) { 1427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * if (x == y) { 1428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 0; 1429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x < y) { 1430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return -1; 1431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else if (x > y) { 1432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } else { 1434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * return 1; 1435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * } 1437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 1439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 14405162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 14435162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 1444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 14455162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden fldd d0, [r2] @ d0<- vBB 1446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 1447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcmped d0, d1 @ compare (vBB, vCC) 1448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 1449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ r0<- 1 (default) 1450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmstat @ export status flags 1452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnmi r0, #0 @ (less than) r1<- -1 1453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r0, #0 @ (equal) r1<- 0 14545162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden b .LOP_CMPG_DOUBLE_finish @ argh 1455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_CMP_LONG: /* 0x31 */ 1460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_CMP_LONG.S */ 1461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * register based on the results of the comparison. 1464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We load the full values with LDM, but in practice many values could 1466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be resolved by only looking at the high word. This could be made 1467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * faster or slower by splitting the LDM into a pair of LDRs. 1468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If we just wanted to set condition flags, we could do this: 1470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subs ip, r0, r2 1471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sbcs ip, r1, r3 1472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * subeqs ip, r0, r2 1473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Leaving { <0, 0, >0 } in ip. However, we have to set it to a specific 1474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * integer value, which we can do with 2 conditional mov/mvn instructions 1475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (set 1, set -1; if they're equal we already have 0 in ip), giving 1476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * us a constant 5-cycle path plus a branch at the end to the 1477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instruction epilogue code. The multi-compare approach below needs 1478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2 or 3 cycles + branch if the high word doesn't match, 6 + branch 1479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * in the worst case (the 64-bit values are equal). 1480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* cmp-long vAA, vBB, vCC */ 1482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 1483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 1484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 1485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 1486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 1487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 1488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare (vBB+1, vCC+1) 1491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LOP_CMP_LONG_less @ signed compare on high part 1492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt .LOP_CMP_LONG_greater 1493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1, r0, r2 @ r1<- r0 - r2 1494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bhi .LOP_CMP_LONG_greater @ unsigned compare on low part 1495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CMP_LONG_less 1496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CMP_LONG_finish @ equal; r1 already holds 0 1497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQ: /* 0x32 */ 1501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_EQ.S */ 1502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NE: /* 0x33 */ 1537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_NE.S */ 1538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LT: /* 0x34 */ 1573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LT.S */ 1574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GE: /* 0x35 */ 1609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GE.S */ 1610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GT: /* 0x36 */ 1645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_GT.S */ 1646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LE: /* 0x37 */ 1681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IF_LE.S */ 1682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/bincmp.S */ 1683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic two-operand compare-and-branch operation. Provide a "revcmp" 1685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vA, vB, +CCCC */ 1691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 1692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 1693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r1) @ r3<- vB 1694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vA 1695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (vA, vB) 1697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ yes, do periodic checks 1701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_testUpdateProfile 1706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_EQZ: /* 0x38 */ 1717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_EQZ.S */ 1718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ branch to 1 if comparison failed 1732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_NEZ: /* 0x39 */ 1754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_NEZ.S */ 1755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ branch to 1 if comparison failed 1769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LTZ: /* 0x3a */ 1791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LTZ.S */ 1792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bge 1f @ branch to 1 if comparison failed 1806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GEZ: /* 0x3b */ 1828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GEZ.S */ 1829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt 1f @ branch to 1 if comparison failed 1843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_GTZ: /* 0x3c */ 1865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_GTZ.S */ 1866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ble 1f @ branch to 1 if comparison failed 1880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IF_LEZ: /* 0x3d */ 1902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IF_LEZ.S */ 1903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/zcmp.S */ 1904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic one-operand compare-and-branch operation. Provide a "revcmp" 1906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * fragment that specifies the *reverse* comparison to perform, e.g. 1907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for "if-le" you would use "gt". 1908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 1911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* if-cmp vAA, +BBBB */ 1912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 1913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vAA 1914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #4 @ r0<- BYTE branch dist for not-taken 1915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ compare (vA, 0) 1916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bgt 1f @ branch to 1 if comparison failed 1917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r9, 1) @ r9<- branch offset, in code units 1918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r9, r9, asl #1 @ convert to bytes, check sign 1919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi common_backwardBranch @ backward branch, do periodic checks 1920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 1921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 1922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 1923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 1925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 1926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 1929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 1930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 1931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 1932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 1933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3E: /* 0x3e */ 1939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3E.S */ 1940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_3F: /* 0x3f */ 1948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_3F.S */ 1949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_40: /* 0x40 */ 1957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_40.S */ 1958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_41: /* 0x41 */ 1966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_41.S */ 1967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_42: /* 0x42 */ 1975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_42.S */ 1976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_43: /* 0x43 */ 1984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_43.S */ 1985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 1986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 1987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 1990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 1991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 1992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET: /* 0x44 */ 1993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 1994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 1995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 1996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 1997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 1999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_WIDE: /* 0x45 */ 2024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_WIDE.S */ 2025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 64 bits. vAA <- vBB[vCC]. 2027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 2029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aget-wide vAA, vBB, vCC */ 2031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_AGET_WIDE_finish @ okay, continue below 2043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_OBJECT: /* 0x46 */ 2051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_OBJECT.S */ 2052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BOOLEAN: /* 0x47 */ 2084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BOOLEAN.S */ 2085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_BYTE: /* 0x48 */ 2117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_BYTE.S */ 2118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsb r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_CHAR: /* 0x49 */ 2150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_CHAR.S */ 2151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AGET_SHORT: /* 0x4a */ 2183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET_SHORT.S */ 2184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AGET.S */ 2185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array get, 32 bits or less. vAA <- vBB[vCC]. 2187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aget, aget-object, aget-boolean, aget-byte, aget-char, aget-short 2192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrsh r2, [r0, #offArrayObject_contents] @ r2<- vBB[vCC] 2207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r9) @ vAA<- r2 2209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT: /* 0x4b */ 2216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_WIDE: /* 0x4c */ 2247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_WIDE.S */ 2248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 64 bits. vBB[vCC] <- vAA. 2250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* aput-wide vAA, vBB, vCC */ 2254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 2266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_WIDE_finish @ okay, continue below 2267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ May want to swap the order of these two branches depending on how the 2269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ branch prediction (if any) handles conditional forward branches vs. 2270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ unconditional forward branches. 2271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_OBJECT: /* 0x4d */ 2275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_OBJECT.S */ 2276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Store an object into an array. vBB[vCC] <- vAA. 2278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 2284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 2286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 2287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- vBB (array object) 2288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vCC (requested index) 2289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null array object? 2290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r9) @ r9<- vAA 2291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offArrayObject_length] @ r3<- arrayObj->length 2293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r1, r0, lsl #2 @ r10<- arrayObj + index*width 2294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, r3 @ compare unsigned index, length 2295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcc .LOP_APUT_OBJECT_finish @ we're okay, continue on 2296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errArrayIndex @ index >= length, bail 2297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BOOLEAN: /* 0x4e */ 2302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BOOLEAN.S */ 2303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_BYTE: /* 0x4f */ 2335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_BYTE.S */ 2336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strb r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_CHAR: /* 0x50 */ 2368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_CHAR.S */ 2369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_APUT_SHORT: /* 0x51 */ 2401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT_SHORT.S */ 2402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_APUT.S */ 2403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Array put, 32 bits or less. vBB[vCC] <- vAA. 2405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * instructions. We use a pair of FETCH_Bs instead. 2408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, vBB, vCC */ 2412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r2, 1, 0) @ r2<- BB 2413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 2414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_B(r3, 1, 1) @ r3<- CC 2415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB (array object) 2416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC (requested index) 2417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null array object? 2418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, bail 2419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offArrayObject_length] @ r3<- arrayObj->length 2420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, r3 @ compare unsigned index, length 2422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs common_errArrayIndex @ index >= length, bail 2423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r9) @ r2<- vAA 2425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strh r2, [r0, #offArrayObject_contents] @ vBB[vCC]<- r2 2427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET: /* 0x52 */ 2434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET.S */ 2435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish @ no, already resolved 2449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_finish 2455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE: /* 0x53 */ 2460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE.S */ 2461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Wide 32-bit instance field get. 2463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide vA, vB, field@CCCC */ 2465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish @ no, already resolved 2473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_WIDE_finish 2479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT: /* 0x54 */ 2484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT.S */ 2485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish @ no, already resolved 2500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_OBJECT_finish 2506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BOOLEAN: /* 0x55 */ 2512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BOOLEAN.S */ 2513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrb", "sqnum":"1" } 2514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish @ no, already resolved 2529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BOOLEAN_finish 2535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_BYTE: /* 0x56 */ 2541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_BYTE.S */ 2542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsb", "sqnum":"2" } 2543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish @ no, already resolved 2558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_BYTE_finish 2564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_CHAR: /* 0x57 */ 2570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_CHAR.S */ 2571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrh", "sqnum":"3" } 2572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish @ no, already resolved 2587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_CHAR_finish 2593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_SHORT: /* 0x58 */ 2599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_SHORT.S */ 2600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IGET.S" { "load":"ldrsh", "sqnum":"4" } 2601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET.S */ 2602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field get. 2604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish @ no, already resolved 2616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 2621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IGET_SHORT_finish 2622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT: /* 0x59 */ 2628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT.S */ 2629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ no, already resolved 2643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_finish @ yes, finish up 2649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE: /* 0x5a */ 2654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE.S */ 2655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide vA, vB, field@CCCC */ 2656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pResFields 2660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ no, already resolved 2664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_WIDE_finish @ yes, finish up 2670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT: /* 0x5b */ 2675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT.S */ 2676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ no, already resolved 2691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_OBJECT_finish @ yes, finish up 2697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BOOLEAN: /* 0x5c */ 2703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BOOLEAN.S */ 2704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"1" } 2705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ no, already resolved 2720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BOOLEAN_finish @ yes, finish up 2726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_BYTE: /* 0x5d */ 2732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_BYTE.S */ 2733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strb", "sqnum":"2" } 2734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ no, already resolved 2749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_BYTE_finish @ yes, finish up 2755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_CHAR: /* 0x5e */ 2761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_CHAR.S */ 2762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"3" } 2763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ no, already resolved 2778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_CHAR_finish @ yes, finish up 2784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_SHORT: /* 0x5f */ 2790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_SHORT.S */ 2791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv5te/OP_IPUT.S" { "store":"strh", "sqnum":"4" } 2792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT.S */ 2793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit instance field put. 2795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, field@CCCC */ 2799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 2800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- DvmDex 2801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref CCCC 2802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r3, #offDvmDex_pResFields] @ r2<- pDvmDex->pResFields 2803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r9, r0) @ r9<- fp[B], the object pointer 2804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved InstField ptr 2805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ no, already resolved 2807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden8: ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 2808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 2809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 2810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveInstField @ r0<- resolved InstField ptr 2811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 2812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_IPUT_SHORT_finish @ yes, finish up 2813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 2814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET: /* 0x60 */ 2819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_resolve @ yes, do resolve 2832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_finish: @ field ptr in r0 2833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_WIDE: /* 0x61 */ 2843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_WIDE.S */ 2844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SGET handler. 2846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sget-wide vAA, field@BBBB */ 2848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_WIDE_resolve @ yes, do resolve 2854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_finish: 2855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 2856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offStaticField_value] @ r2/r3<- field value (aligned) 2857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[AA] 2858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r1, {r2-r3} @ vAA/vAA+1<- r2/r3 2860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_OBJECT: /* 0x62 */ 2866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_OBJECT.S */ 2867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_OBJECT_resolve @ yes, do resolve 2880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_finish: @ field ptr in r0 2881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BOOLEAN: /* 0x63 */ 2892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BOOLEAN.S */ 2893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BOOLEAN_resolve @ yes, do resolve 2906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_finish: @ field ptr in r0 2907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_BYTE: /* 0x64 */ 2918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_BYTE.S */ 2919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_BYTE_resolve @ yes, do resolve 2932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_finish: @ field ptr in r0 2933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_CHAR: /* 0x65 */ 2944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_CHAR.S */ 2945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_CHAR_resolve @ yes, do resolve 2958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_finish: @ field ptr in r0 2959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SGET_SHORT: /* 0x66 */ 2970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET_SHORT.S */ 2971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SGET.S */ 2972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SGET handler. 2974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 2975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 2977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 2978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 2979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 2980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 2981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 2982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 2983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SGET_SHORT_resolve @ yes, do resolve 2984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_finish: @ field ptr in r0 2985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offStaticField_value] @ r1<- field value 2986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 2987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 2988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r2) @ fp[AA]<- r1 2989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 2990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 2991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 2993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 2994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 2995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT: /* 0x67 */ 2996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 2997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 2998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 2999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_resolve @ yes, do resolve 3009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_finish: @ field ptr in r0 3010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_WIDE: /* 0x68 */ 3020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_WIDE.S */ 3021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 64-bit SPUT handler. 3023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* sput-wide vAA, field@BBBB */ 3025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 3029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 3031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_WIDE_resolve @ yes, do resolve 3033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_finish: @ field ptr in r0, AA in r9 3034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 3036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offStaticField_value] @ field<- vAA/vAA+1 3038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_OBJECT: /* 0x69 */ 3043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_OBJECT.S */ 3044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_OBJECT_resolve @ yes, do resolve 3057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_finish: @ field ptr in r0 3058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BOOLEAN: /* 0x6a */ 3069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BOOLEAN.S */ 3070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BOOLEAN_resolve @ yes, do resolve 3083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_finish: @ field ptr in r0 3084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_BYTE: /* 0x6b */ 3095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_BYTE.S */ 3096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_BYTE_resolve @ yes, do resolve 3109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_finish: @ field ptr in r0 3110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_CHAR: /* 0x6c */ 3121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_CHAR.S */ 3122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_CHAR_resolve @ yes, do resolve 3135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_finish: @ field ptr in r0 3136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SPUT_SHORT: /* 0x6d */ 3147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT_SHORT.S */ 3148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SPUT.S */ 3149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * General 32-bit SPUT handler. 3151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: sput, sput-object, sput-boolean, sput-byte, sput-char, sput-short 3153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, field@BBBB */ 3155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_methodClassDex] @ r2<- DvmDex 3156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field ref BBBB 3157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offDvmDex_pResFields] @ r2<- dvmDex->pResFields 3158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- resolved StaticField ptr 3159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is resolved entry null? 3160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_SPUT_SHORT_resolve @ yes, do resolve 3161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_finish: @ field ptr in r0 3162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- AA 3163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 3164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r2) @ r1<- fp[AA] 3165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r0, #offStaticField_value] @ field<- vAA 3167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL: /* 0x6e */ 3173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ yes, continue on 3192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_continue @ no, continue 3198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER: /* 0x6f */ 3203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ resolved, continue on 3227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_resolve @ do resolve now 3228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT: /* 0x70 */ 3232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_resolve @ not resolved, do it now 3257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_finish: 3258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue on 3260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC: /* 0x71 */ 3265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ yes, continue on 3280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodNoRange @ no, continue 3286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE: /* 0x72 */ 3292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 3303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodNoRange @ jump to common handler 3316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_73: /* 0x73 */ 3321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_73.S */ 3322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_RANGE: /* 0x74 */ 3330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_RANGE.S */ 3331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL.S */ 3332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a virtual method call. 3334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-virtual, invoke-virtual/range 3336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ yes, continue on 3350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 3353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_VIRTUAL_RANGE_continue @ no, continue 3356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_RANGE: /* 0x75 */ 3362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_RANGE.S */ 3363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER.S */ 3364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a "super" method call. 3366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-super, invoke-super/range 3368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved baseMethod 3380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this"? 3381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_method] @ r9<- current method 3382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 3383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r9, #offMethod_clazz] @ r9<- method->clazz 3385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ resolved, continue on 3387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INVOKE_SUPER_RANGE_resolve @ do resolve now 3388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_RANGE: /* 0x76 */ 3393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_RANGE.S */ 3394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT.S */ 3395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a direct method call. 3397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (We could defer the "is 'this' pointer null" test to the common 3399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * method invocation code, and use a flag to indicate that static 3400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * calls don't count. If we do this as part of copying the arguments 3401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out we could avoiding loading the first arg twice.) 3402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-direct, invoke-direct/range 3404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 3411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 3414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr 3418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_INVOKE_DIRECT_RANGE_resolve @ not resolved, do it now 3419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_finish: 3420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ null "this" ref? 3421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue on 3422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNullObject @ yes, throw exception 3423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_STATIC_RANGE: /* 0x77 */ 3428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC_RANGE.S */ 3429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_STATIC.S */ 3430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a static method call. 3432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-static, invoke-static/range 3434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- pDvmDex 3438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offDvmDex_pResMethods] @ r3<- pDvmDex->pResMethods 3440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1, lsl #2] @ r0<- resolved methodToCall 3441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ already resolved? 3442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ yes, continue on 3444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 3445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 3446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_STATIC @ resolver method type 3447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 3448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 3449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_invokeMethodRange @ no, continue 3450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 3451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_INTERFACE_RANGE: /* 0x78 */ 3457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE_RANGE.S */ 3458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_INTERFACE.S */ 3459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an interface method call. 3461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: invoke-interface, invoke-interface/range 3463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 2) @ r2<- FEDC or CCCC 3467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 3468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 3469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- C (or stays CCCC) 3470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 3471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 3472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- first arg ("this") 3473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_methodClassDex] @ r3<- methodClassDex 3474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null obj? 3475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- method 3476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ yes, fail 3477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- thisPtr->clazz 3478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindInterfaceMethodInCache @ r0<- call(class, ref, method, dex) 3479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 3480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 3481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_invokeMethodRange @ jump to common handler 3482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_79: /* 0x79 */ 3488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_79.S */ 3489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_7A: /* 0x7a */ 3497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_7A.S */ 3498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 3499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 3500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_INT: /* 0x7b */ 3506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_INT.S */ 3507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_INT: /* 0x7c */ 3532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_INT.S */ 3533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ r0<- op, r0-r3 changed 3549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_LONG: /* 0x7d */ 3558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_LONG.S */ 3559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsbs r0, r0, #0 @ optional op; may set condition codes 3575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NOT_LONG: /* 0x7e */ 3586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NOT_LONG.S */ 3587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r0, r0 @ optional op; may set condition codes 3603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_FLOAT: /* 0x7f */ 3614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_FLOAT.S */ 3615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_NEG_DOUBLE: /* 0x80 */ 3640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_NEG_DOUBLE.S */ 3641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_LONG: /* 0x81 */ 3668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_LONG.S */ 3669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_FLOAT: /* 0x82 */ 3694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_FLOAT.S */ 3695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitos s1, s0 @ s1<- op 3710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_DOUBLE: /* 0x83 */ 3719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_INT_TO_DOUBLE.S */ 3720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsitod d0, s0 @ d0<- op 3735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_INT: /* 0x84 */ 3744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_LONG_TO_INT.S */ 3745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MOVE.S */ 3747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* for move, move-object, long-to-int */ 3748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB */ 3749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B from 15:12 3750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- A from 11:8 3751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B] 3753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, #15 3754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 3755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r2, r0) @ fp[A]<- r2 3756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute next instruction 3757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_FLOAT: /* 0x85 */ 3763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_FLOAT.S */ 3764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopNarrower.S */ 3765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0/r1", where 3768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 32-bit quantity in r0. 3769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: long-to-float, double-to-int, double-to-float 3771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (This would work for long-to-int, but that instruction is actually 3773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an exact match for OP_MOVE.) 3774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2f @ r0<- op, r0-r3 changed 3783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 3785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_LONG_TO_DOUBLE: /* 0x86 */ 3792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_LONG_TO_DOUBLE.S */ 3793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_l2d @ r0/r1<- op, r2-r3 changed 3810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_INT: /* 0x87 */ 3820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_INT.S */ 3821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funop.S */ 3822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary floating-point operation. Provide an "instr" 3824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * line that specifies an instruction that performs "s1 = op s0". 3825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: int-to-float, float-to-int 3827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizs s1, s0 @ s1<- op 3836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s1, [r9] @ vA<- s1 3839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_LONG: /* 0x88 */ 3845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_FLOAT_TO_LONG.S */ 3846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWider.S" {"instr":"bl __aeabi_f2lz"} 3847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWider.S */ 3848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = op r0", where 3851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "result" is a 64-bit quantity in r0/r1. 3852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-long, int-to-double, float-to-long, float-to-double 3854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl f2l_doconv @ r0<- op, r0-r3 changed 3863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9-10 instructions */ 3867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_FLOAT_TO_DOUBLE: /* 0x89 */ 3873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_FLOAT_TO_DOUBLE.S */ 3874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopWider.S */ 3875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32bit-to-64bit floating point unary operation. Provide an 3877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "d0 = op s0". 3878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: int-to-double, float-to-double 3880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r3] @ s0<- vB 3886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtds d0, s0 @ d0<- op 3889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d0, [r9] @ vA<- d0 3892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_INT: /* 0x8a */ 3898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_INT.S */ 3899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ftosizd s0, d0 @ s0<- op 3914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_LONG: /* 0x8b */ 3923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DOUBLE_TO_LONG.S */ 3924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@include "armv6t2/unopWide.S" {"instr":"bl __aeabi_d2lz"} 3925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unopWide.S */ 3926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit unary operation. Provide an "instr" line that 3928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0/r1". 3929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[B] 3937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 3938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vAA 3939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA<- r0/r1 3944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-11 instructions */ 3946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DOUBLE_TO_FLOAT: /* 0x8c */ 3953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DOUBLE_TO_FLOAT.S */ 3954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/funopNarrower.S */ 3955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64bit-to-32bit unary floating point operation. Provide an 3957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "instr" line that specifies an instruction that performs "s0 = op d0". 3958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: double-to-int, double-to-float 3960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 3964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 3965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r3] @ d0<- vB 3966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 3968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fcvtsd s0, d0 @ s0<- op 3969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 3971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s0, [r9] @ vA<- s0 3972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 3975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 3976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 3977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_BYTE: /* 0x8d */ 3978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_BYTE.S */ 3979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 3980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 3981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 3982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 3983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 3984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 3985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 3987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 3988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 3989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 3990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 3991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 3992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 3993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 3994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxtb r0, r0 @ r0<- op, r0-r3 changed 3995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 3996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 3997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 3998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 3999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_CHAR: /* 0x8e */ 4004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_CHAR.S */ 4005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden uxth r0, r0 @ r0<- op, r0-r3 changed 4021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INT_TO_SHORT: /* 0x8f */ 4030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_INT_TO_SHORT.S */ 4031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/unop.S */ 4032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit unary operation. Provide an "instr" line that 4034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = op r0". 4035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. 4036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 4038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * int-to-byte, int-to-char, int-to-short 4039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* unop vA, vB */ 4041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 4042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 4043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB 4044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 4046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sxth r0, r0 @ r0<- op, r0-r3 changed 4047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8-9 instructions */ 4051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT: /* 0x90 */ 4056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT.S */ 4057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 4088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT: /* 0x91 */ 4098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_INT.S */ 4099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 4130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT: /* 0x92 */ 4140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT.S */ 4141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 4142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 4173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT: /* 0x93 */ 4183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT.S */ 4184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 4215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT: /* 0x94 */ 4225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT.S */ 4226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 4227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 4260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT: /* 0x95 */ 4268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT.S */ 4269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 4300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT: /* 0x96 */ 4310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT.S */ 4311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 4342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT: /* 0x97 */ 4352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT.S */ 4353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 4384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT: /* 0x98 */ 4394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT.S */ 4395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT: /* 0x99 */ 4436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT.S */ 4437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT: /* 0x9a */ 4478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT.S */ 4479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 4480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 4482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 4483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 4488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 4490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 4494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 4501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 4502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 4504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 4509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 4512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 4514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG: /* 0x9b */ 4520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_LONG.S */ 4521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 4554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 4555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG: /* 0x9c */ 4565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SUB_LONG.S */ 4566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 4599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 4600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG: /* 0x9d */ 4610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_LONG.S */ 4611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply. 4613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * WX 4616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * x YZ 4617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * -------- 4618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * ZW ZX 4619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * YW YX 4620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The low word of the result holds ZX, the high word holds 4622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * it doesn't fit in the low 64 bits. 4624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Unlike most ARM math operations, multiply instructions have 4626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * restrictions on using the same register more than once (Rd and Rm 4627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * cannot be the same). 4628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long vAA, vBB, vCC */ 4630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 4638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 4639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #8 @ r0<- AA 4641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 4642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, rFP, r0, lsl #2 @ r0<- &fp[AA] 4643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_MUL_LONG_finish 4645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG: /* 0x9e */ 4649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_LONG.S */ 4650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG: /* 0x9f */ 4694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_LONG.S */ 4695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 4723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 4729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG: /* 0xa0 */ 4740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_LONG.S */ 4741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 4774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 4775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG: /* 0xa1 */ 4785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_LONG.S */ 4786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 4819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 4820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG: /* 0xa2 */ 4830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_LONG.S */ 4831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 4832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 4834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 4835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 4836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 4837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 4839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 4840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 4843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 4844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 4848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 4854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 4855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 4858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 4860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 4861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 4864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 4865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 4869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG: /* 0xa3 */ 4875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_LONG.S */ 4876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long vAA, vBB, vCC */ 4883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 4891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 4894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_finish 4900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG: /* 0xa4 */ 4904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_LONG.S */ 4905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long vAA, vBB, vCC */ 4912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_finish 4929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG: /* 0xa5 */ 4933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_LONG.S */ 4934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift. This is different from the generic 32/64-bit 4936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * binary operations because vAA/vBB are 64-bit but vCC (the shift 4937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6 bits of the shift distance. 4939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long vAA, vBB, vCC */ 4941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r0, #255 @ r3<- BB 4944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr #8 @ r0<- CC 4945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[BB] 4946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r0) @ r2<- vCC 4947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r0<- r0 & 0x3f 4949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 4950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 4952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 4953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 4955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_finish 4958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT: /* 0xa6 */ 4962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT.S */ 4963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 4970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 4971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 4972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 4973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 4974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 4975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 4976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 4977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 4978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 4979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 4980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 4982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 4983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 4984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 4985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 4986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 4987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 4989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 4990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 4991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT: /* 0xa7 */ 4992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT.S */ 4993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 4994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 4995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 4996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 4997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 4998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 4999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 5013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT: /* 0xa8 */ 5022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT.S */ 5023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 5043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT: /* 0xa9 */ 5052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT.S */ 5053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop.S */ 5054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating-point operation. Provide an "instr" line that 5056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "s2 = s0 op s1". Because we 5057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * use the "softfp" ABI, this must be an instruction, not a function call. 5058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float, sub-float, mul-float, div-float 5060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* floatop vAA, vBB, vCC */ 5062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vCC 5069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r2] @ s0<- vBB 5070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 5073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 5076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT: /* 0xaa */ 5082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_FLOAT.S */ 5083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 5084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binop.S */ 5085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit binary operation. Provide an "instr" line that 5087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0 op r1". 5088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. Note that we 5093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * *don't* check for (INT_MIN / -1) here, because the ARM math lib 5094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * handles it correctly. 5095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 5097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 5098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mul-float, div-float, rem-float 5099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vCC 5106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 5107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 5115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 11-14 instructions */ 5119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE: /* 0xab */ 5125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE.S */ 5126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ s2<- op 5146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE: /* 0xac */ 5155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE.S */ 5156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ s2<- op 5176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE: /* 0xad */ 5185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE.S */ 5186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ s2<- op 5206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE: /* 0xae */ 5215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE.S */ 5216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide.S */ 5217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit double-precision floating point binary operation. 5219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Provide an "instr" line that specifies an instruction that performs 5220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 5221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-double, sub-double, mul-double, div-double 5223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* doubleop vAA, vBB, vCC */ 5225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vCC 5230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r2, r2) @ r2<- &vBB 5231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vCC 5232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r2] @ d0<- vBB 5233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ s2<- op 5236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vAA 5238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 5239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE: /* 0xaf */ 5245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_DOUBLE.S */ 5246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 5247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopWide.S */ 5248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit binary operation. Provide an "instr" line that 5250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * specifies an instruction that performs "result = r0-r1 op r2-r3". 5251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * xor-long, add-double, sub-double, mul-double, div-double, 5259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double 5260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop vAA, vBB, vCC */ 5264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r0, 1) @ r0<- CCBB 5265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 5266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r0, #255 @ r2<- BB 5267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r0, lsr #8 @ r3<- CC 5268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 5269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] 5270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] 5271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 5278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 5281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 14-17 instructions */ 5285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_2ADDR: /* 0xb0 */ 5291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_2ADDR.S */ 5292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 5320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_INT_2ADDR: /* 0xb1 */ 5330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_INT_2ADDR.S */ 5331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r0, r0, r1 @ r0<- op, r0-r3 changed 5359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_2ADDR: /* 0xb2 */ 5369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_2ADDR.S */ 5370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 5399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_2ADDR: /* 0xb3 */ 5409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_2ADDR.S */ 5410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 5438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_2ADDR: /* 0xb4 */ 5448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_2ADDR.S */ 5449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 5450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 5480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_2ADDR: /* 0xb5 */ 5488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_2ADDR.S */ 5489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 5517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_2ADDR: /* 0xb6 */ 5527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_2ADDR.S */ 5528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 5556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_2ADDR: /* 0xb7 */ 5566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_2ADDR.S */ 5567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 5595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_2ADDR: /* 0xb8 */ 5605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_INT_2ADDR.S */ 5606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_2ADDR: /* 0xb9 */ 5644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_INT_2ADDR.S */ 5645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_2ADDR: /* 0xba */ 5683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_INT_2ADDR.S */ 5684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 5685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 5688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 5701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 5703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 5704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 5706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 5711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 5714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 5716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_LONG_2ADDR: /* 0xbb */ 5722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_LONG_2ADDR.S */ 5723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adds r0, r0, r2 @ optional op; may set condition codes 5752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adc r1, r1, r3 @ result<- op, r0-r3 changed 5753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_LONG_2ADDR: /* 0xbc */ 5763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SUB_LONG_2ADDR.S */ 5764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r0, r0, r2 @ optional op; may set condition codes 5793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sbc r1, r1, r3 @ result<- op, r0-r3 changed 5794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_LONG_2ADDR: /* 0xbd */ 5804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_LONG_2ADDR.S */ 5805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Signed 64-bit integer multiply, "/2addr" version. 5807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * See OP_MUL_LONG for an explanation. 5809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We get a little tight on registers, so to avoid looking up &fp[A] 5811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * again we stuff it into rINST. 5812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* mul-long/2addr vA, vB */ 5814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rINST, rFP, r9, lsl #2 @ rINST<- &fp[A] 5818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul ip, r2, r1 @ ip<- ZxW 5821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden umull r9, r10, r2, r0 @ r9/r10 <- ZxX 5822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST @ r0<- &fp[A] (free up rINST) 5824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r10, r2, r10 @ r10<- r10 + low(ZxW + (YxX)) 5826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 5828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_LONG_2ADDR: /* 0xbe */ 5834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_LONG_2ADDR.S */ 5835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_LONG_2ADDR: /* 0xbf */ 5875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_LONG_2ADDR.S */ 5876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 5900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 5906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_LONG_2ADDR: /* 0xc0 */ 5917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_LONG_2ADDR.S */ 5918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r2 @ optional op; may set condition codes 5947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, r3 @ result<- op, r0-r3 changed 5948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_LONG_2ADDR: /* 0xc1 */ 5958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_LONG_2ADDR.S */ 5959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 5960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 5961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 5964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 5965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 5967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 5968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 5969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 5972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 5973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 5974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 5975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 5976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 5977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 5978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 5979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 5982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 5984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 5985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 5986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r2 @ optional op; may set condition codes 5988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r3 @ result<- op, r0-r3 changed 5989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 5990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 5992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 5993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 5996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 5997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 5998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_LONG_2ADDR: /* 0xc2 */ 5999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_LONG_2ADDR.S */ 6000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r2 @ optional op; may set condition codes 6029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r1, r1, r3 @ result<- op, r0-r3 changed 6030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_LONG_2ADDR: /* 0xc3 */ 6040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHL_LONG_2ADDR.S */ 6041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shl-long/2addr vA, vB */ 6046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asl r2 @ r1<- r1 << r2 6054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 6056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 6059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 6060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHL_LONG_2ADDR_finish 6061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_LONG_2ADDR: /* 0xc4 */ 6065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_SHR_LONG_2ADDR.S */ 6066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* shr-long/2addr vA, vB */ 6071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 6084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 6085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_SHR_LONG_2ADDR_finish 6086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_LONG_2ADDR: /* 0xc5 */ 6090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_USHR_LONG_2ADDR.S */ 6091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 32-bit shift distance. 6094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* ushr-long/2addr vA, vB */ 6096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vB 6099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #63 @ r2<- r2 & 0x3f 6101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r2 @ r0<- r2 >> r2 6104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r3, r2, #32 @ r3<- 32 - r2 6105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 6106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs ip, r2, #32 @ ip<- r2 - 32 6107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 6109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 6110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_USHR_LONG_2ADDR_finish 6111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_FLOAT_2ADDR: /* 0xc6 */ 6115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_FLOAT_2ADDR.S */ 6116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fadds s2, s0, s1 @ s2<- op 6135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_FLOAT_2ADDR: /* 0xc7 */ 6143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_FLOAT_2ADDR.S */ 6144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubs s2, s0, s1 @ s2<- op 6163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_FLOAT_2ADDR: /* 0xc8 */ 6171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_FLOAT_2ADDR.S */ 6172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuls s2, s0, s1 @ s2<- op 6191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_FLOAT_2ADDR: /* 0xc9 */ 6199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_FLOAT_2ADDR.S */ 6200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinop2addr.S */ 6201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit floating point "/2addr" binary operation. Provide 6203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "s2 = s0 op s1". 6205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s1, [r3] @ s1<- vB 6214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden flds s0, [r9] @ s0<- vA 6217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivs s2, s0, s1 @ s2<- op 6219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsts s2, [r9] @ vAA<- s2 6221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_FLOAT_2ADDR: /* 0xca */ 6227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_FLOAT_2ADDR.S */ 6228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a float remainder function, but libm does */ 6229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binop2addr.S */ 6230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r3) @ r1<- vB 6248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r9) @ r0<- vA 6249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmodf @ r0<- op, r0-r3 changed 6257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_DOUBLE_2ADDR: /* 0xcb */ 6267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_ADD_DOUBLE_2ADDR.S */ 6268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden faddd d2, d0, d1 @ d2<- op 6288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SUB_DOUBLE_2ADDR: /* 0xcc */ 6296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_SUB_DOUBLE_2ADDR.S */ 6297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fsubd d2, d0, d1 @ d2<- op 6317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_DOUBLE_2ADDR: /* 0xcd */ 6325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_MUL_DOUBLE_2ADDR.S */ 6326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmuld d2, d0, d1 @ d2<- op 6346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_DOUBLE_2ADDR: /* 0xce */ 6354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/OP_DIV_DOUBLE_2ADDR.S */ 6355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: arm-vfp/fbinopWide2addr.S */ 6356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit floating point "/2addr" binary operation. Provide 6358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * an "instr" line that specifies an instruction that performs 6359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * "d2 = d0 op d1". 6360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * div-double/2addr 6363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 6366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- A+ 6367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r3, r3) @ r3<- &vB 6368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r9, r9, #15 @ r9<- A 6369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d1, [r3] @ d1<- vB 6370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden VREG_INDEX_TO_ADDR(r9, r9) @ r9<- &vA 6371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fldd d0, [r9] @ d0<- vA 6373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fdivd d2, d0, d1 @ d2<- op 6375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fstd d2, [r9] @ vAA<- d2 6377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_DOUBLE_2ADDR: /* 0xcf */ 6383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_DOUBLE_2ADDR.S */ 6384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* EABI doesn't define a double remainder function, but libm does */ 6385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopWide2addr.S */ 6386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * sub-double/2addr, mul-double/2addr, div-double/2addr, 6398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-double/2addr 6399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/2addr vA, vB */ 6401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 6402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rFP, r1, lsl #2 @ r1<- &fp[B] 6404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[A] 6405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(1) @ advance rPC, load rINST 6412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl fmod @ result<- op, r0-r3 changed 6415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 12-15 instructions */ 6419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT16: /* 0xd0 */ 6425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_ADD_INT_LIT16.S */ 6426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT: /* 0xd1 */ 6461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_RSUB_INT.S */ 6462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT16: /* 0xd2 */ 6498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_MUL_INT_LIT16.S */ 6499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT16: /* 0xd3 */ 6535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_DIV_INT_LIT16.S */ 6536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT16: /* 0xd4 */ 6571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_REM_INT_LIT16.S */ 6572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT16: /* 0xd5 */ 6608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_AND_INT_LIT16.S */ 6609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT16: /* 0xd6 */ 6644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_OR_INT_LIT16.S */ 6645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT16: /* 0xd7 */ 6680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_XOR_INT_LIT16.S */ 6681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/binopLit16.S */ 6682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit16 vA, vB, #+CCCC */ 6695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r1, 1) @ r1<- ssssCCCC (sign-extended) 6696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 6697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r9, rINST, #8, #4 @ r9<- A 6698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vB 6699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is second operand zero? 6701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 6706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-13 instructions */ 6710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_ADD_INT_LIT8: /* 0xd8 */ 6716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_ADD_INT_LIT8.S */ 6717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, r1 @ r0<- op, r0-r3 changed 6745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_RSUB_INT_LIT8: /* 0xd9 */ 6755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_RSUB_INT_LIT8.S */ 6756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_MUL_INT_LIT8: /* 0xda */ 6794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_MUL_INT_LIT8.S */ 6795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mul r0, r1, r0 @ r0<- op, r0-r3 changed 6824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_DIV_INT_LIT8: /* 0xdb */ 6834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_DIV_INT_LIT8.S */ 6835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idiv @ r0<- op, r0-r3 changed 6863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_REM_INT_LIT8: /* 0xdc */ 6873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_REM_INT_LIT8.S */ 6874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* idivmod returns quotient in r0 and remainder in r1 */ 6875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 6896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 6905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_AND_INT_LIT8: /* 0xdd */ 6913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_AND_INT_LIT8.S */ 6914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ r0<- op, r0-r3 changed 6942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_OR_INT_LIT8: /* 0xde */ 6952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_OR_INT_LIT8.S */ 6953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 6961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 6962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 6967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 6968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 6969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 6970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 6971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 6972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 6974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 6975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 6976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 6977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 6978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 6980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r0, r0, r1 @ r0<- op, r0-r3 changed 6981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 6982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 6983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 6984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 6985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 6988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 6989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 6990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_XOR_INT_LIT8: /* 0xdf */ 6991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_XOR_INT_LIT8.S */ 6992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 6993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 6994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 6996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 6997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 6998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 6999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ optional op; may set condition codes 7019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r0, r0, r1 @ r0<- op, r0-r3 changed 7020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHL_INT_LIT8: /* 0xe0 */ 7030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHL_INT_LIT8.S */ 7031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 7059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_SHR_INT_LIT8: /* 0xe1 */ 7069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_SHR_INT_LIT8.S */ 7070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 7098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_USHR_INT_LIT8: /* 0xe2 */ 7108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_USHR_INT_LIT8.S */ 7109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/binopLit8.S */ 7110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that specifies an instruction that performs "result = r0 op r1". 7113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This could be an ARM instruction or a function call. (If the result 7114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * comes back in a register other than r0, you can override "result".) 7115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If "chkzero" is set to 1, we perform a divide-by-zero check on 7117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * vCC (r1). Useful for integer division and modulus. 7118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* binop/lit8 vAA, vBB, #+CC */ 7124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_S(r3, 1) @ r3<- ssssCCBB (sign-extended for CC) 7125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, rINST, lsr #8 @ r9<- AA 7126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r3, #255 @ r2<- BB 7127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- vBB 7128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 7129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @cmp r1, #0 @ is second operand zero? 7131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errDivideByZero 7132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #31 @ optional op; may set condition codes 7136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 7137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 10-12 instructions */ 7141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E3: /* 0xe3 */ 7147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E3.S */ 7148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E4: /* 0xe4 */ 7156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E4.S */ 7157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E5: /* 0xe5 */ 7165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E5.S */ 7166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E6: /* 0xe6 */ 7174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E6.S */ 7175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E7: /* 0xe7 */ 7183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E7.S */ 7184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E8: /* 0xe8 */ 7192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E8.S */ 7193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_E9: /* 0xe9 */ 7201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_E9.S */ 7202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EA: /* 0xea */ 7210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EA.S */ 7211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_EB: /* 0xeb */ 7219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_EB.S */ 7220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 722796516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden.L_OP_BREAKPOINT: /* 0xec */ 722896516932f1557d8f48a8b2dbbb885af01a11ef6eAndy McFadden/* File: armv5te/OP_BREAKPOINT.S */ 7229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_THROW_VERIFICATION_ERROR: /* 0xed */ 7237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_THROW_VERIFICATION_ERROR.S */ 7238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle a throw-verification-error instruction. This throws an 7240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception for an error discovered during verification. The 7241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * exception is indicated by AA, with some detail provided by BBBB. 7242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op AA, ref@BBBB */ 7244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r2, 1) @ r2<- BBBB 7246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ export the PC 7247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- AA 7248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowVerificationError @ always throws 7249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ handle exception 7250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_EXECUTE_INLINE: /* 0xee */ 7255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_EXECUTE_INLINE.S */ 7256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Execute a "native inline" instruction. 7258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7259b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7260b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7262b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7263b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7264b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* [opt] execute-inline vAA, {vC, vD, vE, vF}, inline@BBBB */ 7267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 1) @ r10<- BBBB 7268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ can throw 7270b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rINST, lsr #12 @ r0<- B 7272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [sp] @ push &glue->retval 7273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl .LOP_EXECUTE_INLINE_continue @ make call; will return after 7274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ pop stack 7275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ test boolean result of inline 7276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ returned false, handle exception 7277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7283b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.L_OP_EXECUTE_INLINE_RANGE: /* 0xef */ 7284b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* File: armv5te/OP_EXECUTE_INLINE_RANGE.S */ 7285b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 7286b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Execute a "native inline" instruction, using "/range" semantics. 7287b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Same idea as execute-inline, but we get the args differently. 7288b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7289b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * We need to call an InlineOp4Func: 7290b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * bool (func)(u4 arg0, u4 arg1, u4 arg2, u4 arg3, JValue* pResult) 7291b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * 7292b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * The first four args are in r0-r3, pointer to return value storage 7293b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * is on the stack. The function's return value is a flag that tells 7294b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * us if an exception was thrown. 7295b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 7296b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* [opt] execute-inline/range {vCCCC..v(CCCC+AA-1)}, inline@BBBB */ 7297b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r10, 1) @ r10<- BBBB 7298b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &glue->retval 7299b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden EXPORT_PC() @ can throw 7300b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden sub sp, sp, #8 @ make room for arg, +64 bit align 7301b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden mov r0, rINST, lsr #8 @ r0<- AA 7302b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden str r1, [sp] @ push &glue->retval 7303b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl .LOP_EXECUTE_INLINE_RANGE_continue @ make call; will return after 7304b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add sp, sp, #8 @ pop stack 7305b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden cmp r0, #0 @ test boolean result of inline 7306b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden beq common_exceptionThrown @ returned false, handle exception 7307b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7308b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7309b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_DIRECT_EMPTY: /* 0xf0 */ 7314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_DIRECT_EMPTY.S */ 7315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invoke-direct-empty is a no-op in a "standard" interpreter. 7317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_F1: /* 0xf1 */ 7325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_F1.S */ 7326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_QUICK: /* 0xf2 */ 7334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_QUICK.S */ 7335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_WIDE_QUICK: /* 0xf3 */ 7353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IGET_WIDE_QUICK.S */ 7354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iget-wide-quick vA, vB, offset@CCCC */ 7355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) 7362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 7364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 7366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IGET_OBJECT_QUICK: /* 0xf4 */ 7372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_OBJECT_QUICK.S */ 7373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IGET_QUICK.S */ 7374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iget-quick, iget-object-quick */ 7375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- object we're operating on 7378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r1] @ r0<- obj.field (always 32 bits) 7383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 7387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_QUICK: /* 0xf5 */ 7394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_QUICK.S */ 7395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 7401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_WIDE_QUICK: /* 0xf6 */ 7413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv6t2/OP_IPUT_WIDE_QUICK.S */ 7414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* iput-wide-quick vA, vB, offset@CCCC */ 7415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #12 @ r1<- B 7416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r0, rINST, #8, #4 @ r0<- A 7417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r1) @ r2<- fp[B], the object pointer 7418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r0, lsl #2 @ r3<- &fp[A] 7419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ check object for null 7420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r3, {r0-r1} @ r0/r1<- fp[A] 7421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 1) @ r3<- field byte offset 7423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r2, r3] @ obj.field (64 bits, aligned)<- r0/r1 7425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_IPUT_OBJECT_QUICK: /* 0xf7 */ 7432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_OBJECT_QUICK.S */ 7433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_IPUT_QUICK.S */ 7434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* For: iput-quick, iput-object-quick */ 7435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vA, vB, offset@CCCC */ 7436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #12 @ r2<- B 7437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- fp[B], the object pointer 7438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- field byte offset 7439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ check object for null 7440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A(+) 7441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 7442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 7443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r2) @ r0<- fp[A] 7444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r3, r1] @ obj.field (always 32 bits)<- r0 7446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK: /* 0xf8 */ 7454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_VIRTUAL_QUICK_RANGE: /* 0xf9 */ 7479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK_RANGE.S */ 7480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_VIRTUAL_QUICK.S */ 7481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized virtual method call. 7483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-virtual-quick, invoke-virtual-quick/range 7485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r3, 2) @ r3<- FEDC or CCCC 7489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r3, r3, #15 @ r3<- C (or stays CCCC) 7492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r3) @ r2<- vC ("this" ptr) 7494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is "this" null? 7495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 7496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offObject_clazz] @ r2<- thisPtr->clazz 7497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- thisPtr->clazz->vtable 7498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ invoke must export 7499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r3<- vtable[BBBB] 7500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK: /* 0xfa */ 7506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) 7517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 7529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_INVOKE_SUPER_QUICK_RANGE: /* 0xfb */ 7534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK_RANGE.S */ 7535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_INVOKE_SUPER_QUICK.S */ 7536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Handle an optimized "super" method call. 7538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for: [opt] invoke-super-quick, invoke-super-quick/range 7540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r10, 2) @ r10<- GFED or CCCC 7544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 7545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) 7546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r10, r10, #15 @ r10<- D (or stays CCCC) 7547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 1) @ r1<- BBBB 7549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offMethod_clazz] @ r2<- method->clazz 7550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 7551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_super] @ r2<- method->clazz->super 7552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r10) @ r3<- "this" 7553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_vtable] @ r2<- ...clazz->super->vtable 7554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ null "this" ref? 7555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, r1, lsl #2] @ r0<- super->vtable[BBBB] 7556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ "this" is null, throw exception 7557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 7558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FC: /* 0xfc */ 7564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FC.S */ 7565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FD: /* 0xfd */ 7573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FD.S */ 7574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FE: /* 0xfe */ 7582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FE.S */ 7583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* ------------------------------ */ 7589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_OP_UNUSED_FF: /* 0xff */ 7591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/OP_UNUSED_FF.S */ 7592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/unused.S */ 7593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort 7594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 64 7599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmInstructionStart, .-dvmAsmInstructionStart 7600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmInstructionEnd 7601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmInstructionEnd: 7602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 7604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Sister implementations 7606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 7607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterStart 7609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmAsmSisterStart, %function 7610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 7611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 4 7612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterStart: 7613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING */ 7615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (String ref) 7619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_resolve: 7622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_STRING_JUMBO */ 7635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the String has not yet been resolved. 7638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBBBBBB (String ref) 7639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_STRING_JUMBO_resolve: 7642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveString @ r0<- String reference 7646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 7649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CONST_CLASS */ 7655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the Class has not yet been resolved. 7658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB (Class ref) 7659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: target register 7660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CONST_CLASS_resolve: 7662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 7663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- Class reference 7667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yup, handle the exception 7669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 7672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CHECK_CAST */ 7676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_fullcheck: 7684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_CHECK_CAST_okay @ no, success 7687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ A cast has failed. We need to throw a ClassCastException with the 7689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ class of the object that failed to be cast. 7690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ about to throw 7691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] @ r3<- obj->clazz 7692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .LstrClassCastExceptionPtr 7693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r3, #offClassObject_descriptor] @ r1<- obj->clazz->descriptor 7694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowExceptionWithClassMessage 7695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds BBBB 7701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 7702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CHECK_CAST_resolve: 7704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- BBBB 7707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 7714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_CHECK_CAST_resolved @ pick up where we left off 7715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastExceptionPtr: 7717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrClassCastException 7718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INSTANCE_OF */ 7721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test failed, need to perform full check. This is common. 7724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds obj->clazz 7725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds class resolved from BBBB 7726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_fullcheck: 7729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInstanceofNonTrivial @ r0<- boolean result 7730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_INSTANCE_OF_store 7731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds boolean result 7734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_store: 7737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Trivial test succeeded, save and bail. 7744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_trivial: 7747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #1 @ indicate success 7748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ could b OP_INSTANCE_OF_store, but copying is faster and cheaper 7749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vA<- r0 7751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r3 holds BBBB 7758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds A 7759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INSTANCE_OF_resolve: 7761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw 7762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] @ r0<- glue->method 7763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r3 @ r1<- BBBB 7764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #1 @ r2<- true 7765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offMethod_clazz] @ r0<- method->clazz 7766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 @ r1<- class resolved from BBB 7770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #12 @ r3<- B 7771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r3) @ r0<- vB (object) 7772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r0, #offObject_clazz] @ r0<- obj->clazz 7773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LOP_INSTANCE_OF_resolved @ pick up where we left off 7774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_INSTANCE */ 7777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .balign 32 @ minimize cache lines 7779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_finish: @ r0=new object 7780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ r3<- AA 7781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r3) @ vAA<- r0 7786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Class initialization required. 7790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class object 7792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_needinit: 7794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r0 @ save r0 7795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmInitClass @ initialize class 7796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ check boolean result 7797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ restore r0 7798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_initialized @ success, continue 7799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ failed, deal with init exception 7800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolution required. This is the least-likely path. 7803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds BBBB 7805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_INSTANCE_resolve: 7807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- resolved ClassObject ptr 7811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_NEW_INSTANCE_resolved @ no, continue 7813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 7814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationErrorPtr: 7816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInstantiationError 7817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_NEW_ARRAY */ 7820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Resolve class. (This is an uncommon case.) 7824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r2 holds class ref CCCC 7827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_resolve: 7829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 7830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ r9<- length (save) 7831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r2 @ r1<- CCCC 7832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #0 @ r2<- false 7833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 7834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveClass @ r0<- call(clazz, ref) 7835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 7836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ r1<- length (restore) 7837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle exception 7838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to OP_NEW_ARRAY_finish 7839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Finish allocation. 7842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 7843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds class 7844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 holds array length 7845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_NEW_ARRAY_finish: 7847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ don't track in local refs table 7848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(clazz, length, flags) 7849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ failed? 7850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 7851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ yes, handle the exception 7852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 7853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 7854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 7855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ vA<- r0 7856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 7857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY */ 7860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_continue: 7867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 7876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 7877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 7878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 7879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_notimpl @ no, not handled yet 7880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 7882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 7888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 7890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 7892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 7894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 7902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 7903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 7904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 7905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 7906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 7907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 7917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 7922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 7923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_notimpl: 7925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 7926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 7927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 7928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 7929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!0) @ define in one or the other, not both 7931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 7932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 7933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 7934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 7935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FILLED_NEW_ARRAY_RANGE */ 7939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 7941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 7942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds array class 7943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 holds AA or BA 7944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 7945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_continue: 7946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offClassObject_descriptor] @ r3<- arrayClass->descriptor 7947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #ALLOC_DONT_TRACK @ r2<- alloc flags 7948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r3, [r3, #1] @ r3<- descriptor[1] 7949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 7950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- AA (length) 7951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10, lsr #4 @ r1<- B (length) 7953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #'I' @ array of ints? 7955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'L' @ array of objects? 7956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmpne r3, #'[' @ array of arrays? 7957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r1 @ save length in r9 7958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_FILLED_NEW_ARRAY_RANGE_notimpl @ no, not handled yet 7959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAllocArrayByClass @ r0<- call(arClass, length, flags) 7960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ null return? 7961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_exceptionThrown @ alloc failed, handle exception 7962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- FEDC or CCCC 7964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_retval] @ retval.l <- new array 7965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r0, r0, #offArrayObject_contents @ r0<- newArray->contents 7966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ length--, check for neg 7967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance to next instr, load rINST 7968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi 2f @ was zero, bail 7969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ copy values from registers into the array 7971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=array, r1=CCCC/FEDC, r9=length (from AA or B), r10=AA/BA 7972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 1 7973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r1, lsl #2 @ r2<- &fp[CCCC] 7974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r3, [r2], #4 @ r3<- *r2++ 7975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .else 7980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #4 @ length was initially 5? 7981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r10, #15 @ r2<- A 7982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f @ <= 4 args, branch 7983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vA 7984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r9, r9, #1 @ count-- 7985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0, #16] @ contents[4] = vA 7986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and r2, r1, #15 @ r2<- F/E/D/C 7987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r3, r2) @ r3<- vF/vE/vD/vC 7988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr #4 @ r1<- next reg in low 4 7989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r9, r9, #1 @ count-- 7990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r0], #4 @ *contents++ = vX 7991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bpl 1b 7992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ continue at 2 7993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 7994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 7996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ ip<- opcode from rINST 7997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ execute it 7998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 7999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw an exception indicating that we have not implemented this 8001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * mode of filled-new-array. 8002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_FILLED_NEW_ARRAY_RANGE_notimpl: 8004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, .L_strInternalError 8005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, .L_strFilledNewArrayNotImpl 8006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 8007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 8008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if (!1) @ define in one or the other, not both 8010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strFilledNewArrayNotImpl: 8011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrFilledNewArrayNotImpl 8012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.L_strInternalError: 8013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrInternalError 8014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 8015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_FLOAT */ 8018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_FLOAT_finish: 8019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_FLOAT */ 8024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_FLOAT_finish: 8025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPL_DOUBLE */ 8030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPL_DOUBLE_finish: 8031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMPG_DOUBLE */ 8036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMPG_DOUBLE_finish: 8037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r9) @ vAA<- r0 8038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_CMP_LONG */ 8042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_less: 8044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, #0 @ r1<- -1 8045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Want to cond code the next mov so we can avoid branch, but don't see it; 8046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ instead, we just replicate the tail end. 8047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_greater: 8053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ r1<- 1 8054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ fall through to _finish 8055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_CMP_LONG_finish: 8057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r1, r9) @ vAA<- r1 8059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_AGET_WIDE */ 8064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_AGET_WIDE_finish: 8066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] 8069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 8071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_WIDE */ 8075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_WIDE_finish: 8077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 8079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r2, [r0, #offArrayObject_contents] @ r2/r3<- vBB[vCC] 8081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_APUT_OBJECT */ 8085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = vBB (arrayObj) 8088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = vAA (obj) 8089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = offset into array (vBB + vCC * width) 8090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_finish: 8092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ storing null reference? 8093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LOP_APUT_OBJECT_skip_check @ yes, skip type checks 8094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, #offObject_clazz] @ r0<- obj->clazz 8095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offObject_clazz] @ r1<- arrayObj->clazz 8096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCanPutArrayElement @ test object type vs. array type 8097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ okay? 8098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errArrayStore @ no 8099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_APUT_OBJECT_skip_check: 8100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offArrayObject_contents] @ vBB[vCC]<- vAA 8103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET */ 8107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_finish: 8114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8126a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_WIDE */ 8127a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8128a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_WIDE_finish: 8134a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrd r0, [r9, r3] @ r0/r1<- obj.field (64-bit align ok) 8138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8139a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8140a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r2, lsl #2 @ r3<- &fp[A] 8141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r3, {r0-r1} @ fp[A]<- r0/r1 8143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_OBJECT */ 8147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_OBJECT_finish: 8154a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8157a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8158a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8159a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8162a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BOOLEAN */ 8168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BOOLEAN_finish: 8175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_BYTE */ 8189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8190a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8191a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8194a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_BYTE_finish: 8196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8203a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8204a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8205a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8209a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_CHAR */ 8210a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8211a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8213a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8215a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8216a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_CHAR_finish: 8217a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8218a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8219a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8220a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8221a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8222a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8223a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8224a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8225a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8226a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8227a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8228a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8229a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8230a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IGET_SHORT */ 8231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8234a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8235a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IGET_SHORT_finish: 8238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8239a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8240a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8241a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8242a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r9, r3] @ r0<- obj.field (8/16/32 bits) 8243a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, rINST, lsr #8 @ r2<- A+ 8244a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8245a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, #15 @ r2<- A 8246a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8247a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SET_VREG(r0, r2) @ fp[A]<- r0 8248a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8249a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8250a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8251a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT */ 8252a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8253a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8254a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8255a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8256a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8257a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8258a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_finish: 8259a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8260a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8261a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r1, rINST, #8, #4 @ r1<- A 8262a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8263a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8264a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8265a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8266a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8267a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8268a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8269a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8270a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8271a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_WIDE */ 8272a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8273a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8274a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8275a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8276a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8277a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8278a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_WIDE_finish: 8279a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ubfx r2, rINST, #8, #4 @ r2<- A 8280a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8281a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8282a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r2, rFP, r2, lsl #2 @ r3<- &fp[A] 8283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmia r2, {r0-r1} @ r0/r1<- fp[A] 8286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden strd r0, [r9, r3] @ obj.field (64 bits, aligned)<- r0 8288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_OBJECT */ 8292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_OBJECT_finish: 8299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak0 8300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BOOLEAN */ 8313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BOOLEAN_finish: 8320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak1 8321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8324a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8325a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8326a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_BYTE */ 8334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_BYTE_finish: 8341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak2 8342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_CHAR */ 8355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8361a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_CHAR_finish: 8362a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak3 8363a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8364a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8365a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8366a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8368a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8370a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8371a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8372a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8373a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8374a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_IPUT_SHORT */ 8376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Currently: 8379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 holds resolved field 8380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 holds object 8381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_IPUT_SHORT_finish: 8383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_squeak4 8384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, rINST, lsr #8 @ r1<- A+ 8385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offInstField_byteOffset] @ r3<- byte offset of field 8386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r1, r1, #15 @ r1<- A 8387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r9, #0 @ check object for null 8388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r0, r1) @ r0<- fp[A] 8389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ object was null 8390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 8391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r9, r3] @ obj.field (8/16/32 bits)<- r0 8393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET */ 8397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_resolve: 8403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_finish @ yes, finish 8409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_WIDE */ 8413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_WIDE_resolve: 8419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_WIDE_finish @ yes, finish 8425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_OBJECT */ 8429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_OBJECT_resolve: 8435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_OBJECT_finish @ yes, finish 8441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BOOLEAN */ 8445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BOOLEAN_resolve: 8451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BOOLEAN_finish @ yes, finish 8457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_BYTE */ 8461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_BYTE_resolve: 8467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_BYTE_finish @ yes, finish 8473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_CHAR */ 8477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_CHAR_resolve: 8483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_CHAR_finish @ yes, finish 8489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SGET_SHORT */ 8493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SGET_SHORT_resolve: 8499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SGET_SHORT_finish @ yes, finish 8505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT */ 8509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_resolve: 8515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_finish @ yes, finish 8521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_WIDE */ 8525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9: &fp[AA] 8530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_WIDE_resolve: 8532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_WIDE_finish @ yes, finish 8538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_OBJECT */ 8542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8546a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_OBJECT_resolve: 8548a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_OBJECT_finish @ yes, finish 8554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BOOLEAN */ 8558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BOOLEAN_resolve: 8564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BOOLEAN_finish @ yes, finish 8570a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8571a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8572a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8573a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_BYTE */ 8574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8576a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8578a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8579a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_BYTE_resolve: 8580a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8583a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8584a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8585a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_BYTE_finish @ yes, finish 8586a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_CHAR */ 8590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8593a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8594a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_CHAR_resolve: 8596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_CHAR_finish @ yes, finish 8602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SPUT_SHORT */ 8606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Continuation if the field has not yet been resolved. 8609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1: BBBB field ref 8610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SPUT_SHORT_resolve: 8612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_method] @ r2<- current method 8613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ resolve() could throw, so export now 8614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r2, #offMethod_clazz] @ r0<- method->clazz 8615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveStaticField @ r0<- resolved StaticField ptr 8616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ success? 8617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_SPUT_SHORT_finish @ yes, finish 8618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ no, handle exception 8619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL */ 8622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_continue: 8629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER */ 8640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_continue: 8647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_nsm @ method not present in superclass 8653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodNoRange @ continue on 8656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_resolve: 8658a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8662a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_continue @ no, continue 8663a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8664a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_nsm: 8670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT */ 8675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_resolve: 8682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_finish @ no, continue 8689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_VIRTUAL_RANGE */ 8693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = C or CCCC (index of first arg, which is the "this" ptr) 8698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_VIRTUAL_RANGE_continue: 8700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r1, r10) @ r1<- "this" ptr 8701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ is "this" null? 8703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_errNullObject @ null "this", throw exception 8704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offObject_clazz] @ r1<- thisPtr->clazz 8705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_vtable] @ r3<- thisPtr->clazz->vtable 8706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, r2, lsl #2] @ r3<- vtable[methodIndex] 8707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_SUPER_RANGE */ 8711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * At this point: 8714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 = method->clazz 8716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_continue: 8718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offClassObject_super] @ r1<- method->clazz->super 8719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r2, [r0, #offMethod_methodIndex] @ r2<- baseMethod->methodIndex 8720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offClassObject_vtableCount] @ r3<- super->vtableCount 8721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ must export for invoke 8722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, r3 @ compare (methodIndex, vtableCount) 8723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bcs .LOP_INVOKE_SUPER_RANGE_nsm @ method not present in superclass 8724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offClassObject_vtable] @ r1<- ...clazz->super->vtable 8725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r1, r2, lsl #2] @ r3<- vtable[methodIndex] 8726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_invokeMethodRange @ continue on 8727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_resolve: 8729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- method->clazz 8730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_VIRTUAL @ resolver method type 8731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_SUPER_RANGE_continue @ no, continue 8734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Throw a NoSuchMethodError with the method name as the message. 8738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = resolved base method 8739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_SUPER_RANGE_nsm: 8741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_name] @ r1<- method name 8742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_errNoSuchMethod 8743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_INVOKE_DIRECT_RANGE */ 8746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 8749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 = reference (BBBB or CCCC) 8750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = "this" register 8751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_INVOKE_DIRECT_RANGE_resolve: 8753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_method] @ r3<- glue->method 8754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [r3, #offMethod_clazz] @ r0<- method->clazz 8755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, #METHOD_DIRECT @ resolver method type 8756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmResolveMethod @ r0<- call(clazz, ref, flags) 8757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ got null? 8758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_VREG(r2, r10) @ r2<- "this" ptr (reload) 8759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LOP_INVOKE_DIRECT_RANGE_finish @ no, continue 8760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown @ yes, handle exception 8761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_FLOAT_TO_LONG */ 8764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the float in r0 to a long in r0/r1. 8766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenf2l_doconv: 8772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, lr} 8773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0x5f000000 @ (float)maxlong 8774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r4, r0 8775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpge @ is arg >= maxlong? 8776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffff) 8778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0xdf000000 @ (float)minlong 8783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmple @ is arg <= minlong? 8784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (80000000) 8786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmnefd sp!, {r4, pc} 8788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r4 8791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_fcmpeq @ is arg == self? 8792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmeqfd sp!, {r4, pc} 8795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_f2lz @ convert float to long 8798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, pc} 8799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_DOUBLE_TO_LONG */ 8802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Convert the double in r0/r1 to a long in r0/r1. 8804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We have to clip values to long min/max per the specification. The 8806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * expected common case is a "reasonable" value that converts directly 8807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to modest integer. The EABI convert function isn't doing this for us. 8808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddend2l_doconv: 8810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r4, r5, lr} @ save regs 88115162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0x43000000 @ maxlong, as a double (high word) 88125162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0x43e00000 88135162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ maxlong, as a double (low word) 8814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #4 @ align for EABI 88155162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r4, r0 @ save a copy of r0 8816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r5, r1 @ and r1 8817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpge @ is arg >= maxlong? 8818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r0, #0 @ return maxlong (7fffffffffffffff) 8820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvnne r1, #0x80000000 8821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 88255162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r3, #0xc3000000 @ minlong, as a double (high word) 88265162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden add r3, #0x00e00000 @ 0xc3e00000 88275162c5fbc20b7ba7791e79c640ac51b9fcd7937aAndy McFadden mov r2, #0 @ minlong, as a double (low word) 8828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmple @ is arg <= minlong? 8829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ nonzero == yes 8830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, #0 @ return minlong (8000000000000000) 8831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r1, #0x80000000 8832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1f 8833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r4 @ compare against self 8837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r5 8838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_dcmpeq @ is arg == self? 8839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ zero == no 8840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden moveq r1, #0 @ return zero for NaN 8841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f 8842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r4 @ recover arg 8844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r5 8845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __aeabi_d2lz @ convert double to long 8846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 8848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #4 8849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r4, r5, pc} 8850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_MUL_LONG */ 8853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_MUL_LONG_finish: 8855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r0, {r9-r10} @ vAA/vAA+1<- r9/r10 8857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG */ 8861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_finish: 8863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0, asl r2 @ r0<- r0 << r2 8864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG */ 8870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_finish: 8872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr r2 @ r1<- r1 >> r2 8873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG */ 8879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_finish: 8881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, lsr r2 @ r1<- r1 >>> r2 8882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHL_LONG_2ADDR */ 8888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHL_LONG_2ADDR_finish: 8890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_SHR_LONG_2ADDR */ 8896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_SHR_LONG_2ADDR_finish: 8898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_USHR_LONG_2ADDR */ 8904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_USHR_LONG_2ADDR_finish: 8906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 8907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 8908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 8909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* continuation for OP_EXECUTE_INLINE */ 8912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 8914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Extract args, call function. 8915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 = #of args (0-4) 8916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r10 = call index 8917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 8919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Other ideas: 8920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Use a jump table from the main piece to jump directly into the 8921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * AND/LDR pairs. Costs a data load, saves a branch. 8922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * - Have five separate pieces that do the loading, so we can work the 8923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interleave a little better. Increases code size. 8924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_continue: 8926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r9, 2) @ r9<- FEDC 8928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 8930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r9, #0xf000 @ isolate F 8931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2) 8932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r9, #0x0f00 @ isolate E 8933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vE 8934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r9, #0x00f0 @ isolate D 8935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rFP, ip, lsr #2] @ r1<- vD 8936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r9, #0x000f @ isolate C 8937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rFP, ip, lsl #2] @ r0<- vC 8938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: 8939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, .LOP_EXECUTE_INLINE_table @ table of InlineOperation 8940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 8941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (not reached) 8942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LOP_EXECUTE_INLINE_table: 8944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word gDvmInlineOpsTable 8945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8947b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden/* continuation for OP_EXECUTE_INLINE_RANGE */ 8948b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 8949b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden /* 8950b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * Extract args, call function. 8951b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r0 = #of args (0-4) 8952b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * r10 = call index 8953b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden * lr = return addr, above [DO NOT bl out of here w/o preserving LR] 8954b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden */ 8955b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_continue: 8956b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden rsb r0, r0, #4 @ r0<- 4-r0 8957b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden FETCH(r9, 2) @ r9<- CCCC 8958b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden add pc, pc, r0, lsl #3 @ computed goto, 2 instrs each 8959b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden bl common_abort @ (skipped due to ARM prefetch) 8960b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden4: add ip, r9, #3 @ base+3 8961b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r3, ip) @ r3<- vBase[3] 8962b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden3: add ip, r9, #2 @ base+2 8963b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r2, ip) @ r2<- vBase[2] 8964b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden2: add ip, r9, #1 @ base+1 8965b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r1, ip) @ r1<- vBase[1] 8966b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden1: add ip, r9, #0 @ (nop) 8967b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden GET_VREG(r0, ip) @ r0<- vBase[0] 8968b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden0: 8969b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden ldr r9, .LOP_EXECUTE_INLINE_RANGE_table @ table of InlineOperation 8970b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden LDR_PC "[r9, r10, lsl #4]" @ sizeof=16, "func" is first entry 8971b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden @ (not reached) 8972b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 8973b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden.LOP_EXECUTE_INLINE_RANGE_table: 8974b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden .word gDvmInlineOpsTable 8975b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 8976b0a0541b59d1126ff77c88de742b4a74579fe296Andy McFadden 8977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .size dvmAsmSisterStart, .-dvmAsmSisterStart 8978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmAsmSisterEnd 8979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmAsmSisterEnd: 8980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* File: armv5te/footer.S */ 8982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 8984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 8985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common subroutines and data 8986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * =========================================================================== 8987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 8988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .text 8992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 8993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 8994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 899597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 899697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpPunt 899797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpPunt: 899897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSPunt @ r2<- interpreter entry point 899997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 900097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 900197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpSingleStep 900297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpSingleStep: 900397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSSingleStep @ r2<- interpreter entry point 900497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 900597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 900697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToTraceSelect 900797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToTraceSelect: 90089a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 900997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSTraceSelect @ r2<- interpreter entry point 901097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 901197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 901297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToBackwardBranch 901397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToBackwardBranch: 90149a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 901597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSBackwardBranch @ r2<- interpreter entry point 901697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 901797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 901897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNormal 901997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNormal: 90209a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr r0,[lr, #-1] @ pass our target PC 902197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNormal @ r2<- interpreter entry point 902297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 902397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 902497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao .global dvmJitToInterpNoChain 902597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitToInterpNoChain: 902697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ pass our target PC 902797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kSVSNoChain @ r2<- interpreter entry point 902897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b dvmJitSelfVerificationEnd @ doesn't return 902997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 9030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter when the compiler is 9032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * having issues translating/executing a Dalvik instruction. We have to skip 9033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the code cache lookup otherwise it is possible to indefinitely bouce 9034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * between the interpreter and the code cache if the instruction that fails 9035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to be compiled happens to be at a trace start. 9036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpPunt 9038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpPunt: 90397a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r0 9041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 9042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,lr 9043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpPunt; 9044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 90467a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r0, #0 90477a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ Back to the interp land 9048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return to the interpreter to handle a single instruction. 9055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 <= PC 9057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 <= PC of resume instruction 9058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * lr <= resume point in translation 9059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpSingleStep 9061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpSingleStep: 9062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str lr,[rGLUE,#offGlue_jitResume] 9063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1,[rGLUE,#offGlue_jitResumePC] 9064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#kInterpEntryInstr 9065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ enum is 4 byte in aapcs-EABI 9066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_entryPoint] 9067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC,r0 9068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 90697a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng 9070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitSingleStep @ Ask for single step and then revert 9072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp to bail to debug interp 9074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache and immediately request 9079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a translation for the exit target. Commonly used following 9080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * invokes. 9081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToTraceSelect 9083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToTraceSelect: 90849a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 90857a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 90869a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 90887a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng bl dvmJitGetCodeAddr @ Is there a translation? 90897a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 2f 9092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 90949a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 90959a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* No translation, so request one if profiling isn't disabled*/ 9101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: 9102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 9106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_selectTrace 9107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9108a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9109a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9110a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9111a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter. 9112a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The return was done with a BLX from thumb mode, and 9113a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the following 32-bit word contains the target rPC value. 9114a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Note that lr (r14) will have its low-order bit set to denote 9115a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * its thumb-mode origin. 9116a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9117a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We'll need to stash our lr origin away, recover the new 9118a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * target and then check to see if there is a translation available 9119a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * for our new target. If so, we do a translation chain and 9120a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * go back to native execution. Otherwise, it's back to the 9121a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * interpreter (after treating this entry as a potential 9122a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace start). 9123a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9124a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNormal 9125a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNormal: 91269a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee ldr rPC,[lr, #-1] @ get our target PC 91277a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 91289a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee add rINST,lr,#-5 @ save start of chain branch 9129a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 9130a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNormal 9131a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9132a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9133a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 91347a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 9135a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9136a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq toInterpreter @ go if not, otherwise do chain 9137a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,rINST 9138a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitChain @ r0<- dvmJitChain(codeAddr,chainAddr) 91399a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91409a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9141a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 @ successful chain? 9142a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution 9143a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b toInterpreter @ didn't chain - resume with interpreter 9144a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9145a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9146a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return from the translation cache to the interpreter to do method invocation. 9147a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Check if translation exists for the callee, but don't chain to it. 9148a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9149a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmJitToInterpNoChain 9150a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmJitToInterpNoChain: 9151a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EXIT_STATS 9152a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmBumpNoChain 9153a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 91547a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 9155a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9156a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ Is there a translation? 91577a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 91589a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r1, rPC @ arg1 of translation may need this 91599a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov lr, #0 @ in case target is HANDLER_INTERPRET 9160a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9161a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ continue native execution if so 916297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 9163a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9164a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9165a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * No translation, restore interpreter regs and start interpreting. 9166a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * rGLUE & rFP were preserved in the translated code, and rPC has 9167a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * already been restored by the time we get here. We'll need to set 9168a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * up rIBASE & rINST, and load the address of the JitTable into r0. 9169a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9170a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddentoInterpreter: 9171a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9172a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden adrl rIBASE, dvmAsmInstructionStart 9173a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() 9174a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9175a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ NOTE: intended fallthrough 9176a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9177a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code to update potential trace start counter, and initiate 9178a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * a trace-build if appropriate. On entry, rPC should point to the 9179a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * next instruction to execute, and rINST should be already loaded with 9180a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * the next opcode word, and r0 holds a pointer to the jit profile 9181a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * table (pJitProfTable). 9182a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9183a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_testUpdateProfile: 9184a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9185a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9186a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFEQ(ip) @ if not profiling, fallthrough otherwise */ 9187a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9188a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_updateProfile: 9189a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden eor r3,rPC,rPC,lsr #12 @ cheap, but fast hash function 91909797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee lsl r3,r3,#21 @ shift out excess 2047 91919797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee ldrb r1,[r0,r3,lsr #21] @ get counter 9192a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9193a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r1,r1,#1 @ decrement counter 91949797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ and store it 9195a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE_IFNE(ip) @ if not threshold, fallthrough otherwise */ 9196a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9197a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9198a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Here, we switch to the debug interpreter to request 9199a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * trace selection. First, though, check to see if there 9200a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * is already a native translation in place (and, if so, 9201a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * jump to it now). 9202a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9203d726991ba52466cde88e37aba4de2395b62477faBill Buzbee GET_JIT_THRESHOLD(r1) 92047a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [rGLUE, #offGlue_self] @ callee saved r10 <- glue->self 92059797a237b48e880c33e2a2f497f48fb6f67c7a16Bill Buzbee strb r1,[r0,r3,lsr #21] @ reset counter 9206a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9207a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0,rPC 9208a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmJitGetCodeAddr @ r0<- dvmJitGetCodeAddr(rPC) 92097a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r0, [r10, #offThread_inJitCodeCache] @ set the inJitCodeCache flag 92107a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov r1, rPC @ arg1 of translation may need this 92117a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng mov lr, #0 @ in case target is HANDLER_INTERPRET 9212a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 921397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if !defined(WITH_SELF_VERIFICATION) 9214a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bxne r0 @ jump to the translation 921597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#else 92169a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee beq common_selectTrace 92179a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* 92189a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * At this point, we have a target translation. However, if 92199a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * that translation is actually the interpret-only pseudo-translation 92209a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * we want to treat it the same as no translation. 92219a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee */ 92229a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r10, r0 @ save target 92239a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bl dvmCompilerGetInterpretTemplate 92249a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee cmp r0, r10 @ special case? 92259a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee bne dvmJitSelfVerificationStart @ set up self verification 92269a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GET_INST_OPCODE(ip) 92279a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee GOTO_OPCODE(ip) 92289a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee /* no return */ 922997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 92309a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee 9231a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_selectTrace: 9232a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitTSelectRequest @ ask for trace selection 9233a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 92349c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng mov r2,#kInterpEntryInstr @ normal entry reason 92359c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r2,[rGLUE,#offGlue_entryPoint] 9236a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1,#1 @ set changeInterp 9237a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9238a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 923997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#if defined(WITH_SELF_VERIFICATION) 924097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 924197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Save PC and registers to shadow memory for self verification mode 924297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping to native translation. 92439a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee * On entry, r10 contains the address of the target translation. 924497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 924597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationStart: 924697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r0,rPC @ r0<- program counter 924797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ r1<- frame pointer 924897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,rGLUE @ r2<- InterpState pointer 92499a8c75adb2abf551d06dbf757bff558c1feded08Bill Buzbee mov r3,r10 @ r3<- target translation 925097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationSaveState @ save registers to shadow space 9251ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_shadowFP] @ rFP<- fp in shadow space 9252ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng add rGLUE,r0,#offShadowSpace_interpState @ rGLUE<- rGLUE in shadow space 9253ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng bx r10 @ jump to the translation 925497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 925597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao/* 925697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * Restore PC, registers, and interpState to original values 925797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao * before jumping back to the interpreter. 925897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao */ 925997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff HaodvmJitSelfVerificationEnd: 926097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,rFP @ pass ending fp 926197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao bl dvmSelfVerificationRestoreState @ restore pc and fp values 9262ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rPC,[r0,#offShadowSpace_startPC] @ restore PC 9263ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rFP,[r0,#offShadowSpace_fp] @ restore FP 9264ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr rGLUE,[r0,#offShadowSpace_glue] @ restore InterpState 9265ccd6c0102d1f898aaea1c94761167fdd083b5275Ben Cheng ldr r1,[r0,#offShadowSpace_svState] @ get self verification state 926697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao cmp r1,#0 @ check for punt condition 926797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao beq 1f 926897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r2,#kJitSelfVerification @ ask for self verification 926997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao str r2,[rGLUE,#offGlue_jitState] 927030f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng mov r2,#kInterpEntryInstr @ normal entry reason 927130f1f463b132c7b6daf2de825c5fa44ce356ca13Ben Cheng str r2,[rGLUE,#offGlue_entryPoint] 927297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao mov r1,#1 @ set changeInterp 927397319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao b common_gotoBail 927497319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 927597319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao1: @ exit to interpreter without check 927697319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao EXPORT_PC() 927797319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao adrl rIBASE, dvmAsmInstructionStart 927897319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao FETCH_INST() 927997319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GET_INST_OPCODE(ip) 928097319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao GOTO_OPCODE(ip) 928197319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao#endif 928297319a8a234e9fe1cf90ca39aa6eca37d729afd5Jeff Hao 9283a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9284a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9285a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9286a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code when a backward branch is taken. 9287a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9288a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9289a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is PC adjustment *in bytes* 9290a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9291a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_backwardBranch: 9292a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryInstr 9293a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9294a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9295a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9296a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9297a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9298a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9299a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) 9300a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) 9301a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9302a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST_RB(r9) @ update rPC, load rINST 9303a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9304a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9305a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9306a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9307a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9308a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9309a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Need to see if the thread needs to be suspended or debugger/profiler 9310a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * activity has begun. 9311a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9312a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: if JDWP isn't running, zero out pDebuggerActive pointer so we don't 9313a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * have to do the second ldr. 9314a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9315a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: reduce this so we're just checking a single location. 9316a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9317a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9318a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is reentry type, e.g. kInterpEntryInstr 9319a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is trampoline PC adjustment *in bytes* 9320a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9321a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_periodicChecks: 9322a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_pSelfSuspendCount] @ r3<- &suspendCount 9323a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 93249c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng @ speculatively store r0 before it is clobbered by dvmCheckSuspendPending 93259c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng str r0, [rGLUE, #offGlue_entryPoint] 93269c147b84ff7fe2c39228742b06a9ef180d39b48fBen Cheng 9327a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9328a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_pDebuggerActive] @ r1<- &debuggerActive 9329a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9330a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_PROFILER) 9331a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_pActiveProfilers] @ r2<- &activeProfilers 9332a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9333a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9334a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3] @ r3<- suspendCount (int) 9335a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9336a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) 9337a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r1] @ r1<- debuggerActive (boolean) 9338a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9339a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined (WITH_PROFILER) 9340a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2] @ r2<- activeProfilers (int) 9341a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9342a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9343a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, #0 @ suspend pending? 9344a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 2f @ yes, do full suspension check 9345a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9346a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_DEBUGGER) || defined(WITH_PROFILER) 9347a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# if defined(WITH_DEBUGGER) && defined(WITH_PROFILER) 9348a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orrs r1, r1, r2 @ r1<- r1 | r2 9349a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached or profiler started? 9350a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_DEBUGGER) 9351a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ debugger attached? 9352a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# elif defined(WITH_PROFILER) 9353a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ profiler started? 9354a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden# endif 9355a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 3f @ debugger/profiler, switch interp 9356a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9357a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9358a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr @ nothing to do, return 9359a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9360a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: @ check suspend 9361964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9362964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee /* 9363964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * Refresh the Jit's cached copy of profile table pointer. This pointer 9364964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee * doubles as the Jit's on/off switch. 9365964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee */ 9366964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ r10<-&gDvmJit.pJitProfTable 9367a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9368964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r10 <- pJitProfTable 9369a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() @ need for precise GC 9370964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh Jit's on/off switch 9371964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#else 9372964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r0, [rGLUE, #offGlue_self] @ r0<- glue->self 9373964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee EXPORT_PC() @ need for precise GC 9374964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9375a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmCheckSuspendPending @ suspend if necessary, then return 9376a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9377a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: @ debugger/profiler enabled, bail out 9378a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, rPC, r9 @ update rPC 9379a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #1 @ "want switch" = true 9380a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail 9381a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9382a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9383a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9384a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * The equivalent of "goto bail", this calls through the "bail handler". 9385a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9386a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * State registers will be saved to the "glue" area before bailing. 9387a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9388a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9389a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r1 is "bool changeInterp", indicating if we want to switch to the 9390a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * other interpreter or just bail all the way out 9391a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9392a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_gotoBail: 9393a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9394a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ r0<- glue ptr 9395a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b dvmMterpStdBail @ call(glue, changeInterp) 9396a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9397a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r1, r1, #1 @ using (boolean+1) 9398a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @add r0, rGLUE, #offGlue_jmpBuf @ r0<- &glue->jmpBuf 9399a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl _longjmp @ does not return 9400a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @bl common_abort 9401a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9402a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9403a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9404a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation with range. 9405a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9406a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9407a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9408a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9409a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodRange: 9410a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewRange: 9411a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9412a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #8 @ r2<- AA (arg count) -- test for zero 9413a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9414a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone @ if no args, skip the rest 9415a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- CCCC 9416a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9417a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=CCCC, r2=count, r10=outs 9418a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ (very few methods have > 10 args; could unroll for common cases) 9419a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r3, rFP, r1, lsl #2 @ r3<- &fp[CCCC] 9420a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r10, r10, r2, lsl #2 @ r10<- "outs" area, for call args 9421a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9422a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: ldr r1, [r3], #4 @ val = *fp++ 9423a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden subs r2, r2, #1 @ count-- 9424a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r10], #4 @ *outs++ = val 9425a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne 1b @ ...while count != 0 9426a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9427a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .LinvokeArgsDone 9428a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9429a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9430a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation without range. 9431a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9432a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9433a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9434a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9435a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_invokeMethodNoRange: 9436a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNewNoRange: 9437a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ prepare to copy args to "outs" area of current frame 9438a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movs r2, rINST, lsr #12 @ r2<- B (arg count) -- test for zero 9439a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, rFP) @ r10<- stack save area 9440a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(r1, 2) @ r1<- GFED (load here to hide latency) 9441a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r0, #offMethod_registersSize] @ r9<- methodToCall->regsSize 9442a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r3, [r0, #offMethod_outsSize] @ r3<- methodToCall->outsSize 9443a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq .LinvokeArgsDone 9444a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9445a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=GFED, r3=outSize, r2=count, r9=regSize, r10=outs 9446a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNonRange: 9447a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden rsb r2, r2, #5 @ r2<- 5-r2 9448a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add pc, pc, r2, lsl #4 @ computed goto, 4 instrs each 9449a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_abort @ (skipped due to ARM prefetch) 9450a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden5: and ip, rINST, #0x0f00 @ isolate A 9451a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vA (shift right 8, left 2) 9452a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9453a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vA 9454a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden4: and ip, r1, #0xf000 @ isolate G 9455a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #10] @ r2<- vG (shift right 12, left 2) 9456a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9457a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vG 9458a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden3: and ip, r1, #0x0f00 @ isolate F 9459a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #6] @ r2<- vF 9460a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9461a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vF 9462a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden2: and ip, r1, #0x00f0 @ isolate E 9463a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsr #2] @ r2<- vE 9464a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9465a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vE 9466a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: and ip, r1, #0x000f @ isolate D 9467a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, ip, lsl #2] @ r2<- vD 9468a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r0 @ nop 9469a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [r10, #-4]! @ *--outs = vD 9470a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden0: @ fall through to .LinvokeArgsDone 9471a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9472a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeArgsDone: @ r0=methodToCall, r3=outSize, r9=regSize 9473a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r0, #offMethod_insns] @ r2<- method->insns 9474a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rINST, [r0, #offMethod_clazz] @ rINST<- method->clazz 9475a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ find space for the new stack frame, check for overflow 9476a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- stack save area 9477a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, r1, r9, lsl #2 @ r1<- newFp (old savearea - regsSize) 9478a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r10, r1) @ r10<- newSaveArea 9479a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden@ bl common_dumpRegs 9480a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [rGLUE, #offGlue_interpStackEnd] @ r9<- interpStackEnd 9481a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r3, r10, r3, lsl #2 @ r3<- bottom (newsave - outsSize) 9482a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r3, r9 @ bottom < interpStackEnd? 9483a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r0, #offMethod_accessFlags] @ r3<- methodToCall->accessFlags 9484a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blt .LstackOverflow @ yes, this frame will overflow stack 9485a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9486a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ set up newSaveArea 9487a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef EASY_GDB 9488a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(ip, rFP) @ ip<- stack save area 9489a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [r10, #offStackSaveArea_prevSave] 9490a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9491a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r10, #offStackSaveArea_prevFrame] 9492a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rPC, [r10, #offStackSaveArea_savedPc] 9493a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9494a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9495a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offStackSaveArea_returnAddr] 9496a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9497a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [r10, #offStackSaveArea_method] 9498a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden tst r3, #ACC_NATIVE 9499a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne .LinvokeNative 9500a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9501a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9502a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9503a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9504a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP 9505a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9506a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9507a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9508a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0-r3} 9509a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 9510a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 9511a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmDumpFp 9512a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_printNewline 9513a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0-r3} 9514a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9515a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9516a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrh r9, [r2] @ r9 <- load INST from new PC 9517a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rINST, #offClassObject_pDvmDex] @ r3<- method->clazz->pDvmDex 9518a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r2 @ publish new rPC 9519a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rGLUE, #offGlue_self] @ r2<- glue->self 9520a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9521a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Update "glue" values for the new method 9522a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r2=self, r3=newMethodClass, r9=newINST 9523a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [rGLUE, #offGlue_method] @ glue->method = methodToCall 9524a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [rGLUE, #offGlue_methodClassDex] @ glue->methodClassDex = ... 9525a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9526a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9527a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9528a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9529a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9530a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9531a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9532a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9533a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9534a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9535a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r1 @ fp = newFp 9536a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_PREFETCHED_OPCODE(ip, r9) @ extract prefetched opcode from r9 9537a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rINST, r9 @ publish new rINST 9538a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r2, #offThread_curFrame] @ self->curFrame = newFp 9539a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9540a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9541a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9542a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeNative: 9543a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ Prep for the native call 9544a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r0=methodToCall, r1=newFp, r10=newSaveArea 9545a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9546d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r9, [r3, #offThread_jniLocal_topCookie] @ r9<- thread->localRef->... 9547a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [r3, #offThread_curFrame] @ self->curFrame = newFp 9548d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r9, [r10, #offStackSaveArea_localRefCookie] @newFp->localRefCookie=top 9549a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, r3 @ r9<- glue->self (preserve) 9550a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9551a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ r2<- methodToCall 9552a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r1 @ r0<- newFp (points to args) 9553a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, rGLUE, #offGlue_retval @ r1<- &retval 9554a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9555a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9556a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* insert fake function header to help gdb find the stack frame */ 9557a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b .Lskip 9558a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dalvik_mterp, %function 9559a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendalvik_mterp: 9560a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnstart 9561a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY1 9562a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden MTERP_ENTRY2 9563a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.Lskip: 9564a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9565a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9566a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @mov lr, pc @ set return addr 9567a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ldr pc, [r2, #offMethod_nativeFunc] @ pc<- methodToCall->nativeFunc 9568a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LDR_PC_LR "[r2, #offMethod_nativeFunc]" 9569a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9570964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9571964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [rGLUE, #offGlue_ppJitProfTable] @ Refresh Jit's on/off status 9572964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9573964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee 9574a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ native return; r9=self, r10=newSaveArea 9575a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ equivalent to dvmPopJniLocals 9576d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden ldr r0, [r10, #offStackSaveArea_localRefCookie] @ r0<- saved top 9577a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r9, #offThread_exception] @ check for exception 9578964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9579964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee ldr r3, [r3] @ r3 <- gDvmJit.pProfTable 9580964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9581a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r9, #offThread_curFrame] @ self->curFrame = fp 9582a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ null? 9583d5ab726b65d7271be261864c7e224fb90bfe06e0Andy McFadden str r0, [r9, #offThread_jniLocal_topCookie] @ new top <- old top 9584964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#if defined(WITH_JIT) 9585964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee str r3, [rGLUE, #offGlue_pJitProfTable] @ refresh cached on/off switch 9586964a7b06a9134947b5985c7f712d18d57ed665d2Bill Buzbee#endif 9587a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_exceptionThrown @ no, handle exception 9588a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9589a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_ADVANCE_INST(3) @ advance rPC, load rINST 9590a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9591a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9592a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 95936ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden.LstackOverflow: @ r0=methodToCall 95946ed1a0f396a1857c31b486d3e93ee2dbeb49a6cdAndy McFadden mov r1, r0 @ r1<- methodToCall 9595a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_self] @ r0<- self 9596a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmHandleStackOverflow 9597a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9598a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#ifdef ASSIST_DEBUGGER 9599a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .fnend 9600a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9601a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9602a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9603a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9604a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for method invocation, calling through "glue code". 9605a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9606a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * TODO: now that we have range and non-range invoke handlers, this 9607a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * needs to be split into two. Maybe just create entry points 9608a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * that set r9 and jump here? 9609a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9610a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On entry: 9611a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r0 is "Method* methodToCall", the method we're trying to call 9612a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * r9 is "bool methodCallRange", indicating if this is a /range variant 9613a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9614a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9615a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LinvokeOld: 9616a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub sp, sp, #8 @ space for args + pad 9617a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH(ip, 2) @ ip<- FEDC or CCCC 9618a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 @ A2<- methodToCall 9619a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ A0<- glue 9620a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state to "glue" 9621a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r9 @ A1<- methodCallRange 9622a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, rINST, lsr #8 @ A3<- AA 9623a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #0] @ A4<- ip 9624a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_invokeMethod @ call the C invokeMethod 9625a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ remove arg area 9626a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall @ continue to next instruction 9627a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9628a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9629a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9630a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9631a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9632a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Common code for handling a return instruction. 9633a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9634a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9635a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9636a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_returnFromMethod: 9637a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnNew: 9638a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryReturn 9639a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9640a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9641a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9642a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r0, rFP) @ r0<- saveArea (old) 9643a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [r0, #offStackSaveArea_prevFrame] @ fp = saveArea->prevFrame 9644a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r0, #offStackSaveArea_savedPc] @ r9 = saveArea->savedPc 9645a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [rFP, #(offStackSaveArea_method - sizeofStackSaveArea)] 9646a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ r2<- method we're returning to 9647a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [rGLUE, #offGlue_self] @ r3<- glue->self 9648a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r2, #0 @ is this a break frame? 9649a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrne r10, [r2, #offMethod_clazz] @ r10<- method->clazz 9650a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 9651a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq common_gotoBail @ break frame, bail out completely 9652a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9653a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden PREFETCH_ADVANCE_INST(rINST, r9, 3) @ advance r9, update new rINST 9654a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_method]@ glue->method = newSave->method 9655a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r10, #offClassObject_pDvmDex] @ r1<- method->clazz->pDvmDex 9656a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [r3, #offThread_curFrame] @ self->curFrame = fp 9657a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 96587a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng ldr r10, [r0, #offStackSaveArea_returnAddr] @ r10 = saveArea->returnAddr 9659a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_JIT_PROF_TABLE(r0) 9660a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9661a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 96627a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng str r10, [r3, #offThread_inJitCodeCache] @ may return to JIT'ed land 96637a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng cmp r10, #0 @ caller is compiled code 96647a0bcd0de6c4da6499a088a18d1750e51204c2a6Ben Cheng blxne r10 9665a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9666a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0,#0 9667a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bne common_updateProfile 9668a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9669a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#else 9670a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9671a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rPC, r9 @ publish new rPC 9672a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_methodClassDex] 9673a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9674a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9675a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9676a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9677a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Return handling, calls through "glue code". 9678a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9679a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9680a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LreturnOld: 9681a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9682a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 9683a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_returnFromMethod 9684a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 9685a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9686a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9687a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9688a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9689a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Somebody has thrown an exception. Handle it. 9690a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9691a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * If the exception processing code returns to us (instead of falling 9692a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * out of the interpreter), continue with whatever the next instruction 9693a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * now happens to be. 9694a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9695a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * This does not return. 9696a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9697a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmMterpCommonExceptionThrown 9698a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmMterpCommonExceptionThrown: 9699a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_exceptionThrown: 9700a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionNew: 9701a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #kInterpEntryThrow 9702a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r9, #0 9703a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_periodicChecks 9704a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9705a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if defined(WITH_JIT) 9706a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2,#kJitTSelectAbort @ abandon trace selection in progress 9707a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2,[rGLUE,#offGlue_jitState] 9708a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9709a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9710a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r10, [rGLUE, #offGlue_self] @ r10<- glue->self 9711a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r9, [r10, #offThread_exception] @ r9<- self->exception 9712a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9713a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9714a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmAddTrackedAlloc @ don't let the exception be GCed 9715a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- NULL 9716a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r3, [r10, #offThread_exception] @ self->exception = NULL 9717a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9718a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* set up args and a local for "&fp" */ 9719a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* (str sp, [sp, #-4]! would be perfect here, but is discouraged) */ 9720a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str rFP, [sp, #-4]! @ *--sp = fp 9721a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov ip, sp @ ip<- &fp 9722a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, #0 @ r3<- false 9723a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str ip, [sp, #-4]! @ *--sp = &fp 9724a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [rGLUE, #offGlue_method] @ r1<- glue->method 9725a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 9726a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offMethod_insns] @ r1<- method->insns 9727a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r9 @ r2<- exception 9728a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 @ r1<- pc - method->insns 9729a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r1, asr #1 @ r1<- offset in code units 9730a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9731a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call, r0 gets catchRelPc (a code-unit offset) */ 9732a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmFindCatchBlock @ call(self, relPc, exc, scan?, &fp) 9733a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9734a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix earlier stack overflow if necessary; may trash rFP */ 9735a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9736a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 9737a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden beq 1f @ no, skip ahead 9738a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov rFP, r0 @ save relPc result in rFP 9739a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r10 @ r0<- self 9740a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmCleanupStackOverflow @ call(self) 9741a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rFP @ restore result 9742a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden1: 9743a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9744a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* update frame pointer and check result from dvmFindCatchBlock */ 9745a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr rFP, [sp, #4] @ retrieve the updated rFP 9746a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r0, #0 @ is catchRelPc < 0? 9747a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add sp, sp, #8 @ restore stack 9748a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bmi .LnotCaughtLocally 9749a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9750a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* adjust locals to match self->curFrame and updated PC */ 9751a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVEAREA_FROM_FP(r1, rFP) @ r1<- new save area 9752a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r1, #offStackSaveArea_method] @ r1<- new method 9753a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r1, [rGLUE, #offGlue_method] @ glue->method = new method 9754a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r1, #offMethod_clazz] @ r2<- method->clazz 9755a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r1, #offMethod_insns] @ r3<- method->insns 9756a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, [r2, #offClassObject_pDvmDex] @ r2<- method->clazz->pDvmDex 9757a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add rPC, r3, r0, asl #1 @ rPC<- method->insns + catchRelPc 9758a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r2, [rGLUE, #offGlue_methodClassDex] @ glue->pDvmDex = meth... 9759a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9760a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* release the tracked alloc on the exception */ 9761a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9762a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9763a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9764a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9765a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* restore the exception if the handler wants it */ 9766a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 9767a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9768a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp ip, #OP_MOVE_EXCEPTION @ is it "move-exception"? 9769a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden streq r9, [r10, #offThread_exception] @ yes, restore the exception 9770a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9771a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9772a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LnotCaughtLocally: @ r9=exception, r10=self 9773a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* fix stack overflow if necessary */ 9774a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldrb r1, [r10, #offThread_stackOverflowed] 9775a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden cmp r1, #0 @ did we overflow earlier? 9776a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden movne r0, r10 @ if yes: r0<- self 9777a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden blne dvmCleanupStackOverflow @ if yes: call(self) 9778a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9779a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ may want to show "not caught locally" debug messages here 9780a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if DVM_SHOW_EXCEPTION >= 2 9781a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* call __android_log_print(prio, tag, format, ...) */ 9782a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* "Exception %s from %s:%d not caught locally" */ 9783a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmLineNumFromPC(method, pc - method->insns) 9784a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 9785a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, [r0, #offMethod_insns] 9786a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden sub r1, rPC, r1 9787a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden asr r1, r1, #1 9788a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmLineNumFromPC 9789a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 9790a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ dvmGetMethodSourceFile(method) 9791a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, [rGLUE, #offGlue_method] 9792a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmGetMethodSourceFile 9793a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r0, [sp, #-4]! 9794a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ exception->clazz->descriptor 9795a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r9, #offObject_clazz] 9796a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r3, [r3, #offClassObject_descriptor] 9797a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden @ 9798a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r2, strExceptionNotCaughtLocally 9799a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strLogTag 9800a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #3 @ LOG_DEBUG 9801a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl __android_log_print 9802a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 9803a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden str r9, [r10, #offThread_exception] @ restore exception 9804a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r9 @ r0<- exception 9805a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r10 @ r1<- self 9806a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmReleaseTrackedAlloc @ release the exception 9807a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 @ "want switch" = false 9808a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_gotoBail @ bail out 9809a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9810a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9811a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9812a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Exception handling, calls through "glue code". 9813a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9814a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9815a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LexceptionOld: 9816a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SAVE_PC_FP_TO_GLUE() @ export state 9817a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, rGLUE @ arg to function 9818a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterp_exceptionThrown 9819a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_resumeAfterGlueCall 9820a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9821a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9822a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9823a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9824a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * After returning from a "glued" function, pull out the updated 9825a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * values and start executing at the next instruction. 9826a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9827a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_resumeAfterGlueCall: 9828a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden LOAD_PC_FP_FROM_GLUE() @ pull rPC and rFP out of glue 9829a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden FETCH_INST() @ load rINST from rPC 9830a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GET_INST_OPCODE(ip) @ extract opcode from rINST 9831a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden GOTO_OPCODE(ip) @ jump to next instruction 9832a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9833a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9834a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array index. 9835a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9836a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayIndex: 9837a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9838a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayIndexException 9839a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9840a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9841a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9842a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9843a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9844a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invalid array value. 9845a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9846a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errArrayStore: 9847a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9848a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArrayStoreException 9849a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9850a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9851a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9852a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9853a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9854a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Integer divide or mod by zero. 9855a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9856a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errDivideByZero: 9857a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9858a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strArithmeticException 9859a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r1, strDivideByZero 9860a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9861a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9862a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9863a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9864a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Attempt to allocate an array with a negative size. 9865a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9866a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNegativeArraySize: 9867a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9868a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNegativeArraySizeException 9869a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9870a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9871a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9872a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9873a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9874a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Invocation of a non-existent method. 9875a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9876a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNoSuchMethod: 9877a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9878a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNoSuchMethodError 9879a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9880a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9881a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9882a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9883a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9884a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * We encountered a null object when we weren't expecting one. We 9885a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * export the PC, throw a NullPointerException, and goto the exception 9886a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * processing code. 9887a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9888a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_errNullObject: 9889a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden EXPORT_PC() 9890a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNullPointerException 9891a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #0 9892a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmThrowException 9893a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden b common_exceptionThrown 9894a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9895a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9896a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * For debugging, cause an immediate fault. The source address will 9897a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * be in lr (use a bl instruction to jump here). 9898a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9899a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_abort: 9900a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr pc, .LdeadFood 9901a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LdeadFood: 9902a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word 0xdeadf00d 9903a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9904a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9905a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out a "we were here", preserving all registers. (The attempt 9906a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * to save ip won't work, but we need to save an even number of 9907a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * registers for EABI 64-bit stack alignment.) 9908a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9909a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .macro SQUEAK num 9910a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_squeak\num: 9911a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9912a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 9913a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, #\num 9914a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9915a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9916a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9917a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endm 9918a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9919a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 0 9920a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 1 9921a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 2 9922a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 3 9923a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 4 9924a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden SQUEAK 5 9925a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9926a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9927a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Spit out the number in r0, preserving registers. 9928a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9929a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNum: 9930a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9931a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 9932a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strSqueak 9933a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9934a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9935a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9936a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9937a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9938a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print a newline, preserving registers. 9939a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9940a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printNewline: 9941a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9942a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strNewline 9943a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9944a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9945a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9946a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9947a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 9948a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 32-bit quantity in r0 as a hex value, preserving registers. 9949a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9950a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printHex: 9951a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9952a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r1, r0 9953a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintHex 9954a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9955a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9956a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9957a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9958a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9959a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print the 64-bit quantity in r0-r1, preserving registers. 9960a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9961a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printLong: 9962a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9963a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r3, r1 9964a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r2, r0 9965a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldr r0, strPrintLong 9966a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl printf 9967a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9968a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9969a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9970a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9971a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Print full method info. Pass the Method* in r0. Preserves regs. 9972a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9973a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_printMethod: 9974a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9975a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpPrintMethod 9976a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9977a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9978a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9979a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9980a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Call a C helper function that dumps regs and possibly some 9981a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * additional info. Requires the C function to be compiled in. 9982a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9983a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .if 0 9984a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddencommon_dumpRegs: 9985a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {r0, r1, r2, r3, ip, lr} 9986a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl dvmMterpDumpArmRegs 9987a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {r0, r1, r2, r3, ip, lr} 9988a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 9989a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .endif 9990a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 9991a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#if 0 9992a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 9993a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Experiment on VFP mode. 9994a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9995a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * uint32_t setFPSCR(uint32_t val, uint32_t mask) 9996a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 9997a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Updates the bits specified by "mask", setting them to the values in "val". 9998a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 9999a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddensetFPSCR: 10000a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r0, r0, r1 @ make sure no stray bits are set 10001a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmrx r2, fpscr @ get VFP reg 10002a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mvn r1, r1 @ bit-invert mask 10003a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden and r2, r2, r1 @ clear masked bits 10004a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden orr r2, r2, r0 @ set specified bits 10005a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden fmxr fpscr, r2 @ set VFP reg 10006a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, r2 @ return new value 10007a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bx lr 10008a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10009a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10010a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .global dvmConfigureFP 10011a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .type dvmConfigureFP, %function 10012a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddendvmConfigureFP: 10013a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden stmfd sp!, {ip, lr} 10014a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x03000000 sets DN/FZ */ 10015a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden /* 0x00009f00 clears the six exception enable flags */ 10016a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl common_squeak0 10017a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden mov r0, #0x03000000 @ r0<- 0x03000000 10018a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden add r1, r0, #0x9f00 @ r1<- 0x03009f00 10019a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden bl setFPSCR 10020a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden ldmfd sp!, {ip, pc} 10021a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden#endif 10022a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10023a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10024a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10025a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * String references, must be close to the code that uses them. 10026a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10027a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .align 2 10028a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArithmeticException: 10029a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArithmeticException 10030a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayIndexException: 10031a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayIndexException 10032a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrArrayStoreException: 10033a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrArrayStoreException 10034a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrDivideByZero: 10035a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrDivideByZero 10036a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNegativeArraySizeException: 10037a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNegativeArraySizeException 10038a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNoSuchMethodError: 10039a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNoSuchMethodError 10040a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNullPointerException: 10041a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNullPointerException 10042a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10043a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrLogTag: 10044a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrLogTag 10045a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrExceptionNotCaughtLocally: 10046a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrExceptionNotCaughtLocally 10047a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10048a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrNewline: 10049a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrNewline 10050a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrSqueak: 10051a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrSqueak 10052a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintHex: 10053a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintHex 10054a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFaddenstrPrintLong: 10055a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .word .LstrPrintLong 10056a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10057a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden/* 10058a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * Zero-terminated ASCII string data. 10059a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * 10060a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * On ARM we have two choices: do like gcc does, and LDR from a .word 10061a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * with the address, or use an ADR pseudo-op to get the address 10062a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * directly. ADR saves 4 bytes and an indirection, but it's using a 10063a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * PC-relative addressing mode and hence has a limited range, which 10064a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden * makes it not work well with mergeable string sections. 10065a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden */ 10066a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .section .rodata.str1.4,"aMS",%progbits,1 10067a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10068a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrBadEntryPoint: 10069a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Bad entry point %d\n" 10070a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArithmeticException: 10071a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArithmeticException;" 10072a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayIndexException: 10073a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayIndexOutOfBoundsException;" 10074a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrArrayStoreException: 10075a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ArrayStoreException;" 10076a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrClassCastException: 10077a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/ClassCastException;" 10078a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrDivideByZero: 10079a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "divide by zero" 10080a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrFilledNewArrayNotImpl: 10081a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "filled-new-array only implemented for objects and 'int'" 10082a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInternalError: 10083a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InternalError;" 10084a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrInstantiationError: 10085a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/InstantiationError;" 10086a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNegativeArraySizeException: 10087a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NegativeArraySizeException;" 10088a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNoSuchMethodError: 10089a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NoSuchMethodError;" 10090a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNullPointerException: 10091a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Ljava/lang/NullPointerException;" 10092a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10093a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrLogTag: 10094a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "mterp" 10095a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrExceptionNotCaughtLocally: 10096a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "Exception %s from %s:%d not caught locally\n" 10097a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10098a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrNewline: 10099a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "\n" 10100a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrSqueak: 10101a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%d>" 10102a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintHex: 10103a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<0x%x>" 10104a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden.LstrPrintLong: 10105a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden .asciz "<%lld>" 10106a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10107a5069fb7eb2da846ff1fc2c903ebd8ce9fa3647fAndy McFadden 10108