1// Copyright (c) 2006-2008 The Chromium Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5// For atomic operations on reference counts, see atomic_refcount.h.
6// For atomic operations on sequence numbers, see atomic_sequence_num.h.
7
8// The routines exported by this module are subtle.  If you use them, even if
9// you get the code right, it will depend on careful reasoning about atomicity
10// and memory ordering; it will be less readable, and harder to maintain.  If
11// you plan to use these routines, you should have a good reason, such as solid
12// evidence that performance would otherwise suffer, or there being no
13// alternative.  You should assume only properties explicitly guaranteed by the
14// specifications in this file.  You are almost certainly _not_ writing code
15// just for the x86; if you assume x86 semantics, x86 hardware bugs and
16// implementations on other archtectures will cause your code to break.  If you
17// do not know what you are doing, avoid these routines, and use a Mutex.
18//
19// It is incorrect to make direct assignments to/from an atomic variable.
20// You should use one of the Load or Store routines.  The NoBarrier
21// versions are provided when no barriers are needed:
22//   NoBarrier_Store()
23//   NoBarrier_Load()
24// Although there are currently no compiler enforcement, you are encouraged
25// to use these.
26//
27
28#ifndef BASE_ATOMICOPS_H_
29#define BASE_ATOMICOPS_H_
30
31#include "base/basictypes.h"
32#include "base/port.h"
33
34namespace base {
35namespace subtle {
36
37// Bug 1308991.  We need this for /Wp64, to mark it safe for AtomicWord casting.
38#ifndef OS_WIN
39#define __w64
40#endif
41typedef __w64 int32 Atomic32;
42#ifdef ARCH_CPU_64_BITS
43// We need to be able to go between Atomic64 and AtomicWord implicitly.  This
44// means Atomic64 and AtomicWord should be the same type on 64-bit.
45typedef intptr_t Atomic64;
46#endif
47
48// Use AtomicWord for a machine-sized pointer.  It will use the Atomic32 or
49// Atomic64 routines below, depending on your architecture.
50typedef intptr_t AtomicWord;
51
52// Atomically execute:
53//      result = *ptr;
54//      if (*ptr == old_value)
55//        *ptr = new_value;
56//      return result;
57//
58// I.e., replace "*ptr" with "new_value" if "*ptr" used to be "old_value".
59// Always return the old value of "*ptr"
60//
61// This routine implies no memory barriers.
62Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
63                                  Atomic32 old_value,
64                                  Atomic32 new_value);
65
66// Atomically store new_value into *ptr, returning the previous value held in
67// *ptr.  This routine implies no memory barriers.
68Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr, Atomic32 new_value);
69
70// Atomically increment *ptr by "increment".  Returns the new value of
71// *ptr with the increment applied.  This routine implies no memory barriers.
72Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr, Atomic32 increment);
73
74Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
75                                 Atomic32 increment);
76
77// These following lower-level operations are typically useful only to people
78// implementing higher-level synchronization operations like spinlocks,
79// mutexes, and condition-variables.  They combine CompareAndSwap(), a load, or
80// a store with appropriate memory-ordering instructions.  "Acquire" operations
81// ensure that no later memory access can be reordered ahead of the operation.
82// "Release" operations ensure that no previous memory access can be reordered
83// after the operation.  "Barrier" operations have both "Acquire" and "Release"
84// semantics.   A MemoryBarrier() has "Barrier" semantics, but does no memory
85// access.
86Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
87                                Atomic32 old_value,
88                                Atomic32 new_value);
89Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
90                                Atomic32 old_value,
91                                Atomic32 new_value);
92
93void MemoryBarrier();
94void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value);
95void Acquire_Store(volatile Atomic32* ptr, Atomic32 value);
96void Release_Store(volatile Atomic32* ptr, Atomic32 value);
97
98Atomic32 NoBarrier_Load(volatile const Atomic32* ptr);
99Atomic32 Acquire_Load(volatile const Atomic32* ptr);
100Atomic32 Release_Load(volatile const Atomic32* ptr);
101
102// 64-bit atomic operations (only available on 64-bit processors).
103#ifdef ARCH_CPU_64_BITS
104Atomic64 NoBarrier_CompareAndSwap(volatile Atomic64* ptr,
105                                  Atomic64 old_value,
106                                  Atomic64 new_value);
107Atomic64 NoBarrier_AtomicExchange(volatile Atomic64* ptr, Atomic64 new_value);
108Atomic64 NoBarrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
109Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr, Atomic64 increment);
110
111Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
112                                Atomic64 old_value,
113                                Atomic64 new_value);
114Atomic64 Release_CompareAndSwap(volatile Atomic64* ptr,
115                                Atomic64 old_value,
116                                Atomic64 new_value);
117void NoBarrier_Store(volatile Atomic64* ptr, Atomic64 value);
118void Acquire_Store(volatile Atomic64* ptr, Atomic64 value);
119void Release_Store(volatile Atomic64* ptr, Atomic64 value);
120Atomic64 NoBarrier_Load(volatile const Atomic64* ptr);
121Atomic64 Acquire_Load(volatile const Atomic64* ptr);
122Atomic64 Release_Load(volatile const Atomic64* ptr);
123#endif  // ARCH_CPU_64_BITS
124
125}  // namespace base::subtle
126}  // namespace base
127
128// Include our platform specific implementation.
129#if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)
130#include "base/atomicops_internals_x86_msvc.h"
131#elif defined(OS_MACOSX) && defined(ARCH_CPU_X86_FAMILY)
132#include "base/atomicops_internals_x86_macosx.h"
133#elif defined(COMPILER_GCC) && defined(ARCH_CPU_X86_FAMILY)
134#include "base/atomicops_internals_x86_gcc.h"
135#elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)
136#include "base/atomicops_internals_arm_gcc.h"
137#else
138#error "Atomic operations are not supported on your platform"
139#endif
140
141#endif  // BASE_ATOMICOPS_H_
142