Searched defs:rIndex (Results 1 - 3 of 3) sorted by relevance

/dalvik/vm/compiler/codegen/arm/
H A DCodegenFactory.c305 static ArmLIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex, argument
308 return genRegRegCheck(cUnit, kArmCondCs, rIndex, rBound, dOffset,
/dalvik/vm/compiler/codegen/arm/Thumb/
H A DFactory.c449 int rIndex, int rDest, int scale, OpSize size)
454 int rNewIndex = rIndex;
458 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
492 int rIndex, int rSrc, int scale, OpSize size)
497 int rNewIndex = rIndex;
500 first = opRegRegImm(cUnit, kOpLsl, rNewIndex, rIndex, scale);
448 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
491 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
/dalvik/vm/compiler/codegen/arm/Thumb2/
H A DFactory.c677 int rIndex, int rDest, int scale, OpSize size)
679 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
699 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
702 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
729 load = newLIR3(cUnit, opCode, rDest, rBase, rIndex);
731 load = newLIR4(cUnit, opCode, rDest, rBase, rIndex, scale);
741 int rIndex, int rSrc, int scale, OpSize size)
743 bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
763 newLIR4(cUnit, kThumb2AddRRR, regPtr, rBase, rIndex,
766 opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex);
676 loadBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rDest, int scale, OpSize size) argument
740 storeBaseIndexed(CompilationUnit *cUnit, int rBase, int rIndex, int rSrc, int scale, OpSize size) argument
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