Lines Matching refs:memline
62 Addr memline, iaddr;
63 line_use* dep_use; /* point to higher-level cacheblock for this memline */
162 c->loaded[i].memline = 0;
703 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
720 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
747 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
762 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
784 idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
799 i, idx, L.loaded[idx].memline, L.loaded[idx].iaddr, \
840 static void update_LL_use(int idx, Addr memline)
846 CLG_DEBUG(2, " LL.miss [%d]: at %#lx accessing memline %#lx\n",
847 idx, CLG_(bb_base) + current_ii->instr_offset, memline);
850 use->count, i, use->mask, loaded->memline, loaded->iaddr);
863 loaded->memline = memline;
871 CacheModelResult cacheuse_LL_access(Addr memline, line_loaded* l1_loaded)
873 UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);
875 UWord tag = memline & LL.tag_mask;
880 CLG_DEBUG(6,"LL.Acc(Memline %#lx): Set %d\n", memline, setNo);
887 idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
902 i, idx, LL.loaded[idx].memline, LL.loaded[idx].iaddr,
917 update_LL_use(idx, memline);
928 UInt mask, Addr memline) \
934 CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \
935 cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
938 use->count, c, use->mask, loaded->memline, loaded->iaddr); \
954 loaded->memline = memline; \
960 if (memline == 0) return LL_Hit; \
961 return cacheuse_LL_access(memline, loaded); \