Searched defs:AM (Results 1 - 24 of 24) sorted by relevance

/external/llvm/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h50 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) { argument
51 AM.print(OS);
75 Instruction *MI, ExtAddrMode &AM)
76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) {
73 AddressingModeMatcher(SmallVectorImpl<Instruction*> &AMI, const TargetLowering &T, Type *AT, Instruction *MI, ExtAddrMode &AM) argument
/external/llvm/lib/Analysis/
H A DTypeBasedAliasAnalysis.cpp220 const MDNode *AM = LocA.TBAATag; local
221 if (!AM) return AliasAnalysis::alias(LocA, LocB);
226 if (Aliases(AM, BM))
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h90 addFullAddress(const MachineInstrBuilder &MIB, const SystemZAddressMode &AM) { argument
91 if (AM.BaseType == SystemZAddressMode::RegBase)
92 MIB.addReg(AM.Base.Reg);
93 else if (AM.BaseType == SystemZAddressMode::FrameIndexBase)
94 MIB.addFrameIndex(AM.Base.FrameIndex);
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
H A DSystemZISelDAGToDAG.cpp85 void getAddressOperandsRI(const SystemZRRIAddressMode &AM,
87 void getAddressOperands(const SystemZRRIAddressMode &AM,
141 bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
143 bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
182 bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM, argument
185 DEBUG(errs() << "MatchAddress: "; AM.dump());
188 return MatchAddressBase(N, AM);
199 isImmZExt12(AM.Disp + Val, Imm) :
200 isImmSExt20(AM.Disp + Val, Imm));
202 AM
317 MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM) argument
337 getAddressOperandsRI(const SystemZRRIAddressMode &AM, SDValue &Base, SDValue &Disp) argument
346 getAddressOperands(const SystemZRRIAddressMode &AM, SDValue &Base, SDValue &Disp, SDValue &Index) argument
504 SystemZRRIAddressMode AM; local
548 SystemZRRIAddressMode AM; local
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
139 bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) { argument
142 if (AM.hasSymbolicDisplacement())
148 AM.GV = G->getGlobal();
149 AM.Disp += G->getOffset();
150 //AM.SymbolFlags = G->getTargetFlags();
152 AM.CP = CP->getConstVal();
153 AM
171 MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) argument
184 MatchAddress(SDValue N, MSP430ISelAddressMode &AM) argument
250 MSP430ISelAddressMode AM; local
303 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
[all...]
H A DMSP430ISelLowering.cpp943 ISD::MemIndexedMode &AM,
965 AM = ISD::POST_INC;
940 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h124 const X86AddressMode &AM) {
125 assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
127 if (AM.BaseType == X86AddressMode::RegBase)
128 MIB.addReg(AM.Base.Reg);
130 assert(AM.BaseType == X86AddressMode::FrameIndexBase);
131 MIB.addFrameIndex(AM.Base.FrameIndex);
134 MIB.addImm(AM
123 addFullAddress(const MachineInstrBuilder &MIB, const X86AddressMode &AM) argument
[all...]
H A DX86FastISel.cpp81 bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR);
83 bool X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM);
84 bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM);
89 bool X86SelectAddress(const Value *V, X86AddressMode &AM);
90 bool X86SelectCallAddress(const Value *V, X86AddressMode &AM);
176 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, argument
226 DL, TII.get(Opc), ResultReg), AM);
235 X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { argument
276 DL, TII.get(Opc)), AM).addReg(Val);
281 const X86AddressMode &AM) {
280 X86FastEmitStore(EVT VT, const Value *Val, const X86AddressMode &AM) argument
337 X86SelectAddress(const Value *V, X86AddressMode &AM) argument
597 X86SelectCallAddress(const Value *V, X86AddressMode &AM) argument
1433 X86AddressMode AM; local
1440 X86AddressMode AM; local
1747 X86AddressMode AM; local
2042 X86AddressMode AM; local
2157 X86AddressMode AM; local
[all...]
H A DX86ISelDAGToDAG.cpp195 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
196 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
197 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
198 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
199 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
201 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
230 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, argument
233 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
234 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
235 AM
566 FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM) argument
585 MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM) argument
613 MatchWrapper(SDValue N, X86ISelAddressMode &AM) argument
699 MatchAddress(SDValue N, X86ISelAddressMode &AM) argument
728 MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned Depth) argument
1107 MatchAddressBase(SDValue N, X86ISelAddressMode &AM) argument
1137 X86ISelAddressMode AM; local
1222 X86ISelAddressMode AM; local
1286 X86ISelAddressMode AM; local
[all...]
H A DX86InstrInfo.cpp2436 X86AddressMode AM; local
2437 AM.BaseType = X86AddressMode::FrameIndexBase;
2438 AM.Base.FrameIndex = FrameIx;
2440 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
H A DX86ISelLowering.cpp10759 // by AM is legal for this target, for a load/store of the specified type.
10760 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
10767 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10770 if (AM.BaseGV) {
10772 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10780 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10785 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10789 switch (AM
12070 X86AddressMode AM; local
[all...]
/external/chromium/chrome/common/extensions/docs/examples/extensions/benchmark/jquery/
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[all...]
/external/icu4c/i18n/unicode/
H A Dcalendar.h257 AM, enumerator in enum:Calendar::EAmpm
/external/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp727 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
730 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
763 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
766 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
783 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
786 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
856 ISD::MemIndexedMode AM local
942 ISD::MemIndexedMode AM = LdSt->getAddressingMode(); local
1258 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD) local
1331 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
1404 ISD::MemIndexedMode AM = LD->getAddressingMode(); local
[all...]
H A DARMISelLowering.cpp8205 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, argument
8207 int Scale = AM.Scale;
8224 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8239 /// by AM is legal for this target, for a load/store of the specified type.
8240 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
8243 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
8247 if (AM.BaseGV)
8250 switch (AM.Scale) {
8259 if (AM.BaseOffs)
8266 return isLegalT2ScaledAddressingMode(AM, V
8408 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
8446 getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1555 /// by AM is legal for this target, for a load/store of the specified type.
1557 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
1560 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1564 if (AM.BaseGV) {
1565 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1566 AM.BaseOffs%4 == 0;
1572 if (AM
[all...]
/external/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h606 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
1563 unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,
1566 SubclassData |= AM << 2;
1567 assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
1601 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1604 VTs, AM, MemVT, MMO) {
1632 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
1635 VTs, AM, MemVT, MMO) {
1562 LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands, unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT, MachineMemOperand *MMO) argument
1600 LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT, MachineMemOperand *MMO) argument
1631 StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT, MachineMemOperand *MMO) argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp3182 /// by AM is legal for this target, for a load/store of the specified type.
3183 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
3189 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3193 if (AM.BaseGV)
3197 switch (AM.Scale) {
3201 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3206 if (AM.HasBaseReg || AM
[all...]
H A DDAGCombiner.cpp5906 ISD::MemIndexedMode AM = ISD::UNINDEXED; local
5907 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5962 BasePtr, Offset, AM);
5965 BasePtr, Offset, AM);
6041 ISD::MemIndexedMode AM = ISD::UNINDEXED; local
6042 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6093 BasePtr, Offset, AM)
6095 BasePtr, Offset, AM);
H A DSelectionDAG.cpp477 encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, bool isVolatile, argument
481 assert((AM & 7) == AM &&
482 "AM may not require more than 3 bits!");
484 (AM << 2) |
4137 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4163 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
4167 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4188 bool Indexed = AM != ISD::UNINDEXED;
4198 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MM
4235 getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument
4366 getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM) argument
6126 getIndexedModeName(ISD::MemIndexedMode AM) argument
6290 const char *AM = getIndexedModeName(LD->getAddressingMode()); local
6292 OS << ", " << AM; local
6301 const char *AM = getIndexedModeName(ST->getAddressingMode()); local
6303 OS << ", " << AM; local
[all...]
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp3258 SPUTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
3262 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0)
3266 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs))
3270 if (AM
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenDAGPatterns.cpp703 const ComplexPattern *AM = P->getComplexPatternInfo(CGP); local
704 if (AM)
705 Size += AM->getNumOperands() * 3;
/external/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp215 /// AM - This is used to represent complex addressing, as well as other kinds
217 TargetLowering::AddrMode AM; member in struct:__anon7038::Formula
220 /// non-empty, AM.HasBaseReg should be set to true.
224 /// when AM.Scale is not zero.
318 AM.HasBaseReg = true;
324 AM.HasBaseReg = true;
340 AM.BaseGV ? AM.BaseGV->getType() :
373 if (AM.BaseGV) {
375 WriteAsOperand(OS, AM
1178 isLegalUse(const TargetLowering::AddrMode &AM, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument
1226 isLegalUse(TargetLowering::AddrMode AM, int64_t MinOffset, int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy, const TargetLowering *TLI) argument
1836 TargetLowering::AddrMode AM; local
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1057 ISD::MemIndexedMode &AM,
1100 AM = ISD::PRE_INC;
5660 // by AM is legal for this target, for a load/store of the specified type.
5661 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, argument
5666 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5670 if (AM.BaseGV)
5674 switch (AM.Scale) {
5678 if (AM.HasBaseReg && AM
1055 getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const argument
[all...]

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