Searched defs:Opcode (Results 1 - 25 of 89) sorted by relevance

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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument
20 switch (Opcode) {
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument
24 switch (Opcode) {
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode(); local
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
85 unsigned Opcode = MI->getOpcode(); local
88 } else if (Opcode == ARM::t2IT) {
H A DMLxExpansionPass.cpp144 unsigned Opcode = MCID.getOpcode(); local
145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp79 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument
83 if ((int)Opcode >= 0) {
87 Opcode = ~Opcode;
89 const MCInstrDesc &MCID = TII.get(Opcode);
147 unsigned Opcode = Node->getMachineOpcode(); local
179 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
186 switch (Opcode) {
246 unsigned Opcode local
[all...]
/external/webkit/Source/JavaScriptCore/bytecode/
H A DOpcode.h220 typedef void* Opcode; typedef in namespace:JSC
222 typedef const void* Opcode; typedef in namespace:JSC
225 typedef OpcodeID Opcode; typedef in namespace:JSC
/external/llvm/lib/Target/Alpha/
H A DAlphaInstrInfo.cpp71 static bool isAlphaIntCondCode(unsigned Opcode) { argument
72 switch (Opcode) {
195 static unsigned AlphaRevCondCode(unsigned Opcode) { argument
196 switch (Opcode) {
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelDAGToDAG.cpp190 unsigned Opcode = Node->getOpcode(); local
201 switch (Opcode) {
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCCodeEmitter.cpp182 unsigned Opcode = MI.getOpcode(); local
183 const MCInstrDesc &Desc = MCII.get(Opcode);
/external/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; local
166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; local
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
H A DSparcInstrInfo.cpp166 unsigned Opcode = I->getOpcode(); local
167 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
168 return true; //Unknown Opcode
194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
/external/llvm/lib/VMCore/
H A DInstruction.cpp367 bool Instruction::isAssociative(unsigned Opcode) { argument
368 return Opcode == And || Opcode == Or || Opcode == Xor ||
369 Opcode == Add || Opcode == Mul;
/external/llvm/utils/TableGen/
H A DX86RecognizableInstr.h46 uint8_t Opcode; member in class:llvm::X86Disassembler::RecognizableInstr
/external/webkit/Source/WebCore/xml/
H A DXPathPredicate.h67 enum Opcode { enum in class:WebCore::XPath::NumericOp
70 NumericOp(Opcode, Expression* lhs, Expression* rhs);
75 Opcode m_opcode;
80 enum Opcode { OP_EQ, OP_NE, OP_GT, OP_LT, OP_GE, OP_LE }; enum in class:WebCore::XPath::EqTestOp
81 EqTestOp(Opcode, Expression* lhs, Expression* rhs);
87 Opcode m_opcode;
92 enum Opcode { OP_And, OP_Or }; enum in class:WebCore::XPath::LogicalOp
93 LogicalOp(Opcode, Expression* lhs, Expression* rhs);
99 Opcode m_opcode;
/external/llvm/include/llvm/MC/
H A DMCInst.h131 unsigned Opcode; member in class:llvm::MCInst
134 MCInst() : Opcode(0) {}
136 void setOpcode(unsigned Op) { Opcode = Op; }
138 unsigned getOpcode() const { return Opcode; }
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp336 unsigned Opcode = 0; local
339 Opcode = MSP430::MOV8rm_POST;
342 Opcode = MSP430::MOV16rm_POST;
348 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp190 unsigned Opcode = Node->getOpcode(); local
206 switch(Opcode) {
218 if (Opcode == ISD::ADDE) {
249 Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
275 assert((Opcode == ISD::MUL || Node->getValueType(0) != MVT::i64) &&
281 unsigned MulOp = (Opcode == ISD::MULHU ?
289 if (Opcode == ISD::MUL) {
/external/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp231 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { argument
246 Inst.setOpcode(Opcode);
252 unsigned Opcode) {
297 Inst.setOpcode(Opcode);
397 unsigned Opcode = OutMI.getOpcode(); local
400 OutMI.setOpcode(Opcode);
416 unsigned Opcode; local
419 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
421 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
426 OutMI.setOpcode(Opcode);
251 SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode) argument
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/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; local
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; local
70 BuildMI(MBB, I, dl, TII.get(Opcode))
127 int Opcode; local
129 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
134 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
264 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; local
265 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
268 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; local
[all...]
H A DXCoreInstrInfo.cpp58 int Opcode = MI->getOpcode(); local
59 if (Opcode == XCore::LDWFI)
80 int Opcode = MI->getOpcode(); local
81 if (Opcode == XCore::STWFI)
H A DXCoreRegisterInfo.cpp147 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; local
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
152 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; local
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
255 llvm_unreachable("Unexpected Opcode");
276 llvm_unreachable("Unexpected Opcode");
304 llvm_unreachable("Unexpected Opcode");
319 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6; local
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
/external/llvm/lib/Transforms/Utils/
H A DAddrModeMatcher.cpp153 bool AddressingModeMatcher::MatchOperationAddr(User *AddrInst, unsigned Opcode, argument
158 switch (Opcode) {
210 if (Opcode == Instruction::Shl)
/external/llvm/include/llvm/
H A DConstants.h586 /// constant expressions. The Opcode field for the ConstantExpr class is
594 ConstantExpr(Type *ty, unsigned Opcode, Use *Ops, unsigned NumOps) argument
597 setValueSubclassData(Opcode);
775 static Constant *get(unsigned Opcode, Constant *C1, Constant *C2,
H A DInstruction.h96 static inline bool isBinaryOp(unsigned Opcode) { argument
97 return Opcode >= BinaryOpsBegin && Opcode < BinaryOpsEnd;
100 /// @brief Determine if the Opcode is one of the shift instructions.
101 static inline bool isShift(unsigned Opcode) { argument
102 return Opcode >= Shl && Opcode <= AShr;
/external/llvm/lib/CodeGen/
H A DMachineSSAUpdater.cpp112 MachineInstr *InsertNewDef(unsigned Opcode, argument
118 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);

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