Searched refs:DW_OP_reg0 (Results 1 - 11 of 11) sorted by relevance

/external/elfutils/libdw/
H A Ddwarf_getloclist.c159 case DW_OP_reg0 ... DW_OP_reg31:
H A Ddwarf.h281 DW_OP_reg0 = 0x50, /* Register 0. */ enumerator in enum:__anon4153
/external/valgrind/main/coregrind/m_debuginfo/
H A Dd3basics.c512 && expr[0] >= DW_OP_reg0 && expr[0] <= DW_OP_reg31) {
514 res.word = (UWord)(expr[0] - DW_OP_reg0);
634 case DW_OP_reg0 ... DW_OP_reg31:
1080 else if (nbytes >= 1 && *p >= DW_OP_reg0 && *p <= DW_OP_reg31) {
H A Dpriv_d3basics.h466 DW_OP_reg0 = 0x50, enumerator in enum:__anon10828
H A Dreaddwarf.c2793 case DW_OP_reg0 ... DW_OP_reg31:
2795 reg = (Int)opcode - (Int)DW_OP_reg0;
/external/llvm/lib/Support/
H A DDwarf.cpp364 case DW_OP_reg0: return "DW_OP_reg0";
/external/llvm/include/llvm/Support/
H A DDwarf.h375 DW_OP_reg0 = 0x50, enumerator in enum:llvm::dwarf::dwarf_constants
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfCompileUnit.cpp215 addUInt(TheDie, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + DWReg);
400 addUInt(Block, 0, dwarf::DW_FORM_data1, dwarf::DW_OP_reg0 + Reg);
H A DAsmPrinter.cpp827 dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
828 EmitInt8(dwarf::DW_OP_reg0 + Reg);
/external/qemu/elff/
H A Ddwarf.h518 #define DW_OP_reg0 0x50 macro
/external/elfutils/src/
H A Dreadelf.c3008 [DW_OP_reg0] = "reg0",

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