Searched refs:SUBC (Results 1 - 12 of 12) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 201 // like ADDC/SUBC, which indicate the carry result is always false.
208 ADDC, SUBC, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelDAGToDAG.cpp | 214 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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| H A D | MipsISelLowering.cpp | 326 // SUBENode's second operand must be a flag output of an SUBC node in order
330 if (SUBCNode->getOpcode() != ISD::SUBC)
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 76 SUBC, // Sub with carry enumerator in enum:llvm::ARMISD::NodeType
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| H A D | ARMISelLowering.cpp | 570 setOperationAction(ISD::SUBC, MVT::i32, Custom);
848 case ARMISD::SUBC: return "ARMISD::SUBC";
4882 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4986 case ISD::SUBC:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 2973 if (ConstantSDNode *SUBC =
2975 if (SUBC->getAPIntValue() == OpSizeInBits) {
2990 if (ConstantSDNode *SUBC =
2992 if (SUBC->getAPIntValue() == OpSizeInBits) {
3020 if (ConstantSDNode *SUBC =
3022 if (SUBC->getAPIntValue() == OpSizeInBits) {
3034 if (ConstantSDNode *SUBC =
3036 if (SUBC->getAPIntValue() == OpSizeInBits) {
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| H A D | LegalizeIntegerTypes.cpp | 1143 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1512 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1514 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1519 ISD::ADDC : ISD::SUBC,
1529 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1578 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
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| H A D | TargetLowering.cpp | 2455 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2459 DAG.getConstant(SUBC->getAPIntValue() -
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| H A D | SelectionDAG.cpp | 6024 case ISD::SUBC: return "subc";
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| /external/llvm/lib/Target/Alpha/ |
| H A D | AlphaISelLowering.cpp | 104 setOperationAction(ISD::SUBC , MVT::i64, Expand);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 91 setOperationAction(ISD::SUBC, MVT::i32, Expand);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 363 setOperationAction(ISD::SUBC, VT, Custom);
10370 case ISD::SUBC: Opc = X86ISD::SUB; break;
10449 case ISD::SUBC:
10513 case ISD::SUBC:
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