Searched refs:X0010 (Results 1 - 5 of 5) sorted by relevance
| /external/valgrind/main/VEX/priv/ |
| H A D | host_arm_defs.c | 2526 #define X0010 BITS4(0,0,1,0) macro
2707 case ARMalu_SUB: subopc = X0010; break;
2733 case ARMsh_SAR: subopc = X0010; break;
2954 instr = XXX___XX(i->ARMin.Call.cond, X0001, X0010, /*___*/
3503 insn = XXXXXXXX(0xF, X0010, BITS4(0,D,1,0), regM, regD, X0001,
3508 regD, X0010, BITS4(0,0,M,0), regM);
3512 regD, X0010, BITS4(1,0,M,0), regM);
3516 regD, X0010, BITS4(0,1,M,0), regM);
3520 regD, X0010, BITS4(1,1,M,0), regM);
3525 insn = XXXXXXXX(0xF, X0010,
4093 #undef X0010 macro
[all...] |
| /external/oprofile/events/ppc64/970MP/ |
| H A D | event_mappings | 12 event:0X0010 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
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| /external/oprofile/events/ppc64/power5++/ |
| H A D | event_mappings | 15 event:0X0010 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
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| /external/oprofile/events/ppc64/power6/ |
| H A D | event_mappings | 16 event:0X0010 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
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| /external/oprofile/events/ppc64/power7/ |
| H A D | event_mappings | 15 event:0X0010 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
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