Searched refs:shiftAmount (Results 1 - 4 of 4) sorted by relevance
/external/webkit/Source/JavaScriptCore/dfg/ |
H A D | DFGJITCodeGenerator.h | 340 void shiftOp(NodeType op, MacroAssembler::RegisterID op1, int32_t shiftAmount, MacroAssembler::RegisterID result) argument 344 m_jit.rshift32(op1, Imm32(shiftAmount), result); 347 m_jit.lshift32(op1, Imm32(shiftAmount), result); 350 m_jit.urshift32(op1, Imm32(shiftAmount), result); 356 void shiftOp(NodeType op, MacroAssembler::RegisterID op1, MacroAssembler::RegisterID shiftAmount, MacroAssembler::RegisterID result) argument 360 m_jit.rshift32(op1, shiftAmount, result); 363 m_jit.lshift32(op1, shiftAmount, result); 366 m_jit.urshift32(op1, shiftAmount, result);
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H A D | DFGNonSpeculativeJIT.cpp | 252 int shiftAmount = valueOfInt32Constant(node.child2) & 0x1f; local 254 ASSERT(shiftAmount); 255 shiftOp(op, op1.registerID(), shiftAmount, result.registerID());
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/external/webkit/Source/JavaScriptCore/assembler/ |
H A D | ARMv7Assembler.h | 197 unsigned shiftAmount : 5; 287 encoding.shiftAmount = 8 + leadingZeros; 868 void asr(RegisterID rd, RegisterID rm, int32_t shiftAmount) argument 872 ShiftTypeAndAmount shift(SRType_ASR, shiftAmount); 1171 void lsl(RegisterID rd, RegisterID rm, int32_t shiftAmount) argument 1175 ShiftTypeAndAmount shift(SRType_LSL, shiftAmount); 1187 void lsr(RegisterID rd, RegisterID rm, int32_t shiftAmount) argument 1191 ShiftTypeAndAmount shift(SRType_LSR, shiftAmount); 1310 void ror(RegisterID rd, RegisterID rm, int32_t shiftAmount) argument 1314 ShiftTypeAndAmount shift(SRType_ROR, shiftAmount); [all...] |
H A D | MacroAssemblerMIPS.h | 258 void lshift32(RegisterID shiftAmount, RegisterID dest) argument 260 m_assembler.sllv(dest, dest, shiftAmount); 318 void rshift32(RegisterID shiftAmount, RegisterID dest) argument 320 m_assembler.srav(dest, dest, shiftAmount); 328 void urshift32(RegisterID shiftAmount, RegisterID dest) argument 330 m_assembler.srlv(dest, dest, shiftAmount);
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