MCInst.h revision 0dd2c9331887b9d0aa06b1e201c5eda4361365fc
1//===-- llvm/MC/MCInst.h - MCInst class -------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the declaration of the MCInst and MCOperand classes, which 11// is the basic representation used to represent low-level machine code 12// instructions. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_MC_MCINST_H 17#define LLVM_MC_MCINST_H 18 19#include "llvm/ADT/SmallVector.h" 20#include "llvm/ADT/StringRef.h" 21#include "llvm/System/DataTypes.h" 22 23namespace llvm { 24class raw_ostream; 25class MCAsmInfo; 26class MCInstPrinter; 27class MCExpr; 28 29/// MCOperand - Instances of this class represent operands of the MCInst class. 30/// This is a simple discriminated union. 31class MCOperand { 32 enum MachineOperandType { 33 kInvalid, ///< Uninitialized. 34 kRegister, ///< Register operand. 35 kImmediate, ///< Immediate operand. 36 kExpr ///< Relocatable immediate operand. 37 }; 38 unsigned char Kind; 39 40 union { 41 unsigned RegVal; 42 int64_t ImmVal; 43 const MCExpr *ExprVal; 44 }; 45public: 46 47 MCOperand() : Kind(kInvalid) {} 48 49 bool isValid() const { return Kind != kInvalid; } 50 bool isReg() const { return Kind == kRegister; } 51 bool isImm() const { return Kind == kImmediate; } 52 bool isExpr() const { return Kind == kExpr; } 53 54 /// getReg - Returns the register number. 55 unsigned getReg() const { 56 assert(isReg() && "This is not a register operand!"); 57 return RegVal; 58 } 59 60 /// setReg - Set the register number. 61 void setReg(unsigned Reg) { 62 assert(isReg() && "This is not a register operand!"); 63 RegVal = Reg; 64 } 65 66 int64_t getImm() const { 67 assert(isImm() && "This is not an immediate"); 68 return ImmVal; 69 } 70 void setImm(int64_t Val) { 71 assert(isImm() && "This is not an immediate"); 72 ImmVal = Val; 73 } 74 75 const MCExpr *getExpr() const { 76 assert(isExpr() && "This is not an expression"); 77 return ExprVal; 78 } 79 void setExpr(const MCExpr *Val) { 80 assert(isExpr() && "This is not an expression"); 81 ExprVal = Val; 82 } 83 84 static MCOperand CreateReg(unsigned Reg) { 85 MCOperand Op; 86 Op.Kind = kRegister; 87 Op.RegVal = Reg; 88 return Op; 89 } 90 static MCOperand CreateImm(int64_t Val) { 91 MCOperand Op; 92 Op.Kind = kImmediate; 93 Op.ImmVal = Val; 94 return Op; 95 } 96 static MCOperand CreateExpr(const MCExpr *Val) { 97 MCOperand Op; 98 Op.Kind = kExpr; 99 Op.ExprVal = Val; 100 return Op; 101 } 102 103 void print(raw_ostream &OS, const MCAsmInfo *MAI) const; 104 void dump() const; 105}; 106 107 108/// MCInst - Instances of this class represent a single low-level machine 109/// instruction. 110class MCInst { 111 unsigned Opcode; 112 SmallVector<MCOperand, 8> Operands; 113public: 114 MCInst() : Opcode(0) {} 115 116 void setOpcode(unsigned Op) { Opcode = Op; } 117 118 unsigned getOpcode() const { return Opcode; } 119 120 const MCOperand &getOperand(unsigned i) const { return Operands[i]; } 121 MCOperand &getOperand(unsigned i) { return Operands[i]; } 122 unsigned getNumOperands() const { return Operands.size(); } 123 124 void addOperand(const MCOperand &Op) { 125 Operands.push_back(Op); 126 } 127 128 void print(raw_ostream &OS, const MCAsmInfo *MAI) const; 129 void dump() const; 130 131 /// \brief Dump the MCInst as prettily as possible using the additional MC 132 /// structures, if given. Operators are separated by the \arg Separator 133 /// string. 134 void dump_pretty(raw_ostream &OS, const MCAsmInfo *MAI = 0, 135 const MCInstPrinter *Printer = 0, 136 StringRef Separator = " ") const; 137}; 138 139 140} // end namespace llvm 141 142#endif 143