TargetInstrInfo.h revision b9f550ddfbaf963a0aced2df8cd40c71021fd3e5
1//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2// 3// This file describes the target machine instructions to the code generator. 4// 5//===---------------------------------------------------------------------===// 6 7#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8#define LLVM_TARGET_MACHINEINSTRINFO_H 9 10#include "llvm/Target/TargetMachine.h" 11#include "llvm/Support/DataTypes.h" 12#include <vector> 13 14class MachineInstrDescriptor; 15class TmpInstruction; 16class MachineInstr; 17class Value; 18class Instruction; 19 20 21typedef int InstrSchedClass; 22 23// Global variable holding an array of descriptors for machine instructions. 24// The actual object needs to be created separately for each target machine. 25// This variable is initialized and reset by class MachineInstrInfo. 26// 27// FIXME: This should be a property of the target so that more than one target 28// at a time can be active... 29// 30extern const MachineInstrDescriptor *TargetInstrDescriptors; 31 32 33//--------------------------------------------------------------------------- 34// struct MachineInstrDescriptor: 35// Predefined information about each machine instruction. 36// Designed to initialized statically. 37// 38// class MachineInstructionInfo 39// Interface to description of machine instructions 40// 41//--------------------------------------------------------------------------- 42 43 44const unsigned int M_NOP_FLAG = 1; 45const unsigned int M_BRANCH_FLAG = 1 << 1; 46const unsigned int M_CALL_FLAG = 1 << 2; 47const unsigned int M_RET_FLAG = 1 << 3; 48const unsigned int M_ARITH_FLAG = 1 << 4; 49const unsigned int M_CC_FLAG = 1 << 6; 50const unsigned int M_LOGICAL_FLAG = 1 << 6; 51const unsigned int M_INT_FLAG = 1 << 7; 52const unsigned int M_FLOAT_FLAG = 1 << 8; 53const unsigned int M_CONDL_FLAG = 1 << 9; 54const unsigned int M_LOAD_FLAG = 1 << 10; 55const unsigned int M_PREFETCH_FLAG = 1 << 11; 56const unsigned int M_STORE_FLAG = 1 << 12; 57const unsigned int M_DUMMY_PHI_FLAG = 1 << 13; 58const unsigned int M_PSEUDO_FLAG = 1 << 14; 59 60 61struct MachineInstrDescriptor { 62 string opCodeString; // Assembly language mnemonic for the opcode. 63 int numOperands; // Number of args; -1 if variable #args 64 int resultPos; // Position of the result; -1 if no result 65 unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0. 66 bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 67 // smallest -ve value is -(maxImmedConst+1). 68 unsigned int numDelaySlots; // Number of delay slots after instruction 69 unsigned int latency; // Latency in machine cycles 70 InstrSchedClass schedClass; // enum identifying instr sched class 71 unsigned int iclass; // flags identifying machine instr class 72}; 73 74 75class MachineInstrInfo : public NonCopyableV { 76public: 77 const TargetMachine& target; 78 79protected: 80 const MachineInstrDescriptor* desc; // raw array to allow static init'n 81 unsigned int descSize; // number of entries in the desc array 82 unsigned int numRealOpCodes; // number of non-dummy op codes 83 84public: 85 MachineInstrInfo(const TargetMachine& tgt, 86 const MachineInstrDescriptor *desc, unsigned descSize, 87 unsigned numRealOpCodes); 88 virtual ~MachineInstrInfo(); 89 90 unsigned getNumRealOpCodes() const { return numRealOpCodes; } 91 unsigned getNumTotalOpCodes() const { return descSize; } 92 93 const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 94 assert(opCode >= 0 && opCode < (int)descSize); 95 return desc[opCode]; 96 } 97 98 int getNumOperands(MachineOpCode opCode) const { 99 return getDescriptor(opCode).numOperands; 100 } 101 102 int getResultPos(MachineOpCode opCode) const { 103 return getDescriptor(opCode).resultPos; 104 } 105 106 unsigned getNumDelaySlots(MachineOpCode opCode) const { 107 return getDescriptor(opCode).numDelaySlots; 108 } 109 110 InstrSchedClass getSchedClass(MachineOpCode opCode) const { 111 return getDescriptor(opCode).schedClass; 112 } 113 114 // 115 // Query instruction class flags according to the machine-independent 116 // flags listed above. 117 // 118 unsigned int getIClass(MachineOpCode opCode) const { 119 return getDescriptor(opCode).iclass; 120 } 121 bool isNop(MachineOpCode opCode) const { 122 return getDescriptor(opCode).iclass & M_NOP_FLAG; 123 } 124 bool isBranch(MachineOpCode opCode) const { 125 return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 126 } 127 bool isCall(MachineOpCode opCode) const { 128 return getDescriptor(opCode).iclass & M_CALL_FLAG; 129 } 130 bool isReturn(MachineOpCode opCode) const { 131 return getDescriptor(opCode).iclass & M_RET_FLAG; 132 } 133 bool isControlFlow(MachineOpCode opCode) const { 134 return getDescriptor(opCode).iclass & M_BRANCH_FLAG 135 || getDescriptor(opCode).iclass & M_CALL_FLAG 136 || getDescriptor(opCode).iclass & M_RET_FLAG; 137 } 138 bool isArith(MachineOpCode opCode) const { 139 return getDescriptor(opCode).iclass & M_RET_FLAG; 140 } 141 bool isCCInstr(MachineOpCode opCode) const { 142 return getDescriptor(opCode).iclass & M_CC_FLAG; 143 } 144 bool isLogical(MachineOpCode opCode) const { 145 return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 146 } 147 bool isIntInstr(MachineOpCode opCode) const { 148 return getDescriptor(opCode).iclass & M_INT_FLAG; 149 } 150 bool isFloatInstr(MachineOpCode opCode) const { 151 return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 152 } 153 bool isConditional(MachineOpCode opCode) const { 154 return getDescriptor(opCode).iclass & M_CONDL_FLAG; 155 } 156 bool isLoad(MachineOpCode opCode) const { 157 return getDescriptor(opCode).iclass & M_LOAD_FLAG; 158 } 159 bool isPrefetch(MachineOpCode opCode) const { 160 return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 161 } 162 bool isLoadOrPrefetch(MachineOpCode opCode) const { 163 return getDescriptor(opCode).iclass & M_LOAD_FLAG 164 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 165 } 166 bool isStore(MachineOpCode opCode) const { 167 return getDescriptor(opCode).iclass & M_STORE_FLAG; 168 } 169 bool isMemoryAccess(MachineOpCode opCode) const { 170 return getDescriptor(opCode).iclass & M_LOAD_FLAG 171 || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 172 || getDescriptor(opCode).iclass & M_STORE_FLAG; 173 } 174 bool isDummyPhiInstr(const MachineOpCode opCode) const { 175 return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 176 } 177 178 179 // delete this later ******* 180 bool isPhi(const MachineOpCode opCode) const 181 { return isDummyPhiInstr(opCode); } 182 183 bool isPseudoInstr(const MachineOpCode opCode) const { 184 return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; 185 } 186 187 188 189 // Check if an instruction can be issued before its operands are ready, 190 // or if a subsequent instruction that uses its result can be issued 191 // before the results are ready. 192 // Default to true since most instructions on many architectures allow this. 193 // 194 virtual bool hasOperandInterlock(MachineOpCode opCode) const { 195 return true; 196 } 197 198 virtual bool hasResultInterlock(MachineOpCode opCode) const { 199 return true; 200 } 201 202 // 203 // Latencies for individual instructions and instruction pairs 204 // 205 virtual int minLatency(MachineOpCode opCode) const { 206 return getDescriptor(opCode).latency; 207 } 208 209 virtual int maxLatency(MachineOpCode opCode) const { 210 return getDescriptor(opCode).latency; 211 } 212 213 // Check if the specified constant fits in the immediate field 214 // of this machine instruction 215 // 216 virtual bool constantFitsInImmedField(MachineOpCode opCode, 217 int64_t intValue) const; 218 219 // Return the largest +ve constant that can be held in the IMMMED field 220 // of this machine instruction. 221 // isSignExtended is set to true if the value is sign-extended before use 222 // (this is true for all immediate fields in SPARC instructions). 223 // Return 0 if the instruction has no IMMED field. 224 // 225 virtual uint64_t maxImmedConstant(MachineOpCode opCode, 226 bool &isSignExtended) const { 227 isSignExtended = getDescriptor(opCode).immedIsSignExtended; 228 return getDescriptor(opCode).maxImmedConst; 229 } 230 231 //------------------------------------------------------------------------- 232 // Code generation support for creating individual machine instructions 233 //------------------------------------------------------------------------- 234 235 // Create an instruction sequence to put the constant `val' into 236 // the virtual register `dest'. `val' may be a ConstPoolVal or a 237 // GlobalValue, viz., the constant address of a global variable or function. 238 // The generated instructions are returned in `minstrVec'. 239 // Any temp. registers (TmpInstruction) created are returned in `tempVec'. 240 // 241 virtual void CreateCodeToLoadConst(Value* val, 242 Instruction* dest, 243 vector<MachineInstr*>& minstrVec, 244 vector<TmpInstruction*>& temps) const =0; 245 246 // Create an instruction sequence to copy an integer value `val' 247 // to a floating point value `dest' by copying to memory and back. 248 // val must be an integral type. dest must be a Float or Double. 249 // The generated instructions are returned in `minstrVec'. 250 // Any temp. registers (TmpInstruction) created are returned in `tempVec'. 251 // 252 virtual void CreateCodeToCopyIntToFloat(Method* method, 253 Value* val, 254 Instruction* dest, 255 vector<MachineInstr*>& minstrVec, 256 vector<TmpInstruction*>& tempVec, 257 TargetMachine& target) const = 0; 258 259 // Similarly, create an instruction sequence to copy an FP value 260 // `val' to an integer value `dest' by copying to memory and back. 261 // See the previous function for information about return values. 262 // 263 virtual void CreateCodeToCopyFloatToInt(Method* method, 264 Value* val, 265 Instruction* dest, 266 vector<MachineInstr*>& minstrVec, 267 vector<TmpInstruction*>& tempVec, 268 TargetMachine& target) const = 0; 269 270 271 // create copy instruction(s) 272 virtual void 273 CreateCopyInstructionsByType(const TargetMachine& target, 274 Value* src, 275 Instruction* dest, 276 vector<MachineInstr*>& minstrVec) const = 0; 277 278 279 280}; 281 282#endif 283