DAGCombiner.cpp revision 267010864e139781ef5949939e081c41f954de0a
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 142 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 143 ISD::NodeType ExtType); 144 145 /// combine - call the node-specific routine that knows how to fold each 146 /// particular type of node. If that doesn't do anything, try the 147 /// target-specific DAG combines. 148 SDValue combine(SDNode *N); 149 150 // Visitation implementation - Implement dag node combining for different 151 // node types. The semantics are as follows: 152 // Return Value: 153 // SDValue.getNode() == 0 - No change was made 154 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 155 // otherwise - N should be replaced by the returned Operand. 156 // 157 SDValue visitTokenFactor(SDNode *N); 158 SDValue visitMERGE_VALUES(SDNode *N); 159 SDValue visitADD(SDNode *N); 160 SDValue visitSUB(SDNode *N); 161 SDValue visitADDC(SDNode *N); 162 SDValue visitADDE(SDNode *N); 163 SDValue visitMUL(SDNode *N); 164 SDValue visitSDIV(SDNode *N); 165 SDValue visitUDIV(SDNode *N); 166 SDValue visitSREM(SDNode *N); 167 SDValue visitUREM(SDNode *N); 168 SDValue visitMULHU(SDNode *N); 169 SDValue visitMULHS(SDNode *N); 170 SDValue visitSMUL_LOHI(SDNode *N); 171 SDValue visitUMUL_LOHI(SDNode *N); 172 SDValue visitSMULO(SDNode *N); 173 SDValue visitUMULO(SDNode *N); 174 SDValue visitSDIVREM(SDNode *N); 175 SDValue visitUDIVREM(SDNode *N); 176 SDValue visitAND(SDNode *N); 177 SDValue visitOR(SDNode *N); 178 SDValue visitXOR(SDNode *N); 179 SDValue SimplifyVBinOp(SDNode *N); 180 SDValue visitSHL(SDNode *N); 181 SDValue visitSRA(SDNode *N); 182 SDValue visitSRL(SDNode *N); 183 SDValue visitCTLZ(SDNode *N); 184 SDValue visitCTTZ(SDNode *N); 185 SDValue visitCTPOP(SDNode *N); 186 SDValue visitSELECT(SDNode *N); 187 SDValue visitSELECT_CC(SDNode *N); 188 SDValue visitSETCC(SDNode *N); 189 SDValue visitSIGN_EXTEND(SDNode *N); 190 SDValue visitZERO_EXTEND(SDNode *N); 191 SDValue visitANY_EXTEND(SDNode *N); 192 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 193 SDValue visitTRUNCATE(SDNode *N); 194 SDValue visitBITCAST(SDNode *N); 195 SDValue visitBUILD_PAIR(SDNode *N); 196 SDValue visitFADD(SDNode *N); 197 SDValue visitFSUB(SDNode *N); 198 SDValue visitFMUL(SDNode *N); 199 SDValue visitFDIV(SDNode *N); 200 SDValue visitFREM(SDNode *N); 201 SDValue visitFCOPYSIGN(SDNode *N); 202 SDValue visitSINT_TO_FP(SDNode *N); 203 SDValue visitUINT_TO_FP(SDNode *N); 204 SDValue visitFP_TO_SINT(SDNode *N); 205 SDValue visitFP_TO_UINT(SDNode *N); 206 SDValue visitFP_ROUND(SDNode *N); 207 SDValue visitFP_ROUND_INREG(SDNode *N); 208 SDValue visitFP_EXTEND(SDNode *N); 209 SDValue visitFNEG(SDNode *N); 210 SDValue visitFABS(SDNode *N); 211 SDValue visitBRCOND(SDNode *N); 212 SDValue visitBR_CC(SDNode *N); 213 SDValue visitLOAD(SDNode *N); 214 SDValue visitSTORE(SDNode *N); 215 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 216 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 217 SDValue visitBUILD_VECTOR(SDNode *N); 218 SDValue visitCONCAT_VECTORS(SDNode *N); 219 SDValue visitVECTOR_SHUFFLE(SDNode *N); 220 SDValue visitMEMBARRIER(SDNode *N); 221 222 SDValue XformToShuffleWithZero(SDNode *N); 223 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 224 225 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 226 227 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 228 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 229 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 230 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 231 SDValue N3, ISD::CondCode CC, 232 bool NotExtCompare = false); 233 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 234 DebugLoc DL, bool foldBooleans = true); 235 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 236 unsigned HiOp); 237 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 238 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 239 SDValue BuildSDIV(SDNode *N); 240 SDValue BuildUDIV(SDNode *N); 241 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 242 bool DemandHighBits = true); 243 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 244 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 245 SDValue ReduceLoadWidth(SDNode *N); 246 SDValue ReduceLoadOpStoreWidth(SDNode *N); 247 SDValue TransformFPLoadStorePair(SDNode *N); 248 249 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 250 251 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 252 /// looking for aliasing nodes and adding them to the Aliases vector. 253 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 254 SmallVector<SDValue, 8> &Aliases); 255 256 /// isAlias - Return true if there is any possibility that the two addresses 257 /// overlap. 258 bool isAlias(SDValue Ptr1, int64_t Size1, 259 const Value *SrcValue1, int SrcValueOffset1, 260 unsigned SrcValueAlign1, 261 const MDNode *TBAAInfo1, 262 SDValue Ptr2, int64_t Size2, 263 const Value *SrcValue2, int SrcValueOffset2, 264 unsigned SrcValueAlign2, 265 const MDNode *TBAAInfo2) const; 266 267 /// FindAliasInfo - Extracts the relevant alias information from the memory 268 /// node. Returns true if the operand was a load. 269 bool FindAliasInfo(SDNode *N, 270 SDValue &Ptr, int64_t &Size, 271 const Value *&SrcValue, int &SrcValueOffset, 272 unsigned &SrcValueAlignment, 273 const MDNode *&TBAAInfo) const; 274 275 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 276 /// looking for a better chain (aliasing node.) 277 SDValue FindBetterChain(SDNode *N, SDValue Chain); 278 279 public: 280 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 281 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 282 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 283 284 /// Run - runs the dag combiner on all nodes in the work list 285 void Run(CombineLevel AtLevel); 286 287 SelectionDAG &getDAG() const { return DAG; } 288 289 /// getShiftAmountTy - Returns a type large enough to hold any valid 290 /// shift amount - before type legalization these can be huge. 291 EVT getShiftAmountTy(EVT LHSTy) { 292 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 293 } 294 295 /// isTypeLegal - This method returns true if we are running before type 296 /// legalization or if the specified VT is legal. 297 bool isTypeLegal(const EVT &VT) { 298 if (!LegalTypes) return true; 299 return TLI.isTypeLegal(VT); 300 } 301 }; 302} 303 304 305namespace { 306/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 307/// nodes from the worklist. 308class WorkListRemover : public SelectionDAG::DAGUpdateListener { 309 DAGCombiner &DC; 310public: 311 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 312 313 virtual void NodeDeleted(SDNode *N, SDNode *E) { 314 DC.removeFromWorkList(N); 315 } 316 317 virtual void NodeUpdated(SDNode *N) { 318 // Ignore updates. 319 } 320}; 321} 322 323//===----------------------------------------------------------------------===// 324// TargetLowering::DAGCombinerInfo implementation 325//===----------------------------------------------------------------------===// 326 327void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 328 ((DAGCombiner*)DC)->AddToWorkList(N); 329} 330 331void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 332 ((DAGCombiner*)DC)->removeFromWorkList(N); 333} 334 335SDValue TargetLowering::DAGCombinerInfo:: 336CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 337 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 338} 339 340SDValue TargetLowering::DAGCombinerInfo:: 341CombineTo(SDNode *N, SDValue Res, bool AddTo) { 342 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 343} 344 345 346SDValue TargetLowering::DAGCombinerInfo:: 347CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 348 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 349} 350 351void TargetLowering::DAGCombinerInfo:: 352CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 353 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 354} 355 356//===----------------------------------------------------------------------===// 357// Helper Functions 358//===----------------------------------------------------------------------===// 359 360/// isNegatibleForFree - Return 1 if we can compute the negated form of the 361/// specified expression for the same cost as the expression itself, or 2 if we 362/// can compute the negated form more cheaply than the expression itself. 363static char isNegatibleForFree(SDValue Op, bool LegalOperations, 364 unsigned Depth = 0) { 365 // No compile time optimizations on this type. 366 if (Op.getValueType() == MVT::ppcf128) 367 return 0; 368 369 // fneg is removable even if it has multiple uses. 370 if (Op.getOpcode() == ISD::FNEG) return 2; 371 372 // Don't allow anything with multiple uses. 373 if (!Op.hasOneUse()) return 0; 374 375 // Don't recurse exponentially. 376 if (Depth > 6) return 0; 377 378 switch (Op.getOpcode()) { 379 default: return false; 380 case ISD::ConstantFP: 381 // Don't invert constant FP values after legalize. The negated constant 382 // isn't necessarily legal. 383 return LegalOperations ? 0 : 1; 384 case ISD::FADD: 385 // FIXME: determine better conditions for this xform. 386 if (!UnsafeFPMath) return 0; 387 388 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 389 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 390 return V; 391 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 392 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 393 case ISD::FSUB: 394 // We can't turn -(A-B) into B-A when we honor signed zeros. 395 if (!UnsafeFPMath) return 0; 396 397 // fold (fneg (fsub A, B)) -> (fsub B, A) 398 return 1; 399 400 case ISD::FMUL: 401 case ISD::FDIV: 402 if (HonorSignDependentRoundingFPMath()) return 0; 403 404 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 405 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 406 return V; 407 408 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 409 410 case ISD::FP_EXTEND: 411 case ISD::FP_ROUND: 412 case ISD::FSIN: 413 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 414 } 415} 416 417/// GetNegatedExpression - If isNegatibleForFree returns true, this function 418/// returns the newly negated expression. 419static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 420 bool LegalOperations, unsigned Depth = 0) { 421 // fneg is removable even if it has multiple uses. 422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 423 424 // Don't allow anything with multiple uses. 425 assert(Op.hasOneUse() && "Unknown reuse!"); 426 427 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 428 switch (Op.getOpcode()) { 429 default: llvm_unreachable("Unknown code"); 430 case ISD::ConstantFP: { 431 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 432 V.changeSign(); 433 return DAG.getConstantFP(V, Op.getValueType()); 434 } 435 case ISD::FADD: 436 // FIXME: determine better conditions for this xform. 437 assert(UnsafeFPMath); 438 439 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 440 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 441 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 442 GetNegatedExpression(Op.getOperand(0), DAG, 443 LegalOperations, Depth+1), 444 Op.getOperand(1)); 445 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1), 449 Op.getOperand(0)); 450 case ISD::FSUB: 451 // We can't turn -(A-B) into B-A when we honor signed zeros. 452 assert(UnsafeFPMath); 453 454 // fold (fneg (fsub 0, B)) -> B 455 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 456 if (N0CFP->getValueAPF().isZero()) 457 return Op.getOperand(1); 458 459 // fold (fneg (fsub A, B)) -> (fsub B, A) 460 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 461 Op.getOperand(1), Op.getOperand(0)); 462 463 case ISD::FMUL: 464 case ISD::FDIV: 465 assert(!HonorSignDependentRoundingFPMath()); 466 467 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 468 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 469 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 470 GetNegatedExpression(Op.getOperand(0), DAG, 471 LegalOperations, Depth+1), 472 Op.getOperand(1)); 473 474 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 475 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 476 Op.getOperand(0), 477 GetNegatedExpression(Op.getOperand(1), DAG, 478 LegalOperations, Depth+1)); 479 480 case ISD::FP_EXTEND: 481 case ISD::FSIN: 482 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 483 GetNegatedExpression(Op.getOperand(0), DAG, 484 LegalOperations, Depth+1)); 485 case ISD::FP_ROUND: 486 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 487 GetNegatedExpression(Op.getOperand(0), DAG, 488 LegalOperations, Depth+1), 489 Op.getOperand(1)); 490 } 491} 492 493 494// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 495// that selects between the values 1 and 0, making it equivalent to a setcc. 496// Also, set the incoming LHS, RHS, and CC references to the appropriate 497// nodes based on the type of node we are checking. This simplifies life a 498// bit for the callers. 499static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 500 SDValue &CC) { 501 if (N.getOpcode() == ISD::SETCC) { 502 LHS = N.getOperand(0); 503 RHS = N.getOperand(1); 504 CC = N.getOperand(2); 505 return true; 506 } 507 if (N.getOpcode() == ISD::SELECT_CC && 508 N.getOperand(2).getOpcode() == ISD::Constant && 509 N.getOperand(3).getOpcode() == ISD::Constant && 510 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 511 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 512 LHS = N.getOperand(0); 513 RHS = N.getOperand(1); 514 CC = N.getOperand(4); 515 return true; 516 } 517 return false; 518} 519 520// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 521// one use. If this is true, it allows the users to invert the operation for 522// free when it is profitable to do so. 523static bool isOneUseSetCC(SDValue N) { 524 SDValue N0, N1, N2; 525 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 526 return true; 527 return false; 528} 529 530SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 531 SDValue N0, SDValue N1) { 532 EVT VT = N0.getValueType(); 533 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 534 if (isa<ConstantSDNode>(N1)) { 535 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 536 SDValue OpNode = 537 DAG.FoldConstantArithmetic(Opc, VT, 538 cast<ConstantSDNode>(N0.getOperand(1)), 539 cast<ConstantSDNode>(N1)); 540 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 541 } 542 if (N0.hasOneUse()) { 543 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 544 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 545 N0.getOperand(0), N1); 546 AddToWorkList(OpNode.getNode()); 547 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 548 } 549 } 550 551 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 552 if (isa<ConstantSDNode>(N0)) { 553 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 554 SDValue OpNode = 555 DAG.FoldConstantArithmetic(Opc, VT, 556 cast<ConstantSDNode>(N1.getOperand(1)), 557 cast<ConstantSDNode>(N0)); 558 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 559 } 560 if (N1.hasOneUse()) { 561 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 562 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 563 N1.getOperand(0), N0); 564 AddToWorkList(OpNode.getNode()); 565 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 566 } 567 } 568 569 return SDValue(); 570} 571 572SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 573 bool AddTo) { 574 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 575 ++NodesCombined; 576 DEBUG(dbgs() << "\nReplacing.1 "; 577 N->dump(&DAG); 578 dbgs() << "\nWith: "; 579 To[0].getNode()->dump(&DAG); 580 dbgs() << " and " << NumTo-1 << " other values\n"; 581 for (unsigned i = 0, e = NumTo; i != e; ++i) 582 assert((!To[i].getNode() || 583 N->getValueType(i) == To[i].getValueType()) && 584 "Cannot combine value to value of different type!")); 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 587 588 if (AddTo) { 589 // Push the new nodes and any users onto the worklist 590 for (unsigned i = 0, e = NumTo; i != e; ++i) { 591 if (To[i].getNode()) { 592 AddToWorkList(To[i].getNode()); 593 AddUsersToWorkList(To[i].getNode()); 594 } 595 } 596 } 597 598 // Finally, if the node is now dead, remove it from the graph. The node 599 // may not be dead if the replacement process recursively simplified to 600 // something else needing this node. 601 if (N->use_empty()) { 602 // Nodes can be reintroduced into the worklist. Make sure we do not 603 // process a node that has been replaced. 604 removeFromWorkList(N); 605 606 // Finally, since the node is now dead, remove it from the graph. 607 DAG.DeleteNode(N); 608 } 609 return SDValue(N, 0); 610} 611 612void DAGCombiner:: 613CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 614 // Replace all uses. If any nodes become isomorphic to other nodes and 615 // are deleted, make sure to remove them from our worklist. 616 WorkListRemover DeadNodes(*this); 617 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 618 619 // Push the new node and any (possibly new) users onto the worklist. 620 AddToWorkList(TLO.New.getNode()); 621 AddUsersToWorkList(TLO.New.getNode()); 622 623 // Finally, if the node is now dead, remove it from the graph. The node 624 // may not be dead if the replacement process recursively simplified to 625 // something else needing this node. 626 if (TLO.Old.getNode()->use_empty()) { 627 removeFromWorkList(TLO.Old.getNode()); 628 629 // If the operands of this node are only used by the node, they will now 630 // be dead. Make sure to visit them first to delete dead nodes early. 631 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 632 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 633 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 634 635 DAG.DeleteNode(TLO.Old.getNode()); 636 } 637} 638 639/// SimplifyDemandedBits - Check the specified integer node value to see if 640/// it can be simplified or if things it uses can be simplified by bit 641/// propagation. If so, return true. 642bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 643 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 644 APInt KnownZero, KnownOne; 645 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 646 return false; 647 648 // Revisit the node. 649 AddToWorkList(Op.getNode()); 650 651 // Replace the old value with the new one. 652 ++NodesCombined; 653 DEBUG(dbgs() << "\nReplacing.2 "; 654 TLO.Old.getNode()->dump(&DAG); 655 dbgs() << "\nWith: "; 656 TLO.New.getNode()->dump(&DAG); 657 dbgs() << '\n'); 658 659 CommitTargetLoweringOpt(TLO); 660 return true; 661} 662 663void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 664 DebugLoc dl = Load->getDebugLoc(); 665 EVT VT = Load->getValueType(0); 666 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 667 668 DEBUG(dbgs() << "\nReplacing.9 "; 669 Load->dump(&DAG); 670 dbgs() << "\nWith: "; 671 Trunc.getNode()->dump(&DAG); 672 dbgs() << '\n'); 673 WorkListRemover DeadNodes(*this); 674 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 675 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 676 &DeadNodes); 677 removeFromWorkList(Load); 678 DAG.DeleteNode(Load); 679 AddToWorkList(Trunc.getNode()); 680} 681 682SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 683 Replace = false; 684 DebugLoc dl = Op.getDebugLoc(); 685 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 686 EVT MemVT = LD->getMemoryVT(); 687 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 688 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 689 : ISD::EXTLOAD) 690 : LD->getExtensionType(); 691 Replace = true; 692 return DAG.getExtLoad(ExtType, dl, PVT, 693 LD->getChain(), LD->getBasePtr(), 694 LD->getPointerInfo(), 695 MemVT, LD->isVolatile(), 696 LD->isNonTemporal(), LD->getAlignment()); 697 } 698 699 unsigned Opc = Op.getOpcode(); 700 switch (Opc) { 701 default: break; 702 case ISD::AssertSext: 703 return DAG.getNode(ISD::AssertSext, dl, PVT, 704 SExtPromoteOperand(Op.getOperand(0), PVT), 705 Op.getOperand(1)); 706 case ISD::AssertZext: 707 return DAG.getNode(ISD::AssertZext, dl, PVT, 708 ZExtPromoteOperand(Op.getOperand(0), PVT), 709 Op.getOperand(1)); 710 case ISD::Constant: { 711 unsigned ExtOpc = 712 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 713 return DAG.getNode(ExtOpc, dl, PVT, Op); 714 } 715 } 716 717 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 718 return SDValue(); 719 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 720} 721 722SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 723 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 724 return SDValue(); 725 EVT OldVT = Op.getValueType(); 726 DebugLoc dl = Op.getDebugLoc(); 727 bool Replace = false; 728 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 729 if (NewOp.getNode() == 0) 730 return SDValue(); 731 AddToWorkList(NewOp.getNode()); 732 733 if (Replace) 734 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 735 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 736 DAG.getValueType(OldVT)); 737} 738 739SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 740 EVT OldVT = Op.getValueType(); 741 DebugLoc dl = Op.getDebugLoc(); 742 bool Replace = false; 743 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 744 if (NewOp.getNode() == 0) 745 return SDValue(); 746 AddToWorkList(NewOp.getNode()); 747 748 if (Replace) 749 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 750 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 751} 752 753/// PromoteIntBinOp - Promote the specified integer binary operation if the 754/// target indicates it is beneficial. e.g. On x86, it's usually better to 755/// promote i16 operations to i32 since i16 instructions are longer. 756SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 757 if (!LegalOperations) 758 return SDValue(); 759 760 EVT VT = Op.getValueType(); 761 if (VT.isVector() || !VT.isInteger()) 762 return SDValue(); 763 764 // If operation type is 'undesirable', e.g. i16 on x86, consider 765 // promoting it. 766 unsigned Opc = Op.getOpcode(); 767 if (TLI.isTypeDesirableForOp(Opc, VT)) 768 return SDValue(); 769 770 EVT PVT = VT; 771 // Consult target whether it is a good idea to promote this operation and 772 // what's the right type to promote it to. 773 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 774 assert(PVT != VT && "Don't know what type to promote to!"); 775 776 bool Replace0 = false; 777 SDValue N0 = Op.getOperand(0); 778 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 779 if (NN0.getNode() == 0) 780 return SDValue(); 781 782 bool Replace1 = false; 783 SDValue N1 = Op.getOperand(1); 784 SDValue NN1; 785 if (N0 == N1) 786 NN1 = NN0; 787 else { 788 NN1 = PromoteOperand(N1, PVT, Replace1); 789 if (NN1.getNode() == 0) 790 return SDValue(); 791 } 792 793 AddToWorkList(NN0.getNode()); 794 if (NN1.getNode()) 795 AddToWorkList(NN1.getNode()); 796 797 if (Replace0) 798 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 799 if (Replace1) 800 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 801 802 DEBUG(dbgs() << "\nPromoting "; 803 Op.getNode()->dump(&DAG)); 804 DebugLoc dl = Op.getDebugLoc(); 805 return DAG.getNode(ISD::TRUNCATE, dl, VT, 806 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 807 } 808 return SDValue(); 809} 810 811/// PromoteIntShiftOp - Promote the specified integer shift operation if the 812/// target indicates it is beneficial. e.g. On x86, it's usually better to 813/// promote i16 operations to i32 since i16 instructions are longer. 814SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 815 if (!LegalOperations) 816 return SDValue(); 817 818 EVT VT = Op.getValueType(); 819 if (VT.isVector() || !VT.isInteger()) 820 return SDValue(); 821 822 // If operation type is 'undesirable', e.g. i16 on x86, consider 823 // promoting it. 824 unsigned Opc = Op.getOpcode(); 825 if (TLI.isTypeDesirableForOp(Opc, VT)) 826 return SDValue(); 827 828 EVT PVT = VT; 829 // Consult target whether it is a good idea to promote this operation and 830 // what's the right type to promote it to. 831 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 832 assert(PVT != VT && "Don't know what type to promote to!"); 833 834 bool Replace = false; 835 SDValue N0 = Op.getOperand(0); 836 if (Opc == ISD::SRA) 837 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 838 else if (Opc == ISD::SRL) 839 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 840 else 841 N0 = PromoteOperand(N0, PVT, Replace); 842 if (N0.getNode() == 0) 843 return SDValue(); 844 845 AddToWorkList(N0.getNode()); 846 if (Replace) 847 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 848 849 DEBUG(dbgs() << "\nPromoting "; 850 Op.getNode()->dump(&DAG)); 851 DebugLoc dl = Op.getDebugLoc(); 852 return DAG.getNode(ISD::TRUNCATE, dl, VT, 853 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 854 } 855 return SDValue(); 856} 857 858SDValue DAGCombiner::PromoteExtend(SDValue Op) { 859 if (!LegalOperations) 860 return SDValue(); 861 862 EVT VT = Op.getValueType(); 863 if (VT.isVector() || !VT.isInteger()) 864 return SDValue(); 865 866 // If operation type is 'undesirable', e.g. i16 on x86, consider 867 // promoting it. 868 unsigned Opc = Op.getOpcode(); 869 if (TLI.isTypeDesirableForOp(Opc, VT)) 870 return SDValue(); 871 872 EVT PVT = VT; 873 // Consult target whether it is a good idea to promote this operation and 874 // what's the right type to promote it to. 875 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 876 assert(PVT != VT && "Don't know what type to promote to!"); 877 // fold (aext (aext x)) -> (aext x) 878 // fold (aext (zext x)) -> (zext x) 879 // fold (aext (sext x)) -> (sext x) 880 DEBUG(dbgs() << "\nPromoting "; 881 Op.getNode()->dump(&DAG)); 882 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 883 } 884 return SDValue(); 885} 886 887bool DAGCombiner::PromoteLoad(SDValue Op) { 888 if (!LegalOperations) 889 return false; 890 891 EVT VT = Op.getValueType(); 892 if (VT.isVector() || !VT.isInteger()) 893 return false; 894 895 // If operation type is 'undesirable', e.g. i16 on x86, consider 896 // promoting it. 897 unsigned Opc = Op.getOpcode(); 898 if (TLI.isTypeDesirableForOp(Opc, VT)) 899 return false; 900 901 EVT PVT = VT; 902 // Consult target whether it is a good idea to promote this operation and 903 // what's the right type to promote it to. 904 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 905 assert(PVT != VT && "Don't know what type to promote to!"); 906 907 DebugLoc dl = Op.getDebugLoc(); 908 SDNode *N = Op.getNode(); 909 LoadSDNode *LD = cast<LoadSDNode>(N); 910 EVT MemVT = LD->getMemoryVT(); 911 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 912 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 913 : ISD::EXTLOAD) 914 : LD->getExtensionType(); 915 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 916 LD->getChain(), LD->getBasePtr(), 917 LD->getPointerInfo(), 918 MemVT, LD->isVolatile(), 919 LD->isNonTemporal(), LD->getAlignment()); 920 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 921 922 DEBUG(dbgs() << "\nPromoting "; 923 N->dump(&DAG); 924 dbgs() << "\nTo: "; 925 Result.getNode()->dump(&DAG); 926 dbgs() << '\n'); 927 WorkListRemover DeadNodes(*this); 928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 930 removeFromWorkList(N); 931 DAG.DeleteNode(N); 932 AddToWorkList(Result.getNode()); 933 return true; 934 } 935 return false; 936} 937 938 939//===----------------------------------------------------------------------===// 940// Main DAG Combiner implementation 941//===----------------------------------------------------------------------===// 942 943void DAGCombiner::Run(CombineLevel AtLevel) { 944 // set the instance variables, so that the various visit routines may use it. 945 Level = AtLevel; 946 LegalOperations = Level >= NoIllegalOperations; 947 LegalTypes = Level >= NoIllegalTypes; 948 949 // Add all the dag nodes to the worklist. 950 WorkList.reserve(DAG.allnodes_size()); 951 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 952 E = DAG.allnodes_end(); I != E; ++I) 953 WorkList.push_back(I); 954 955 // Create a dummy node (which is not added to allnodes), that adds a reference 956 // to the root node, preventing it from being deleted, and tracking any 957 // changes of the root. 958 HandleSDNode Dummy(DAG.getRoot()); 959 960 // The root of the dag may dangle to deleted nodes until the dag combiner is 961 // done. Set it to null to avoid confusion. 962 DAG.setRoot(SDValue()); 963 964 // while the worklist isn't empty, inspect the node on the end of it and 965 // try and combine it. 966 while (!WorkList.empty()) { 967 SDNode *N = WorkList.back(); 968 WorkList.pop_back(); 969 970 // If N has no uses, it is dead. Make sure to revisit all N's operands once 971 // N is deleted from the DAG, since they too may now be dead or may have a 972 // reduced number of uses, allowing other xforms. 973 if (N->use_empty() && N != &Dummy) { 974 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 975 AddToWorkList(N->getOperand(i).getNode()); 976 977 DAG.DeleteNode(N); 978 continue; 979 } 980 981 SDValue RV = combine(N); 982 983 if (RV.getNode() == 0) 984 continue; 985 986 ++NodesCombined; 987 988 // If we get back the same node we passed in, rather than a new node or 989 // zero, we know that the node must have defined multiple values and 990 // CombineTo was used. Since CombineTo takes care of the worklist 991 // mechanics for us, we have no work to do in this case. 992 if (RV.getNode() == N) 993 continue; 994 995 assert(N->getOpcode() != ISD::DELETED_NODE && 996 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 997 "Node was deleted but visit returned new node!"); 998 999 DEBUG(dbgs() << "\nReplacing.3 "; 1000 N->dump(&DAG); 1001 dbgs() << "\nWith: "; 1002 RV.getNode()->dump(&DAG); 1003 dbgs() << '\n'); 1004 1005 // Transfer debug value. 1006 DAG.TransferDbgValues(SDValue(N, 0), RV); 1007 WorkListRemover DeadNodes(*this); 1008 if (N->getNumValues() == RV.getNode()->getNumValues()) 1009 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1010 else { 1011 assert(N->getValueType(0) == RV.getValueType() && 1012 N->getNumValues() == 1 && "Type mismatch"); 1013 SDValue OpV = RV; 1014 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1015 } 1016 1017 // Push the new node and any users onto the worklist 1018 AddToWorkList(RV.getNode()); 1019 AddUsersToWorkList(RV.getNode()); 1020 1021 // Add any uses of the old node to the worklist in case this node is the 1022 // last one that uses them. They may become dead after this node is 1023 // deleted. 1024 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1025 AddToWorkList(N->getOperand(i).getNode()); 1026 1027 // Finally, if the node is now dead, remove it from the graph. The node 1028 // may not be dead if the replacement process recursively simplified to 1029 // something else needing this node. 1030 if (N->use_empty()) { 1031 // Nodes can be reintroduced into the worklist. Make sure we do not 1032 // process a node that has been replaced. 1033 removeFromWorkList(N); 1034 1035 // Finally, since the node is now dead, remove it from the graph. 1036 DAG.DeleteNode(N); 1037 } 1038 } 1039 1040 // If the root changed (e.g. it was a dead load, update the root). 1041 DAG.setRoot(Dummy.getValue()); 1042} 1043 1044SDValue DAGCombiner::visit(SDNode *N) { 1045 switch (N->getOpcode()) { 1046 default: break; 1047 case ISD::TokenFactor: return visitTokenFactor(N); 1048 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1049 case ISD::ADD: return visitADD(N); 1050 case ISD::SUB: return visitSUB(N); 1051 case ISD::ADDC: return visitADDC(N); 1052 case ISD::ADDE: return visitADDE(N); 1053 case ISD::MUL: return visitMUL(N); 1054 case ISD::SDIV: return visitSDIV(N); 1055 case ISD::UDIV: return visitUDIV(N); 1056 case ISD::SREM: return visitSREM(N); 1057 case ISD::UREM: return visitUREM(N); 1058 case ISD::MULHU: return visitMULHU(N); 1059 case ISD::MULHS: return visitMULHS(N); 1060 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1061 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1062 case ISD::SMULO: return visitSMULO(N); 1063 case ISD::UMULO: return visitUMULO(N); 1064 case ISD::SDIVREM: return visitSDIVREM(N); 1065 case ISD::UDIVREM: return visitUDIVREM(N); 1066 case ISD::AND: return visitAND(N); 1067 case ISD::OR: return visitOR(N); 1068 case ISD::XOR: return visitXOR(N); 1069 case ISD::SHL: return visitSHL(N); 1070 case ISD::SRA: return visitSRA(N); 1071 case ISD::SRL: return visitSRL(N); 1072 case ISD::CTLZ: return visitCTLZ(N); 1073 case ISD::CTTZ: return visitCTTZ(N); 1074 case ISD::CTPOP: return visitCTPOP(N); 1075 case ISD::SELECT: return visitSELECT(N); 1076 case ISD::SELECT_CC: return visitSELECT_CC(N); 1077 case ISD::SETCC: return visitSETCC(N); 1078 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1079 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1080 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1081 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1082 case ISD::TRUNCATE: return visitTRUNCATE(N); 1083 case ISD::BITCAST: return visitBITCAST(N); 1084 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1085 case ISD::FADD: return visitFADD(N); 1086 case ISD::FSUB: return visitFSUB(N); 1087 case ISD::FMUL: return visitFMUL(N); 1088 case ISD::FDIV: return visitFDIV(N); 1089 case ISD::FREM: return visitFREM(N); 1090 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1091 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1092 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1093 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1094 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1095 case ISD::FP_ROUND: return visitFP_ROUND(N); 1096 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1097 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1098 case ISD::FNEG: return visitFNEG(N); 1099 case ISD::FABS: return visitFABS(N); 1100 case ISD::BRCOND: return visitBRCOND(N); 1101 case ISD::BR_CC: return visitBR_CC(N); 1102 case ISD::LOAD: return visitLOAD(N); 1103 case ISD::STORE: return visitSTORE(N); 1104 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1105 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1106 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1107 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1108 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1109 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1110 } 1111 return SDValue(); 1112} 1113 1114SDValue DAGCombiner::combine(SDNode *N) { 1115 SDValue RV = visit(N); 1116 1117 // If nothing happened, try a target-specific DAG combine. 1118 if (RV.getNode() == 0) { 1119 assert(N->getOpcode() != ISD::DELETED_NODE && 1120 "Node was deleted but visit returned NULL!"); 1121 1122 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1123 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1124 1125 // Expose the DAG combiner to the target combiner impls. 1126 TargetLowering::DAGCombinerInfo 1127 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1128 1129 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1130 } 1131 } 1132 1133 // If nothing happened still, try promoting the operation. 1134 if (RV.getNode() == 0) { 1135 switch (N->getOpcode()) { 1136 default: break; 1137 case ISD::ADD: 1138 case ISD::SUB: 1139 case ISD::MUL: 1140 case ISD::AND: 1141 case ISD::OR: 1142 case ISD::XOR: 1143 RV = PromoteIntBinOp(SDValue(N, 0)); 1144 break; 1145 case ISD::SHL: 1146 case ISD::SRA: 1147 case ISD::SRL: 1148 RV = PromoteIntShiftOp(SDValue(N, 0)); 1149 break; 1150 case ISD::SIGN_EXTEND: 1151 case ISD::ZERO_EXTEND: 1152 case ISD::ANY_EXTEND: 1153 RV = PromoteExtend(SDValue(N, 0)); 1154 break; 1155 case ISD::LOAD: 1156 if (PromoteLoad(SDValue(N, 0))) 1157 RV = SDValue(N, 0); 1158 break; 1159 } 1160 } 1161 1162 // If N is a commutative binary node, try commuting it to enable more 1163 // sdisel CSE. 1164 if (RV.getNode() == 0 && 1165 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1166 N->getNumValues() == 1) { 1167 SDValue N0 = N->getOperand(0); 1168 SDValue N1 = N->getOperand(1); 1169 1170 // Constant operands are canonicalized to RHS. 1171 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1172 SDValue Ops[] = { N1, N0 }; 1173 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1174 Ops, 2); 1175 if (CSENode) 1176 return SDValue(CSENode, 0); 1177 } 1178 } 1179 1180 return RV; 1181} 1182 1183/// getInputChainForNode - Given a node, return its input chain if it has one, 1184/// otherwise return a null sd operand. 1185static SDValue getInputChainForNode(SDNode *N) { 1186 if (unsigned NumOps = N->getNumOperands()) { 1187 if (N->getOperand(0).getValueType() == MVT::Other) 1188 return N->getOperand(0); 1189 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1190 return N->getOperand(NumOps-1); 1191 for (unsigned i = 1; i < NumOps-1; ++i) 1192 if (N->getOperand(i).getValueType() == MVT::Other) 1193 return N->getOperand(i); 1194 } 1195 return SDValue(); 1196} 1197 1198SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1199 // If N has two operands, where one has an input chain equal to the other, 1200 // the 'other' chain is redundant. 1201 if (N->getNumOperands() == 2) { 1202 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1203 return N->getOperand(0); 1204 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1205 return N->getOperand(1); 1206 } 1207 1208 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1209 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1210 SmallPtrSet<SDNode*, 16> SeenOps; 1211 bool Changed = false; // If we should replace this token factor. 1212 1213 // Start out with this token factor. 1214 TFs.push_back(N); 1215 1216 // Iterate through token factors. The TFs grows when new token factors are 1217 // encountered. 1218 for (unsigned i = 0; i < TFs.size(); ++i) { 1219 SDNode *TF = TFs[i]; 1220 1221 // Check each of the operands. 1222 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1223 SDValue Op = TF->getOperand(i); 1224 1225 switch (Op.getOpcode()) { 1226 case ISD::EntryToken: 1227 // Entry tokens don't need to be added to the list. They are 1228 // rededundant. 1229 Changed = true; 1230 break; 1231 1232 case ISD::TokenFactor: 1233 if (Op.hasOneUse() && 1234 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1235 // Queue up for processing. 1236 TFs.push_back(Op.getNode()); 1237 // Clean up in case the token factor is removed. 1238 AddToWorkList(Op.getNode()); 1239 Changed = true; 1240 break; 1241 } 1242 // Fall thru 1243 1244 default: 1245 // Only add if it isn't already in the list. 1246 if (SeenOps.insert(Op.getNode())) 1247 Ops.push_back(Op); 1248 else 1249 Changed = true; 1250 break; 1251 } 1252 } 1253 } 1254 1255 SDValue Result; 1256 1257 // If we've change things around then replace token factor. 1258 if (Changed) { 1259 if (Ops.empty()) { 1260 // The entry token is the only possible outcome. 1261 Result = DAG.getEntryNode(); 1262 } else { 1263 // New and improved token factor. 1264 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1265 MVT::Other, &Ops[0], Ops.size()); 1266 } 1267 1268 // Don't add users to work list. 1269 return CombineTo(N, Result, false); 1270 } 1271 1272 return Result; 1273} 1274 1275/// MERGE_VALUES can always be eliminated. 1276SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1277 WorkListRemover DeadNodes(*this); 1278 // Replacing results may cause a different MERGE_VALUES to suddenly 1279 // be CSE'd with N, and carry its uses with it. Iterate until no 1280 // uses remain, to ensure that the node can be safely deleted. 1281 do { 1282 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1283 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1284 &DeadNodes); 1285 } while (!N->use_empty()); 1286 removeFromWorkList(N); 1287 DAG.DeleteNode(N); 1288 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1289} 1290 1291static 1292SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1293 SelectionDAG &DAG) { 1294 EVT VT = N0.getValueType(); 1295 SDValue N00 = N0.getOperand(0); 1296 SDValue N01 = N0.getOperand(1); 1297 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1298 1299 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1300 isa<ConstantSDNode>(N00.getOperand(1))) { 1301 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1302 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1303 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1304 N00.getOperand(0), N01), 1305 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1306 N00.getOperand(1), N01)); 1307 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1308 } 1309 1310 return SDValue(); 1311} 1312 1313/// isCarryMaterialization - Returns true if V is an ADDE node that is known to 1314/// return 0 or 1 depending on the carry flag. 1315static bool isCarryMaterialization(SDValue V) { 1316 if (V.getOpcode() != ISD::ADDE) 1317 return false; 1318 1319 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0)); 1320 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); 1321} 1322 1323SDValue DAGCombiner::visitADD(SDNode *N) { 1324 SDValue N0 = N->getOperand(0); 1325 SDValue N1 = N->getOperand(1); 1326 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1327 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1328 EVT VT = N0.getValueType(); 1329 1330 // fold vector ops 1331 if (VT.isVector()) { 1332 SDValue FoldedVOp = SimplifyVBinOp(N); 1333 if (FoldedVOp.getNode()) return FoldedVOp; 1334 } 1335 1336 // fold (add x, undef) -> undef 1337 if (N0.getOpcode() == ISD::UNDEF) 1338 return N0; 1339 if (N1.getOpcode() == ISD::UNDEF) 1340 return N1; 1341 // fold (add c1, c2) -> c1+c2 1342 if (N0C && N1C) 1343 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1344 // canonicalize constant to RHS 1345 if (N0C && !N1C) 1346 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1347 // fold (add x, 0) -> x 1348 if (N1C && N1C->isNullValue()) 1349 return N0; 1350 // fold (add Sym, c) -> Sym+c 1351 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1352 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1353 GA->getOpcode() == ISD::GlobalAddress) 1354 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1355 GA->getOffset() + 1356 (uint64_t)N1C->getSExtValue()); 1357 // fold ((c1-A)+c2) -> (c1+c2)-A 1358 if (N1C && N0.getOpcode() == ISD::SUB) 1359 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1360 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1361 DAG.getConstant(N1C->getAPIntValue()+ 1362 N0C->getAPIntValue(), VT), 1363 N0.getOperand(1)); 1364 // reassociate add 1365 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1366 if (RADD.getNode() != 0) 1367 return RADD; 1368 // fold ((0-A) + B) -> B-A 1369 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1370 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1372 // fold (A + (0-B)) -> A-B 1373 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1374 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1375 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1376 // fold (A+(B-A)) -> B 1377 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1378 return N1.getOperand(0); 1379 // fold ((B-A)+A) -> B 1380 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1381 return N0.getOperand(0); 1382 // fold (A+(B-(A+C))) to (B-C) 1383 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1384 N0 == N1.getOperand(1).getOperand(0)) 1385 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1386 N1.getOperand(1).getOperand(1)); 1387 // fold (A+(B-(C+A))) to (B-C) 1388 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1389 N0 == N1.getOperand(1).getOperand(1)) 1390 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1391 N1.getOperand(1).getOperand(0)); 1392 // fold (A+((B-A)+or-C)) to (B+or-C) 1393 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1394 N1.getOperand(0).getOpcode() == ISD::SUB && 1395 N0 == N1.getOperand(0).getOperand(1)) 1396 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1397 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1398 1399 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1400 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1401 SDValue N00 = N0.getOperand(0); 1402 SDValue N01 = N0.getOperand(1); 1403 SDValue N10 = N1.getOperand(0); 1404 SDValue N11 = N1.getOperand(1); 1405 1406 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1408 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1409 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1410 } 1411 1412 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1413 return SDValue(N, 0); 1414 1415 // fold (a+b) -> (a|b) iff a and b share no bits. 1416 if (VT.isInteger() && !VT.isVector()) { 1417 APInt LHSZero, LHSOne; 1418 APInt RHSZero, RHSOne; 1419 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1420 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1421 1422 if (LHSZero.getBoolValue()) { 1423 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1424 1425 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1426 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1427 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1428 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1429 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1430 } 1431 } 1432 1433 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1434 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1435 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1436 if (Result.getNode()) return Result; 1437 } 1438 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1439 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1440 if (Result.getNode()) return Result; 1441 } 1442 1443 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1444 if (N1.getOpcode() == ISD::SHL && 1445 N1.getOperand(0).getOpcode() == ISD::SUB) 1446 if (ConstantSDNode *C = 1447 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1448 if (C->getAPIntValue() == 0) 1449 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1450 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1451 N1.getOperand(0).getOperand(1), 1452 N1.getOperand(1))); 1453 if (N0.getOpcode() == ISD::SHL && 1454 N0.getOperand(0).getOpcode() == ISD::SUB) 1455 if (ConstantSDNode *C = 1456 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1457 if (C->getAPIntValue() == 0) 1458 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1459 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1460 N0.getOperand(0).getOperand(1), 1461 N0.getOperand(1))); 1462 1463 if (N1.getOpcode() == ISD::AND) { 1464 SDValue AndOp0 = N1.getOperand(0); 1465 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1466 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1467 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1468 1469 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1470 // and similar xforms where the inner op is either ~0 or 0. 1471 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1472 DebugLoc DL = N->getDebugLoc(); 1473 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1474 } 1475 } 1476 1477 // add (sext i1), X -> sub X, (zext i1) 1478 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1479 N0.getOperand(0).getValueType() == MVT::i1 && 1480 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1481 DebugLoc DL = N->getDebugLoc(); 1482 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1483 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1484 } 1485 1486 // add (adde 0, 0, glue), X -> adde X, 0, glue 1487 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1488 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1489 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), 1490 N0.getOperand(2)); 1491 1492 // add X, (adde 0, 0, glue) -> adde X, 0, glue 1493 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1494 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1495 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), 1496 N1.getOperand(2)); 1497 1498 return SDValue(); 1499} 1500 1501SDValue DAGCombiner::visitADDC(SDNode *N) { 1502 SDValue N0 = N->getOperand(0); 1503 SDValue N1 = N->getOperand(1); 1504 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1505 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1506 EVT VT = N0.getValueType(); 1507 1508 // If the flag result is dead, turn this into an ADD. 1509 if (N->hasNUsesOfValue(0, 1)) 1510 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1511 DAG.getNode(ISD::CARRY_FALSE, 1512 N->getDebugLoc(), MVT::Glue)); 1513 1514 // canonicalize constant to RHS. 1515 if (N0C && !N1C) 1516 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1517 1518 // fold (addc x, 0) -> x + no carry out 1519 if (N1C && N1C->isNullValue()) 1520 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1521 N->getDebugLoc(), MVT::Glue)); 1522 1523 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1524 APInt LHSZero, LHSOne; 1525 APInt RHSZero, RHSOne; 1526 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1527 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1528 1529 if (LHSZero.getBoolValue()) { 1530 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1531 1532 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1533 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1534 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1535 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1536 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1537 DAG.getNode(ISD::CARRY_FALSE, 1538 N->getDebugLoc(), MVT::Glue)); 1539 } 1540 1541 // addc (adde 0, 0, glue), X -> adde X, 0, glue 1542 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1543 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, 1544 DAG.getConstant(0, VT), N0.getOperand(2)); 1545 1546 // addc X, (adde 0, 0, glue) -> adde X, 0, glue 1547 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1548 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, 1549 DAG.getConstant(0, VT), N1.getOperand(2)); 1550 1551 return SDValue(); 1552} 1553 1554SDValue DAGCombiner::visitADDE(SDNode *N) { 1555 SDValue N0 = N->getOperand(0); 1556 SDValue N1 = N->getOperand(1); 1557 SDValue CarryIn = N->getOperand(2); 1558 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1560 1561 // If both operands are null we know that carry out will always be false. 1562 if (N0C && N0C->isNullValue() && N0 == N1) 1563 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE, 1564 N->getDebugLoc(), 1565 MVT::Glue)); 1566 1567 // canonicalize constant to RHS 1568 if (N0C && !N1C) 1569 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1570 N1, N0, CarryIn); 1571 1572 // fold (adde x, y, false) -> (addc x, y) 1573 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1574 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1575 1576 return SDValue(); 1577} 1578 1579// Since it may not be valid to emit a fold to zero for vector initializers 1580// check if we can before folding. 1581static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1582 SelectionDAG &DAG, bool LegalOperations) { 1583 if (!VT.isVector()) { 1584 return DAG.getConstant(0, VT); 1585 } 1586 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1587 // Produce a vector of zeros. 1588 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1589 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1590 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1591 &Ops[0], Ops.size()); 1592 } 1593 return SDValue(); 1594} 1595 1596SDValue DAGCombiner::visitSUB(SDNode *N) { 1597 SDValue N0 = N->getOperand(0); 1598 SDValue N1 = N->getOperand(1); 1599 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1601 EVT VT = N0.getValueType(); 1602 1603 // fold vector ops 1604 if (VT.isVector()) { 1605 SDValue FoldedVOp = SimplifyVBinOp(N); 1606 if (FoldedVOp.getNode()) return FoldedVOp; 1607 } 1608 1609 // fold (sub x, x) -> 0 1610 // FIXME: Refactor this and xor and other similar operations together. 1611 if (N0 == N1) 1612 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1613 // fold (sub c1, c2) -> c1-c2 1614 if (N0C && N1C) 1615 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1616 // fold (sub x, c) -> (add x, -c) 1617 if (N1C) 1618 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1619 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1620 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1621 if (N0C && N0C->isAllOnesValue()) 1622 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1623 // fold A-(A-B) -> B 1624 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1625 return N1.getOperand(1); 1626 // fold (A+B)-A -> B 1627 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1628 return N0.getOperand(1); 1629 // fold (A+B)-B -> A 1630 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1631 return N0.getOperand(0); 1632 // fold ((A+(B+or-C))-B) -> A+or-C 1633 if (N0.getOpcode() == ISD::ADD && 1634 (N0.getOperand(1).getOpcode() == ISD::SUB || 1635 N0.getOperand(1).getOpcode() == ISD::ADD) && 1636 N0.getOperand(1).getOperand(0) == N1) 1637 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1638 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1639 // fold ((A+(C+B))-B) -> A+C 1640 if (N0.getOpcode() == ISD::ADD && 1641 N0.getOperand(1).getOpcode() == ISD::ADD && 1642 N0.getOperand(1).getOperand(1) == N1) 1643 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1644 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1645 // fold ((A-(B-C))-C) -> A-B 1646 if (N0.getOpcode() == ISD::SUB && 1647 N0.getOperand(1).getOpcode() == ISD::SUB && 1648 N0.getOperand(1).getOperand(1) == N1) 1649 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1650 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1651 1652 // If either operand of a sub is undef, the result is undef 1653 if (N0.getOpcode() == ISD::UNDEF) 1654 return N0; 1655 if (N1.getOpcode() == ISD::UNDEF) 1656 return N1; 1657 1658 // If the relocation model supports it, consider symbol offsets. 1659 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1660 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1661 // fold (sub Sym, c) -> Sym-c 1662 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1663 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1664 GA->getOffset() - 1665 (uint64_t)N1C->getSExtValue()); 1666 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1667 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1668 if (GA->getGlobal() == GB->getGlobal()) 1669 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1670 VT); 1671 } 1672 1673 return SDValue(); 1674} 1675 1676SDValue DAGCombiner::visitMUL(SDNode *N) { 1677 SDValue N0 = N->getOperand(0); 1678 SDValue N1 = N->getOperand(1); 1679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1681 EVT VT = N0.getValueType(); 1682 1683 // fold vector ops 1684 if (VT.isVector()) { 1685 SDValue FoldedVOp = SimplifyVBinOp(N); 1686 if (FoldedVOp.getNode()) return FoldedVOp; 1687 } 1688 1689 // fold (mul x, undef) -> 0 1690 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1691 return DAG.getConstant(0, VT); 1692 // fold (mul c1, c2) -> c1*c2 1693 if (N0C && N1C) 1694 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1695 // canonicalize constant to RHS 1696 if (N0C && !N1C) 1697 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1698 // fold (mul x, 0) -> 0 1699 if (N1C && N1C->isNullValue()) 1700 return N1; 1701 // fold (mul x, -1) -> 0-x 1702 if (N1C && N1C->isAllOnesValue()) 1703 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1704 DAG.getConstant(0, VT), N0); 1705 // fold (mul x, (1 << c)) -> x << c 1706 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1707 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1708 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1709 getShiftAmountTy(N0.getValueType()))); 1710 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1711 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1712 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1713 // FIXME: If the input is something that is easily negated (e.g. a 1714 // single-use add), we should put the negate there. 1715 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1716 DAG.getConstant(0, VT), 1717 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1718 DAG.getConstant(Log2Val, 1719 getShiftAmountTy(N0.getValueType())))); 1720 } 1721 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1722 if (N1C && N0.getOpcode() == ISD::SHL && 1723 isa<ConstantSDNode>(N0.getOperand(1))) { 1724 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1725 N1, N0.getOperand(1)); 1726 AddToWorkList(C3.getNode()); 1727 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1728 N0.getOperand(0), C3); 1729 } 1730 1731 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1732 // use. 1733 { 1734 SDValue Sh(0,0), Y(0,0); 1735 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1736 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1737 N0.getNode()->hasOneUse()) { 1738 Sh = N0; Y = N1; 1739 } else if (N1.getOpcode() == ISD::SHL && 1740 isa<ConstantSDNode>(N1.getOperand(1)) && 1741 N1.getNode()->hasOneUse()) { 1742 Sh = N1; Y = N0; 1743 } 1744 1745 if (Sh.getNode()) { 1746 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1747 Sh.getOperand(0), Y); 1748 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1749 Mul, Sh.getOperand(1)); 1750 } 1751 } 1752 1753 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1754 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1755 isa<ConstantSDNode>(N0.getOperand(1))) 1756 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1757 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1758 N0.getOperand(0), N1), 1759 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1760 N0.getOperand(1), N1)); 1761 1762 // reassociate mul 1763 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1764 if (RMUL.getNode() != 0) 1765 return RMUL; 1766 1767 return SDValue(); 1768} 1769 1770SDValue DAGCombiner::visitSDIV(SDNode *N) { 1771 SDValue N0 = N->getOperand(0); 1772 SDValue N1 = N->getOperand(1); 1773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1775 EVT VT = N->getValueType(0); 1776 1777 // fold vector ops 1778 if (VT.isVector()) { 1779 SDValue FoldedVOp = SimplifyVBinOp(N); 1780 if (FoldedVOp.getNode()) return FoldedVOp; 1781 } 1782 1783 // fold (sdiv c1, c2) -> c1/c2 1784 if (N0C && N1C && !N1C->isNullValue()) 1785 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1786 // fold (sdiv X, 1) -> X 1787 if (N1C && N1C->getSExtValue() == 1LL) 1788 return N0; 1789 // fold (sdiv X, -1) -> 0-X 1790 if (N1C && N1C->isAllOnesValue()) 1791 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1792 DAG.getConstant(0, VT), N0); 1793 // If we know the sign bits of both operands are zero, strength reduce to a 1794 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1795 if (!VT.isVector()) { 1796 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1797 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1798 N0, N1); 1799 } 1800 // fold (sdiv X, pow2) -> simple ops after legalize 1801 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1802 (isPowerOf2_64(N1C->getSExtValue()) || 1803 isPowerOf2_64(-N1C->getSExtValue()))) { 1804 // If dividing by powers of two is cheap, then don't perform the following 1805 // fold. 1806 if (TLI.isPow2DivCheap()) 1807 return SDValue(); 1808 1809 int64_t pow2 = N1C->getSExtValue(); 1810 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1811 unsigned lg2 = Log2_64(abs2); 1812 1813 // Splat the sign bit into the register 1814 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1815 DAG.getConstant(VT.getSizeInBits()-1, 1816 getShiftAmountTy(N0.getValueType()))); 1817 AddToWorkList(SGN.getNode()); 1818 1819 // Add (N0 < 0) ? abs2 - 1 : 0; 1820 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1821 DAG.getConstant(VT.getSizeInBits() - lg2, 1822 getShiftAmountTy(SGN.getValueType()))); 1823 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1824 AddToWorkList(SRL.getNode()); 1825 AddToWorkList(ADD.getNode()); // Divide by pow2 1826 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1827 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1828 1829 // If we're dividing by a positive value, we're done. Otherwise, we must 1830 // negate the result. 1831 if (pow2 > 0) 1832 return SRA; 1833 1834 AddToWorkList(SRA.getNode()); 1835 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1836 DAG.getConstant(0, VT), SRA); 1837 } 1838 1839 // if integer divide is expensive and we satisfy the requirements, emit an 1840 // alternate sequence. 1841 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1842 !TLI.isIntDivCheap()) { 1843 SDValue Op = BuildSDIV(N); 1844 if (Op.getNode()) return Op; 1845 } 1846 1847 // undef / X -> 0 1848 if (N0.getOpcode() == ISD::UNDEF) 1849 return DAG.getConstant(0, VT); 1850 // X / undef -> undef 1851 if (N1.getOpcode() == ISD::UNDEF) 1852 return N1; 1853 1854 return SDValue(); 1855} 1856 1857SDValue DAGCombiner::visitUDIV(SDNode *N) { 1858 SDValue N0 = N->getOperand(0); 1859 SDValue N1 = N->getOperand(1); 1860 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1861 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1862 EVT VT = N->getValueType(0); 1863 1864 // fold vector ops 1865 if (VT.isVector()) { 1866 SDValue FoldedVOp = SimplifyVBinOp(N); 1867 if (FoldedVOp.getNode()) return FoldedVOp; 1868 } 1869 1870 // fold (udiv c1, c2) -> c1/c2 1871 if (N0C && N1C && !N1C->isNullValue()) 1872 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1873 // fold (udiv x, (1 << c)) -> x >>u c 1874 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1876 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1877 getShiftAmountTy(N0.getValueType()))); 1878 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1879 if (N1.getOpcode() == ISD::SHL) { 1880 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1881 if (SHC->getAPIntValue().isPowerOf2()) { 1882 EVT ADDVT = N1.getOperand(1).getValueType(); 1883 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1884 N1.getOperand(1), 1885 DAG.getConstant(SHC->getAPIntValue() 1886 .logBase2(), 1887 ADDVT)); 1888 AddToWorkList(Add.getNode()); 1889 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1890 } 1891 } 1892 } 1893 // fold (udiv x, c) -> alternate 1894 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1895 SDValue Op = BuildUDIV(N); 1896 if (Op.getNode()) return Op; 1897 } 1898 1899 // undef / X -> 0 1900 if (N0.getOpcode() == ISD::UNDEF) 1901 return DAG.getConstant(0, VT); 1902 // X / undef -> undef 1903 if (N1.getOpcode() == ISD::UNDEF) 1904 return N1; 1905 1906 return SDValue(); 1907} 1908 1909SDValue DAGCombiner::visitSREM(SDNode *N) { 1910 SDValue N0 = N->getOperand(0); 1911 SDValue N1 = N->getOperand(1); 1912 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1913 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1914 EVT VT = N->getValueType(0); 1915 1916 // fold (srem c1, c2) -> c1%c2 1917 if (N0C && N1C && !N1C->isNullValue()) 1918 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1919 // If we know the sign bits of both operands are zero, strength reduce to a 1920 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1921 if (!VT.isVector()) { 1922 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1923 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1924 } 1925 1926 // If X/C can be simplified by the division-by-constant logic, lower 1927 // X%C to the equivalent of X-X/C*C. 1928 if (N1C && !N1C->isNullValue()) { 1929 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1930 AddToWorkList(Div.getNode()); 1931 SDValue OptimizedDiv = combine(Div.getNode()); 1932 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1933 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1934 OptimizedDiv, N1); 1935 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1936 AddToWorkList(Mul.getNode()); 1937 return Sub; 1938 } 1939 } 1940 1941 // undef % X -> 0 1942 if (N0.getOpcode() == ISD::UNDEF) 1943 return DAG.getConstant(0, VT); 1944 // X % undef -> undef 1945 if (N1.getOpcode() == ISD::UNDEF) 1946 return N1; 1947 1948 return SDValue(); 1949} 1950 1951SDValue DAGCombiner::visitUREM(SDNode *N) { 1952 SDValue N0 = N->getOperand(0); 1953 SDValue N1 = N->getOperand(1); 1954 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1955 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1956 EVT VT = N->getValueType(0); 1957 1958 // fold (urem c1, c2) -> c1%c2 1959 if (N0C && N1C && !N1C->isNullValue()) 1960 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1961 // fold (urem x, pow2) -> (and x, pow2-1) 1962 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1963 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1964 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1965 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1966 if (N1.getOpcode() == ISD::SHL) { 1967 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1968 if (SHC->getAPIntValue().isPowerOf2()) { 1969 SDValue Add = 1970 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1971 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1972 VT)); 1973 AddToWorkList(Add.getNode()); 1974 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1975 } 1976 } 1977 } 1978 1979 // If X/C can be simplified by the division-by-constant logic, lower 1980 // X%C to the equivalent of X-X/C*C. 1981 if (N1C && !N1C->isNullValue()) { 1982 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1983 AddToWorkList(Div.getNode()); 1984 SDValue OptimizedDiv = combine(Div.getNode()); 1985 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1986 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1987 OptimizedDiv, N1); 1988 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1989 AddToWorkList(Mul.getNode()); 1990 return Sub; 1991 } 1992 } 1993 1994 // undef % X -> 0 1995 if (N0.getOpcode() == ISD::UNDEF) 1996 return DAG.getConstant(0, VT); 1997 // X % undef -> undef 1998 if (N1.getOpcode() == ISD::UNDEF) 1999 return N1; 2000 2001 return SDValue(); 2002} 2003 2004SDValue DAGCombiner::visitMULHS(SDNode *N) { 2005 SDValue N0 = N->getOperand(0); 2006 SDValue N1 = N->getOperand(1); 2007 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2008 EVT VT = N->getValueType(0); 2009 DebugLoc DL = N->getDebugLoc(); 2010 2011 // fold (mulhs x, 0) -> 0 2012 if (N1C && N1C->isNullValue()) 2013 return N1; 2014 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2015 if (N1C && N1C->getAPIntValue() == 1) 2016 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2017 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2018 getShiftAmountTy(N0.getValueType()))); 2019 // fold (mulhs x, undef) -> 0 2020 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2021 return DAG.getConstant(0, VT); 2022 2023 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2024 // plus a shift. 2025 if (VT.isSimple() && !VT.isVector()) { 2026 MVT Simple = VT.getSimpleVT(); 2027 unsigned SimpleSize = Simple.getSizeInBits(); 2028 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2029 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2030 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2031 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2032 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2033 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2034 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2035 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2036 } 2037 } 2038 2039 return SDValue(); 2040} 2041 2042SDValue DAGCombiner::visitMULHU(SDNode *N) { 2043 SDValue N0 = N->getOperand(0); 2044 SDValue N1 = N->getOperand(1); 2045 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2046 EVT VT = N->getValueType(0); 2047 DebugLoc DL = N->getDebugLoc(); 2048 2049 // fold (mulhu x, 0) -> 0 2050 if (N1C && N1C->isNullValue()) 2051 return N1; 2052 // fold (mulhu x, 1) -> 0 2053 if (N1C && N1C->getAPIntValue() == 1) 2054 return DAG.getConstant(0, N0.getValueType()); 2055 // fold (mulhu x, undef) -> 0 2056 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2057 return DAG.getConstant(0, VT); 2058 2059 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2060 // plus a shift. 2061 if (VT.isSimple() && !VT.isVector()) { 2062 MVT Simple = VT.getSimpleVT(); 2063 unsigned SimpleSize = Simple.getSizeInBits(); 2064 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2065 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2066 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2067 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2068 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2069 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2070 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2071 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2072 } 2073 } 2074 2075 return SDValue(); 2076} 2077 2078/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2079/// compute two values. LoOp and HiOp give the opcodes for the two computations 2080/// that are being performed. Return true if a simplification was made. 2081/// 2082SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2083 unsigned HiOp) { 2084 // If the high half is not needed, just compute the low half. 2085 bool HiExists = N->hasAnyUseOfValue(1); 2086 if (!HiExists && 2087 (!LegalOperations || 2088 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2089 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2090 N->op_begin(), N->getNumOperands()); 2091 return CombineTo(N, Res, Res); 2092 } 2093 2094 // If the low half is not needed, just compute the high half. 2095 bool LoExists = N->hasAnyUseOfValue(0); 2096 if (!LoExists && 2097 (!LegalOperations || 2098 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2099 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2100 N->op_begin(), N->getNumOperands()); 2101 return CombineTo(N, Res, Res); 2102 } 2103 2104 // If both halves are used, return as it is. 2105 if (LoExists && HiExists) 2106 return SDValue(); 2107 2108 // If the two computed results can be simplified separately, separate them. 2109 if (LoExists) { 2110 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2111 N->op_begin(), N->getNumOperands()); 2112 AddToWorkList(Lo.getNode()); 2113 SDValue LoOpt = combine(Lo.getNode()); 2114 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2115 (!LegalOperations || 2116 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2117 return CombineTo(N, LoOpt, LoOpt); 2118 } 2119 2120 if (HiExists) { 2121 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2122 N->op_begin(), N->getNumOperands()); 2123 AddToWorkList(Hi.getNode()); 2124 SDValue HiOpt = combine(Hi.getNode()); 2125 if (HiOpt.getNode() && HiOpt != Hi && 2126 (!LegalOperations || 2127 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2128 return CombineTo(N, HiOpt, HiOpt); 2129 } 2130 2131 return SDValue(); 2132} 2133 2134SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2135 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2136 if (Res.getNode()) return Res; 2137 2138 EVT VT = N->getValueType(0); 2139 DebugLoc DL = N->getDebugLoc(); 2140 2141 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2142 // plus a shift. 2143 if (VT.isSimple() && !VT.isVector()) { 2144 MVT Simple = VT.getSimpleVT(); 2145 unsigned SimpleSize = Simple.getSizeInBits(); 2146 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2147 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2148 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2149 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2150 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2151 // Compute the high part as N1. 2152 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2153 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2154 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2155 // Compute the low part as N0. 2156 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2157 return CombineTo(N, Lo, Hi); 2158 } 2159 } 2160 2161 return SDValue(); 2162} 2163 2164SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2165 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2166 if (Res.getNode()) return Res; 2167 2168 EVT VT = N->getValueType(0); 2169 DebugLoc DL = N->getDebugLoc(); 2170 2171 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2172 // plus a shift. 2173 if (VT.isSimple() && !VT.isVector()) { 2174 MVT Simple = VT.getSimpleVT(); 2175 unsigned SimpleSize = Simple.getSizeInBits(); 2176 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2177 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2178 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2179 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2180 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2181 // Compute the high part as N1. 2182 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2183 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2184 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2185 // Compute the low part as N0. 2186 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2187 return CombineTo(N, Lo, Hi); 2188 } 2189 } 2190 2191 return SDValue(); 2192} 2193 2194SDValue DAGCombiner::visitSMULO(SDNode *N) { 2195 // (smulo x, 2) -> (saddo x, x) 2196 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2197 if (C2->getAPIntValue() == 2) 2198 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2199 N->getOperand(0), N->getOperand(0)); 2200 2201 return SDValue(); 2202} 2203 2204SDValue DAGCombiner::visitUMULO(SDNode *N) { 2205 // (umulo x, 2) -> (uaddo x, x) 2206 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2207 if (C2->getAPIntValue() == 2) 2208 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2209 N->getOperand(0), N->getOperand(0)); 2210 2211 return SDValue(); 2212} 2213 2214SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2216 if (Res.getNode()) return Res; 2217 2218 return SDValue(); 2219} 2220 2221SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2222 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2223 if (Res.getNode()) return Res; 2224 2225 return SDValue(); 2226} 2227 2228/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2229/// two operands of the same opcode, try to simplify it. 2230SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2231 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2232 EVT VT = N0.getValueType(); 2233 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2234 2235 // Bail early if none of these transforms apply. 2236 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2237 2238 // For each of OP in AND/OR/XOR: 2239 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2240 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2241 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2242 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2243 // 2244 // do not sink logical op inside of a vector extend, since it may combine 2245 // into a vsetcc. 2246 EVT Op0VT = N0.getOperand(0).getValueType(); 2247 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2248 N0.getOpcode() == ISD::SIGN_EXTEND || 2249 // Avoid infinite looping with PromoteIntBinOp. 2250 (N0.getOpcode() == ISD::ANY_EXTEND && 2251 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2252 (N0.getOpcode() == ISD::TRUNCATE && 2253 (!TLI.isZExtFree(VT, Op0VT) || 2254 !TLI.isTruncateFree(Op0VT, VT)) && 2255 TLI.isTypeLegal(Op0VT))) && 2256 !VT.isVector() && 2257 Op0VT == N1.getOperand(0).getValueType() && 2258 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2259 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2260 N0.getOperand(0).getValueType(), 2261 N0.getOperand(0), N1.getOperand(0)); 2262 AddToWorkList(ORNode.getNode()); 2263 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2264 } 2265 2266 // For each of OP in SHL/SRL/SRA/AND... 2267 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2268 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2269 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2270 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2271 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2272 N0.getOperand(1) == N1.getOperand(1)) { 2273 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2274 N0.getOperand(0).getValueType(), 2275 N0.getOperand(0), N1.getOperand(0)); 2276 AddToWorkList(ORNode.getNode()); 2277 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2278 ORNode, N0.getOperand(1)); 2279 } 2280 2281 return SDValue(); 2282} 2283 2284SDValue DAGCombiner::visitAND(SDNode *N) { 2285 SDValue N0 = N->getOperand(0); 2286 SDValue N1 = N->getOperand(1); 2287 SDValue LL, LR, RL, RR, CC0, CC1; 2288 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2290 EVT VT = N1.getValueType(); 2291 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2292 2293 // fold vector ops 2294 if (VT.isVector()) { 2295 SDValue FoldedVOp = SimplifyVBinOp(N); 2296 if (FoldedVOp.getNode()) return FoldedVOp; 2297 } 2298 2299 // fold (and x, undef) -> 0 2300 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2301 return DAG.getConstant(0, VT); 2302 // fold (and c1, c2) -> c1&c2 2303 if (N0C && N1C) 2304 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2305 // canonicalize constant to RHS 2306 if (N0C && !N1C) 2307 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2308 // fold (and x, -1) -> x 2309 if (N1C && N1C->isAllOnesValue()) 2310 return N0; 2311 // if (and x, c) is known to be zero, return 0 2312 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2313 APInt::getAllOnesValue(BitWidth))) 2314 return DAG.getConstant(0, VT); 2315 // reassociate and 2316 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2317 if (RAND.getNode() != 0) 2318 return RAND; 2319 // fold (and (or x, C), D) -> D if (C & D) == D 2320 if (N1C && N0.getOpcode() == ISD::OR) 2321 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2322 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2323 return N1; 2324 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2325 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2326 SDValue N0Op0 = N0.getOperand(0); 2327 APInt Mask = ~N1C->getAPIntValue(); 2328 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2329 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2330 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2331 N0.getValueType(), N0Op0); 2332 2333 // Replace uses of the AND with uses of the Zero extend node. 2334 CombineTo(N, Zext); 2335 2336 // We actually want to replace all uses of the any_extend with the 2337 // zero_extend, to avoid duplicating things. This will later cause this 2338 // AND to be folded. 2339 CombineTo(N0.getNode(), Zext); 2340 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2341 } 2342 } 2343 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2344 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2345 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2346 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2347 2348 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2349 LL.getValueType().isInteger()) { 2350 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2351 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2352 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2353 LR.getValueType(), LL, RL); 2354 AddToWorkList(ORNode.getNode()); 2355 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2356 } 2357 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2358 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2359 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2360 LR.getValueType(), LL, RL); 2361 AddToWorkList(ANDNode.getNode()); 2362 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2363 } 2364 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2365 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2366 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2367 LR.getValueType(), LL, RL); 2368 AddToWorkList(ORNode.getNode()); 2369 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2370 } 2371 } 2372 // canonicalize equivalent to ll == rl 2373 if (LL == RR && LR == RL) { 2374 Op1 = ISD::getSetCCSwappedOperands(Op1); 2375 std::swap(RL, RR); 2376 } 2377 if (LL == RL && LR == RR) { 2378 bool isInteger = LL.getValueType().isInteger(); 2379 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2380 if (Result != ISD::SETCC_INVALID && 2381 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2382 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2383 LL, LR, Result); 2384 } 2385 } 2386 2387 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2388 if (N0.getOpcode() == N1.getOpcode()) { 2389 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2390 if (Tmp.getNode()) return Tmp; 2391 } 2392 2393 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2394 // fold (and (sra)) -> (and (srl)) when possible. 2395 if (!VT.isVector() && 2396 SimplifyDemandedBits(SDValue(N, 0))) 2397 return SDValue(N, 0); 2398 2399 // fold (zext_inreg (extload x)) -> (zextload x) 2400 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2401 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2402 EVT MemVT = LN0->getMemoryVT(); 2403 // If we zero all the possible extended bits, then we can turn this into 2404 // a zextload if we are running before legalize or the operation is legal. 2405 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2406 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2407 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2408 ((!LegalOperations && !LN0->isVolatile()) || 2409 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2410 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2411 LN0->getChain(), LN0->getBasePtr(), 2412 LN0->getPointerInfo(), MemVT, 2413 LN0->isVolatile(), LN0->isNonTemporal(), 2414 LN0->getAlignment()); 2415 AddToWorkList(N); 2416 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2417 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2418 } 2419 } 2420 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2421 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2422 N0.hasOneUse()) { 2423 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2424 EVT MemVT = LN0->getMemoryVT(); 2425 // If we zero all the possible extended bits, then we can turn this into 2426 // a zextload if we are running before legalize or the operation is legal. 2427 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2428 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2429 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2430 ((!LegalOperations && !LN0->isVolatile()) || 2431 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2432 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2433 LN0->getChain(), 2434 LN0->getBasePtr(), LN0->getPointerInfo(), 2435 MemVT, 2436 LN0->isVolatile(), LN0->isNonTemporal(), 2437 LN0->getAlignment()); 2438 AddToWorkList(N); 2439 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2440 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2441 } 2442 } 2443 2444 // fold (and (load x), 255) -> (zextload x, i8) 2445 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2446 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2447 if (N1C && (N0.getOpcode() == ISD::LOAD || 2448 (N0.getOpcode() == ISD::ANY_EXTEND && 2449 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2450 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2451 LoadSDNode *LN0 = HasAnyExt 2452 ? cast<LoadSDNode>(N0.getOperand(0)) 2453 : cast<LoadSDNode>(N0); 2454 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2455 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2456 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2457 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2458 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2459 EVT LoadedVT = LN0->getMemoryVT(); 2460 2461 if (ExtVT == LoadedVT && 2462 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2463 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2464 2465 SDValue NewLoad = 2466 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2467 LN0->getChain(), LN0->getBasePtr(), 2468 LN0->getPointerInfo(), 2469 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2470 LN0->getAlignment()); 2471 AddToWorkList(N); 2472 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2473 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2474 } 2475 2476 // Do not change the width of a volatile load. 2477 // Do not generate loads of non-round integer types since these can 2478 // be expensive (and would be wrong if the type is not byte sized). 2479 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2480 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2481 EVT PtrType = LN0->getOperand(1).getValueType(); 2482 2483 unsigned Alignment = LN0->getAlignment(); 2484 SDValue NewPtr = LN0->getBasePtr(); 2485 2486 // For big endian targets, we need to add an offset to the pointer 2487 // to load the correct bytes. For little endian systems, we merely 2488 // need to read fewer bytes from the same pointer. 2489 if (TLI.isBigEndian()) { 2490 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2491 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2492 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2493 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2494 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2495 Alignment = MinAlign(Alignment, PtrOff); 2496 } 2497 2498 AddToWorkList(NewPtr.getNode()); 2499 2500 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2501 SDValue Load = 2502 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2503 LN0->getChain(), NewPtr, 2504 LN0->getPointerInfo(), 2505 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2506 Alignment); 2507 AddToWorkList(N); 2508 CombineTo(LN0, Load, Load.getValue(1)); 2509 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2510 } 2511 } 2512 } 2513 } 2514 2515 return SDValue(); 2516} 2517 2518/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2519/// 2520SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2521 bool DemandHighBits) { 2522 if (!LegalOperations) 2523 return SDValue(); 2524 2525 EVT VT = N->getValueType(0); 2526 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2527 return SDValue(); 2528 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2529 return SDValue(); 2530 2531 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2532 bool LookPassAnd0 = false; 2533 bool LookPassAnd1 = false; 2534 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2535 std::swap(N0, N1); 2536 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2537 std::swap(N0, N1); 2538 if (N0.getOpcode() == ISD::AND) { 2539 if (!N0.getNode()->hasOneUse()) 2540 return SDValue(); 2541 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2542 if (!N01C || N01C->getZExtValue() != 0xFF00) 2543 return SDValue(); 2544 N0 = N0.getOperand(0); 2545 LookPassAnd0 = true; 2546 } 2547 2548 if (N1.getOpcode() == ISD::AND) { 2549 if (!N1.getNode()->hasOneUse()) 2550 return SDValue(); 2551 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2552 if (!N11C || N11C->getZExtValue() != 0xFF) 2553 return SDValue(); 2554 N1 = N1.getOperand(0); 2555 LookPassAnd1 = true; 2556 } 2557 2558 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2559 std::swap(N0, N1); 2560 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2561 return SDValue(); 2562 if (!N0.getNode()->hasOneUse() || 2563 !N1.getNode()->hasOneUse()) 2564 return SDValue(); 2565 2566 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2567 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2568 if (!N01C || !N11C) 2569 return SDValue(); 2570 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2571 return SDValue(); 2572 2573 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2574 SDValue N00 = N0->getOperand(0); 2575 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2576 if (!N00.getNode()->hasOneUse()) 2577 return SDValue(); 2578 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2579 if (!N001C || N001C->getZExtValue() != 0xFF) 2580 return SDValue(); 2581 N00 = N00.getOperand(0); 2582 LookPassAnd0 = true; 2583 } 2584 2585 SDValue N10 = N1->getOperand(0); 2586 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2587 if (!N10.getNode()->hasOneUse()) 2588 return SDValue(); 2589 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2590 if (!N101C || N101C->getZExtValue() != 0xFF00) 2591 return SDValue(); 2592 N10 = N10.getOperand(0); 2593 LookPassAnd1 = true; 2594 } 2595 2596 if (N00 != N10) 2597 return SDValue(); 2598 2599 // Make sure everything beyond the low halfword is zero since the SRL 16 2600 // will clear the top bits. 2601 unsigned OpSizeInBits = VT.getSizeInBits(); 2602 if (DemandHighBits && OpSizeInBits > 16 && 2603 (!LookPassAnd0 || !LookPassAnd1) && 2604 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2605 return SDValue(); 2606 2607 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2608 if (OpSizeInBits > 16) 2609 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2610 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2611 return Res; 2612} 2613 2614/// isBSwapHWordElement - Return true if the specified node is an element 2615/// that makes up a 32-bit packed halfword byteswap. i.e. 2616/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2617static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2618 if (!N.getNode()->hasOneUse()) 2619 return false; 2620 2621 unsigned Opc = N.getOpcode(); 2622 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2623 return false; 2624 2625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2626 if (!N1C) 2627 return false; 2628 2629 unsigned Num; 2630 switch (N1C->getZExtValue()) { 2631 default: 2632 return false; 2633 case 0xFF: Num = 0; break; 2634 case 0xFF00: Num = 1; break; 2635 case 0xFF0000: Num = 2; break; 2636 case 0xFF000000: Num = 3; break; 2637 } 2638 2639 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2640 SDValue N0 = N.getOperand(0); 2641 if (Opc == ISD::AND) { 2642 if (Num == 0 || Num == 2) { 2643 // (x >> 8) & 0xff 2644 // (x >> 8) & 0xff0000 2645 if (N0.getOpcode() != ISD::SRL) 2646 return false; 2647 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2648 if (!C || C->getZExtValue() != 8) 2649 return false; 2650 } else { 2651 // (x << 8) & 0xff00 2652 // (x << 8) & 0xff000000 2653 if (N0.getOpcode() != ISD::SHL) 2654 return false; 2655 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2656 if (!C || C->getZExtValue() != 8) 2657 return false; 2658 } 2659 } else if (Opc == ISD::SHL) { 2660 // (x & 0xff) << 8 2661 // (x & 0xff0000) << 8 2662 if (Num != 0 && Num != 2) 2663 return false; 2664 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2665 if (!C || C->getZExtValue() != 8) 2666 return false; 2667 } else { // Opc == ISD::SRL 2668 // (x & 0xff00) >> 8 2669 // (x & 0xff000000) >> 8 2670 if (Num != 1 && Num != 3) 2671 return false; 2672 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2673 if (!C || C->getZExtValue() != 8) 2674 return false; 2675 } 2676 2677 if (Parts[Num]) 2678 return false; 2679 2680 Parts[Num] = N0.getOperand(0).getNode(); 2681 return true; 2682} 2683 2684/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2685/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2686/// => (rotl (bswap x), 16) 2687SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2688 if (!LegalOperations) 2689 return SDValue(); 2690 2691 EVT VT = N->getValueType(0); 2692 if (VT != MVT::i32) 2693 return SDValue(); 2694 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2695 return SDValue(); 2696 2697 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2698 // Look for either 2699 // (or (or (and), (and)), (or (and), (and))) 2700 // (or (or (or (and), (and)), (and)), (and)) 2701 if (N0.getOpcode() != ISD::OR) 2702 return SDValue(); 2703 SDValue N00 = N0.getOperand(0); 2704 SDValue N01 = N0.getOperand(1); 2705 2706 if (N1.getOpcode() == ISD::OR) { 2707 // (or (or (and), (and)), (or (and), (and))) 2708 SDValue N000 = N00.getOperand(0); 2709 if (!isBSwapHWordElement(N000, Parts)) 2710 return SDValue(); 2711 2712 SDValue N001 = N00.getOperand(1); 2713 if (!isBSwapHWordElement(N001, Parts)) 2714 return SDValue(); 2715 SDValue N010 = N01.getOperand(0); 2716 if (!isBSwapHWordElement(N010, Parts)) 2717 return SDValue(); 2718 SDValue N011 = N01.getOperand(1); 2719 if (!isBSwapHWordElement(N011, Parts)) 2720 return SDValue(); 2721 } else { 2722 // (or (or (or (and), (and)), (and)), (and)) 2723 if (!isBSwapHWordElement(N1, Parts)) 2724 return SDValue(); 2725 if (!isBSwapHWordElement(N01, Parts)) 2726 return SDValue(); 2727 if (N00.getOpcode() != ISD::OR) 2728 return SDValue(); 2729 SDValue N000 = N00.getOperand(0); 2730 if (!isBSwapHWordElement(N000, Parts)) 2731 return SDValue(); 2732 SDValue N001 = N00.getOperand(1); 2733 if (!isBSwapHWordElement(N001, Parts)) 2734 return SDValue(); 2735 } 2736 2737 // Make sure the parts are all coming from the same node. 2738 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2739 return SDValue(); 2740 2741 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2742 SDValue(Parts[0],0)); 2743 2744 // Result of the bswap should be rotated by 16. If it's not legal, than 2745 // do (x << 16) | (x >> 16). 2746 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2747 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2748 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2749 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2750 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2751 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2752 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2753 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2754} 2755 2756SDValue DAGCombiner::visitOR(SDNode *N) { 2757 SDValue N0 = N->getOperand(0); 2758 SDValue N1 = N->getOperand(1); 2759 SDValue LL, LR, RL, RR, CC0, CC1; 2760 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2761 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2762 EVT VT = N1.getValueType(); 2763 2764 // fold vector ops 2765 if (VT.isVector()) { 2766 SDValue FoldedVOp = SimplifyVBinOp(N); 2767 if (FoldedVOp.getNode()) return FoldedVOp; 2768 } 2769 2770 // fold (or x, undef) -> -1 2771 if (!LegalOperations && 2772 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2773 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2774 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2775 } 2776 // fold (or c1, c2) -> c1|c2 2777 if (N0C && N1C) 2778 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2779 // canonicalize constant to RHS 2780 if (N0C && !N1C) 2781 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2782 // fold (or x, 0) -> x 2783 if (N1C && N1C->isNullValue()) 2784 return N0; 2785 // fold (or x, -1) -> -1 2786 if (N1C && N1C->isAllOnesValue()) 2787 return N1; 2788 // fold (or x, c) -> c iff (x & ~c) == 0 2789 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2790 return N1; 2791 2792 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2793 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2794 if (BSwap.getNode() != 0) 2795 return BSwap; 2796 BSwap = MatchBSwapHWordLow(N, N0, N1); 2797 if (BSwap.getNode() != 0) 2798 return BSwap; 2799 2800 // reassociate or 2801 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2802 if (ROR.getNode() != 0) 2803 return ROR; 2804 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2805 // iff (c1 & c2) == 0. 2806 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2807 isa<ConstantSDNode>(N0.getOperand(1))) { 2808 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2809 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2810 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2811 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2812 N0.getOperand(0), N1), 2813 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2814 } 2815 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2816 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2817 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2818 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2819 2820 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2821 LL.getValueType().isInteger()) { 2822 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2823 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2824 if (cast<ConstantSDNode>(LR)->isNullValue() && 2825 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2826 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2827 LR.getValueType(), LL, RL); 2828 AddToWorkList(ORNode.getNode()); 2829 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2830 } 2831 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2832 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2833 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2834 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2835 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2836 LR.getValueType(), LL, RL); 2837 AddToWorkList(ANDNode.getNode()); 2838 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2839 } 2840 } 2841 // canonicalize equivalent to ll == rl 2842 if (LL == RR && LR == RL) { 2843 Op1 = ISD::getSetCCSwappedOperands(Op1); 2844 std::swap(RL, RR); 2845 } 2846 if (LL == RL && LR == RR) { 2847 bool isInteger = LL.getValueType().isInteger(); 2848 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2849 if (Result != ISD::SETCC_INVALID && 2850 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2851 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2852 LL, LR, Result); 2853 } 2854 } 2855 2856 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2857 if (N0.getOpcode() == N1.getOpcode()) { 2858 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2859 if (Tmp.getNode()) return Tmp; 2860 } 2861 2862 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2863 if (N0.getOpcode() == ISD::AND && 2864 N1.getOpcode() == ISD::AND && 2865 N0.getOperand(1).getOpcode() == ISD::Constant && 2866 N1.getOperand(1).getOpcode() == ISD::Constant && 2867 // Don't increase # computations. 2868 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2869 // We can only do this xform if we know that bits from X that are set in C2 2870 // but not in C1 are already zero. Likewise for Y. 2871 const APInt &LHSMask = 2872 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2873 const APInt &RHSMask = 2874 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2875 2876 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2877 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2878 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2879 N0.getOperand(0), N1.getOperand(0)); 2880 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2881 DAG.getConstant(LHSMask | RHSMask, VT)); 2882 } 2883 } 2884 2885 // See if this is some rotate idiom. 2886 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2887 return SDValue(Rot, 0); 2888 2889 // Simplify the operands using demanded-bits information. 2890 if (!VT.isVector() && 2891 SimplifyDemandedBits(SDValue(N, 0))) 2892 return SDValue(N, 0); 2893 2894 return SDValue(); 2895} 2896 2897/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2898static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2899 if (Op.getOpcode() == ISD::AND) { 2900 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2901 Mask = Op.getOperand(1); 2902 Op = Op.getOperand(0); 2903 } else { 2904 return false; 2905 } 2906 } 2907 2908 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2909 Shift = Op; 2910 return true; 2911 } 2912 2913 return false; 2914} 2915 2916// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2917// idioms for rotate, and if the target supports rotation instructions, generate 2918// a rot[lr]. 2919SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2920 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2921 EVT VT = LHS.getValueType(); 2922 if (!TLI.isTypeLegal(VT)) return 0; 2923 2924 // The target must have at least one rotate flavor. 2925 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2926 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2927 if (!HasROTL && !HasROTR) return 0; 2928 2929 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2930 SDValue LHSShift; // The shift. 2931 SDValue LHSMask; // AND value if any. 2932 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2933 return 0; // Not part of a rotate. 2934 2935 SDValue RHSShift; // The shift. 2936 SDValue RHSMask; // AND value if any. 2937 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2938 return 0; // Not part of a rotate. 2939 2940 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2941 return 0; // Not shifting the same value. 2942 2943 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2944 return 0; // Shifts must disagree. 2945 2946 // Canonicalize shl to left side in a shl/srl pair. 2947 if (RHSShift.getOpcode() == ISD::SHL) { 2948 std::swap(LHS, RHS); 2949 std::swap(LHSShift, RHSShift); 2950 std::swap(LHSMask , RHSMask ); 2951 } 2952 2953 unsigned OpSizeInBits = VT.getSizeInBits(); 2954 SDValue LHSShiftArg = LHSShift.getOperand(0); 2955 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2956 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2957 2958 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2959 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2960 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2961 RHSShiftAmt.getOpcode() == ISD::Constant) { 2962 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2963 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2964 if ((LShVal + RShVal) != OpSizeInBits) 2965 return 0; 2966 2967 SDValue Rot; 2968 if (HasROTL) 2969 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2970 else 2971 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2972 2973 // If there is an AND of either shifted operand, apply it to the result. 2974 if (LHSMask.getNode() || RHSMask.getNode()) { 2975 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2976 2977 if (LHSMask.getNode()) { 2978 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2979 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2980 } 2981 if (RHSMask.getNode()) { 2982 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2983 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2984 } 2985 2986 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2987 } 2988 2989 return Rot.getNode(); 2990 } 2991 2992 // If there is a mask here, and we have a variable shift, we can't be sure 2993 // that we're masking out the right stuff. 2994 if (LHSMask.getNode() || RHSMask.getNode()) 2995 return 0; 2996 2997 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2998 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2999 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3000 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3001 if (ConstantSDNode *SUBC = 3002 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3003 if (SUBC->getAPIntValue() == OpSizeInBits) { 3004 if (HasROTL) 3005 return DAG.getNode(ISD::ROTL, DL, VT, 3006 LHSShiftArg, LHSShiftAmt).getNode(); 3007 else 3008 return DAG.getNode(ISD::ROTR, DL, VT, 3009 LHSShiftArg, RHSShiftAmt).getNode(); 3010 } 3011 } 3012 } 3013 3014 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3015 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3016 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3017 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3018 if (ConstantSDNode *SUBC = 3019 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3020 if (SUBC->getAPIntValue() == OpSizeInBits) { 3021 if (HasROTR) 3022 return DAG.getNode(ISD::ROTR, DL, VT, 3023 LHSShiftArg, RHSShiftAmt).getNode(); 3024 else 3025 return DAG.getNode(ISD::ROTL, DL, VT, 3026 LHSShiftArg, LHSShiftAmt).getNode(); 3027 } 3028 } 3029 } 3030 3031 // Look for sign/zext/any-extended or truncate cases: 3032 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3033 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3034 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3035 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3036 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3037 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3038 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3039 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3040 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3041 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3042 if (RExtOp0.getOpcode() == ISD::SUB && 3043 RExtOp0.getOperand(1) == LExtOp0) { 3044 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3045 // (rotl x, y) 3046 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3047 // (rotr x, (sub 32, y)) 3048 if (ConstantSDNode *SUBC = 3049 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3050 if (SUBC->getAPIntValue() == OpSizeInBits) { 3051 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3052 LHSShiftArg, 3053 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3054 } 3055 } 3056 } else if (LExtOp0.getOpcode() == ISD::SUB && 3057 RExtOp0 == LExtOp0.getOperand(1)) { 3058 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3059 // (rotr x, y) 3060 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3061 // (rotl x, (sub 32, y)) 3062 if (ConstantSDNode *SUBC = 3063 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3064 if (SUBC->getAPIntValue() == OpSizeInBits) { 3065 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3066 LHSShiftArg, 3067 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3068 } 3069 } 3070 } 3071 } 3072 3073 return 0; 3074} 3075 3076SDValue DAGCombiner::visitXOR(SDNode *N) { 3077 SDValue N0 = N->getOperand(0); 3078 SDValue N1 = N->getOperand(1); 3079 SDValue LHS, RHS, CC; 3080 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3081 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3082 EVT VT = N0.getValueType(); 3083 3084 // fold vector ops 3085 if (VT.isVector()) { 3086 SDValue FoldedVOp = SimplifyVBinOp(N); 3087 if (FoldedVOp.getNode()) return FoldedVOp; 3088 } 3089 3090 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3091 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3092 return DAG.getConstant(0, VT); 3093 // fold (xor x, undef) -> undef 3094 if (N0.getOpcode() == ISD::UNDEF) 3095 return N0; 3096 if (N1.getOpcode() == ISD::UNDEF) 3097 return N1; 3098 // fold (xor c1, c2) -> c1^c2 3099 if (N0C && N1C) 3100 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3101 // canonicalize constant to RHS 3102 if (N0C && !N1C) 3103 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3104 // fold (xor x, 0) -> x 3105 if (N1C && N1C->isNullValue()) 3106 return N0; 3107 // reassociate xor 3108 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3109 if (RXOR.getNode() != 0) 3110 return RXOR; 3111 3112 // fold !(x cc y) -> (x !cc y) 3113 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3114 bool isInt = LHS.getValueType().isInteger(); 3115 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3116 isInt); 3117 3118 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3119 switch (N0.getOpcode()) { 3120 default: 3121 llvm_unreachable("Unhandled SetCC Equivalent!"); 3122 case ISD::SETCC: 3123 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3124 case ISD::SELECT_CC: 3125 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3126 N0.getOperand(3), NotCC); 3127 } 3128 } 3129 } 3130 3131 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3132 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3133 N0.getNode()->hasOneUse() && 3134 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3135 SDValue V = N0.getOperand(0); 3136 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3137 DAG.getConstant(1, V.getValueType())); 3138 AddToWorkList(V.getNode()); 3139 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3140 } 3141 3142 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3143 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3144 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3145 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3146 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3147 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3148 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3149 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3150 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3151 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3152 } 3153 } 3154 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3155 if (N1C && N1C->isAllOnesValue() && 3156 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3157 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3158 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3159 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3160 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3161 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3162 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3163 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3164 } 3165 } 3166 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3167 if (N1C && N0.getOpcode() == ISD::XOR) { 3168 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3169 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3170 if (N00C) 3171 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3172 DAG.getConstant(N1C->getAPIntValue() ^ 3173 N00C->getAPIntValue(), VT)); 3174 if (N01C) 3175 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3176 DAG.getConstant(N1C->getAPIntValue() ^ 3177 N01C->getAPIntValue(), VT)); 3178 } 3179 // fold (xor x, x) -> 0 3180 if (N0 == N1) 3181 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3182 3183 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3184 if (N0.getOpcode() == N1.getOpcode()) { 3185 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3186 if (Tmp.getNode()) return Tmp; 3187 } 3188 3189 // Simplify the expression using non-local knowledge. 3190 if (!VT.isVector() && 3191 SimplifyDemandedBits(SDValue(N, 0))) 3192 return SDValue(N, 0); 3193 3194 return SDValue(); 3195} 3196 3197/// visitShiftByConstant - Handle transforms common to the three shifts, when 3198/// the shift amount is a constant. 3199SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3200 SDNode *LHS = N->getOperand(0).getNode(); 3201 if (!LHS->hasOneUse()) return SDValue(); 3202 3203 // We want to pull some binops through shifts, so that we have (and (shift)) 3204 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3205 // thing happens with address calculations, so it's important to canonicalize 3206 // it. 3207 bool HighBitSet = false; // Can we transform this if the high bit is set? 3208 3209 switch (LHS->getOpcode()) { 3210 default: return SDValue(); 3211 case ISD::OR: 3212 case ISD::XOR: 3213 HighBitSet = false; // We can only transform sra if the high bit is clear. 3214 break; 3215 case ISD::AND: 3216 HighBitSet = true; // We can only transform sra if the high bit is set. 3217 break; 3218 case ISD::ADD: 3219 if (N->getOpcode() != ISD::SHL) 3220 return SDValue(); // only shl(add) not sr[al](add). 3221 HighBitSet = false; // We can only transform sra if the high bit is clear. 3222 break; 3223 } 3224 3225 // We require the RHS of the binop to be a constant as well. 3226 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3227 if (!BinOpCst) return SDValue(); 3228 3229 // FIXME: disable this unless the input to the binop is a shift by a constant. 3230 // If it is not a shift, it pessimizes some common cases like: 3231 // 3232 // void foo(int *X, int i) { X[i & 1235] = 1; } 3233 // int bar(int *X, int i) { return X[i & 255]; } 3234 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3235 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3236 BinOpLHSVal->getOpcode() != ISD::SRA && 3237 BinOpLHSVal->getOpcode() != ISD::SRL) || 3238 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3239 return SDValue(); 3240 3241 EVT VT = N->getValueType(0); 3242 3243 // If this is a signed shift right, and the high bit is modified by the 3244 // logical operation, do not perform the transformation. The highBitSet 3245 // boolean indicates the value of the high bit of the constant which would 3246 // cause it to be modified for this operation. 3247 if (N->getOpcode() == ISD::SRA) { 3248 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3249 if (BinOpRHSSignSet != HighBitSet) 3250 return SDValue(); 3251 } 3252 3253 // Fold the constants, shifting the binop RHS by the shift amount. 3254 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3255 N->getValueType(0), 3256 LHS->getOperand(1), N->getOperand(1)); 3257 3258 // Create the new shift. 3259 SDValue NewShift = DAG.getNode(N->getOpcode(), 3260 LHS->getOperand(0).getDebugLoc(), 3261 VT, LHS->getOperand(0), N->getOperand(1)); 3262 3263 // Create the new binop. 3264 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3265} 3266 3267SDValue DAGCombiner::visitSHL(SDNode *N) { 3268 SDValue N0 = N->getOperand(0); 3269 SDValue N1 = N->getOperand(1); 3270 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3271 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3272 EVT VT = N0.getValueType(); 3273 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3274 3275 // fold (shl c1, c2) -> c1<<c2 3276 if (N0C && N1C) 3277 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3278 // fold (shl 0, x) -> 0 3279 if (N0C && N0C->isNullValue()) 3280 return N0; 3281 // fold (shl x, c >= size(x)) -> undef 3282 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3283 return DAG.getUNDEF(VT); 3284 // fold (shl x, 0) -> x 3285 if (N1C && N1C->isNullValue()) 3286 return N0; 3287 // fold (shl undef, x) -> 0 3288 if (N0.getOpcode() == ISD::UNDEF) 3289 return DAG.getConstant(0, VT); 3290 // if (shl x, c) is known to be zero, return 0 3291 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3292 APInt::getAllOnesValue(OpSizeInBits))) 3293 return DAG.getConstant(0, VT); 3294 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3295 if (N1.getOpcode() == ISD::TRUNCATE && 3296 N1.getOperand(0).getOpcode() == ISD::AND && 3297 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3298 SDValue N101 = N1.getOperand(0).getOperand(1); 3299 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3300 EVT TruncVT = N1.getValueType(); 3301 SDValue N100 = N1.getOperand(0).getOperand(0); 3302 APInt TruncC = N101C->getAPIntValue(); 3303 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3304 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3305 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3306 DAG.getNode(ISD::TRUNCATE, 3307 N->getDebugLoc(), 3308 TruncVT, N100), 3309 DAG.getConstant(TruncC, TruncVT))); 3310 } 3311 } 3312 3313 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3314 return SDValue(N, 0); 3315 3316 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3317 if (N1C && N0.getOpcode() == ISD::SHL && 3318 N0.getOperand(1).getOpcode() == ISD::Constant) { 3319 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3320 uint64_t c2 = N1C->getZExtValue(); 3321 if (c1 + c2 >= OpSizeInBits) 3322 return DAG.getConstant(0, VT); 3323 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3324 DAG.getConstant(c1 + c2, N1.getValueType())); 3325 } 3326 3327 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3328 // For this to be valid, the second form must not preserve any of the bits 3329 // that are shifted out by the inner shift in the first form. This means 3330 // the outer shift size must be >= the number of bits added by the ext. 3331 // As a corollary, we don't care what kind of ext it is. 3332 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3333 N0.getOpcode() == ISD::ANY_EXTEND || 3334 N0.getOpcode() == ISD::SIGN_EXTEND) && 3335 N0.getOperand(0).getOpcode() == ISD::SHL && 3336 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3337 uint64_t c1 = 3338 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3339 uint64_t c2 = N1C->getZExtValue(); 3340 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3341 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3342 if (c2 >= OpSizeInBits - InnerShiftSize) { 3343 if (c1 + c2 >= OpSizeInBits) 3344 return DAG.getConstant(0, VT); 3345 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3346 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3347 N0.getOperand(0)->getOperand(0)), 3348 DAG.getConstant(c1 + c2, N1.getValueType())); 3349 } 3350 } 3351 3352 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3353 // (and (srl x, (sub c1, c2), MASK) 3354 if (N1C && N0.getOpcode() == ISD::SRL && 3355 N0.getOperand(1).getOpcode() == ISD::Constant) { 3356 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3357 if (c1 < VT.getSizeInBits()) { 3358 uint64_t c2 = N1C->getZExtValue(); 3359 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3360 VT.getSizeInBits() - c1); 3361 SDValue Shift; 3362 if (c2 > c1) { 3363 Mask = Mask.shl(c2-c1); 3364 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3365 DAG.getConstant(c2-c1, N1.getValueType())); 3366 } else { 3367 Mask = Mask.lshr(c1-c2); 3368 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3369 DAG.getConstant(c1-c2, N1.getValueType())); 3370 } 3371 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3372 DAG.getConstant(Mask, VT)); 3373 } 3374 } 3375 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3376 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3377 SDValue HiBitsMask = 3378 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3379 VT.getSizeInBits() - 3380 N1C->getZExtValue()), 3381 VT); 3382 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3383 HiBitsMask); 3384 } 3385 3386 if (N1C) { 3387 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3388 if (NewSHL.getNode()) 3389 return NewSHL; 3390 } 3391 3392 return SDValue(); 3393} 3394 3395SDValue DAGCombiner::visitSRA(SDNode *N) { 3396 SDValue N0 = N->getOperand(0); 3397 SDValue N1 = N->getOperand(1); 3398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3400 EVT VT = N0.getValueType(); 3401 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3402 3403 // fold (sra c1, c2) -> (sra c1, c2) 3404 if (N0C && N1C) 3405 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3406 // fold (sra 0, x) -> 0 3407 if (N0C && N0C->isNullValue()) 3408 return N0; 3409 // fold (sra -1, x) -> -1 3410 if (N0C && N0C->isAllOnesValue()) 3411 return N0; 3412 // fold (sra x, (setge c, size(x))) -> undef 3413 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3414 return DAG.getUNDEF(VT); 3415 // fold (sra x, 0) -> x 3416 if (N1C && N1C->isNullValue()) 3417 return N0; 3418 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3419 // sext_inreg. 3420 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3421 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3422 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3423 if (VT.isVector()) 3424 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3425 ExtVT, VT.getVectorNumElements()); 3426 if ((!LegalOperations || 3427 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3428 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3429 N0.getOperand(0), DAG.getValueType(ExtVT)); 3430 } 3431 3432 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3433 if (N1C && N0.getOpcode() == ISD::SRA) { 3434 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3435 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3436 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3437 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3438 DAG.getConstant(Sum, N1C->getValueType(0))); 3439 } 3440 } 3441 3442 // fold (sra (shl X, m), (sub result_size, n)) 3443 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3444 // result_size - n != m. 3445 // If truncate is free for the target sext(shl) is likely to result in better 3446 // code. 3447 if (N0.getOpcode() == ISD::SHL) { 3448 // Get the two constanst of the shifts, CN0 = m, CN = n. 3449 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3450 if (N01C && N1C) { 3451 // Determine what the truncate's result bitsize and type would be. 3452 EVT TruncVT = 3453 EVT::getIntegerVT(*DAG.getContext(), 3454 OpSizeInBits - N1C->getZExtValue()); 3455 // Determine the residual right-shift amount. 3456 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3457 3458 // If the shift is not a no-op (in which case this should be just a sign 3459 // extend already), the truncated to type is legal, sign_extend is legal 3460 // on that type, and the truncate to that type is both legal and free, 3461 // perform the transform. 3462 if ((ShiftAmt > 0) && 3463 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3464 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3465 TLI.isTruncateFree(VT, TruncVT)) { 3466 3467 SDValue Amt = DAG.getConstant(ShiftAmt, 3468 getShiftAmountTy(N0.getOperand(0).getValueType())); 3469 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3470 N0.getOperand(0), Amt); 3471 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3472 Shift); 3473 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3474 N->getValueType(0), Trunc); 3475 } 3476 } 3477 } 3478 3479 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3480 if (N1.getOpcode() == ISD::TRUNCATE && 3481 N1.getOperand(0).getOpcode() == ISD::AND && 3482 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3483 SDValue N101 = N1.getOperand(0).getOperand(1); 3484 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3485 EVT TruncVT = N1.getValueType(); 3486 SDValue N100 = N1.getOperand(0).getOperand(0); 3487 APInt TruncC = N101C->getAPIntValue(); 3488 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3489 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3490 DAG.getNode(ISD::AND, N->getDebugLoc(), 3491 TruncVT, 3492 DAG.getNode(ISD::TRUNCATE, 3493 N->getDebugLoc(), 3494 TruncVT, N100), 3495 DAG.getConstant(TruncC, TruncVT))); 3496 } 3497 } 3498 3499 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3500 // if c1 is equal to the number of bits the trunc removes 3501 if (N0.getOpcode() == ISD::TRUNCATE && 3502 (N0.getOperand(0).getOpcode() == ISD::SRL || 3503 N0.getOperand(0).getOpcode() == ISD::SRA) && 3504 N0.getOperand(0).hasOneUse() && 3505 N0.getOperand(0).getOperand(1).hasOneUse() && 3506 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3507 EVT LargeVT = N0.getOperand(0).getValueType(); 3508 ConstantSDNode *LargeShiftAmt = 3509 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3510 3511 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3512 LargeShiftAmt->getZExtValue()) { 3513 SDValue Amt = 3514 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3515 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3516 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3517 N0.getOperand(0).getOperand(0), Amt); 3518 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3519 } 3520 } 3521 3522 // Simplify, based on bits shifted out of the LHS. 3523 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3524 return SDValue(N, 0); 3525 3526 3527 // If the sign bit is known to be zero, switch this to a SRL. 3528 if (DAG.SignBitIsZero(N0)) 3529 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3530 3531 if (N1C) { 3532 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3533 if (NewSRA.getNode()) 3534 return NewSRA; 3535 } 3536 3537 return SDValue(); 3538} 3539 3540SDValue DAGCombiner::visitSRL(SDNode *N) { 3541 SDValue N0 = N->getOperand(0); 3542 SDValue N1 = N->getOperand(1); 3543 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3544 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3545 EVT VT = N0.getValueType(); 3546 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3547 3548 // fold (srl c1, c2) -> c1 >>u c2 3549 if (N0C && N1C) 3550 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3551 // fold (srl 0, x) -> 0 3552 if (N0C && N0C->isNullValue()) 3553 return N0; 3554 // fold (srl x, c >= size(x)) -> undef 3555 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3556 return DAG.getUNDEF(VT); 3557 // fold (srl x, 0) -> x 3558 if (N1C && N1C->isNullValue()) 3559 return N0; 3560 // if (srl x, c) is known to be zero, return 0 3561 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3562 APInt::getAllOnesValue(OpSizeInBits))) 3563 return DAG.getConstant(0, VT); 3564 3565 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3566 if (N1C && N0.getOpcode() == ISD::SRL && 3567 N0.getOperand(1).getOpcode() == ISD::Constant) { 3568 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3569 uint64_t c2 = N1C->getZExtValue(); 3570 if (c1 + c2 >= OpSizeInBits) 3571 return DAG.getConstant(0, VT); 3572 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3573 DAG.getConstant(c1 + c2, N1.getValueType())); 3574 } 3575 3576 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3577 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3578 N0.getOperand(0).getOpcode() == ISD::SRL && 3579 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3580 uint64_t c1 = 3581 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3582 uint64_t c2 = N1C->getZExtValue(); 3583 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3584 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3585 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3586 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3587 if (c1 + OpSizeInBits == InnerShiftSize) { 3588 if (c1 + c2 >= InnerShiftSize) 3589 return DAG.getConstant(0, VT); 3590 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3591 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3592 N0.getOperand(0)->getOperand(0), 3593 DAG.getConstant(c1 + c2, ShiftCountVT))); 3594 } 3595 } 3596 3597 // fold (srl (shl x, c), c) -> (and x, cst2) 3598 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3599 N0.getValueSizeInBits() <= 64) { 3600 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3601 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3602 DAG.getConstant(~0ULL >> ShAmt, VT)); 3603 } 3604 3605 3606 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3607 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3608 // Shifting in all undef bits? 3609 EVT SmallVT = N0.getOperand(0).getValueType(); 3610 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3611 return DAG.getUNDEF(VT); 3612 3613 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3614 uint64_t ShiftAmt = N1C->getZExtValue(); 3615 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3616 N0.getOperand(0), 3617 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3618 AddToWorkList(SmallShift.getNode()); 3619 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3620 } 3621 } 3622 3623 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3624 // bit, which is unmodified by sra. 3625 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3626 if (N0.getOpcode() == ISD::SRA) 3627 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3628 } 3629 3630 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3631 if (N1C && N0.getOpcode() == ISD::CTLZ && 3632 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3633 APInt KnownZero, KnownOne; 3634 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3635 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3636 3637 // If any of the input bits are KnownOne, then the input couldn't be all 3638 // zeros, thus the result of the srl will always be zero. 3639 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3640 3641 // If all of the bits input the to ctlz node are known to be zero, then 3642 // the result of the ctlz is "32" and the result of the shift is one. 3643 APInt UnknownBits = ~KnownZero & Mask; 3644 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3645 3646 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3647 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3648 // Okay, we know that only that the single bit specified by UnknownBits 3649 // could be set on input to the CTLZ node. If this bit is set, the SRL 3650 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3651 // to an SRL/XOR pair, which is likely to simplify more. 3652 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3653 SDValue Op = N0.getOperand(0); 3654 3655 if (ShAmt) { 3656 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3657 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3658 AddToWorkList(Op.getNode()); 3659 } 3660 3661 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3662 Op, DAG.getConstant(1, VT)); 3663 } 3664 } 3665 3666 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3667 if (N1.getOpcode() == ISD::TRUNCATE && 3668 N1.getOperand(0).getOpcode() == ISD::AND && 3669 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3670 SDValue N101 = N1.getOperand(0).getOperand(1); 3671 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3672 EVT TruncVT = N1.getValueType(); 3673 SDValue N100 = N1.getOperand(0).getOperand(0); 3674 APInt TruncC = N101C->getAPIntValue(); 3675 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3676 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3677 DAG.getNode(ISD::AND, N->getDebugLoc(), 3678 TruncVT, 3679 DAG.getNode(ISD::TRUNCATE, 3680 N->getDebugLoc(), 3681 TruncVT, N100), 3682 DAG.getConstant(TruncC, TruncVT))); 3683 } 3684 } 3685 3686 // fold operands of srl based on knowledge that the low bits are not 3687 // demanded. 3688 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3689 return SDValue(N, 0); 3690 3691 if (N1C) { 3692 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3693 if (NewSRL.getNode()) 3694 return NewSRL; 3695 } 3696 3697 // Attempt to convert a srl of a load into a narrower zero-extending load. 3698 SDValue NarrowLoad = ReduceLoadWidth(N); 3699 if (NarrowLoad.getNode()) 3700 return NarrowLoad; 3701 3702 // Here is a common situation. We want to optimize: 3703 // 3704 // %a = ... 3705 // %b = and i32 %a, 2 3706 // %c = srl i32 %b, 1 3707 // brcond i32 %c ... 3708 // 3709 // into 3710 // 3711 // %a = ... 3712 // %b = and %a, 2 3713 // %c = setcc eq %b, 0 3714 // brcond %c ... 3715 // 3716 // However when after the source operand of SRL is optimized into AND, the SRL 3717 // itself may not be optimized further. Look for it and add the BRCOND into 3718 // the worklist. 3719 if (N->hasOneUse()) { 3720 SDNode *Use = *N->use_begin(); 3721 if (Use->getOpcode() == ISD::BRCOND) 3722 AddToWorkList(Use); 3723 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3724 // Also look pass the truncate. 3725 Use = *Use->use_begin(); 3726 if (Use->getOpcode() == ISD::BRCOND) 3727 AddToWorkList(Use); 3728 } 3729 } 3730 3731 return SDValue(); 3732} 3733 3734SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3735 SDValue N0 = N->getOperand(0); 3736 EVT VT = N->getValueType(0); 3737 3738 // fold (ctlz c1) -> c2 3739 if (isa<ConstantSDNode>(N0)) 3740 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3741 return SDValue(); 3742} 3743 3744SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3745 SDValue N0 = N->getOperand(0); 3746 EVT VT = N->getValueType(0); 3747 3748 // fold (cttz c1) -> c2 3749 if (isa<ConstantSDNode>(N0)) 3750 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3751 return SDValue(); 3752} 3753 3754SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3755 SDValue N0 = N->getOperand(0); 3756 EVT VT = N->getValueType(0); 3757 3758 // fold (ctpop c1) -> c2 3759 if (isa<ConstantSDNode>(N0)) 3760 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3761 return SDValue(); 3762} 3763 3764SDValue DAGCombiner::visitSELECT(SDNode *N) { 3765 SDValue N0 = N->getOperand(0); 3766 SDValue N1 = N->getOperand(1); 3767 SDValue N2 = N->getOperand(2); 3768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3770 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3771 EVT VT = N->getValueType(0); 3772 EVT VT0 = N0.getValueType(); 3773 3774 // fold (select C, X, X) -> X 3775 if (N1 == N2) 3776 return N1; 3777 // fold (select true, X, Y) -> X 3778 if (N0C && !N0C->isNullValue()) 3779 return N1; 3780 // fold (select false, X, Y) -> Y 3781 if (N0C && N0C->isNullValue()) 3782 return N2; 3783 // fold (select C, 1, X) -> (or C, X) 3784 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3785 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3786 // fold (select C, 0, 1) -> (xor C, 1) 3787 if (VT.isInteger() && 3788 (VT0 == MVT::i1 || 3789 (VT0.isInteger() && 3790 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3791 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3792 SDValue XORNode; 3793 if (VT == VT0) 3794 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3795 N0, DAG.getConstant(1, VT0)); 3796 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3797 N0, DAG.getConstant(1, VT0)); 3798 AddToWorkList(XORNode.getNode()); 3799 if (VT.bitsGT(VT0)) 3800 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3801 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3802 } 3803 // fold (select C, 0, X) -> (and (not C), X) 3804 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3805 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3806 AddToWorkList(NOTNode.getNode()); 3807 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3808 } 3809 // fold (select C, X, 1) -> (or (not C), X) 3810 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3811 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3812 AddToWorkList(NOTNode.getNode()); 3813 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3814 } 3815 // fold (select C, X, 0) -> (and C, X) 3816 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3817 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3818 // fold (select X, X, Y) -> (or X, Y) 3819 // fold (select X, 1, Y) -> (or X, Y) 3820 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3821 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3822 // fold (select X, Y, X) -> (and X, Y) 3823 // fold (select X, Y, 0) -> (and X, Y) 3824 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3825 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3826 3827 // If we can fold this based on the true/false value, do so. 3828 if (SimplifySelectOps(N, N1, N2)) 3829 return SDValue(N, 0); // Don't revisit N. 3830 3831 // fold selects based on a setcc into other things, such as min/max/abs 3832 if (N0.getOpcode() == ISD::SETCC) { 3833 // FIXME: 3834 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3835 // having to say they don't support SELECT_CC on every type the DAG knows 3836 // about, since there is no way to mark an opcode illegal at all value types 3837 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3838 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3839 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3840 N0.getOperand(0), N0.getOperand(1), 3841 N1, N2, N0.getOperand(2)); 3842 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3843 } 3844 3845 return SDValue(); 3846} 3847 3848SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3849 SDValue N0 = N->getOperand(0); 3850 SDValue N1 = N->getOperand(1); 3851 SDValue N2 = N->getOperand(2); 3852 SDValue N3 = N->getOperand(3); 3853 SDValue N4 = N->getOperand(4); 3854 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3855 3856 // fold select_cc lhs, rhs, x, x, cc -> x 3857 if (N2 == N3) 3858 return N2; 3859 3860 // Determine if the condition we're dealing with is constant 3861 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3862 N0, N1, CC, N->getDebugLoc(), false); 3863 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3864 3865 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3866 if (!SCCC->isNullValue()) 3867 return N2; // cond always true -> true val 3868 else 3869 return N3; // cond always false -> false val 3870 } 3871 3872 // Fold to a simpler select_cc 3873 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3874 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3875 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3876 SCC.getOperand(2)); 3877 3878 // If we can fold this based on the true/false value, do so. 3879 if (SimplifySelectOps(N, N2, N3)) 3880 return SDValue(N, 0); // Don't revisit N. 3881 3882 // fold select_cc into other things, such as min/max/abs 3883 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3884} 3885 3886SDValue DAGCombiner::visitSETCC(SDNode *N) { 3887 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3888 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3889 N->getDebugLoc()); 3890} 3891 3892// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3893// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3894// transformation. Returns true if extension are possible and the above 3895// mentioned transformation is profitable. 3896static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3897 unsigned ExtOpc, 3898 SmallVector<SDNode*, 4> &ExtendNodes, 3899 const TargetLowering &TLI) { 3900 bool HasCopyToRegUses = false; 3901 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3902 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3903 UE = N0.getNode()->use_end(); 3904 UI != UE; ++UI) { 3905 SDNode *User = *UI; 3906 if (User == N) 3907 continue; 3908 if (UI.getUse().getResNo() != N0.getResNo()) 3909 continue; 3910 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3911 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3912 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3913 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3914 // Sign bits will be lost after a zext. 3915 return false; 3916 bool Add = false; 3917 for (unsigned i = 0; i != 2; ++i) { 3918 SDValue UseOp = User->getOperand(i); 3919 if (UseOp == N0) 3920 continue; 3921 if (!isa<ConstantSDNode>(UseOp)) 3922 return false; 3923 Add = true; 3924 } 3925 if (Add) 3926 ExtendNodes.push_back(User); 3927 continue; 3928 } 3929 // If truncates aren't free and there are users we can't 3930 // extend, it isn't worthwhile. 3931 if (!isTruncFree) 3932 return false; 3933 // Remember if this value is live-out. 3934 if (User->getOpcode() == ISD::CopyToReg) 3935 HasCopyToRegUses = true; 3936 } 3937 3938 if (HasCopyToRegUses) { 3939 bool BothLiveOut = false; 3940 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3941 UI != UE; ++UI) { 3942 SDUse &Use = UI.getUse(); 3943 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3944 BothLiveOut = true; 3945 break; 3946 } 3947 } 3948 if (BothLiveOut) 3949 // Both unextended and extended values are live out. There had better be 3950 // a good reason for the transformation. 3951 return ExtendNodes.size(); 3952 } 3953 return true; 3954} 3955 3956void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 3957 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 3958 ISD::NodeType ExtType) { 3959 // Extend SetCC uses if necessary. 3960 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3961 SDNode *SetCC = SetCCs[i]; 3962 SmallVector<SDValue, 4> Ops; 3963 3964 for (unsigned j = 0; j != 2; ++j) { 3965 SDValue SOp = SetCC->getOperand(j); 3966 if (SOp == Trunc) 3967 Ops.push_back(ExtLoad); 3968 else 3969 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 3970 } 3971 3972 Ops.push_back(SetCC->getOperand(2)); 3973 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 3974 &Ops[0], Ops.size())); 3975 } 3976} 3977 3978SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3979 SDValue N0 = N->getOperand(0); 3980 EVT VT = N->getValueType(0); 3981 3982 // fold (sext c1) -> c1 3983 if (isa<ConstantSDNode>(N0)) 3984 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3985 3986 // fold (sext (sext x)) -> (sext x) 3987 // fold (sext (aext x)) -> (sext x) 3988 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3989 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3990 N0.getOperand(0)); 3991 3992 if (N0.getOpcode() == ISD::TRUNCATE) { 3993 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3994 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3995 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3996 if (NarrowLoad.getNode()) { 3997 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3998 if (NarrowLoad.getNode() != N0.getNode()) { 3999 CombineTo(N0.getNode(), NarrowLoad); 4000 // CombineTo deleted the truncate, if needed, but not what's under it. 4001 AddToWorkList(oye); 4002 } 4003 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4004 } 4005 4006 // See if the value being truncated is already sign extended. If so, just 4007 // eliminate the trunc/sext pair. 4008 SDValue Op = N0.getOperand(0); 4009 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4010 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4011 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4012 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4013 4014 if (OpBits == DestBits) { 4015 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4016 // bits, it is already ready. 4017 if (NumSignBits > DestBits-MidBits) 4018 return Op; 4019 } else if (OpBits < DestBits) { 4020 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4021 // bits, just sext from i32. 4022 if (NumSignBits > OpBits-MidBits) 4023 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4024 } else { 4025 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4026 // bits, just truncate to i32. 4027 if (NumSignBits > OpBits-MidBits) 4028 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4029 } 4030 4031 // fold (sext (truncate x)) -> (sextinreg x). 4032 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4033 N0.getValueType())) { 4034 if (OpBits < DestBits) 4035 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4036 else if (OpBits > DestBits) 4037 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4038 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4039 DAG.getValueType(N0.getValueType())); 4040 } 4041 } 4042 4043 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4044 // None of the supported targets knows how to perform load and sign extend 4045 // on vectors in one instruction. We only perform this transformation on 4046 // scalars. 4047 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4048 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4049 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4050 bool DoXform = true; 4051 SmallVector<SDNode*, 4> SetCCs; 4052 if (!N0.hasOneUse()) 4053 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4054 if (DoXform) { 4055 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4056 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4057 LN0->getChain(), 4058 LN0->getBasePtr(), LN0->getPointerInfo(), 4059 N0.getValueType(), 4060 LN0->isVolatile(), LN0->isNonTemporal(), 4061 LN0->getAlignment()); 4062 CombineTo(N, ExtLoad); 4063 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4064 N0.getValueType(), ExtLoad); 4065 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4066 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4067 ISD::SIGN_EXTEND); 4068 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4069 } 4070 } 4071 4072 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4073 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4074 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4075 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4076 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4077 EVT MemVT = LN0->getMemoryVT(); 4078 if ((!LegalOperations && !LN0->isVolatile()) || 4079 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4080 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4081 LN0->getChain(), 4082 LN0->getBasePtr(), LN0->getPointerInfo(), 4083 MemVT, 4084 LN0->isVolatile(), LN0->isNonTemporal(), 4085 LN0->getAlignment()); 4086 CombineTo(N, ExtLoad); 4087 CombineTo(N0.getNode(), 4088 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4089 N0.getValueType(), ExtLoad), 4090 ExtLoad.getValue(1)); 4091 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4092 } 4093 } 4094 4095 // fold (sext (and/or/xor (load x), cst)) -> 4096 // (and/or/xor (sextload x), (sext cst)) 4097 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4098 N0.getOpcode() == ISD::XOR) && 4099 isa<LoadSDNode>(N0.getOperand(0)) && 4100 N0.getOperand(1).getOpcode() == ISD::Constant && 4101 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4102 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4103 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4104 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4105 bool DoXform = true; 4106 SmallVector<SDNode*, 4> SetCCs; 4107 if (!N0.hasOneUse()) 4108 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4109 SetCCs, TLI); 4110 if (DoXform) { 4111 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4112 LN0->getChain(), LN0->getBasePtr(), 4113 LN0->getPointerInfo(), 4114 LN0->getMemoryVT(), 4115 LN0->isVolatile(), 4116 LN0->isNonTemporal(), 4117 LN0->getAlignment()); 4118 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4119 Mask = Mask.sext(VT.getSizeInBits()); 4120 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4121 ExtLoad, DAG.getConstant(Mask, VT)); 4122 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4123 N0.getOperand(0).getDebugLoc(), 4124 N0.getOperand(0).getValueType(), ExtLoad); 4125 CombineTo(N, And); 4126 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4127 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4128 ISD::SIGN_EXTEND); 4129 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4130 } 4131 } 4132 } 4133 4134 if (N0.getOpcode() == ISD::SETCC) { 4135 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4136 // Only do this before legalize for now. 4137 if (VT.isVector() && !LegalOperations) { 4138 EVT N0VT = N0.getOperand(0).getValueType(); 4139 // We know that the # elements of the results is the same as the 4140 // # elements of the compare (and the # elements of the compare result 4141 // for that matter). Check to see that they are the same size. If so, 4142 // we know that the element size of the sext'd result matches the 4143 // element size of the compare operands. 4144 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4145 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4146 N0.getOperand(1), 4147 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4148 // If the desired elements are smaller or larger than the source 4149 // elements we can use a matching integer vector type and then 4150 // truncate/sign extend 4151 else { 4152 EVT MatchingElementType = 4153 EVT::getIntegerVT(*DAG.getContext(), 4154 N0VT.getScalarType().getSizeInBits()); 4155 EVT MatchingVectorType = 4156 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4157 N0VT.getVectorNumElements()); 4158 SDValue VsetCC = 4159 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4160 N0.getOperand(1), 4161 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4162 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4163 } 4164 } 4165 4166 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4167 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4168 SDValue NegOne = 4169 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4170 SDValue SCC = 4171 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4172 NegOne, DAG.getConstant(0, VT), 4173 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4174 if (SCC.getNode()) return SCC; 4175 if (!LegalOperations || 4176 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4177 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4178 DAG.getSetCC(N->getDebugLoc(), 4179 TLI.getSetCCResultType(VT), 4180 N0.getOperand(0), N0.getOperand(1), 4181 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4182 NegOne, DAG.getConstant(0, VT)); 4183 } 4184 4185 // fold (sext x) -> (zext x) if the sign bit is known zero. 4186 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4187 DAG.SignBitIsZero(N0)) 4188 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4189 4190 return SDValue(); 4191} 4192 4193SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4194 SDValue N0 = N->getOperand(0); 4195 EVT VT = N->getValueType(0); 4196 4197 // fold (zext c1) -> c1 4198 if (isa<ConstantSDNode>(N0)) 4199 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4200 // fold (zext (zext x)) -> (zext x) 4201 // fold (zext (aext x)) -> (zext x) 4202 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4203 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4204 N0.getOperand(0)); 4205 4206 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4207 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4208 if (N0.getOpcode() == ISD::TRUNCATE) { 4209 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4210 if (NarrowLoad.getNode()) { 4211 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4212 if (NarrowLoad.getNode() != N0.getNode()) { 4213 CombineTo(N0.getNode(), NarrowLoad); 4214 // CombineTo deleted the truncate, if needed, but not what's under it. 4215 AddToWorkList(oye); 4216 } 4217 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4218 } 4219 } 4220 4221 // fold (zext (truncate x)) -> (and x, mask) 4222 if (N0.getOpcode() == ISD::TRUNCATE && 4223 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4224 4225 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4226 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4227 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4228 if (NarrowLoad.getNode()) { 4229 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4230 if (NarrowLoad.getNode() != N0.getNode()) { 4231 CombineTo(N0.getNode(), NarrowLoad); 4232 // CombineTo deleted the truncate, if needed, but not what's under it. 4233 AddToWorkList(oye); 4234 } 4235 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4236 } 4237 4238 SDValue Op = N0.getOperand(0); 4239 if (Op.getValueType().bitsLT(VT)) { 4240 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4241 } else if (Op.getValueType().bitsGT(VT)) { 4242 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4243 } 4244 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4245 N0.getValueType().getScalarType()); 4246 } 4247 4248 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4249 // if either of the casts is not free. 4250 if (N0.getOpcode() == ISD::AND && 4251 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4252 N0.getOperand(1).getOpcode() == ISD::Constant && 4253 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4254 N0.getValueType()) || 4255 !TLI.isZExtFree(N0.getValueType(), VT))) { 4256 SDValue X = N0.getOperand(0).getOperand(0); 4257 if (X.getValueType().bitsLT(VT)) { 4258 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4259 } else if (X.getValueType().bitsGT(VT)) { 4260 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4261 } 4262 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4263 Mask = Mask.zext(VT.getSizeInBits()); 4264 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4265 X, DAG.getConstant(Mask, VT)); 4266 } 4267 4268 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4269 // None of the supported targets knows how to perform load and vector_zext 4270 // on vectors in one instruction. We only perform this transformation on 4271 // scalars. 4272 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4273 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4274 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4275 bool DoXform = true; 4276 SmallVector<SDNode*, 4> SetCCs; 4277 if (!N0.hasOneUse()) 4278 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4279 if (DoXform) { 4280 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4281 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4282 LN0->getChain(), 4283 LN0->getBasePtr(), LN0->getPointerInfo(), 4284 N0.getValueType(), 4285 LN0->isVolatile(), LN0->isNonTemporal(), 4286 LN0->getAlignment()); 4287 CombineTo(N, ExtLoad); 4288 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4289 N0.getValueType(), ExtLoad); 4290 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4291 4292 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4293 ISD::ZERO_EXTEND); 4294 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4295 } 4296 } 4297 4298 // fold (zext (and/or/xor (load x), cst)) -> 4299 // (and/or/xor (zextload x), (zext cst)) 4300 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4301 N0.getOpcode() == ISD::XOR) && 4302 isa<LoadSDNode>(N0.getOperand(0)) && 4303 N0.getOperand(1).getOpcode() == ISD::Constant && 4304 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4305 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4306 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4307 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4308 bool DoXform = true; 4309 SmallVector<SDNode*, 4> SetCCs; 4310 if (!N0.hasOneUse()) 4311 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4312 SetCCs, TLI); 4313 if (DoXform) { 4314 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4315 LN0->getChain(), LN0->getBasePtr(), 4316 LN0->getPointerInfo(), 4317 LN0->getMemoryVT(), 4318 LN0->isVolatile(), 4319 LN0->isNonTemporal(), 4320 LN0->getAlignment()); 4321 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4322 Mask = Mask.zext(VT.getSizeInBits()); 4323 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4324 ExtLoad, DAG.getConstant(Mask, VT)); 4325 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4326 N0.getOperand(0).getDebugLoc(), 4327 N0.getOperand(0).getValueType(), ExtLoad); 4328 CombineTo(N, And); 4329 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4330 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4331 ISD::ZERO_EXTEND); 4332 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4333 } 4334 } 4335 } 4336 4337 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4338 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4339 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4340 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4341 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4342 EVT MemVT = LN0->getMemoryVT(); 4343 if ((!LegalOperations && !LN0->isVolatile()) || 4344 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4345 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4346 LN0->getChain(), 4347 LN0->getBasePtr(), LN0->getPointerInfo(), 4348 MemVT, 4349 LN0->isVolatile(), LN0->isNonTemporal(), 4350 LN0->getAlignment()); 4351 CombineTo(N, ExtLoad); 4352 CombineTo(N0.getNode(), 4353 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4354 ExtLoad), 4355 ExtLoad.getValue(1)); 4356 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4357 } 4358 } 4359 4360 if (N0.getOpcode() == ISD::SETCC) { 4361 if (!LegalOperations && VT.isVector()) { 4362 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4363 // Only do this before legalize for now. 4364 EVT N0VT = N0.getOperand(0).getValueType(); 4365 EVT EltVT = VT.getVectorElementType(); 4366 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4367 DAG.getConstant(1, EltVT)); 4368 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4369 // We know that the # elements of the results is the same as the 4370 // # elements of the compare (and the # elements of the compare result 4371 // for that matter). Check to see that they are the same size. If so, 4372 // we know that the element size of the sext'd result matches the 4373 // element size of the compare operands. 4374 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4375 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4376 N0.getOperand(1), 4377 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4378 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4379 &OneOps[0], OneOps.size())); 4380 4381 // If the desired elements are smaller or larger than the source 4382 // elements we can use a matching integer vector type and then 4383 // truncate/sign extend 4384 EVT MatchingElementType = 4385 EVT::getIntegerVT(*DAG.getContext(), 4386 N0VT.getScalarType().getSizeInBits()); 4387 EVT MatchingVectorType = 4388 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4389 N0VT.getVectorNumElements()); 4390 SDValue VsetCC = 4391 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4392 N0.getOperand(1), 4393 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4394 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4395 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4396 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4397 &OneOps[0], OneOps.size())); 4398 } 4399 4400 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4401 SDValue SCC = 4402 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4403 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4404 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4405 if (SCC.getNode()) return SCC; 4406 } 4407 4408 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4409 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4410 isa<ConstantSDNode>(N0.getOperand(1)) && 4411 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4412 N0.hasOneUse()) { 4413 SDValue ShAmt = N0.getOperand(1); 4414 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4415 if (N0.getOpcode() == ISD::SHL) { 4416 SDValue InnerZExt = N0.getOperand(0); 4417 // If the original shl may be shifting out bits, do not perform this 4418 // transformation. 4419 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4420 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4421 if (ShAmtVal > KnownZeroBits) 4422 return SDValue(); 4423 } 4424 4425 DebugLoc DL = N->getDebugLoc(); 4426 4427 // Ensure that the shift amount is wide enough for the shifted value. 4428 if (VT.getSizeInBits() >= 256) 4429 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4430 4431 return DAG.getNode(N0.getOpcode(), DL, VT, 4432 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4433 ShAmt); 4434 } 4435 4436 return SDValue(); 4437} 4438 4439SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4440 SDValue N0 = N->getOperand(0); 4441 EVT VT = N->getValueType(0); 4442 4443 // fold (aext c1) -> c1 4444 if (isa<ConstantSDNode>(N0)) 4445 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4446 // fold (aext (aext x)) -> (aext x) 4447 // fold (aext (zext x)) -> (zext x) 4448 // fold (aext (sext x)) -> (sext x) 4449 if (N0.getOpcode() == ISD::ANY_EXTEND || 4450 N0.getOpcode() == ISD::ZERO_EXTEND || 4451 N0.getOpcode() == ISD::SIGN_EXTEND) 4452 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4453 4454 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4455 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4456 if (N0.getOpcode() == ISD::TRUNCATE) { 4457 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4458 if (NarrowLoad.getNode()) { 4459 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4460 if (NarrowLoad.getNode() != N0.getNode()) { 4461 CombineTo(N0.getNode(), NarrowLoad); 4462 // CombineTo deleted the truncate, if needed, but not what's under it. 4463 AddToWorkList(oye); 4464 } 4465 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4466 } 4467 } 4468 4469 // fold (aext (truncate x)) 4470 if (N0.getOpcode() == ISD::TRUNCATE) { 4471 SDValue TruncOp = N0.getOperand(0); 4472 if (TruncOp.getValueType() == VT) 4473 return TruncOp; // x iff x size == zext size. 4474 if (TruncOp.getValueType().bitsGT(VT)) 4475 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4476 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4477 } 4478 4479 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4480 // if the trunc is not free. 4481 if (N0.getOpcode() == ISD::AND && 4482 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4483 N0.getOperand(1).getOpcode() == ISD::Constant && 4484 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4485 N0.getValueType())) { 4486 SDValue X = N0.getOperand(0).getOperand(0); 4487 if (X.getValueType().bitsLT(VT)) { 4488 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4489 } else if (X.getValueType().bitsGT(VT)) { 4490 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4491 } 4492 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4493 Mask = Mask.zext(VT.getSizeInBits()); 4494 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4495 X, DAG.getConstant(Mask, VT)); 4496 } 4497 4498 // fold (aext (load x)) -> (aext (truncate (extload x))) 4499 // None of the supported targets knows how to perform load and any_ext 4500 // on vectors in one instruction. We only perform this transformation on 4501 // scalars. 4502 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4503 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4504 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4505 bool DoXform = true; 4506 SmallVector<SDNode*, 4> SetCCs; 4507 if (!N0.hasOneUse()) 4508 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4509 if (DoXform) { 4510 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4511 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4512 LN0->getChain(), 4513 LN0->getBasePtr(), LN0->getPointerInfo(), 4514 N0.getValueType(), 4515 LN0->isVolatile(), LN0->isNonTemporal(), 4516 LN0->getAlignment()); 4517 CombineTo(N, ExtLoad); 4518 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4519 N0.getValueType(), ExtLoad); 4520 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4521 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4522 ISD::ANY_EXTEND); 4523 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4524 } 4525 } 4526 4527 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4528 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4529 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4530 if (N0.getOpcode() == ISD::LOAD && 4531 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4532 N0.hasOneUse()) { 4533 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4534 EVT MemVT = LN0->getMemoryVT(); 4535 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4536 VT, LN0->getChain(), LN0->getBasePtr(), 4537 LN0->getPointerInfo(), MemVT, 4538 LN0->isVolatile(), LN0->isNonTemporal(), 4539 LN0->getAlignment()); 4540 CombineTo(N, ExtLoad); 4541 CombineTo(N0.getNode(), 4542 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4543 N0.getValueType(), ExtLoad), 4544 ExtLoad.getValue(1)); 4545 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4546 } 4547 4548 if (N0.getOpcode() == ISD::SETCC) { 4549 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4550 // Only do this before legalize for now. 4551 if (VT.isVector() && !LegalOperations) { 4552 EVT N0VT = N0.getOperand(0).getValueType(); 4553 // We know that the # elements of the results is the same as the 4554 // # elements of the compare (and the # elements of the compare result 4555 // for that matter). Check to see that they are the same size. If so, 4556 // we know that the element size of the sext'd result matches the 4557 // element size of the compare operands. 4558 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4559 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4560 N0.getOperand(1), 4561 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4562 // If the desired elements are smaller or larger than the source 4563 // elements we can use a matching integer vector type and then 4564 // truncate/sign extend 4565 else { 4566 EVT MatchingElementType = 4567 EVT::getIntegerVT(*DAG.getContext(), 4568 N0VT.getScalarType().getSizeInBits()); 4569 EVT MatchingVectorType = 4570 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4571 N0VT.getVectorNumElements()); 4572 SDValue VsetCC = 4573 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4574 N0.getOperand(1), 4575 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4576 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4577 } 4578 } 4579 4580 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4581 SDValue SCC = 4582 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4583 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4584 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4585 if (SCC.getNode()) 4586 return SCC; 4587 } 4588 4589 return SDValue(); 4590} 4591 4592/// GetDemandedBits - See if the specified operand can be simplified with the 4593/// knowledge that only the bits specified by Mask are used. If so, return the 4594/// simpler operand, otherwise return a null SDValue. 4595SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4596 switch (V.getOpcode()) { 4597 default: break; 4598 case ISD::OR: 4599 case ISD::XOR: 4600 // If the LHS or RHS don't contribute bits to the or, drop them. 4601 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4602 return V.getOperand(1); 4603 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4604 return V.getOperand(0); 4605 break; 4606 case ISD::SRL: 4607 // Only look at single-use SRLs. 4608 if (!V.getNode()->hasOneUse()) 4609 break; 4610 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4611 // See if we can recursively simplify the LHS. 4612 unsigned Amt = RHSC->getZExtValue(); 4613 4614 // Watch out for shift count overflow though. 4615 if (Amt >= Mask.getBitWidth()) break; 4616 APInt NewMask = Mask << Amt; 4617 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4618 if (SimplifyLHS.getNode()) 4619 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4620 SimplifyLHS, V.getOperand(1)); 4621 } 4622 } 4623 return SDValue(); 4624} 4625 4626/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4627/// bits and then truncated to a narrower type and where N is a multiple 4628/// of number of bits of the narrower type, transform it to a narrower load 4629/// from address + N / num of bits of new type. If the result is to be 4630/// extended, also fold the extension to form a extending load. 4631SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4632 unsigned Opc = N->getOpcode(); 4633 4634 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4635 SDValue N0 = N->getOperand(0); 4636 EVT VT = N->getValueType(0); 4637 EVT ExtVT = VT; 4638 4639 // This transformation isn't valid for vector loads. 4640 if (VT.isVector()) 4641 return SDValue(); 4642 4643 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4644 // extended to VT. 4645 if (Opc == ISD::SIGN_EXTEND_INREG) { 4646 ExtType = ISD::SEXTLOAD; 4647 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4648 } else if (Opc == ISD::SRL) { 4649 // Another special-case: SRL is basically zero-extending a narrower value. 4650 ExtType = ISD::ZEXTLOAD; 4651 N0 = SDValue(N, 0); 4652 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4653 if (!N01) return SDValue(); 4654 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4655 VT.getSizeInBits() - N01->getZExtValue()); 4656 } 4657 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4658 return SDValue(); 4659 4660 unsigned EVTBits = ExtVT.getSizeInBits(); 4661 4662 // Do not generate loads of non-round integer types since these can 4663 // be expensive (and would be wrong if the type is not byte sized). 4664 if (!ExtVT.isRound()) 4665 return SDValue(); 4666 4667 unsigned ShAmt = 0; 4668 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4669 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4670 ShAmt = N01->getZExtValue(); 4671 // Is the shift amount a multiple of size of VT? 4672 if ((ShAmt & (EVTBits-1)) == 0) { 4673 N0 = N0.getOperand(0); 4674 // Is the load width a multiple of size of VT? 4675 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4676 return SDValue(); 4677 } 4678 4679 // At this point, we must have a load or else we can't do the transform. 4680 if (!isa<LoadSDNode>(N0)) return SDValue(); 4681 4682 // If the shift amount is larger than the input type then we're not 4683 // accessing any of the loaded bytes. If the load was a zextload/extload 4684 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4685 // If the load was a sextload then the result is a splat of the sign bit 4686 // of the extended byte. This is not worth optimizing for. 4687 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4688 return SDValue(); 4689 } 4690 } 4691 4692 // If the load is shifted left (and the result isn't shifted back right), 4693 // we can fold the truncate through the shift. 4694 unsigned ShLeftAmt = 0; 4695 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4696 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4697 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4698 ShLeftAmt = N01->getZExtValue(); 4699 N0 = N0.getOperand(0); 4700 } 4701 } 4702 4703 // If we haven't found a load, we can't narrow it. Don't transform one with 4704 // multiple uses, this would require adding a new load. 4705 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4706 // Don't change the width of a volatile load. 4707 cast<LoadSDNode>(N0)->isVolatile()) 4708 return SDValue(); 4709 4710 // Verify that we are actually reducing a load width here. 4711 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4712 return SDValue(); 4713 4714 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4715 EVT PtrType = N0.getOperand(1).getValueType(); 4716 4717 // For big endian targets, we need to adjust the offset to the pointer to 4718 // load the correct bytes. 4719 if (TLI.isBigEndian()) { 4720 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4721 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4722 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4723 } 4724 4725 uint64_t PtrOff = ShAmt / 8; 4726 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4727 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4728 PtrType, LN0->getBasePtr(), 4729 DAG.getConstant(PtrOff, PtrType)); 4730 AddToWorkList(NewPtr.getNode()); 4731 4732 SDValue Load; 4733 if (ExtType == ISD::NON_EXTLOAD) 4734 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4735 LN0->getPointerInfo().getWithOffset(PtrOff), 4736 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4737 else 4738 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4739 LN0->getPointerInfo().getWithOffset(PtrOff), 4740 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4741 NewAlign); 4742 4743 // Replace the old load's chain with the new load's chain. 4744 WorkListRemover DeadNodes(*this); 4745 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4746 &DeadNodes); 4747 4748 // Shift the result left, if we've swallowed a left shift. 4749 SDValue Result = Load; 4750 if (ShLeftAmt != 0) { 4751 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4752 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4753 ShImmTy = VT; 4754 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4755 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4756 } 4757 4758 // Return the new loaded value. 4759 return Result; 4760} 4761 4762SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4763 SDValue N0 = N->getOperand(0); 4764 SDValue N1 = N->getOperand(1); 4765 EVT VT = N->getValueType(0); 4766 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4767 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4768 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4769 4770 // fold (sext_in_reg c1) -> c1 4771 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4772 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4773 4774 // If the input is already sign extended, just drop the extension. 4775 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4776 return N0; 4777 4778 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4779 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4780 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4781 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4782 N0.getOperand(0), N1); 4783 } 4784 4785 // fold (sext_in_reg (sext x)) -> (sext x) 4786 // fold (sext_in_reg (aext x)) -> (sext x) 4787 // if x is small enough. 4788 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4789 SDValue N00 = N0.getOperand(0); 4790 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4791 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4792 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4793 } 4794 4795 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4796 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4797 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4798 4799 // fold operands of sext_in_reg based on knowledge that the top bits are not 4800 // demanded. 4801 if (SimplifyDemandedBits(SDValue(N, 0))) 4802 return SDValue(N, 0); 4803 4804 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4805 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4806 SDValue NarrowLoad = ReduceLoadWidth(N); 4807 if (NarrowLoad.getNode()) 4808 return NarrowLoad; 4809 4810 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4811 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4812 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4813 if (N0.getOpcode() == ISD::SRL) { 4814 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4815 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4816 // We can turn this into an SRA iff the input to the SRL is already sign 4817 // extended enough. 4818 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4819 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4820 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4821 N0.getOperand(0), N0.getOperand(1)); 4822 } 4823 } 4824 4825 // fold (sext_inreg (extload x)) -> (sextload x) 4826 if (ISD::isEXTLoad(N0.getNode()) && 4827 ISD::isUNINDEXEDLoad(N0.getNode()) && 4828 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4829 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4830 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4831 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4832 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4833 LN0->getChain(), 4834 LN0->getBasePtr(), LN0->getPointerInfo(), 4835 EVT, 4836 LN0->isVolatile(), LN0->isNonTemporal(), 4837 LN0->getAlignment()); 4838 CombineTo(N, ExtLoad); 4839 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4840 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4841 } 4842 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4843 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4844 N0.hasOneUse() && 4845 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4846 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4847 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4848 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4849 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4850 LN0->getChain(), 4851 LN0->getBasePtr(), LN0->getPointerInfo(), 4852 EVT, 4853 LN0->isVolatile(), LN0->isNonTemporal(), 4854 LN0->getAlignment()); 4855 CombineTo(N, ExtLoad); 4856 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4857 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4858 } 4859 4860 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 4861 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 4862 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 4863 N0.getOperand(1), false); 4864 if (BSwap.getNode() != 0) 4865 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4866 BSwap, N1); 4867 } 4868 4869 return SDValue(); 4870} 4871 4872SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4873 SDValue N0 = N->getOperand(0); 4874 EVT VT = N->getValueType(0); 4875 4876 // noop truncate 4877 if (N0.getValueType() == N->getValueType(0)) 4878 return N0; 4879 // fold (truncate c1) -> c1 4880 if (isa<ConstantSDNode>(N0)) 4881 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4882 // fold (truncate (truncate x)) -> (truncate x) 4883 if (N0.getOpcode() == ISD::TRUNCATE) 4884 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4885 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4886 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4887 N0.getOpcode() == ISD::SIGN_EXTEND || 4888 N0.getOpcode() == ISD::ANY_EXTEND) { 4889 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4890 // if the source is smaller than the dest, we still need an extend 4891 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4892 N0.getOperand(0)); 4893 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4894 // if the source is larger than the dest, than we just need the truncate 4895 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4896 else 4897 // if the source and dest are the same type, we can drop both the extend 4898 // and the truncate. 4899 return N0.getOperand(0); 4900 } 4901 4902 // See if we can simplify the input to this truncate through knowledge that 4903 // only the low bits are being used. 4904 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4905 // Currently we only perform this optimization on scalars because vectors 4906 // may have different active low bits. 4907 if (!VT.isVector()) { 4908 SDValue Shorter = 4909 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4910 VT.getSizeInBits())); 4911 if (Shorter.getNode()) 4912 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4913 } 4914 // fold (truncate (load x)) -> (smaller load x) 4915 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4916 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4917 SDValue Reduced = ReduceLoadWidth(N); 4918 if (Reduced.getNode()) 4919 return Reduced; 4920 } 4921 4922 // Simplify the operands using demanded-bits information. 4923 if (!VT.isVector() && 4924 SimplifyDemandedBits(SDValue(N, 0))) 4925 return SDValue(N, 0); 4926 4927 return SDValue(); 4928} 4929 4930static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4931 SDValue Elt = N->getOperand(i); 4932 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4933 return Elt.getNode(); 4934 return Elt.getOperand(Elt.getResNo()).getNode(); 4935} 4936 4937/// CombineConsecutiveLoads - build_pair (load, load) -> load 4938/// if load locations are consecutive. 4939SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4940 assert(N->getOpcode() == ISD::BUILD_PAIR); 4941 4942 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4943 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4944 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4945 LD1->getPointerInfo().getAddrSpace() != 4946 LD2->getPointerInfo().getAddrSpace()) 4947 return SDValue(); 4948 EVT LD1VT = LD1->getValueType(0); 4949 4950 if (ISD::isNON_EXTLoad(LD2) && 4951 LD2->hasOneUse() && 4952 // If both are volatile this would reduce the number of volatile loads. 4953 // If one is volatile it might be ok, but play conservative and bail out. 4954 !LD1->isVolatile() && 4955 !LD2->isVolatile() && 4956 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4957 unsigned Align = LD1->getAlignment(); 4958 unsigned NewAlign = TLI.getTargetData()-> 4959 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4960 4961 if (NewAlign <= Align && 4962 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4963 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4964 LD1->getBasePtr(), LD1->getPointerInfo(), 4965 false, false, Align); 4966 } 4967 4968 return SDValue(); 4969} 4970 4971SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4972 SDValue N0 = N->getOperand(0); 4973 EVT VT = N->getValueType(0); 4974 4975 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4976 // Only do this before legalize, since afterward the target may be depending 4977 // on the bitconvert. 4978 // First check to see if this is all constant. 4979 if (!LegalTypes && 4980 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4981 VT.isVector()) { 4982 bool isSimple = true; 4983 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4984 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4985 N0.getOperand(i).getOpcode() != ISD::Constant && 4986 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4987 isSimple = false; 4988 break; 4989 } 4990 4991 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4992 assert(!DestEltVT.isVector() && 4993 "Element type of vector ValueType must not be vector!"); 4994 if (isSimple) 4995 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4996 } 4997 4998 // If the input is a constant, let getNode fold it. 4999 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5000 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5001 if (Res.getNode() != N) { 5002 if (!LegalOperations || 5003 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5004 return Res; 5005 5006 // Folding it resulted in an illegal node, and it's too late to 5007 // do that. Clean up the old node and forego the transformation. 5008 // Ideally this won't happen very often, because instcombine 5009 // and the earlier dagcombine runs (where illegal nodes are 5010 // permitted) should have folded most of them already. 5011 DAG.DeleteNode(Res.getNode()); 5012 } 5013 } 5014 5015 // (conv (conv x, t1), t2) -> (conv x, t2) 5016 if (N0.getOpcode() == ISD::BITCAST) 5017 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5018 N0.getOperand(0)); 5019 5020 // fold (conv (load x)) -> (load (conv*)x) 5021 // If the resultant load doesn't need a higher alignment than the original! 5022 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5023 // Do not change the width of a volatile load. 5024 !cast<LoadSDNode>(N0)->isVolatile() && 5025 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5026 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5027 unsigned Align = TLI.getTargetData()-> 5028 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5029 unsigned OrigAlign = LN0->getAlignment(); 5030 5031 if (Align <= OrigAlign) { 5032 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5033 LN0->getBasePtr(), LN0->getPointerInfo(), 5034 LN0->isVolatile(), LN0->isNonTemporal(), 5035 OrigAlign); 5036 AddToWorkList(N); 5037 CombineTo(N0.getNode(), 5038 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5039 N0.getValueType(), Load), 5040 Load.getValue(1)); 5041 return Load; 5042 } 5043 } 5044 5045 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5046 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5047 // This often reduces constant pool loads. 5048 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 5049 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5050 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5051 N0.getOperand(0)); 5052 AddToWorkList(NewConv.getNode()); 5053 5054 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5055 if (N0.getOpcode() == ISD::FNEG) 5056 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5057 NewConv, DAG.getConstant(SignBit, VT)); 5058 assert(N0.getOpcode() == ISD::FABS); 5059 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5060 NewConv, DAG.getConstant(~SignBit, VT)); 5061 } 5062 5063 // fold (bitconvert (fcopysign cst, x)) -> 5064 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5065 // Note that we don't handle (copysign x, cst) because this can always be 5066 // folded to an fneg or fabs. 5067 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5068 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5069 VT.isInteger() && !VT.isVector()) { 5070 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5071 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5072 if (isTypeLegal(IntXVT)) { 5073 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5074 IntXVT, N0.getOperand(1)); 5075 AddToWorkList(X.getNode()); 5076 5077 // If X has a different width than the result/lhs, sext it or truncate it. 5078 unsigned VTWidth = VT.getSizeInBits(); 5079 if (OrigXWidth < VTWidth) { 5080 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5081 AddToWorkList(X.getNode()); 5082 } else if (OrigXWidth > VTWidth) { 5083 // To get the sign bit in the right place, we have to shift it right 5084 // before truncating. 5085 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5086 X.getValueType(), X, 5087 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5088 AddToWorkList(X.getNode()); 5089 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5090 AddToWorkList(X.getNode()); 5091 } 5092 5093 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5094 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5095 X, DAG.getConstant(SignBit, VT)); 5096 AddToWorkList(X.getNode()); 5097 5098 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5099 VT, N0.getOperand(0)); 5100 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5101 Cst, DAG.getConstant(~SignBit, VT)); 5102 AddToWorkList(Cst.getNode()); 5103 5104 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5105 } 5106 } 5107 5108 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5109 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5110 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5111 if (CombineLD.getNode()) 5112 return CombineLD; 5113 } 5114 5115 return SDValue(); 5116} 5117 5118SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5119 EVT VT = N->getValueType(0); 5120 return CombineConsecutiveLoads(N, VT); 5121} 5122 5123/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5124/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5125/// destination element value type. 5126SDValue DAGCombiner:: 5127ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5128 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5129 5130 // If this is already the right type, we're done. 5131 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5132 5133 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5134 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5135 5136 // If this is a conversion of N elements of one type to N elements of another 5137 // type, convert each element. This handles FP<->INT cases. 5138 if (SrcBitSize == DstBitSize) { 5139 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5140 BV->getValueType(0).getVectorNumElements()); 5141 5142 // Due to the FP element handling below calling this routine recursively, 5143 // we can end up with a scalar-to-vector node here. 5144 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5145 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5146 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5147 DstEltVT, BV->getOperand(0))); 5148 5149 SmallVector<SDValue, 8> Ops; 5150 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5151 SDValue Op = BV->getOperand(i); 5152 // If the vector element type is not legal, the BUILD_VECTOR operands 5153 // are promoted and implicitly truncated. Make that explicit here. 5154 if (Op.getValueType() != SrcEltVT) 5155 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5156 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5157 DstEltVT, Op)); 5158 AddToWorkList(Ops.back().getNode()); 5159 } 5160 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5161 &Ops[0], Ops.size()); 5162 } 5163 5164 // Otherwise, we're growing or shrinking the elements. To avoid having to 5165 // handle annoying details of growing/shrinking FP values, we convert them to 5166 // int first. 5167 if (SrcEltVT.isFloatingPoint()) { 5168 // Convert the input float vector to a int vector where the elements are the 5169 // same sizes. 5170 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5171 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5172 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5173 SrcEltVT = IntVT; 5174 } 5175 5176 // Now we know the input is an integer vector. If the output is a FP type, 5177 // convert to integer first, then to FP of the right size. 5178 if (DstEltVT.isFloatingPoint()) { 5179 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5180 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5181 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5182 5183 // Next, convert to FP elements of the same size. 5184 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5185 } 5186 5187 // Okay, we know the src/dst types are both integers of differing types. 5188 // Handling growing first. 5189 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5190 if (SrcBitSize < DstBitSize) { 5191 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5192 5193 SmallVector<SDValue, 8> Ops; 5194 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5195 i += NumInputsPerOutput) { 5196 bool isLE = TLI.isLittleEndian(); 5197 APInt NewBits = APInt(DstBitSize, 0); 5198 bool EltIsUndef = true; 5199 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5200 // Shift the previously computed bits over. 5201 NewBits <<= SrcBitSize; 5202 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5203 if (Op.getOpcode() == ISD::UNDEF) continue; 5204 EltIsUndef = false; 5205 5206 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5207 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5208 } 5209 5210 if (EltIsUndef) 5211 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5212 else 5213 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5214 } 5215 5216 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5217 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5218 &Ops[0], Ops.size()); 5219 } 5220 5221 // Finally, this must be the case where we are shrinking elements: each input 5222 // turns into multiple outputs. 5223 bool isS2V = ISD::isScalarToVector(BV); 5224 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5225 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5226 NumOutputsPerInput*BV->getNumOperands()); 5227 SmallVector<SDValue, 8> Ops; 5228 5229 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5230 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5231 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5232 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5233 continue; 5234 } 5235 5236 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5237 getAPIntValue().zextOrTrunc(SrcBitSize); 5238 5239 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5240 APInt ThisVal = OpVal.trunc(DstBitSize); 5241 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5242 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5243 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5244 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5245 Ops[0]); 5246 OpVal = OpVal.lshr(DstBitSize); 5247 } 5248 5249 // For big endian targets, swap the order of the pieces of each element. 5250 if (TLI.isBigEndian()) 5251 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5252 } 5253 5254 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5255 &Ops[0], Ops.size()); 5256} 5257 5258SDValue DAGCombiner::visitFADD(SDNode *N) { 5259 SDValue N0 = N->getOperand(0); 5260 SDValue N1 = N->getOperand(1); 5261 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5262 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5263 EVT VT = N->getValueType(0); 5264 5265 // fold vector ops 5266 if (VT.isVector()) { 5267 SDValue FoldedVOp = SimplifyVBinOp(N); 5268 if (FoldedVOp.getNode()) return FoldedVOp; 5269 } 5270 5271 // fold (fadd c1, c2) -> (fadd c1, c2) 5272 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5273 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5274 // canonicalize constant to RHS 5275 if (N0CFP && !N1CFP) 5276 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5277 // fold (fadd A, 0) -> A 5278 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5279 return N0; 5280 // fold (fadd A, (fneg B)) -> (fsub A, B) 5281 if (isNegatibleForFree(N1, LegalOperations) == 2) 5282 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5283 GetNegatedExpression(N1, DAG, LegalOperations)); 5284 // fold (fadd (fneg A), B) -> (fsub B, A) 5285 if (isNegatibleForFree(N0, LegalOperations) == 2) 5286 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5287 GetNegatedExpression(N0, DAG, LegalOperations)); 5288 5289 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5290 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 5291 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5292 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5293 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5294 N0.getOperand(1), N1)); 5295 5296 return SDValue(); 5297} 5298 5299SDValue DAGCombiner::visitFSUB(SDNode *N) { 5300 SDValue N0 = N->getOperand(0); 5301 SDValue N1 = N->getOperand(1); 5302 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5303 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5304 EVT VT = N->getValueType(0); 5305 5306 // fold vector ops 5307 if (VT.isVector()) { 5308 SDValue FoldedVOp = SimplifyVBinOp(N); 5309 if (FoldedVOp.getNode()) return FoldedVOp; 5310 } 5311 5312 // fold (fsub c1, c2) -> c1-c2 5313 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5314 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5315 // fold (fsub A, 0) -> A 5316 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5317 return N0; 5318 // fold (fsub 0, B) -> -B 5319 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 5320 if (isNegatibleForFree(N1, LegalOperations)) 5321 return GetNegatedExpression(N1, DAG, LegalOperations); 5322 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5323 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5324 } 5325 // fold (fsub A, (fneg B)) -> (fadd A, B) 5326 if (isNegatibleForFree(N1, LegalOperations)) 5327 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5328 GetNegatedExpression(N1, DAG, LegalOperations)); 5329 5330 return SDValue(); 5331} 5332 5333SDValue DAGCombiner::visitFMUL(SDNode *N) { 5334 SDValue N0 = N->getOperand(0); 5335 SDValue N1 = N->getOperand(1); 5336 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5337 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5338 EVT VT = N->getValueType(0); 5339 5340 // fold vector ops 5341 if (VT.isVector()) { 5342 SDValue FoldedVOp = SimplifyVBinOp(N); 5343 if (FoldedVOp.getNode()) return FoldedVOp; 5344 } 5345 5346 // fold (fmul c1, c2) -> c1*c2 5347 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5348 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5349 // canonicalize constant to RHS 5350 if (N0CFP && !N1CFP) 5351 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5352 // fold (fmul A, 0) -> 0 5353 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5354 return N1; 5355 // fold (fmul A, 0) -> 0, vector edition. 5356 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5357 return N1; 5358 // fold (fmul X, 2.0) -> (fadd X, X) 5359 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5360 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5361 // fold (fmul X, -1.0) -> (fneg X) 5362 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5363 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5364 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5365 5366 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5367 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5368 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5369 // Both can be negated for free, check to see if at least one is cheaper 5370 // negated. 5371 if (LHSNeg == 2 || RHSNeg == 2) 5372 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5373 GetNegatedExpression(N0, DAG, LegalOperations), 5374 GetNegatedExpression(N1, DAG, LegalOperations)); 5375 } 5376 } 5377 5378 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5379 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5380 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5381 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5382 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5383 N0.getOperand(1), N1)); 5384 5385 return SDValue(); 5386} 5387 5388SDValue DAGCombiner::visitFDIV(SDNode *N) { 5389 SDValue N0 = N->getOperand(0); 5390 SDValue N1 = N->getOperand(1); 5391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5392 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5393 EVT VT = N->getValueType(0); 5394 5395 // fold vector ops 5396 if (VT.isVector()) { 5397 SDValue FoldedVOp = SimplifyVBinOp(N); 5398 if (FoldedVOp.getNode()) return FoldedVOp; 5399 } 5400 5401 // fold (fdiv c1, c2) -> c1/c2 5402 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5403 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5404 5405 5406 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5407 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5408 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5409 // Both can be negated for free, check to see if at least one is cheaper 5410 // negated. 5411 if (LHSNeg == 2 || RHSNeg == 2) 5412 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5413 GetNegatedExpression(N0, DAG, LegalOperations), 5414 GetNegatedExpression(N1, DAG, LegalOperations)); 5415 } 5416 } 5417 5418 return SDValue(); 5419} 5420 5421SDValue DAGCombiner::visitFREM(SDNode *N) { 5422 SDValue N0 = N->getOperand(0); 5423 SDValue N1 = N->getOperand(1); 5424 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5425 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5426 EVT VT = N->getValueType(0); 5427 5428 // fold (frem c1, c2) -> fmod(c1,c2) 5429 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5430 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5431 5432 return SDValue(); 5433} 5434 5435SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5436 SDValue N0 = N->getOperand(0); 5437 SDValue N1 = N->getOperand(1); 5438 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5439 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5440 EVT VT = N->getValueType(0); 5441 5442 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5443 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5444 5445 if (N1CFP) { 5446 const APFloat& V = N1CFP->getValueAPF(); 5447 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5448 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5449 if (!V.isNegative()) { 5450 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5451 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5452 } else { 5453 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5454 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5455 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5456 } 5457 } 5458 5459 // copysign(fabs(x), y) -> copysign(x, y) 5460 // copysign(fneg(x), y) -> copysign(x, y) 5461 // copysign(copysign(x,z), y) -> copysign(x, y) 5462 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5463 N0.getOpcode() == ISD::FCOPYSIGN) 5464 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5465 N0.getOperand(0), N1); 5466 5467 // copysign(x, abs(y)) -> abs(x) 5468 if (N1.getOpcode() == ISD::FABS) 5469 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5470 5471 // copysign(x, copysign(y,z)) -> copysign(x, z) 5472 if (N1.getOpcode() == ISD::FCOPYSIGN) 5473 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5474 N0, N1.getOperand(1)); 5475 5476 // copysign(x, fp_extend(y)) -> copysign(x, y) 5477 // copysign(x, fp_round(y)) -> copysign(x, y) 5478 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5479 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5480 N0, N1.getOperand(0)); 5481 5482 return SDValue(); 5483} 5484 5485SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5486 SDValue N0 = N->getOperand(0); 5487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5488 EVT VT = N->getValueType(0); 5489 EVT OpVT = N0.getValueType(); 5490 5491 // fold (sint_to_fp c1) -> c1fp 5492 if (N0C && OpVT != MVT::ppcf128 && 5493 // ...but only if the target supports immediate floating-point values 5494 (Level == llvm::Unrestricted || 5495 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5496 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5497 5498 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5499 // but UINT_TO_FP is legal on this target, try to convert. 5500 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5501 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5502 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5503 if (DAG.SignBitIsZero(N0)) 5504 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5505 } 5506 5507 return SDValue(); 5508} 5509 5510SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5511 SDValue N0 = N->getOperand(0); 5512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5513 EVT VT = N->getValueType(0); 5514 EVT OpVT = N0.getValueType(); 5515 5516 // fold (uint_to_fp c1) -> c1fp 5517 if (N0C && OpVT != MVT::ppcf128 && 5518 // ...but only if the target supports immediate floating-point values 5519 (Level == llvm::Unrestricted || 5520 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5521 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5522 5523 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5524 // but SINT_TO_FP is legal on this target, try to convert. 5525 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5526 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5527 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5528 if (DAG.SignBitIsZero(N0)) 5529 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5530 } 5531 5532 return SDValue(); 5533} 5534 5535SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5536 SDValue N0 = N->getOperand(0); 5537 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5538 EVT VT = N->getValueType(0); 5539 5540 // fold (fp_to_sint c1fp) -> c1 5541 if (N0CFP) 5542 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5543 5544 return SDValue(); 5545} 5546 5547SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5548 SDValue N0 = N->getOperand(0); 5549 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5550 EVT VT = N->getValueType(0); 5551 5552 // fold (fp_to_uint c1fp) -> c1 5553 if (N0CFP && VT != MVT::ppcf128) 5554 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5555 5556 return SDValue(); 5557} 5558 5559SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5560 SDValue N0 = N->getOperand(0); 5561 SDValue N1 = N->getOperand(1); 5562 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5563 EVT VT = N->getValueType(0); 5564 5565 // fold (fp_round c1fp) -> c1fp 5566 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5567 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5568 5569 // fold (fp_round (fp_extend x)) -> x 5570 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5571 return N0.getOperand(0); 5572 5573 // fold (fp_round (fp_round x)) -> (fp_round x) 5574 if (N0.getOpcode() == ISD::FP_ROUND) { 5575 // This is a value preserving truncation if both round's are. 5576 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5577 N0.getNode()->getConstantOperandVal(1) == 1; 5578 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5579 DAG.getIntPtrConstant(IsTrunc)); 5580 } 5581 5582 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5583 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5584 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5585 N0.getOperand(0), N1); 5586 AddToWorkList(Tmp.getNode()); 5587 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5588 Tmp, N0.getOperand(1)); 5589 } 5590 5591 return SDValue(); 5592} 5593 5594SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5595 SDValue N0 = N->getOperand(0); 5596 EVT VT = N->getValueType(0); 5597 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5598 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5599 5600 // fold (fp_round_inreg c1fp) -> c1fp 5601 if (N0CFP && isTypeLegal(EVT)) { 5602 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5603 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5604 } 5605 5606 return SDValue(); 5607} 5608 5609SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5610 SDValue N0 = N->getOperand(0); 5611 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5612 EVT VT = N->getValueType(0); 5613 5614 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5615 if (N->hasOneUse() && 5616 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5617 return SDValue(); 5618 5619 // fold (fp_extend c1fp) -> c1fp 5620 if (N0CFP && VT != MVT::ppcf128) 5621 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5622 5623 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5624 // value of X. 5625 if (N0.getOpcode() == ISD::FP_ROUND 5626 && N0.getNode()->getConstantOperandVal(1) == 1) { 5627 SDValue In = N0.getOperand(0); 5628 if (In.getValueType() == VT) return In; 5629 if (VT.bitsLT(In.getValueType())) 5630 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5631 In, N0.getOperand(1)); 5632 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5633 } 5634 5635 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5636 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5637 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5638 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5639 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5640 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5641 LN0->getChain(), 5642 LN0->getBasePtr(), LN0->getPointerInfo(), 5643 N0.getValueType(), 5644 LN0->isVolatile(), LN0->isNonTemporal(), 5645 LN0->getAlignment()); 5646 CombineTo(N, ExtLoad); 5647 CombineTo(N0.getNode(), 5648 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5649 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5650 ExtLoad.getValue(1)); 5651 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5652 } 5653 5654 return SDValue(); 5655} 5656 5657SDValue DAGCombiner::visitFNEG(SDNode *N) { 5658 SDValue N0 = N->getOperand(0); 5659 EVT VT = N->getValueType(0); 5660 5661 if (isNegatibleForFree(N0, LegalOperations)) 5662 return GetNegatedExpression(N0, DAG, LegalOperations); 5663 5664 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5665 // constant pool values. 5666 if (N0.getOpcode() == ISD::BITCAST && 5667 !VT.isVector() && 5668 N0.getNode()->hasOneUse() && 5669 N0.getOperand(0).getValueType().isInteger()) { 5670 SDValue Int = N0.getOperand(0); 5671 EVT IntVT = Int.getValueType(); 5672 if (IntVT.isInteger() && !IntVT.isVector()) { 5673 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5674 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5675 AddToWorkList(Int.getNode()); 5676 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5677 VT, Int); 5678 } 5679 } 5680 5681 return SDValue(); 5682} 5683 5684SDValue DAGCombiner::visitFABS(SDNode *N) { 5685 SDValue N0 = N->getOperand(0); 5686 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5687 EVT VT = N->getValueType(0); 5688 5689 // fold (fabs c1) -> fabs(c1) 5690 if (N0CFP && VT != MVT::ppcf128) 5691 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5692 // fold (fabs (fabs x)) -> (fabs x) 5693 if (N0.getOpcode() == ISD::FABS) 5694 return N->getOperand(0); 5695 // fold (fabs (fneg x)) -> (fabs x) 5696 // fold (fabs (fcopysign x, y)) -> (fabs x) 5697 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5698 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5699 5700 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5701 // constant pool values. 5702 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5703 N0.getOperand(0).getValueType().isInteger() && 5704 !N0.getOperand(0).getValueType().isVector()) { 5705 SDValue Int = N0.getOperand(0); 5706 EVT IntVT = Int.getValueType(); 5707 if (IntVT.isInteger() && !IntVT.isVector()) { 5708 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5709 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5710 AddToWorkList(Int.getNode()); 5711 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5712 N->getValueType(0), Int); 5713 } 5714 } 5715 5716 return SDValue(); 5717} 5718 5719SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5720 SDValue Chain = N->getOperand(0); 5721 SDValue N1 = N->getOperand(1); 5722 SDValue N2 = N->getOperand(2); 5723 5724 // If N is a constant we could fold this into a fallthrough or unconditional 5725 // branch. However that doesn't happen very often in normal code, because 5726 // Instcombine/SimplifyCFG should have handled the available opportunities. 5727 // If we did this folding here, it would be necessary to update the 5728 // MachineBasicBlock CFG, which is awkward. 5729 5730 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5731 // on the target. 5732 if (N1.getOpcode() == ISD::SETCC && 5733 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5734 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5735 Chain, N1.getOperand(2), 5736 N1.getOperand(0), N1.getOperand(1), N2); 5737 } 5738 5739 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5740 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5741 (N1.getOperand(0).hasOneUse() && 5742 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5743 SDNode *Trunc = 0; 5744 if (N1.getOpcode() == ISD::TRUNCATE) { 5745 // Look pass the truncate. 5746 Trunc = N1.getNode(); 5747 N1 = N1.getOperand(0); 5748 } 5749 5750 // Match this pattern so that we can generate simpler code: 5751 // 5752 // %a = ... 5753 // %b = and i32 %a, 2 5754 // %c = srl i32 %b, 1 5755 // brcond i32 %c ... 5756 // 5757 // into 5758 // 5759 // %a = ... 5760 // %b = and i32 %a, 2 5761 // %c = setcc eq %b, 0 5762 // brcond %c ... 5763 // 5764 // This applies only when the AND constant value has one bit set and the 5765 // SRL constant is equal to the log2 of the AND constant. The back-end is 5766 // smart enough to convert the result into a TEST/JMP sequence. 5767 SDValue Op0 = N1.getOperand(0); 5768 SDValue Op1 = N1.getOperand(1); 5769 5770 if (Op0.getOpcode() == ISD::AND && 5771 Op1.getOpcode() == ISD::Constant) { 5772 SDValue AndOp1 = Op0.getOperand(1); 5773 5774 if (AndOp1.getOpcode() == ISD::Constant) { 5775 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5776 5777 if (AndConst.isPowerOf2() && 5778 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5779 SDValue SetCC = 5780 DAG.getSetCC(N->getDebugLoc(), 5781 TLI.getSetCCResultType(Op0.getValueType()), 5782 Op0, DAG.getConstant(0, Op0.getValueType()), 5783 ISD::SETNE); 5784 5785 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5786 MVT::Other, Chain, SetCC, N2); 5787 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5788 // will convert it back to (X & C1) >> C2. 5789 CombineTo(N, NewBRCond, false); 5790 // Truncate is dead. 5791 if (Trunc) { 5792 removeFromWorkList(Trunc); 5793 DAG.DeleteNode(Trunc); 5794 } 5795 // Replace the uses of SRL with SETCC 5796 WorkListRemover DeadNodes(*this); 5797 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5798 removeFromWorkList(N1.getNode()); 5799 DAG.DeleteNode(N1.getNode()); 5800 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5801 } 5802 } 5803 } 5804 5805 if (Trunc) 5806 // Restore N1 if the above transformation doesn't match. 5807 N1 = N->getOperand(1); 5808 } 5809 5810 // Transform br(xor(x, y)) -> br(x != y) 5811 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5812 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5813 SDNode *TheXor = N1.getNode(); 5814 SDValue Op0 = TheXor->getOperand(0); 5815 SDValue Op1 = TheXor->getOperand(1); 5816 if (Op0.getOpcode() == Op1.getOpcode()) { 5817 // Avoid missing important xor optimizations. 5818 SDValue Tmp = visitXOR(TheXor); 5819 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5820 DEBUG(dbgs() << "\nReplacing.8 "; 5821 TheXor->dump(&DAG); 5822 dbgs() << "\nWith: "; 5823 Tmp.getNode()->dump(&DAG); 5824 dbgs() << '\n'); 5825 WorkListRemover DeadNodes(*this); 5826 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5827 removeFromWorkList(TheXor); 5828 DAG.DeleteNode(TheXor); 5829 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5830 MVT::Other, Chain, Tmp, N2); 5831 } 5832 } 5833 5834 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5835 bool Equal = false; 5836 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5837 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5838 Op0.getOpcode() == ISD::XOR) { 5839 TheXor = Op0.getNode(); 5840 Equal = true; 5841 } 5842 5843 EVT SetCCVT = N1.getValueType(); 5844 if (LegalTypes) 5845 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5846 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5847 SetCCVT, 5848 Op0, Op1, 5849 Equal ? ISD::SETEQ : ISD::SETNE); 5850 // Replace the uses of XOR with SETCC 5851 WorkListRemover DeadNodes(*this); 5852 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5853 removeFromWorkList(N1.getNode()); 5854 DAG.DeleteNode(N1.getNode()); 5855 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5856 MVT::Other, Chain, SetCC, N2); 5857 } 5858 } 5859 5860 return SDValue(); 5861} 5862 5863// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5864// 5865SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5866 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5867 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5868 5869 // If N is a constant we could fold this into a fallthrough or unconditional 5870 // branch. However that doesn't happen very often in normal code, because 5871 // Instcombine/SimplifyCFG should have handled the available opportunities. 5872 // If we did this folding here, it would be necessary to update the 5873 // MachineBasicBlock CFG, which is awkward. 5874 5875 // Use SimplifySetCC to simplify SETCC's. 5876 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5877 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5878 false); 5879 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5880 5881 // fold to a simpler setcc 5882 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5883 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5884 N->getOperand(0), Simp.getOperand(2), 5885 Simp.getOperand(0), Simp.getOperand(1), 5886 N->getOperand(4)); 5887 5888 return SDValue(); 5889} 5890 5891/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5892/// pre-indexed load / store when the base pointer is an add or subtract 5893/// and it has other uses besides the load / store. After the 5894/// transformation, the new indexed load / store has effectively folded 5895/// the add / subtract in and all of its other uses are redirected to the 5896/// new load / store. 5897bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5898 if (!LegalOperations) 5899 return false; 5900 5901 bool isLoad = true; 5902 SDValue Ptr; 5903 EVT VT; 5904 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5905 if (LD->isIndexed()) 5906 return false; 5907 VT = LD->getMemoryVT(); 5908 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5909 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5910 return false; 5911 Ptr = LD->getBasePtr(); 5912 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5913 if (ST->isIndexed()) 5914 return false; 5915 VT = ST->getMemoryVT(); 5916 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5917 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5918 return false; 5919 Ptr = ST->getBasePtr(); 5920 isLoad = false; 5921 } else { 5922 return false; 5923 } 5924 5925 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5926 // out. There is no reason to make this a preinc/predec. 5927 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5928 Ptr.getNode()->hasOneUse()) 5929 return false; 5930 5931 // Ask the target to do addressing mode selection. 5932 SDValue BasePtr; 5933 SDValue Offset; 5934 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5935 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5936 return false; 5937 // Don't create a indexed load / store with zero offset. 5938 if (isa<ConstantSDNode>(Offset) && 5939 cast<ConstantSDNode>(Offset)->isNullValue()) 5940 return false; 5941 5942 // Try turning it into a pre-indexed load / store except when: 5943 // 1) The new base ptr is a frame index. 5944 // 2) If N is a store and the new base ptr is either the same as or is a 5945 // predecessor of the value being stored. 5946 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5947 // that would create a cycle. 5948 // 4) All uses are load / store ops that use it as old base ptr. 5949 5950 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5951 // (plus the implicit offset) to a register to preinc anyway. 5952 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5953 return false; 5954 5955 // Check #2. 5956 if (!isLoad) { 5957 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5958 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5959 return false; 5960 } 5961 5962 // Now check for #3 and #4. 5963 bool RealUse = false; 5964 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5965 E = Ptr.getNode()->use_end(); I != E; ++I) { 5966 SDNode *Use = *I; 5967 if (Use == N) 5968 continue; 5969 if (Use->isPredecessorOf(N)) 5970 return false; 5971 5972 if (!((Use->getOpcode() == ISD::LOAD && 5973 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5974 (Use->getOpcode() == ISD::STORE && 5975 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5976 RealUse = true; 5977 } 5978 5979 if (!RealUse) 5980 return false; 5981 5982 SDValue Result; 5983 if (isLoad) 5984 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5985 BasePtr, Offset, AM); 5986 else 5987 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5988 BasePtr, Offset, AM); 5989 ++PreIndexedNodes; 5990 ++NodesCombined; 5991 DEBUG(dbgs() << "\nReplacing.4 "; 5992 N->dump(&DAG); 5993 dbgs() << "\nWith: "; 5994 Result.getNode()->dump(&DAG); 5995 dbgs() << '\n'); 5996 WorkListRemover DeadNodes(*this); 5997 if (isLoad) { 5998 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5999 &DeadNodes); 6000 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6001 &DeadNodes); 6002 } else { 6003 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6004 &DeadNodes); 6005 } 6006 6007 // Finally, since the node is now dead, remove it from the graph. 6008 DAG.DeleteNode(N); 6009 6010 // Replace the uses of Ptr with uses of the updated base value. 6011 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6012 &DeadNodes); 6013 removeFromWorkList(Ptr.getNode()); 6014 DAG.DeleteNode(Ptr.getNode()); 6015 6016 return true; 6017} 6018 6019/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6020/// add / sub of the base pointer node into a post-indexed load / store. 6021/// The transformation folded the add / subtract into the new indexed 6022/// load / store effectively and all of its uses are redirected to the 6023/// new load / store. 6024bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6025 if (!LegalOperations) 6026 return false; 6027 6028 bool isLoad = true; 6029 SDValue Ptr; 6030 EVT VT; 6031 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6032 if (LD->isIndexed()) 6033 return false; 6034 VT = LD->getMemoryVT(); 6035 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6036 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6037 return false; 6038 Ptr = LD->getBasePtr(); 6039 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6040 if (ST->isIndexed()) 6041 return false; 6042 VT = ST->getMemoryVT(); 6043 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6044 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6045 return false; 6046 Ptr = ST->getBasePtr(); 6047 isLoad = false; 6048 } else { 6049 return false; 6050 } 6051 6052 if (Ptr.getNode()->hasOneUse()) 6053 return false; 6054 6055 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6056 E = Ptr.getNode()->use_end(); I != E; ++I) { 6057 SDNode *Op = *I; 6058 if (Op == N || 6059 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6060 continue; 6061 6062 SDValue BasePtr; 6063 SDValue Offset; 6064 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6065 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6066 // Don't create a indexed load / store with zero offset. 6067 if (isa<ConstantSDNode>(Offset) && 6068 cast<ConstantSDNode>(Offset)->isNullValue()) 6069 continue; 6070 6071 // Try turning it into a post-indexed load / store except when 6072 // 1) All uses are load / store ops that use it as base ptr. 6073 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6074 // nor a successor of N. Otherwise, if Op is folded that would 6075 // create a cycle. 6076 6077 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6078 continue; 6079 6080 // Check for #1. 6081 bool TryNext = false; 6082 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6083 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6084 SDNode *Use = *II; 6085 if (Use == Ptr.getNode()) 6086 continue; 6087 6088 // If all the uses are load / store addresses, then don't do the 6089 // transformation. 6090 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6091 bool RealUse = false; 6092 for (SDNode::use_iterator III = Use->use_begin(), 6093 EEE = Use->use_end(); III != EEE; ++III) { 6094 SDNode *UseUse = *III; 6095 if (!((UseUse->getOpcode() == ISD::LOAD && 6096 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 6097 (UseUse->getOpcode() == ISD::STORE && 6098 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 6099 RealUse = true; 6100 } 6101 6102 if (!RealUse) { 6103 TryNext = true; 6104 break; 6105 } 6106 } 6107 } 6108 6109 if (TryNext) 6110 continue; 6111 6112 // Check for #2 6113 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6114 SDValue Result = isLoad 6115 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6116 BasePtr, Offset, AM) 6117 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6118 BasePtr, Offset, AM); 6119 ++PostIndexedNodes; 6120 ++NodesCombined; 6121 DEBUG(dbgs() << "\nReplacing.5 "; 6122 N->dump(&DAG); 6123 dbgs() << "\nWith: "; 6124 Result.getNode()->dump(&DAG); 6125 dbgs() << '\n'); 6126 WorkListRemover DeadNodes(*this); 6127 if (isLoad) { 6128 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6129 &DeadNodes); 6130 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6131 &DeadNodes); 6132 } else { 6133 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6134 &DeadNodes); 6135 } 6136 6137 // Finally, since the node is now dead, remove it from the graph. 6138 DAG.DeleteNode(N); 6139 6140 // Replace the uses of Use with uses of the updated base value. 6141 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6142 Result.getValue(isLoad ? 1 : 0), 6143 &DeadNodes); 6144 removeFromWorkList(Op); 6145 DAG.DeleteNode(Op); 6146 return true; 6147 } 6148 } 6149 } 6150 6151 return false; 6152} 6153 6154SDValue DAGCombiner::visitLOAD(SDNode *N) { 6155 LoadSDNode *LD = cast<LoadSDNode>(N); 6156 SDValue Chain = LD->getChain(); 6157 SDValue Ptr = LD->getBasePtr(); 6158 6159 // If load is not volatile and there are no uses of the loaded value (and 6160 // the updated indexed value in case of indexed loads), change uses of the 6161 // chain value into uses of the chain input (i.e. delete the dead load). 6162 if (!LD->isVolatile()) { 6163 if (N->getValueType(1) == MVT::Other) { 6164 // Unindexed loads. 6165 if (N->hasNUsesOfValue(0, 0)) { 6166 // It's not safe to use the two value CombineTo variant here. e.g. 6167 // v1, chain2 = load chain1, loc 6168 // v2, chain3 = load chain2, loc 6169 // v3 = add v2, c 6170 // Now we replace use of chain2 with chain1. This makes the second load 6171 // isomorphic to the one we are deleting, and thus makes this load live. 6172 DEBUG(dbgs() << "\nReplacing.6 "; 6173 N->dump(&DAG); 6174 dbgs() << "\nWith chain: "; 6175 Chain.getNode()->dump(&DAG); 6176 dbgs() << "\n"); 6177 WorkListRemover DeadNodes(*this); 6178 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6179 6180 if (N->use_empty()) { 6181 removeFromWorkList(N); 6182 DAG.DeleteNode(N); 6183 } 6184 6185 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6186 } 6187 } else { 6188 // Indexed loads. 6189 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6190 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 6191 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6192 DEBUG(dbgs() << "\nReplacing.7 "; 6193 N->dump(&DAG); 6194 dbgs() << "\nWith: "; 6195 Undef.getNode()->dump(&DAG); 6196 dbgs() << " and 2 other values\n"); 6197 WorkListRemover DeadNodes(*this); 6198 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6199 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6200 DAG.getUNDEF(N->getValueType(1)), 6201 &DeadNodes); 6202 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6203 removeFromWorkList(N); 6204 DAG.DeleteNode(N); 6205 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6206 } 6207 } 6208 } 6209 6210 // If this load is directly stored, replace the load value with the stored 6211 // value. 6212 // TODO: Handle store large -> read small portion. 6213 // TODO: Handle TRUNCSTORE/LOADEXT 6214 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6215 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6216 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6217 if (PrevST->getBasePtr() == Ptr && 6218 PrevST->getValue().getValueType() == N->getValueType(0)) 6219 return CombineTo(N, Chain.getOperand(1), Chain); 6220 } 6221 } 6222 6223 // Try to infer better alignment information than the load already has. 6224 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6225 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6226 if (Align > LD->getAlignment()) 6227 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6228 LD->getValueType(0), 6229 Chain, Ptr, LD->getPointerInfo(), 6230 LD->getMemoryVT(), 6231 LD->isVolatile(), LD->isNonTemporal(), Align); 6232 } 6233 } 6234 6235 if (CombinerAA) { 6236 // Walk up chain skipping non-aliasing memory nodes. 6237 SDValue BetterChain = FindBetterChain(N, Chain); 6238 6239 // If there is a better chain. 6240 if (Chain != BetterChain) { 6241 SDValue ReplLoad; 6242 6243 // Replace the chain to void dependency. 6244 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6245 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6246 BetterChain, Ptr, LD->getPointerInfo(), 6247 LD->isVolatile(), LD->isNonTemporal(), 6248 LD->getAlignment()); 6249 } else { 6250 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6251 LD->getValueType(0), 6252 BetterChain, Ptr, LD->getPointerInfo(), 6253 LD->getMemoryVT(), 6254 LD->isVolatile(), 6255 LD->isNonTemporal(), 6256 LD->getAlignment()); 6257 } 6258 6259 // Create token factor to keep old chain connected. 6260 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6261 MVT::Other, Chain, ReplLoad.getValue(1)); 6262 6263 // Make sure the new and old chains are cleaned up. 6264 AddToWorkList(Token.getNode()); 6265 6266 // Replace uses with load result and token factor. Don't add users 6267 // to work list. 6268 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6269 } 6270 } 6271 6272 // Try transforming N to an indexed load. 6273 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6274 return SDValue(N, 0); 6275 6276 return SDValue(); 6277} 6278 6279/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6280/// load is having specific bytes cleared out. If so, return the byte size 6281/// being masked out and the shift amount. 6282static std::pair<unsigned, unsigned> 6283CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6284 std::pair<unsigned, unsigned> Result(0, 0); 6285 6286 // Check for the structure we're looking for. 6287 if (V->getOpcode() != ISD::AND || 6288 !isa<ConstantSDNode>(V->getOperand(1)) || 6289 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6290 return Result; 6291 6292 // Check the chain and pointer. 6293 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6294 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6295 6296 // The store should be chained directly to the load or be an operand of a 6297 // tokenfactor. 6298 if (LD == Chain.getNode()) 6299 ; // ok. 6300 else if (Chain->getOpcode() != ISD::TokenFactor) 6301 return Result; // Fail. 6302 else { 6303 bool isOk = false; 6304 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6305 if (Chain->getOperand(i).getNode() == LD) { 6306 isOk = true; 6307 break; 6308 } 6309 if (!isOk) return Result; 6310 } 6311 6312 // This only handles simple types. 6313 if (V.getValueType() != MVT::i16 && 6314 V.getValueType() != MVT::i32 && 6315 V.getValueType() != MVT::i64) 6316 return Result; 6317 6318 // Check the constant mask. Invert it so that the bits being masked out are 6319 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6320 // follow the sign bit for uniformity. 6321 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6322 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6323 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6324 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6325 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6326 if (NotMaskLZ == 64) return Result; // All zero mask. 6327 6328 // See if we have a continuous run of bits. If so, we have 0*1+0* 6329 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6330 return Result; 6331 6332 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6333 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6334 NotMaskLZ -= 64-V.getValueSizeInBits(); 6335 6336 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6337 switch (MaskedBytes) { 6338 case 1: 6339 case 2: 6340 case 4: break; 6341 default: return Result; // All one mask, or 5-byte mask. 6342 } 6343 6344 // Verify that the first bit starts at a multiple of mask so that the access 6345 // is aligned the same as the access width. 6346 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6347 6348 Result.first = MaskedBytes; 6349 Result.second = NotMaskTZ/8; 6350 return Result; 6351} 6352 6353 6354/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6355/// provides a value as specified by MaskInfo. If so, replace the specified 6356/// store with a narrower store of truncated IVal. 6357static SDNode * 6358ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6359 SDValue IVal, StoreSDNode *St, 6360 DAGCombiner *DC) { 6361 unsigned NumBytes = MaskInfo.first; 6362 unsigned ByteShift = MaskInfo.second; 6363 SelectionDAG &DAG = DC->getDAG(); 6364 6365 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6366 // that uses this. If not, this is not a replacement. 6367 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6368 ByteShift*8, (ByteShift+NumBytes)*8); 6369 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6370 6371 // Check that it is legal on the target to do this. It is legal if the new 6372 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6373 // legalization. 6374 MVT VT = MVT::getIntegerVT(NumBytes*8); 6375 if (!DC->isTypeLegal(VT)) 6376 return 0; 6377 6378 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6379 // shifted by ByteShift and truncated down to NumBytes. 6380 if (ByteShift) 6381 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6382 DAG.getConstant(ByteShift*8, 6383 DC->getShiftAmountTy(IVal.getValueType()))); 6384 6385 // Figure out the offset for the store and the alignment of the access. 6386 unsigned StOffset; 6387 unsigned NewAlign = St->getAlignment(); 6388 6389 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6390 StOffset = ByteShift; 6391 else 6392 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6393 6394 SDValue Ptr = St->getBasePtr(); 6395 if (StOffset) { 6396 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6397 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6398 NewAlign = MinAlign(NewAlign, StOffset); 6399 } 6400 6401 // Truncate down to the new size. 6402 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6403 6404 ++OpsNarrowed; 6405 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6406 St->getPointerInfo().getWithOffset(StOffset), 6407 false, false, NewAlign).getNode(); 6408} 6409 6410 6411/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6412/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6413/// of the loaded bits, try narrowing the load and store if it would end up 6414/// being a win for performance or code size. 6415SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6416 StoreSDNode *ST = cast<StoreSDNode>(N); 6417 if (ST->isVolatile()) 6418 return SDValue(); 6419 6420 SDValue Chain = ST->getChain(); 6421 SDValue Value = ST->getValue(); 6422 SDValue Ptr = ST->getBasePtr(); 6423 EVT VT = Value.getValueType(); 6424 6425 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6426 return SDValue(); 6427 6428 unsigned Opc = Value.getOpcode(); 6429 6430 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6431 // is a byte mask indicating a consecutive number of bytes, check to see if 6432 // Y is known to provide just those bytes. If so, we try to replace the 6433 // load + replace + store sequence with a single (narrower) store, which makes 6434 // the load dead. 6435 if (Opc == ISD::OR) { 6436 std::pair<unsigned, unsigned> MaskedLoad; 6437 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6438 if (MaskedLoad.first) 6439 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6440 Value.getOperand(1), ST,this)) 6441 return SDValue(NewST, 0); 6442 6443 // Or is commutative, so try swapping X and Y. 6444 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6445 if (MaskedLoad.first) 6446 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6447 Value.getOperand(0), ST,this)) 6448 return SDValue(NewST, 0); 6449 } 6450 6451 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6452 Value.getOperand(1).getOpcode() != ISD::Constant) 6453 return SDValue(); 6454 6455 SDValue N0 = Value.getOperand(0); 6456 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6457 Chain == SDValue(N0.getNode(), 1)) { 6458 LoadSDNode *LD = cast<LoadSDNode>(N0); 6459 if (LD->getBasePtr() != Ptr || 6460 LD->getPointerInfo().getAddrSpace() != 6461 ST->getPointerInfo().getAddrSpace()) 6462 return SDValue(); 6463 6464 // Find the type to narrow it the load / op / store to. 6465 SDValue N1 = Value.getOperand(1); 6466 unsigned BitWidth = N1.getValueSizeInBits(); 6467 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6468 if (Opc == ISD::AND) 6469 Imm ^= APInt::getAllOnesValue(BitWidth); 6470 if (Imm == 0 || Imm.isAllOnesValue()) 6471 return SDValue(); 6472 unsigned ShAmt = Imm.countTrailingZeros(); 6473 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6474 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6475 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6476 while (NewBW < BitWidth && 6477 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6478 TLI.isNarrowingProfitable(VT, NewVT))) { 6479 NewBW = NextPowerOf2(NewBW); 6480 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6481 } 6482 if (NewBW >= BitWidth) 6483 return SDValue(); 6484 6485 // If the lsb changed does not start at the type bitwidth boundary, 6486 // start at the previous one. 6487 if (ShAmt % NewBW) 6488 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6489 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6490 if ((Imm & Mask) == Imm) { 6491 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6492 if (Opc == ISD::AND) 6493 NewImm ^= APInt::getAllOnesValue(NewBW); 6494 uint64_t PtrOff = ShAmt / 8; 6495 // For big endian targets, we need to adjust the offset to the pointer to 6496 // load the correct bytes. 6497 if (TLI.isBigEndian()) 6498 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6499 6500 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6501 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6502 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6503 return SDValue(); 6504 6505 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6506 Ptr.getValueType(), Ptr, 6507 DAG.getConstant(PtrOff, Ptr.getValueType())); 6508 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6509 LD->getChain(), NewPtr, 6510 LD->getPointerInfo().getWithOffset(PtrOff), 6511 LD->isVolatile(), LD->isNonTemporal(), 6512 NewAlign); 6513 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6514 DAG.getConstant(NewImm, NewVT)); 6515 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6516 NewVal, NewPtr, 6517 ST->getPointerInfo().getWithOffset(PtrOff), 6518 false, false, NewAlign); 6519 6520 AddToWorkList(NewPtr.getNode()); 6521 AddToWorkList(NewLD.getNode()); 6522 AddToWorkList(NewVal.getNode()); 6523 WorkListRemover DeadNodes(*this); 6524 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6525 &DeadNodes); 6526 ++OpsNarrowed; 6527 return NewST; 6528 } 6529 } 6530 6531 return SDValue(); 6532} 6533 6534/// TransformFPLoadStorePair - For a given floating point load / store pair, 6535/// if the load value isn't used by any other operations, then consider 6536/// transforming the pair to integer load / store operations if the target 6537/// deems the transformation profitable. 6538SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6539 StoreSDNode *ST = cast<StoreSDNode>(N); 6540 SDValue Chain = ST->getChain(); 6541 SDValue Value = ST->getValue(); 6542 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6543 Value.hasOneUse() && 6544 Chain == SDValue(Value.getNode(), 1)) { 6545 LoadSDNode *LD = cast<LoadSDNode>(Value); 6546 EVT VT = LD->getMemoryVT(); 6547 if (!VT.isFloatingPoint() || 6548 VT != ST->getMemoryVT() || 6549 LD->isNonTemporal() || 6550 ST->isNonTemporal() || 6551 LD->getPointerInfo().getAddrSpace() != 0 || 6552 ST->getPointerInfo().getAddrSpace() != 0) 6553 return SDValue(); 6554 6555 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6556 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6557 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6558 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6559 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6560 return SDValue(); 6561 6562 unsigned LDAlign = LD->getAlignment(); 6563 unsigned STAlign = ST->getAlignment(); 6564 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6565 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6566 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6567 return SDValue(); 6568 6569 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6570 LD->getChain(), LD->getBasePtr(), 6571 LD->getPointerInfo(), 6572 false, false, LDAlign); 6573 6574 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6575 NewLD, ST->getBasePtr(), 6576 ST->getPointerInfo(), 6577 false, false, STAlign); 6578 6579 AddToWorkList(NewLD.getNode()); 6580 AddToWorkList(NewST.getNode()); 6581 WorkListRemover DeadNodes(*this); 6582 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6583 &DeadNodes); 6584 ++LdStFP2Int; 6585 return NewST; 6586 } 6587 6588 return SDValue(); 6589} 6590 6591SDValue DAGCombiner::visitSTORE(SDNode *N) { 6592 StoreSDNode *ST = cast<StoreSDNode>(N); 6593 SDValue Chain = ST->getChain(); 6594 SDValue Value = ST->getValue(); 6595 SDValue Ptr = ST->getBasePtr(); 6596 6597 // If this is a store of a bit convert, store the input value if the 6598 // resultant store does not need a higher alignment than the original. 6599 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6600 ST->isUnindexed()) { 6601 unsigned OrigAlign = ST->getAlignment(); 6602 EVT SVT = Value.getOperand(0).getValueType(); 6603 unsigned Align = TLI.getTargetData()-> 6604 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6605 if (Align <= OrigAlign && 6606 ((!LegalOperations && !ST->isVolatile()) || 6607 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6608 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6609 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6610 ST->isNonTemporal(), OrigAlign); 6611 } 6612 6613 // Turn 'store undef, Ptr' -> nothing. 6614 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6615 return Chain; 6616 6617 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6618 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6619 // NOTE: If the original store is volatile, this transform must not increase 6620 // the number of stores. For example, on x86-32 an f64 can be stored in one 6621 // processor operation but an i64 (which is not legal) requires two. So the 6622 // transform should not be done in this case. 6623 if (Value.getOpcode() != ISD::TargetConstantFP) { 6624 SDValue Tmp; 6625 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6626 default: llvm_unreachable("Unknown FP type"); 6627 case MVT::f80: // We don't do this for these yet. 6628 case MVT::f128: 6629 case MVT::ppcf128: 6630 break; 6631 case MVT::f32: 6632 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6633 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6634 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6635 bitcastToAPInt().getZExtValue(), MVT::i32); 6636 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6637 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6638 ST->isNonTemporal(), ST->getAlignment()); 6639 } 6640 break; 6641 case MVT::f64: 6642 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6643 !ST->isVolatile()) || 6644 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6645 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6646 getZExtValue(), MVT::i64); 6647 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6648 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6649 ST->isNonTemporal(), ST->getAlignment()); 6650 } 6651 6652 if (!ST->isVolatile() && 6653 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6654 // Many FP stores are not made apparent until after legalize, e.g. for 6655 // argument passing. Since this is so common, custom legalize the 6656 // 64-bit integer store into two 32-bit stores. 6657 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6658 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6659 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6660 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6661 6662 unsigned Alignment = ST->getAlignment(); 6663 bool isVolatile = ST->isVolatile(); 6664 bool isNonTemporal = ST->isNonTemporal(); 6665 6666 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6667 Ptr, ST->getPointerInfo(), 6668 isVolatile, isNonTemporal, 6669 ST->getAlignment()); 6670 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6671 DAG.getConstant(4, Ptr.getValueType())); 6672 Alignment = MinAlign(Alignment, 4U); 6673 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6674 Ptr, ST->getPointerInfo().getWithOffset(4), 6675 isVolatile, isNonTemporal, 6676 Alignment); 6677 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6678 St0, St1); 6679 } 6680 6681 break; 6682 } 6683 } 6684 } 6685 6686 // Try to infer better alignment information than the store already has. 6687 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6688 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6689 if (Align > ST->getAlignment()) 6690 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6691 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6692 ST->isVolatile(), ST->isNonTemporal(), Align); 6693 } 6694 } 6695 6696 // Try transforming a pair floating point load / store ops to integer 6697 // load / store ops. 6698 SDValue NewST = TransformFPLoadStorePair(N); 6699 if (NewST.getNode()) 6700 return NewST; 6701 6702 if (CombinerAA) { 6703 // Walk up chain skipping non-aliasing memory nodes. 6704 SDValue BetterChain = FindBetterChain(N, Chain); 6705 6706 // If there is a better chain. 6707 if (Chain != BetterChain) { 6708 SDValue ReplStore; 6709 6710 // Replace the chain to avoid dependency. 6711 if (ST->isTruncatingStore()) { 6712 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6713 ST->getPointerInfo(), 6714 ST->getMemoryVT(), ST->isVolatile(), 6715 ST->isNonTemporal(), ST->getAlignment()); 6716 } else { 6717 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6718 ST->getPointerInfo(), 6719 ST->isVolatile(), ST->isNonTemporal(), 6720 ST->getAlignment()); 6721 } 6722 6723 // Create token to keep both nodes around. 6724 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6725 MVT::Other, Chain, ReplStore); 6726 6727 // Make sure the new and old chains are cleaned up. 6728 AddToWorkList(Token.getNode()); 6729 6730 // Don't add users to work list. 6731 return CombineTo(N, Token, false); 6732 } 6733 } 6734 6735 // Try transforming N to an indexed store. 6736 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6737 return SDValue(N, 0); 6738 6739 // FIXME: is there such a thing as a truncating indexed store? 6740 if (ST->isTruncatingStore() && ST->isUnindexed() && 6741 Value.getValueType().isInteger()) { 6742 // See if we can simplify the input to this truncstore with knowledge that 6743 // only the low bits are being used. For example: 6744 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6745 SDValue Shorter = 6746 GetDemandedBits(Value, 6747 APInt::getLowBitsSet( 6748 Value.getValueType().getScalarType().getSizeInBits(), 6749 ST->getMemoryVT().getScalarType().getSizeInBits())); 6750 AddToWorkList(Value.getNode()); 6751 if (Shorter.getNode()) 6752 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6753 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6754 ST->isVolatile(), ST->isNonTemporal(), 6755 ST->getAlignment()); 6756 6757 // Otherwise, see if we can simplify the operation with 6758 // SimplifyDemandedBits, which only works if the value has a single use. 6759 if (SimplifyDemandedBits(Value, 6760 APInt::getLowBitsSet( 6761 Value.getValueType().getScalarType().getSizeInBits(), 6762 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6763 return SDValue(N, 0); 6764 } 6765 6766 // If this is a load followed by a store to the same location, then the store 6767 // is dead/noop. 6768 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6769 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6770 ST->isUnindexed() && !ST->isVolatile() && 6771 // There can't be any side effects between the load and store, such as 6772 // a call or store. 6773 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6774 // The store is dead, remove it. 6775 return Chain; 6776 } 6777 } 6778 6779 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6780 // truncating store. We can do this even if this is already a truncstore. 6781 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6782 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6783 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6784 ST->getMemoryVT())) { 6785 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6786 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6787 ST->isVolatile(), ST->isNonTemporal(), 6788 ST->getAlignment()); 6789 } 6790 6791 return ReduceLoadOpStoreWidth(N); 6792} 6793 6794SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6795 SDValue InVec = N->getOperand(0); 6796 SDValue InVal = N->getOperand(1); 6797 SDValue EltNo = N->getOperand(2); 6798 6799 // If the inserted element is an UNDEF, just use the input vector. 6800 if (InVal.getOpcode() == ISD::UNDEF) 6801 return InVec; 6802 6803 EVT VT = InVec.getValueType(); 6804 6805 // If we can't generate a legal BUILD_VECTOR, exit 6806 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6807 return SDValue(); 6808 6809 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6810 // vector with the inserted element. 6811 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6812 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6813 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6814 InVec.getNode()->op_end()); 6815 if (Elt < Ops.size()) 6816 Ops[Elt] = InVal; 6817 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6818 VT, &Ops[0], Ops.size()); 6819 } 6820 // If the invec is an UNDEF and if EltNo is a constant, create a new 6821 // BUILD_VECTOR with undef elements and the inserted element. 6822 if (InVec.getOpcode() == ISD::UNDEF && 6823 isa<ConstantSDNode>(EltNo)) { 6824 EVT EltVT = VT.getVectorElementType(); 6825 unsigned NElts = VT.getVectorNumElements(); 6826 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6827 6828 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6829 if (Elt < Ops.size()) 6830 Ops[Elt] = InVal; 6831 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6832 VT, &Ops[0], Ops.size()); 6833 } 6834 return SDValue(); 6835} 6836 6837SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6838 // (vextract (scalar_to_vector val, 0) -> val 6839 SDValue InVec = N->getOperand(0); 6840 6841 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6842 // Check if the result type doesn't match the inserted element type. A 6843 // SCALAR_TO_VECTOR may truncate the inserted element and the 6844 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6845 SDValue InOp = InVec.getOperand(0); 6846 EVT NVT = N->getValueType(0); 6847 if (InOp.getValueType() != NVT) { 6848 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6849 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6850 } 6851 return InOp; 6852 } 6853 6854 // Perform only after legalization to ensure build_vector / vector_shuffle 6855 // optimizations have already been done. 6856 if (!LegalOperations) return SDValue(); 6857 6858 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6859 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6860 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6861 SDValue EltNo = N->getOperand(1); 6862 6863 if (isa<ConstantSDNode>(EltNo)) { 6864 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6865 bool NewLoad = false; 6866 bool BCNumEltsChanged = false; 6867 EVT VT = InVec.getValueType(); 6868 EVT ExtVT = VT.getVectorElementType(); 6869 EVT LVT = ExtVT; 6870 6871 if (InVec.getOpcode() == ISD::BITCAST) { 6872 EVT BCVT = InVec.getOperand(0).getValueType(); 6873 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6874 return SDValue(); 6875 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6876 BCNumEltsChanged = true; 6877 InVec = InVec.getOperand(0); 6878 ExtVT = BCVT.getVectorElementType(); 6879 NewLoad = true; 6880 } 6881 6882 LoadSDNode *LN0 = NULL; 6883 const ShuffleVectorSDNode *SVN = NULL; 6884 if (ISD::isNormalLoad(InVec.getNode())) { 6885 LN0 = cast<LoadSDNode>(InVec); 6886 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6887 InVec.getOperand(0).getValueType() == ExtVT && 6888 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6889 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6890 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6891 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6892 // => 6893 // (load $addr+1*size) 6894 6895 // If the bit convert changed the number of elements, it is unsafe 6896 // to examine the mask. 6897 if (BCNumEltsChanged) 6898 return SDValue(); 6899 6900 // Select the input vector, guarding against out of range extract vector. 6901 unsigned NumElems = VT.getVectorNumElements(); 6902 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6903 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6904 6905 if (InVec.getOpcode() == ISD::BITCAST) 6906 InVec = InVec.getOperand(0); 6907 if (ISD::isNormalLoad(InVec.getNode())) { 6908 LN0 = cast<LoadSDNode>(InVec); 6909 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6910 } 6911 } 6912 6913 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 6914 return SDValue(); 6915 6916 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6917 if (Elt == -1) 6918 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6919 6920 unsigned Align = LN0->getAlignment(); 6921 if (NewLoad) { 6922 // Check the resultant load doesn't need a higher alignment than the 6923 // original load. 6924 unsigned NewAlign = 6925 TLI.getTargetData() 6926 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6927 6928 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6929 return SDValue(); 6930 6931 Align = NewAlign; 6932 } 6933 6934 SDValue NewPtr = LN0->getBasePtr(); 6935 unsigned PtrOff = 0; 6936 6937 if (Elt) { 6938 PtrOff = LVT.getSizeInBits() * Elt / 8; 6939 EVT PtrType = NewPtr.getValueType(); 6940 if (TLI.isBigEndian()) 6941 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6942 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6943 DAG.getConstant(PtrOff, PtrType)); 6944 } 6945 6946 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6947 LN0->getPointerInfo().getWithOffset(PtrOff), 6948 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6949 } 6950 6951 return SDValue(); 6952} 6953 6954SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6955 unsigned NumInScalars = N->getNumOperands(); 6956 EVT VT = N->getValueType(0); 6957 6958 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6959 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6960 // at most two distinct vectors, turn this into a shuffle node. 6961 SDValue VecIn1, VecIn2; 6962 for (unsigned i = 0; i != NumInScalars; ++i) { 6963 // Ignore undef inputs. 6964 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6965 6966 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6967 // constant index, bail out. 6968 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6969 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6970 VecIn1 = VecIn2 = SDValue(0, 0); 6971 break; 6972 } 6973 6974 // If the input vector type disagrees with the result of the build_vector, 6975 // we can't make a shuffle. 6976 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6977 if (ExtractedFromVec.getValueType() != VT) { 6978 VecIn1 = VecIn2 = SDValue(0, 0); 6979 break; 6980 } 6981 6982 // Otherwise, remember this. We allow up to two distinct input vectors. 6983 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6984 continue; 6985 6986 if (VecIn1.getNode() == 0) { 6987 VecIn1 = ExtractedFromVec; 6988 } else if (VecIn2.getNode() == 0) { 6989 VecIn2 = ExtractedFromVec; 6990 } else { 6991 // Too many inputs. 6992 VecIn1 = VecIn2 = SDValue(0, 0); 6993 break; 6994 } 6995 } 6996 6997 // If everything is good, we can make a shuffle operation. 6998 if (VecIn1.getNode()) { 6999 SmallVector<int, 8> Mask; 7000 for (unsigned i = 0; i != NumInScalars; ++i) { 7001 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7002 Mask.push_back(-1); 7003 continue; 7004 } 7005 7006 // If extracting from the first vector, just use the index directly. 7007 SDValue Extract = N->getOperand(i); 7008 SDValue ExtVal = Extract.getOperand(1); 7009 if (Extract.getOperand(0) == VecIn1) { 7010 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7011 if (ExtIndex > VT.getVectorNumElements()) 7012 return SDValue(); 7013 7014 Mask.push_back(ExtIndex); 7015 continue; 7016 } 7017 7018 // Otherwise, use InIdx + VecSize 7019 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7020 Mask.push_back(Idx+NumInScalars); 7021 } 7022 7023 // Add count and size info. 7024 if (!isTypeLegal(VT)) 7025 return SDValue(); 7026 7027 // Return the new VECTOR_SHUFFLE node. 7028 SDValue Ops[2]; 7029 Ops[0] = VecIn1; 7030 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7031 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7032 } 7033 7034 return SDValue(); 7035} 7036 7037SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7038 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7039 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7040 // inputs come from at most two distinct vectors, turn this into a shuffle 7041 // node. 7042 7043 // If we only have one input vector, we don't need to do any concatenation. 7044 if (N->getNumOperands() == 1) 7045 return N->getOperand(0); 7046 7047 return SDValue(); 7048} 7049 7050SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7051 EVT VT = N->getValueType(0); 7052 unsigned NumElts = VT.getVectorNumElements(); 7053 7054 SDValue N0 = N->getOperand(0); 7055 7056 assert(N0.getValueType().getVectorNumElements() == NumElts && 7057 "Vector shuffle must be normalized in DAG"); 7058 7059 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 7060 7061 // If it is a splat, check if the argument vector is another splat or a 7062 // build_vector with all scalar elements the same. 7063 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7064 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7065 SDNode *V = N0.getNode(); 7066 7067 // If this is a bit convert that changes the element type of the vector but 7068 // not the number of vector elements, look through it. Be careful not to 7069 // look though conversions that change things like v4f32 to v2f64. 7070 if (V->getOpcode() == ISD::BITCAST) { 7071 SDValue ConvInput = V->getOperand(0); 7072 if (ConvInput.getValueType().isVector() && 7073 ConvInput.getValueType().getVectorNumElements() == NumElts) 7074 V = ConvInput.getNode(); 7075 } 7076 7077 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7078 assert(V->getNumOperands() == NumElts && 7079 "BUILD_VECTOR has wrong number of operands"); 7080 SDValue Base; 7081 bool AllSame = true; 7082 for (unsigned i = 0; i != NumElts; ++i) { 7083 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7084 Base = V->getOperand(i); 7085 break; 7086 } 7087 } 7088 // Splat of <u, u, u, u>, return <u, u, u, u> 7089 if (!Base.getNode()) 7090 return N0; 7091 for (unsigned i = 0; i != NumElts; ++i) { 7092 if (V->getOperand(i) != Base) { 7093 AllSame = false; 7094 break; 7095 } 7096 } 7097 // Splat of <x, x, x, x>, return <x, x, x, x> 7098 if (AllSame) 7099 return N0; 7100 } 7101 } 7102 return SDValue(); 7103} 7104 7105SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7106 if (!TLI.getShouldFoldAtomicFences()) 7107 return SDValue(); 7108 7109 SDValue atomic = N->getOperand(0); 7110 switch (atomic.getOpcode()) { 7111 case ISD::ATOMIC_CMP_SWAP: 7112 case ISD::ATOMIC_SWAP: 7113 case ISD::ATOMIC_LOAD_ADD: 7114 case ISD::ATOMIC_LOAD_SUB: 7115 case ISD::ATOMIC_LOAD_AND: 7116 case ISD::ATOMIC_LOAD_OR: 7117 case ISD::ATOMIC_LOAD_XOR: 7118 case ISD::ATOMIC_LOAD_NAND: 7119 case ISD::ATOMIC_LOAD_MIN: 7120 case ISD::ATOMIC_LOAD_MAX: 7121 case ISD::ATOMIC_LOAD_UMIN: 7122 case ISD::ATOMIC_LOAD_UMAX: 7123 break; 7124 default: 7125 return SDValue(); 7126 } 7127 7128 SDValue fence = atomic.getOperand(0); 7129 if (fence.getOpcode() != ISD::MEMBARRIER) 7130 return SDValue(); 7131 7132 switch (atomic.getOpcode()) { 7133 case ISD::ATOMIC_CMP_SWAP: 7134 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7135 fence.getOperand(0), 7136 atomic.getOperand(1), atomic.getOperand(2), 7137 atomic.getOperand(3)), atomic.getResNo()); 7138 case ISD::ATOMIC_SWAP: 7139 case ISD::ATOMIC_LOAD_ADD: 7140 case ISD::ATOMIC_LOAD_SUB: 7141 case ISD::ATOMIC_LOAD_AND: 7142 case ISD::ATOMIC_LOAD_OR: 7143 case ISD::ATOMIC_LOAD_XOR: 7144 case ISD::ATOMIC_LOAD_NAND: 7145 case ISD::ATOMIC_LOAD_MIN: 7146 case ISD::ATOMIC_LOAD_MAX: 7147 case ISD::ATOMIC_LOAD_UMIN: 7148 case ISD::ATOMIC_LOAD_UMAX: 7149 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7150 fence.getOperand(0), 7151 atomic.getOperand(1), atomic.getOperand(2)), 7152 atomic.getResNo()); 7153 default: 7154 return SDValue(); 7155 } 7156} 7157 7158/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7159/// an AND to a vector_shuffle with the destination vector and a zero vector. 7160/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7161/// vector_shuffle V, Zero, <0, 4, 2, 4> 7162SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7163 EVT VT = N->getValueType(0); 7164 DebugLoc dl = N->getDebugLoc(); 7165 SDValue LHS = N->getOperand(0); 7166 SDValue RHS = N->getOperand(1); 7167 if (N->getOpcode() == ISD::AND) { 7168 if (RHS.getOpcode() == ISD::BITCAST) 7169 RHS = RHS.getOperand(0); 7170 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7171 SmallVector<int, 8> Indices; 7172 unsigned NumElts = RHS.getNumOperands(); 7173 for (unsigned i = 0; i != NumElts; ++i) { 7174 SDValue Elt = RHS.getOperand(i); 7175 if (!isa<ConstantSDNode>(Elt)) 7176 return SDValue(); 7177 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7178 Indices.push_back(i); 7179 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7180 Indices.push_back(NumElts); 7181 else 7182 return SDValue(); 7183 } 7184 7185 // Let's see if the target supports this vector_shuffle. 7186 EVT RVT = RHS.getValueType(); 7187 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7188 return SDValue(); 7189 7190 // Return the new VECTOR_SHUFFLE node. 7191 EVT EltVT = RVT.getVectorElementType(); 7192 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7193 DAG.getConstant(0, EltVT)); 7194 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7195 RVT, &ZeroOps[0], ZeroOps.size()); 7196 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7197 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7198 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7199 } 7200 } 7201 7202 return SDValue(); 7203} 7204 7205/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7206SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7207 // After legalize, the target may be depending on adds and other 7208 // binary ops to provide legal ways to construct constants or other 7209 // things. Simplifying them may result in a loss of legality. 7210 if (LegalOperations) return SDValue(); 7211 7212 assert(N->getValueType(0).isVector() && 7213 "SimplifyVBinOp only works on vectors!"); 7214 7215 SDValue LHS = N->getOperand(0); 7216 SDValue RHS = N->getOperand(1); 7217 SDValue Shuffle = XformToShuffleWithZero(N); 7218 if (Shuffle.getNode()) return Shuffle; 7219 7220 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7221 // this operation. 7222 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7223 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7224 SmallVector<SDValue, 8> Ops; 7225 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7226 SDValue LHSOp = LHS.getOperand(i); 7227 SDValue RHSOp = RHS.getOperand(i); 7228 // If these two elements can't be folded, bail out. 7229 if ((LHSOp.getOpcode() != ISD::UNDEF && 7230 LHSOp.getOpcode() != ISD::Constant && 7231 LHSOp.getOpcode() != ISD::ConstantFP) || 7232 (RHSOp.getOpcode() != ISD::UNDEF && 7233 RHSOp.getOpcode() != ISD::Constant && 7234 RHSOp.getOpcode() != ISD::ConstantFP)) 7235 break; 7236 7237 // Can't fold divide by zero. 7238 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7239 N->getOpcode() == ISD::FDIV) { 7240 if ((RHSOp.getOpcode() == ISD::Constant && 7241 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7242 (RHSOp.getOpcode() == ISD::ConstantFP && 7243 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7244 break; 7245 } 7246 7247 EVT VT = LHSOp.getValueType(); 7248 assert(RHSOp.getValueType() == VT && 7249 "SimplifyVBinOp with different BUILD_VECTOR element types"); 7250 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7251 LHSOp, RHSOp); 7252 if (FoldOp.getOpcode() != ISD::UNDEF && 7253 FoldOp.getOpcode() != ISD::Constant && 7254 FoldOp.getOpcode() != ISD::ConstantFP) 7255 break; 7256 Ops.push_back(FoldOp); 7257 AddToWorkList(FoldOp.getNode()); 7258 } 7259 7260 if (Ops.size() == LHS.getNumOperands()) 7261 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7262 LHS.getValueType(), &Ops[0], Ops.size()); 7263 } 7264 7265 return SDValue(); 7266} 7267 7268SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 7269 SDValue N1, SDValue N2){ 7270 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 7271 7272 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 7273 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7274 7275 // If we got a simplified select_cc node back from SimplifySelectCC, then 7276 // break it down into a new SETCC node, and a new SELECT node, and then return 7277 // the SELECT node, since we were called with a SELECT node. 7278 if (SCC.getNode()) { 7279 // Check to see if we got a select_cc back (to turn into setcc/select). 7280 // Otherwise, just return whatever node we got back, like fabs. 7281 if (SCC.getOpcode() == ISD::SELECT_CC) { 7282 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 7283 N0.getValueType(), 7284 SCC.getOperand(0), SCC.getOperand(1), 7285 SCC.getOperand(4)); 7286 AddToWorkList(SETCC.getNode()); 7287 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 7288 SCC.getOperand(2), SCC.getOperand(3), SETCC); 7289 } 7290 7291 return SCC; 7292 } 7293 return SDValue(); 7294} 7295 7296/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 7297/// are the two values being selected between, see if we can simplify the 7298/// select. Callers of this should assume that TheSelect is deleted if this 7299/// returns true. As such, they should return the appropriate thing (e.g. the 7300/// node) back to the top-level of the DAG combiner loop to avoid it being 7301/// looked at. 7302bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 7303 SDValue RHS) { 7304 7305 // Cannot simplify select with vector condition 7306 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 7307 7308 // If this is a select from two identical things, try to pull the operation 7309 // through the select. 7310 if (LHS.getOpcode() != RHS.getOpcode() || 7311 !LHS.hasOneUse() || !RHS.hasOneUse()) 7312 return false; 7313 7314 // If this is a load and the token chain is identical, replace the select 7315 // of two loads with a load through a select of the address to load from. 7316 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7317 // constants have been dropped into the constant pool. 7318 if (LHS.getOpcode() == ISD::LOAD) { 7319 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7320 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7321 7322 // Token chains must be identical. 7323 if (LHS.getOperand(0) != RHS.getOperand(0) || 7324 // Do not let this transformation reduce the number of volatile loads. 7325 LLD->isVolatile() || RLD->isVolatile() || 7326 // If this is an EXTLOAD, the VT's must match. 7327 LLD->getMemoryVT() != RLD->getMemoryVT() || 7328 // If this is an EXTLOAD, the kind of extension must match. 7329 (LLD->getExtensionType() != RLD->getExtensionType() && 7330 // The only exception is if one of the extensions is anyext. 7331 LLD->getExtensionType() != ISD::EXTLOAD && 7332 RLD->getExtensionType() != ISD::EXTLOAD) || 7333 // FIXME: this discards src value information. This is 7334 // over-conservative. It would be beneficial to be able to remember 7335 // both potential memory locations. Since we are discarding 7336 // src value info, don't do the transformation if the memory 7337 // locations are not in the default address space. 7338 LLD->getPointerInfo().getAddrSpace() != 0 || 7339 RLD->getPointerInfo().getAddrSpace() != 0) 7340 return false; 7341 7342 // Check that the select condition doesn't reach either load. If so, 7343 // folding this will induce a cycle into the DAG. If not, this is safe to 7344 // xform, so create a select of the addresses. 7345 SDValue Addr; 7346 if (TheSelect->getOpcode() == ISD::SELECT) { 7347 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7348 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7349 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7350 return false; 7351 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7352 LLD->getBasePtr().getValueType(), 7353 TheSelect->getOperand(0), LLD->getBasePtr(), 7354 RLD->getBasePtr()); 7355 } else { // Otherwise SELECT_CC 7356 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7357 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7358 7359 if ((LLD->hasAnyUseOfValue(1) && 7360 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7361 (LLD->hasAnyUseOfValue(1) && 7362 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7363 return false; 7364 7365 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7366 LLD->getBasePtr().getValueType(), 7367 TheSelect->getOperand(0), 7368 TheSelect->getOperand(1), 7369 LLD->getBasePtr(), RLD->getBasePtr(), 7370 TheSelect->getOperand(4)); 7371 } 7372 7373 SDValue Load; 7374 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7375 Load = DAG.getLoad(TheSelect->getValueType(0), 7376 TheSelect->getDebugLoc(), 7377 // FIXME: Discards pointer info. 7378 LLD->getChain(), Addr, MachinePointerInfo(), 7379 LLD->isVolatile(), LLD->isNonTemporal(), 7380 LLD->getAlignment()); 7381 } else { 7382 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7383 RLD->getExtensionType() : LLD->getExtensionType(), 7384 TheSelect->getDebugLoc(), 7385 TheSelect->getValueType(0), 7386 // FIXME: Discards pointer info. 7387 LLD->getChain(), Addr, MachinePointerInfo(), 7388 LLD->getMemoryVT(), LLD->isVolatile(), 7389 LLD->isNonTemporal(), LLD->getAlignment()); 7390 } 7391 7392 // Users of the select now use the result of the load. 7393 CombineTo(TheSelect, Load); 7394 7395 // Users of the old loads now use the new load's chain. We know the 7396 // old-load value is dead now. 7397 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7398 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7399 return true; 7400 } 7401 7402 return false; 7403} 7404 7405/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7406/// where 'cond' is the comparison specified by CC. 7407SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7408 SDValue N2, SDValue N3, 7409 ISD::CondCode CC, bool NotExtCompare) { 7410 // (x ? y : y) -> y. 7411 if (N2 == N3) return N2; 7412 7413 EVT VT = N2.getValueType(); 7414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7415 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7416 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7417 7418 // Determine if the condition we're dealing with is constant 7419 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7420 N0, N1, CC, DL, false); 7421 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7422 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7423 7424 // fold select_cc true, x, y -> x 7425 if (SCCC && !SCCC->isNullValue()) 7426 return N2; 7427 // fold select_cc false, x, y -> y 7428 if (SCCC && SCCC->isNullValue()) 7429 return N3; 7430 7431 // Check to see if we can simplify the select into an fabs node 7432 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7433 // Allow either -0.0 or 0.0 7434 if (CFP->getValueAPF().isZero()) { 7435 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7436 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7437 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7438 N2 == N3.getOperand(0)) 7439 return DAG.getNode(ISD::FABS, DL, VT, N0); 7440 7441 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7442 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7443 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7444 N2.getOperand(0) == N3) 7445 return DAG.getNode(ISD::FABS, DL, VT, N3); 7446 } 7447 } 7448 7449 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7450 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7451 // in it. This is a win when the constant is not otherwise available because 7452 // it replaces two constant pool loads with one. We only do this if the FP 7453 // type is known to be legal, because if it isn't, then we are before legalize 7454 // types an we want the other legalization to happen first (e.g. to avoid 7455 // messing with soft float) and if the ConstantFP is not legal, because if 7456 // it is legal, we may not need to store the FP constant in a constant pool. 7457 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7458 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7459 if (TLI.isTypeLegal(N2.getValueType()) && 7460 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7461 TargetLowering::Legal) && 7462 // If both constants have multiple uses, then we won't need to do an 7463 // extra load, they are likely around in registers for other users. 7464 (TV->hasOneUse() || FV->hasOneUse())) { 7465 Constant *Elts[] = { 7466 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7467 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7468 }; 7469 const Type *FPTy = Elts[0]->getType(); 7470 const TargetData &TD = *TLI.getTargetData(); 7471 7472 // Create a ConstantArray of the two constants. 7473 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 7474 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7475 TD.getPrefTypeAlignment(FPTy)); 7476 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7477 7478 // Get the offsets to the 0 and 1 element of the array so that we can 7479 // select between them. 7480 SDValue Zero = DAG.getIntPtrConstant(0); 7481 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7482 SDValue One = DAG.getIntPtrConstant(EltSize); 7483 7484 SDValue Cond = DAG.getSetCC(DL, 7485 TLI.getSetCCResultType(N0.getValueType()), 7486 N0, N1, CC); 7487 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7488 Cond, One, Zero); 7489 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7490 CstOffset); 7491 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7492 MachinePointerInfo::getConstantPool(), false, 7493 false, Alignment); 7494 7495 } 7496 } 7497 7498 // Check to see if we can perform the "gzip trick", transforming 7499 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7500 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7501 N0.getValueType().isInteger() && 7502 N2.getValueType().isInteger() && 7503 (N1C->isNullValue() || // (a < 0) ? b : 0 7504 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7505 EVT XType = N0.getValueType(); 7506 EVT AType = N2.getValueType(); 7507 if (XType.bitsGE(AType)) { 7508 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7509 // single-bit constant. 7510 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7511 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7512 ShCtV = XType.getSizeInBits()-ShCtV-1; 7513 SDValue ShCt = DAG.getConstant(ShCtV, 7514 getShiftAmountTy(N0.getValueType())); 7515 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7516 XType, N0, ShCt); 7517 AddToWorkList(Shift.getNode()); 7518 7519 if (XType.bitsGT(AType)) { 7520 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7521 AddToWorkList(Shift.getNode()); 7522 } 7523 7524 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7525 } 7526 7527 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7528 XType, N0, 7529 DAG.getConstant(XType.getSizeInBits()-1, 7530 getShiftAmountTy(N0.getValueType()))); 7531 AddToWorkList(Shift.getNode()); 7532 7533 if (XType.bitsGT(AType)) { 7534 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7535 AddToWorkList(Shift.getNode()); 7536 } 7537 7538 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7539 } 7540 } 7541 7542 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7543 // where y is has a single bit set. 7544 // A plaintext description would be, we can turn the SELECT_CC into an AND 7545 // when the condition can be materialized as an all-ones register. Any 7546 // single bit-test can be materialized as an all-ones register with 7547 // shift-left and shift-right-arith. 7548 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7549 N0->getValueType(0) == VT && 7550 N1C && N1C->isNullValue() && 7551 N2C && N2C->isNullValue()) { 7552 SDValue AndLHS = N0->getOperand(0); 7553 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7554 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7555 // Shift the tested bit over the sign bit. 7556 APInt AndMask = ConstAndRHS->getAPIntValue(); 7557 SDValue ShlAmt = 7558 DAG.getConstant(AndMask.countLeadingZeros(), 7559 getShiftAmountTy(AndLHS.getValueType())); 7560 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7561 7562 // Now arithmetic right shift it all the way over, so the result is either 7563 // all-ones, or zero. 7564 SDValue ShrAmt = 7565 DAG.getConstant(AndMask.getBitWidth()-1, 7566 getShiftAmountTy(Shl.getValueType())); 7567 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7568 7569 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7570 } 7571 } 7572 7573 // fold select C, 16, 0 -> shl C, 4 7574 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7575 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7576 7577 // If the caller doesn't want us to simplify this into a zext of a compare, 7578 // don't do it. 7579 if (NotExtCompare && N2C->getAPIntValue() == 1) 7580 return SDValue(); 7581 7582 // Get a SetCC of the condition 7583 // FIXME: Should probably make sure that setcc is legal if we ever have a 7584 // target where it isn't. 7585 SDValue Temp, SCC; 7586 // cast from setcc result type to select result type 7587 if (LegalTypes) { 7588 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7589 N0, N1, CC); 7590 if (N2.getValueType().bitsLT(SCC.getValueType())) 7591 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7592 else 7593 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7594 N2.getValueType(), SCC); 7595 } else { 7596 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7597 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7598 N2.getValueType(), SCC); 7599 } 7600 7601 AddToWorkList(SCC.getNode()); 7602 AddToWorkList(Temp.getNode()); 7603 7604 if (N2C->getAPIntValue() == 1) 7605 return Temp; 7606 7607 // shl setcc result by log2 n2c 7608 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7609 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7610 getShiftAmountTy(Temp.getValueType()))); 7611 } 7612 7613 // Check to see if this is the equivalent of setcc 7614 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7615 // otherwise, go ahead with the folds. 7616 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7617 EVT XType = N0.getValueType(); 7618 if (!LegalOperations || 7619 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7620 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7621 if (Res.getValueType() != VT) 7622 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7623 return Res; 7624 } 7625 7626 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7627 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7628 (!LegalOperations || 7629 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7630 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7631 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7632 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7633 getShiftAmountTy(Ctlz.getValueType()))); 7634 } 7635 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7636 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7637 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7638 XType, DAG.getConstant(0, XType), N0); 7639 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7640 return DAG.getNode(ISD::SRL, DL, XType, 7641 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7642 DAG.getConstant(XType.getSizeInBits()-1, 7643 getShiftAmountTy(XType))); 7644 } 7645 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7646 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7647 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7648 DAG.getConstant(XType.getSizeInBits()-1, 7649 getShiftAmountTy(N0.getValueType()))); 7650 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7651 } 7652 } 7653 7654 // Check to see if this is an integer abs. 7655 // select_cc setg[te] X, 0, X, -X -> 7656 // select_cc setgt X, -1, X, -X -> 7657 // select_cc setl[te] X, 0, -X, X -> 7658 // select_cc setlt X, 1, -X, X -> 7659 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7660 if (N1C) { 7661 ConstantSDNode *SubC = NULL; 7662 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7663 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7664 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7665 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7666 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7667 (N1C->isOne() && CC == ISD::SETLT)) && 7668 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7669 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7670 7671 EVT XType = N0.getValueType(); 7672 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7673 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7674 N0, 7675 DAG.getConstant(XType.getSizeInBits()-1, 7676 getShiftAmountTy(N0.getValueType()))); 7677 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7678 XType, N0, Shift); 7679 AddToWorkList(Shift.getNode()); 7680 AddToWorkList(Add.getNode()); 7681 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7682 } 7683 } 7684 7685 return SDValue(); 7686} 7687 7688/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7689SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7690 SDValue N1, ISD::CondCode Cond, 7691 DebugLoc DL, bool foldBooleans) { 7692 TargetLowering::DAGCombinerInfo 7693 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7694 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7695} 7696 7697/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7698/// return a DAG expression to select that will generate the same value by 7699/// multiplying by a magic number. See: 7700/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7701SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7702 std::vector<SDNode*> Built; 7703 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7704 7705 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7706 ii != ee; ++ii) 7707 AddToWorkList(*ii); 7708 return S; 7709} 7710 7711/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7712/// return a DAG expression to select that will generate the same value by 7713/// multiplying by a magic number. See: 7714/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7715SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7716 std::vector<SDNode*> Built; 7717 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7718 7719 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7720 ii != ee; ++ii) 7721 AddToWorkList(*ii); 7722 return S; 7723} 7724 7725/// FindBaseOffset - Return true if base is a frame index, which is known not 7726// to alias with anything but itself. Provides base object and offset as 7727// results. 7728static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7729 const GlobalValue *&GV, void *&CV) { 7730 // Assume it is a primitive operation. 7731 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7732 7733 // If it's an adding a simple constant then integrate the offset. 7734 if (Base.getOpcode() == ISD::ADD) { 7735 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7736 Base = Base.getOperand(0); 7737 Offset += C->getZExtValue(); 7738 } 7739 } 7740 7741 // Return the underlying GlobalValue, and update the Offset. Return false 7742 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7743 // by multiple nodes with different offsets. 7744 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7745 GV = G->getGlobal(); 7746 Offset += G->getOffset(); 7747 return false; 7748 } 7749 7750 // Return the underlying Constant value, and update the Offset. Return false 7751 // for ConstantSDNodes since the same constant pool entry may be represented 7752 // by multiple nodes with different offsets. 7753 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7754 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7755 : (void *)C->getConstVal(); 7756 Offset += C->getOffset(); 7757 return false; 7758 } 7759 // If it's any of the following then it can't alias with anything but itself. 7760 return isa<FrameIndexSDNode>(Base); 7761} 7762 7763/// isAlias - Return true if there is any possibility that the two addresses 7764/// overlap. 7765bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7766 const Value *SrcValue1, int SrcValueOffset1, 7767 unsigned SrcValueAlign1, 7768 const MDNode *TBAAInfo1, 7769 SDValue Ptr2, int64_t Size2, 7770 const Value *SrcValue2, int SrcValueOffset2, 7771 unsigned SrcValueAlign2, 7772 const MDNode *TBAAInfo2) const { 7773 // If they are the same then they must be aliases. 7774 if (Ptr1 == Ptr2) return true; 7775 7776 // Gather base node and offset information. 7777 SDValue Base1, Base2; 7778 int64_t Offset1, Offset2; 7779 const GlobalValue *GV1, *GV2; 7780 void *CV1, *CV2; 7781 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7782 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7783 7784 // If they have a same base address then check to see if they overlap. 7785 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7786 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7787 7788 // It is possible for different frame indices to alias each other, mostly 7789 // when tail call optimization reuses return address slots for arguments. 7790 // To catch this case, look up the actual index of frame indices to compute 7791 // the real alias relationship. 7792 if (isFrameIndex1 && isFrameIndex2) { 7793 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7794 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7795 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7796 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7797 } 7798 7799 // Otherwise, if we know what the bases are, and they aren't identical, then 7800 // we know they cannot alias. 7801 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7802 return false; 7803 7804 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7805 // compared to the size and offset of the access, we may be able to prove they 7806 // do not alias. This check is conservative for now to catch cases created by 7807 // splitting vector types. 7808 if ((SrcValueAlign1 == SrcValueAlign2) && 7809 (SrcValueOffset1 != SrcValueOffset2) && 7810 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7811 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7812 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7813 7814 // There is no overlap between these relatively aligned accesses of similar 7815 // size, return no alias. 7816 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7817 return false; 7818 } 7819 7820 if (CombinerGlobalAA) { 7821 // Use alias analysis information. 7822 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7823 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7824 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7825 AliasAnalysis::AliasResult AAResult = 7826 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7827 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7828 if (AAResult == AliasAnalysis::NoAlias) 7829 return false; 7830 } 7831 7832 // Otherwise we have to assume they alias. 7833 return true; 7834} 7835 7836/// FindAliasInfo - Extracts the relevant alias information from the memory 7837/// node. Returns true if the operand was a load. 7838bool DAGCombiner::FindAliasInfo(SDNode *N, 7839 SDValue &Ptr, int64_t &Size, 7840 const Value *&SrcValue, 7841 int &SrcValueOffset, 7842 unsigned &SrcValueAlign, 7843 const MDNode *&TBAAInfo) const { 7844 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7845 Ptr = LD->getBasePtr(); 7846 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7847 SrcValue = LD->getSrcValue(); 7848 SrcValueOffset = LD->getSrcValueOffset(); 7849 SrcValueAlign = LD->getOriginalAlignment(); 7850 TBAAInfo = LD->getTBAAInfo(); 7851 return true; 7852 } 7853 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7854 Ptr = ST->getBasePtr(); 7855 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7856 SrcValue = ST->getSrcValue(); 7857 SrcValueOffset = ST->getSrcValueOffset(); 7858 SrcValueAlign = ST->getOriginalAlignment(); 7859 TBAAInfo = ST->getTBAAInfo(); 7860 return false; 7861 } 7862 llvm_unreachable("FindAliasInfo expected a memory operand"); 7863} 7864 7865/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7866/// looking for aliasing nodes and adding them to the Aliases vector. 7867void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7868 SmallVector<SDValue, 8> &Aliases) { 7869 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7870 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7871 7872 // Get alias information for node. 7873 SDValue Ptr; 7874 int64_t Size; 7875 const Value *SrcValue; 7876 int SrcValueOffset; 7877 unsigned SrcValueAlign; 7878 const MDNode *SrcTBAAInfo; 7879 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7880 SrcValueAlign, SrcTBAAInfo); 7881 7882 // Starting off. 7883 Chains.push_back(OriginalChain); 7884 unsigned Depth = 0; 7885 7886 // Look at each chain and determine if it is an alias. If so, add it to the 7887 // aliases list. If not, then continue up the chain looking for the next 7888 // candidate. 7889 while (!Chains.empty()) { 7890 SDValue Chain = Chains.back(); 7891 Chains.pop_back(); 7892 7893 // For TokenFactor nodes, look at each operand and only continue up the 7894 // chain until we find two aliases. If we've seen two aliases, assume we'll 7895 // find more and revert to original chain since the xform is unlikely to be 7896 // profitable. 7897 // 7898 // FIXME: The depth check could be made to return the last non-aliasing 7899 // chain we found before we hit a tokenfactor rather than the original 7900 // chain. 7901 if (Depth > 6 || Aliases.size() == 2) { 7902 Aliases.clear(); 7903 Aliases.push_back(OriginalChain); 7904 break; 7905 } 7906 7907 // Don't bother if we've been before. 7908 if (!Visited.insert(Chain.getNode())) 7909 continue; 7910 7911 switch (Chain.getOpcode()) { 7912 case ISD::EntryToken: 7913 // Entry token is ideal chain operand, but handled in FindBetterChain. 7914 break; 7915 7916 case ISD::LOAD: 7917 case ISD::STORE: { 7918 // Get alias information for Chain. 7919 SDValue OpPtr; 7920 int64_t OpSize; 7921 const Value *OpSrcValue; 7922 int OpSrcValueOffset; 7923 unsigned OpSrcValueAlign; 7924 const MDNode *OpSrcTBAAInfo; 7925 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7926 OpSrcValue, OpSrcValueOffset, 7927 OpSrcValueAlign, 7928 OpSrcTBAAInfo); 7929 7930 // If chain is alias then stop here. 7931 if (!(IsLoad && IsOpLoad) && 7932 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7933 SrcTBAAInfo, 7934 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7935 OpSrcValueAlign, OpSrcTBAAInfo)) { 7936 Aliases.push_back(Chain); 7937 } else { 7938 // Look further up the chain. 7939 Chains.push_back(Chain.getOperand(0)); 7940 ++Depth; 7941 } 7942 break; 7943 } 7944 7945 case ISD::TokenFactor: 7946 // We have to check each of the operands of the token factor for "small" 7947 // token factors, so we queue them up. Adding the operands to the queue 7948 // (stack) in reverse order maintains the original order and increases the 7949 // likelihood that getNode will find a matching token factor (CSE.) 7950 if (Chain.getNumOperands() > 16) { 7951 Aliases.push_back(Chain); 7952 break; 7953 } 7954 for (unsigned n = Chain.getNumOperands(); n;) 7955 Chains.push_back(Chain.getOperand(--n)); 7956 ++Depth; 7957 break; 7958 7959 default: 7960 // For all other instructions we will just have to take what we can get. 7961 Aliases.push_back(Chain); 7962 break; 7963 } 7964 } 7965} 7966 7967/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7968/// for a better chain (aliasing node.) 7969SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7970 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7971 7972 // Accumulate all the aliases to this node. 7973 GatherAllAliases(N, OldChain, Aliases); 7974 7975 // If no operands then chain to entry token. 7976 if (Aliases.size() == 0) 7977 return DAG.getEntryNode(); 7978 7979 // If a single operand then chain to it. We don't need to revisit it. 7980 if (Aliases.size() == 1) 7981 return Aliases[0]; 7982 7983 // Construct a custom tailored token factor. 7984 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7985 &Aliases[0], Aliases.size()); 7986} 7987 7988// SelectionDAG::Combine - This is the entry point for the file. 7989// 7990void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7991 CodeGenOpt::Level OptLevel) { 7992 /// run - This is the main entry point to this class. 7993 /// 7994 DAGCombiner(*this, AA, OptLevel).Run(Level); 7995} 7996