DAGCombiner.cpp revision 3adf951364c30d30b528133df1d4cedf2c2b7046
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Compiler.h" 41#include "llvm/Support/CommandLine.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include <algorithm> 45using namespace llvm; 46 47STATISTIC(NodesCombined , "Number of dag nodes combined"); 48STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 49STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 50 51namespace { 52#ifndef NDEBUG 53 static cl::opt<bool> 54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 55 cl::desc("Pop up a window to show dags before the first " 56 "dag combine pass")); 57 static cl::opt<bool> 58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 59 cl::desc("Pop up a window to show dags before the second " 60 "dag combine pass")); 61#else 62 static const bool ViewDAGCombine1 = false; 63 static const bool ViewDAGCombine2 = false; 64#endif 65 66 static cl::opt<bool> 67 CombinerAA("combiner-alias-analysis", cl::Hidden, 68 cl::desc("Turn on alias analysis during testing")); 69 70 static cl::opt<bool> 71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 72 cl::desc("Include global information in alias analysis")); 73 74//------------------------------ DAGCombiner ---------------------------------// 75 76 class VISIBILITY_HIDDEN DAGCombiner { 77 SelectionDAG &DAG; 78 TargetLowering &TLI; 79 bool AfterLegalize; 80 81 // Worklist of all of the nodes that need to be simplified. 82 std::vector<SDNode*> WorkList; 83 84 // AA - Used for DAG load/store alias analysis. 85 AliasAnalysis &AA; 86 87 /// AddUsersToWorkList - When an instruction is simplified, add all users of 88 /// the instruction to the work lists because they might get more simplified 89 /// now. 90 /// 91 void AddUsersToWorkList(SDNode *N) { 92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 93 UI != UE; ++UI) 94 AddToWorkList(*UI); 95 } 96 97 /// removeFromWorkList - remove all instances of N from the worklist. 98 /// 99 void removeFromWorkList(SDNode *N) { 100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 101 WorkList.end()); 102 } 103 104 public: 105 /// AddToWorkList - Add to the work list making sure it's instance is at the 106 /// the back (next to be processed.) 107 void AddToWorkList(SDNode *N) { 108 removeFromWorkList(N); 109 WorkList.push_back(N); 110 } 111 112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 113 bool AddTo = true) { 114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 115 ++NodesCombined; 116 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 118 DOUT << " and " << NumTo-1 << " other values\n"; 119 std::vector<SDNode*> NowDead; 120 DAG.ReplaceAllUsesWith(N, To, &NowDead); 121 122 if (AddTo) { 123 // Push the new nodes and any users onto the worklist 124 for (unsigned i = 0, e = NumTo; i != e; ++i) { 125 AddToWorkList(To[i].Val); 126 AddUsersToWorkList(To[i].Val); 127 } 128 } 129 130 // Nodes can be reintroduced into the worklist. Make sure we do not 131 // process a node that has been replaced. 132 removeFromWorkList(N); 133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 134 removeFromWorkList(NowDead[i]); 135 136 // Finally, since the node is now dead, remove it from the graph. 137 DAG.DeleteNode(N); 138 return SDOperand(N, 0); 139 } 140 141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 142 return CombineTo(N, &Res, 1, AddTo); 143 } 144 145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 146 bool AddTo = true) { 147 SDOperand To[] = { Res0, Res1 }; 148 return CombineTo(N, To, 2, AddTo); 149 } 150 private: 151 152 /// SimplifyDemandedBits - Check the specified integer node value to see if 153 /// it can be simplified or if things it uses can be simplified by bit 154 /// propagation. If so, return true. 155 bool SimplifyDemandedBits(SDOperand Op) { 156 TargetLowering::TargetLoweringOpt TLO(DAG); 157 uint64_t KnownZero, KnownOne; 158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 160 return false; 161 162 // Revisit the node. 163 AddToWorkList(Op.Val); 164 165 // Replace the old value with the new one. 166 ++NodesCombined; 167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 169 DOUT << '\n'; 170 171 std::vector<SDNode*> NowDead; 172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 173 174 // Push the new node and any (possibly new) users onto the worklist. 175 AddToWorkList(TLO.New.Val); 176 AddUsersToWorkList(TLO.New.Val); 177 178 // Nodes can end up on the worklist more than once. Make sure we do 179 // not process a node that has been replaced. 180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 181 removeFromWorkList(NowDead[i]); 182 183 // Finally, if the node is now dead, remove it from the graph. The node 184 // may not be dead if the replacement process recursively simplified to 185 // something else needing this node. 186 if (TLO.Old.Val->use_empty()) { 187 removeFromWorkList(TLO.Old.Val); 188 189 // If the operands of this node are only used by the node, they will now 190 // be dead. Make sure to visit them first to delete dead nodes early. 191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 193 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 194 195 DAG.DeleteNode(TLO.Old.Val); 196 } 197 return true; 198 } 199 200 bool CombineToPreIndexedLoadStore(SDNode *N); 201 bool CombineToPostIndexedLoadStore(SDNode *N); 202 203 204 /// visit - call the node-specific routine that knows how to fold each 205 /// particular type of node. 206 SDOperand visit(SDNode *N); 207 208 // Visitation implementation - Implement dag node combining for different 209 // node types. The semantics are as follows: 210 // Return Value: 211 // SDOperand.Val == 0 - No change was made 212 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 213 // otherwise - N should be replaced by the returned Operand. 214 // 215 SDOperand visitTokenFactor(SDNode *N); 216 SDOperand visitADD(SDNode *N); 217 SDOperand visitSUB(SDNode *N); 218 SDOperand visitADDC(SDNode *N); 219 SDOperand visitADDE(SDNode *N); 220 SDOperand visitMUL(SDNode *N); 221 SDOperand visitSDIV(SDNode *N); 222 SDOperand visitUDIV(SDNode *N); 223 SDOperand visitSREM(SDNode *N); 224 SDOperand visitUREM(SDNode *N); 225 SDOperand visitMULHU(SDNode *N); 226 SDOperand visitMULHS(SDNode *N); 227 SDOperand visitAND(SDNode *N); 228 SDOperand visitOR(SDNode *N); 229 SDOperand visitXOR(SDNode *N); 230 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 231 SDOperand visitSHL(SDNode *N); 232 SDOperand visitSRA(SDNode *N); 233 SDOperand visitSRL(SDNode *N); 234 SDOperand visitCTLZ(SDNode *N); 235 SDOperand visitCTTZ(SDNode *N); 236 SDOperand visitCTPOP(SDNode *N); 237 SDOperand visitSELECT(SDNode *N); 238 SDOperand visitSELECT_CC(SDNode *N); 239 SDOperand visitSETCC(SDNode *N); 240 SDOperand visitSIGN_EXTEND(SDNode *N); 241 SDOperand visitZERO_EXTEND(SDNode *N); 242 SDOperand visitANY_EXTEND(SDNode *N); 243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 244 SDOperand visitTRUNCATE(SDNode *N); 245 SDOperand visitBIT_CONVERT(SDNode *N); 246 SDOperand visitVBIT_CONVERT(SDNode *N); 247 SDOperand visitFADD(SDNode *N); 248 SDOperand visitFSUB(SDNode *N); 249 SDOperand visitFMUL(SDNode *N); 250 SDOperand visitFDIV(SDNode *N); 251 SDOperand visitFREM(SDNode *N); 252 SDOperand visitFCOPYSIGN(SDNode *N); 253 SDOperand visitSINT_TO_FP(SDNode *N); 254 SDOperand visitUINT_TO_FP(SDNode *N); 255 SDOperand visitFP_TO_SINT(SDNode *N); 256 SDOperand visitFP_TO_UINT(SDNode *N); 257 SDOperand visitFP_ROUND(SDNode *N); 258 SDOperand visitFP_ROUND_INREG(SDNode *N); 259 SDOperand visitFP_EXTEND(SDNode *N); 260 SDOperand visitFNEG(SDNode *N); 261 SDOperand visitFABS(SDNode *N); 262 SDOperand visitBRCOND(SDNode *N); 263 SDOperand visitBR_CC(SDNode *N); 264 SDOperand visitLOAD(SDNode *N); 265 SDOperand visitSTORE(SDNode *N); 266 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 267 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 268 SDOperand visitVBUILD_VECTOR(SDNode *N); 269 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 270 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 271 272 SDOperand XformToShuffleWithZero(SDNode *N); 273 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 274 275 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 276 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 277 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 278 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 279 SDOperand N3, ISD::CondCode CC, 280 bool NotExtCompare = false); 281 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 282 ISD::CondCode Cond, bool foldBooleans = true); 283 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 284 SDOperand BuildSDIV(SDNode *N); 285 SDOperand BuildUDIV(SDNode *N); 286 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 287 SDOperand ReduceLoadWidth(SDNode *N); 288 289 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 290 /// looking for aliasing nodes and adding them to the Aliases vector. 291 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 292 SmallVector<SDOperand, 8> &Aliases); 293 294 /// isAlias - Return true if there is any possibility that the two addresses 295 /// overlap. 296 bool isAlias(SDOperand Ptr1, int64_t Size1, 297 const Value *SrcValue1, int SrcValueOffset1, 298 SDOperand Ptr2, int64_t Size2, 299 const Value *SrcValue2, int SrcValueOffset2); 300 301 /// FindAliasInfo - Extracts the relevant alias information from the memory 302 /// node. Returns true if the operand was a load. 303 bool FindAliasInfo(SDNode *N, 304 SDOperand &Ptr, int64_t &Size, 305 const Value *&SrcValue, int &SrcValueOffset); 306 307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 308 /// looking for a better chain (aliasing node.) 309 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 310 311public: 312 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 313 : DAG(D), 314 TLI(D.getTargetLoweringInfo()), 315 AfterLegalize(false), 316 AA(A) {} 317 318 /// Run - runs the dag combiner on all nodes in the work list 319 void Run(bool RunningAfterLegalize); 320 }; 321} 322 323//===----------------------------------------------------------------------===// 324// TargetLowering::DAGCombinerInfo implementation 325//===----------------------------------------------------------------------===// 326 327void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 328 ((DAGCombiner*)DC)->AddToWorkList(N); 329} 330 331SDOperand TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 333 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 334} 335 336SDOperand TargetLowering::DAGCombinerInfo:: 337CombineTo(SDNode *N, SDOperand Res) { 338 return ((DAGCombiner*)DC)->CombineTo(N, Res); 339} 340 341 342SDOperand TargetLowering::DAGCombinerInfo:: 343CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 344 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 345} 346 347 348//===----------------------------------------------------------------------===// 349// Helper Functions 350//===----------------------------------------------------------------------===// 351 352/// isNegatibleForFree - Return 1 if we can compute the negated form of the 353/// specified expression for the same cost as the expression itself, or 2 if we 354/// can compute the negated form more cheaply than the expression itself. 355static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 356 // fneg is removable even if it has multiple uses. 357 if (Op.getOpcode() == ISD::FNEG) return 2; 358 359 // Don't allow anything with multiple uses. 360 if (!Op.hasOneUse()) return 0; 361 362 // Don't recurse exponentially. 363 if (Depth > 6) return 0; 364 365 switch (Op.getOpcode()) { 366 default: return false; 367 case ISD::ConstantFP: 368 return 1; 369 case ISD::FADD: 370 // FIXME: determine better conditions for this xform. 371 if (!UnsafeFPMath) return 0; 372 373 // -(A+B) -> -A - B 374 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 375 return V; 376 // -(A+B) -> -B - A 377 return isNegatibleForFree(Op.getOperand(1), Depth+1); 378 case ISD::FSUB: 379 // We can't turn -(A-B) into B-A when we honor signed zeros. 380 if (!UnsafeFPMath) return 0; 381 382 // -(A-B) -> B-A 383 return 1; 384 385 case ISD::FMUL: 386 case ISD::FDIV: 387 if (HonorSignDependentRoundingFPMath()) return 0; 388 389 // -(X*Y) -> (-X * Y) or (X*-Y) 390 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 391 return V; 392 393 return isNegatibleForFree(Op.getOperand(1), Depth+1); 394 395 case ISD::FP_EXTEND: 396 case ISD::FP_ROUND: 397 case ISD::FSIN: 398 return isNegatibleForFree(Op.getOperand(0), Depth+1); 399 } 400} 401 402/// GetNegatedExpression - If isNegatibleForFree returns true, this function 403/// returns the newly negated expression. 404static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 405 unsigned Depth = 0) { 406 // fneg is removable even if it has multiple uses. 407 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 408 409 // Don't allow anything with multiple uses. 410 assert(Op.hasOneUse() && "Unknown reuse!"); 411 412 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 413 switch (Op.getOpcode()) { 414 default: assert(0 && "Unknown code"); 415 case ISD::ConstantFP: 416 return DAG.getConstantFP(-cast<ConstantFPSDNode>(Op)->getValue(), 417 Op.getValueType()); 418 case ISD::FADD: 419 // FIXME: determine better conditions for this xform. 420 assert(UnsafeFPMath); 421 422 // -(A+B) -> -A - B 423 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 424 return DAG.getNode(ISD::FSUB, Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 426 Op.getOperand(1)); 427 // -(A+B) -> -B - A 428 return DAG.getNode(ISD::FSUB, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 430 Op.getOperand(0)); 431 case ISD::FSUB: 432 // We can't turn -(A-B) into B-A when we honor signed zeros. 433 assert(UnsafeFPMath); 434 435 // -(A-B) -> B-A 436 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 437 Op.getOperand(0)); 438 439 case ISD::FMUL: 440 case ISD::FDIV: 441 assert(!HonorSignDependentRoundingFPMath()); 442 443 // -(X*Y) -> -X * Y 444 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 445 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 446 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 447 Op.getOperand(1)); 448 449 // -(X*Y) -> X * -Y 450 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 451 Op.getOperand(0), 452 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 453 454 case ISD::FP_EXTEND: 455 case ISD::FP_ROUND: 456 case ISD::FSIN: 457 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 458 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 459 } 460} 461 462 463// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 464// that selects between the values 1 and 0, making it equivalent to a setcc. 465// Also, set the incoming LHS, RHS, and CC references to the appropriate 466// nodes based on the type of node we are checking. This simplifies life a 467// bit for the callers. 468static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 469 SDOperand &CC) { 470 if (N.getOpcode() == ISD::SETCC) { 471 LHS = N.getOperand(0); 472 RHS = N.getOperand(1); 473 CC = N.getOperand(2); 474 return true; 475 } 476 if (N.getOpcode() == ISD::SELECT_CC && 477 N.getOperand(2).getOpcode() == ISD::Constant && 478 N.getOperand(3).getOpcode() == ISD::Constant && 479 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 480 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 481 LHS = N.getOperand(0); 482 RHS = N.getOperand(1); 483 CC = N.getOperand(4); 484 return true; 485 } 486 return false; 487} 488 489// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 490// one use. If this is true, it allows the users to invert the operation for 491// free when it is profitable to do so. 492static bool isOneUseSetCC(SDOperand N) { 493 SDOperand N0, N1, N2; 494 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 495 return true; 496 return false; 497} 498 499SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 500 MVT::ValueType VT = N0.getValueType(); 501 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 502 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 506 AddToWorkList(OpNode.Val); 507 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 508 } else if (N0.hasOneUse()) { 509 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 510 AddToWorkList(OpNode.Val); 511 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 512 } 513 } 514 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 515 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 516 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 517 if (isa<ConstantSDNode>(N0)) { 518 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 519 AddToWorkList(OpNode.Val); 520 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 521 } else if (N1.hasOneUse()) { 522 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 523 AddToWorkList(OpNode.Val); 524 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 525 } 526 } 527 return SDOperand(); 528} 529 530//===----------------------------------------------------------------------===// 531// Main DAG Combiner implementation 532//===----------------------------------------------------------------------===// 533 534void DAGCombiner::Run(bool RunningAfterLegalize) { 535 // set the instance variable, so that the various visit routines may use it. 536 AfterLegalize = RunningAfterLegalize; 537 538 // Add all the dag nodes to the worklist. 539 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 540 E = DAG.allnodes_end(); I != E; ++I) 541 WorkList.push_back(I); 542 543 // Create a dummy node (which is not added to allnodes), that adds a reference 544 // to the root node, preventing it from being deleted, and tracking any 545 // changes of the root. 546 HandleSDNode Dummy(DAG.getRoot()); 547 548 // The root of the dag may dangle to deleted nodes until the dag combiner is 549 // done. Set it to null to avoid confusion. 550 DAG.setRoot(SDOperand()); 551 552 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 553 TargetLowering::DAGCombinerInfo 554 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 555 556 // while the worklist isn't empty, inspect the node on the end of it and 557 // try and combine it. 558 while (!WorkList.empty()) { 559 SDNode *N = WorkList.back(); 560 WorkList.pop_back(); 561 562 // If N has no uses, it is dead. Make sure to revisit all N's operands once 563 // N is deleted from the DAG, since they too may now be dead or may have a 564 // reduced number of uses, allowing other xforms. 565 if (N->use_empty() && N != &Dummy) { 566 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 567 AddToWorkList(N->getOperand(i).Val); 568 569 DAG.DeleteNode(N); 570 continue; 571 } 572 573 SDOperand RV = visit(N); 574 575 // If nothing happened, try a target-specific DAG combine. 576 if (RV.Val == 0) { 577 assert(N->getOpcode() != ISD::DELETED_NODE && 578 "Node was deleted but visit returned NULL!"); 579 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 580 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 581 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 582 } 583 584 if (RV.Val) { 585 ++NodesCombined; 586 // If we get back the same node we passed in, rather than a new node or 587 // zero, we know that the node must have defined multiple values and 588 // CombineTo was used. Since CombineTo takes care of the worklist 589 // mechanics for us, we have no work to do in this case. 590 if (RV.Val != N) { 591 assert(N->getOpcode() != ISD::DELETED_NODE && 592 RV.Val->getOpcode() != ISD::DELETED_NODE && 593 "Node was deleted but visit returned new node!"); 594 595 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 596 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 597 DOUT << '\n'; 598 std::vector<SDNode*> NowDead; 599 if (N->getNumValues() == RV.Val->getNumValues()) 600 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 601 else { 602 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 603 SDOperand OpV = RV; 604 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 605 } 606 607 // Push the new node and any users onto the worklist 608 AddToWorkList(RV.Val); 609 AddUsersToWorkList(RV.Val); 610 611 // Nodes can be reintroduced into the worklist. Make sure we do not 612 // process a node that has been replaced. 613 removeFromWorkList(N); 614 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 615 removeFromWorkList(NowDead[i]); 616 617 // Finally, since the node is now dead, remove it from the graph. 618 DAG.DeleteNode(N); 619 } 620 } 621 } 622 623 // If the root changed (e.g. it was a dead load, update the root). 624 DAG.setRoot(Dummy.getValue()); 625} 626 627SDOperand DAGCombiner::visit(SDNode *N) { 628 switch(N->getOpcode()) { 629 default: break; 630 case ISD::TokenFactor: return visitTokenFactor(N); 631 case ISD::ADD: return visitADD(N); 632 case ISD::SUB: return visitSUB(N); 633 case ISD::ADDC: return visitADDC(N); 634 case ISD::ADDE: return visitADDE(N); 635 case ISD::MUL: return visitMUL(N); 636 case ISD::SDIV: return visitSDIV(N); 637 case ISD::UDIV: return visitUDIV(N); 638 case ISD::SREM: return visitSREM(N); 639 case ISD::UREM: return visitUREM(N); 640 case ISD::MULHU: return visitMULHU(N); 641 case ISD::MULHS: return visitMULHS(N); 642 case ISD::AND: return visitAND(N); 643 case ISD::OR: return visitOR(N); 644 case ISD::XOR: return visitXOR(N); 645 case ISD::SHL: return visitSHL(N); 646 case ISD::SRA: return visitSRA(N); 647 case ISD::SRL: return visitSRL(N); 648 case ISD::CTLZ: return visitCTLZ(N); 649 case ISD::CTTZ: return visitCTTZ(N); 650 case ISD::CTPOP: return visitCTPOP(N); 651 case ISD::SELECT: return visitSELECT(N); 652 case ISD::SELECT_CC: return visitSELECT_CC(N); 653 case ISD::SETCC: return visitSETCC(N); 654 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 655 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 656 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 657 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 658 case ISD::TRUNCATE: return visitTRUNCATE(N); 659 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 660 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 661 case ISD::FADD: return visitFADD(N); 662 case ISD::FSUB: return visitFSUB(N); 663 case ISD::FMUL: return visitFMUL(N); 664 case ISD::FDIV: return visitFDIV(N); 665 case ISD::FREM: return visitFREM(N); 666 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 667 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 668 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 669 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 670 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 671 case ISD::FP_ROUND: return visitFP_ROUND(N); 672 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 673 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 674 case ISD::FNEG: return visitFNEG(N); 675 case ISD::FABS: return visitFABS(N); 676 case ISD::BRCOND: return visitBRCOND(N); 677 case ISD::BR_CC: return visitBR_CC(N); 678 case ISD::LOAD: return visitLOAD(N); 679 case ISD::STORE: return visitSTORE(N); 680 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 681 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 682 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 683 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 684 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 685 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 686 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 687 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 688 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 689 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 690 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 691 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 692 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 693 } 694 return SDOperand(); 695} 696 697/// getInputChainForNode - Given a node, return its input chain if it has one, 698/// otherwise return a null sd operand. 699static SDOperand getInputChainForNode(SDNode *N) { 700 if (unsigned NumOps = N->getNumOperands()) { 701 if (N->getOperand(0).getValueType() == MVT::Other) 702 return N->getOperand(0); 703 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 704 return N->getOperand(NumOps-1); 705 for (unsigned i = 1; i < NumOps-1; ++i) 706 if (N->getOperand(i).getValueType() == MVT::Other) 707 return N->getOperand(i); 708 } 709 return SDOperand(0, 0); 710} 711 712SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 713 // If N has two operands, where one has an input chain equal to the other, 714 // the 'other' chain is redundant. 715 if (N->getNumOperands() == 2) { 716 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 717 return N->getOperand(0); 718 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 719 return N->getOperand(1); 720 } 721 722 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 723 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 724 SmallPtrSet<SDNode*, 16> SeenOps; 725 bool Changed = false; // If we should replace this token factor. 726 727 // Start out with this token factor. 728 TFs.push_back(N); 729 730 // Iterate through token factors. The TFs grows when new token factors are 731 // encountered. 732 for (unsigned i = 0; i < TFs.size(); ++i) { 733 SDNode *TF = TFs[i]; 734 735 // Check each of the operands. 736 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 737 SDOperand Op = TF->getOperand(i); 738 739 switch (Op.getOpcode()) { 740 case ISD::EntryToken: 741 // Entry tokens don't need to be added to the list. They are 742 // rededundant. 743 Changed = true; 744 break; 745 746 case ISD::TokenFactor: 747 if ((CombinerAA || Op.hasOneUse()) && 748 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 749 // Queue up for processing. 750 TFs.push_back(Op.Val); 751 // Clean up in case the token factor is removed. 752 AddToWorkList(Op.Val); 753 Changed = true; 754 break; 755 } 756 // Fall thru 757 758 default: 759 // Only add if it isn't already in the list. 760 if (SeenOps.insert(Op.Val)) 761 Ops.push_back(Op); 762 else 763 Changed = true; 764 break; 765 } 766 } 767 } 768 769 SDOperand Result; 770 771 // If we've change things around then replace token factor. 772 if (Changed) { 773 if (Ops.size() == 0) { 774 // The entry token is the only possible outcome. 775 Result = DAG.getEntryNode(); 776 } else { 777 // New and improved token factor. 778 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 779 } 780 781 // Don't add users to work list. 782 return CombineTo(N, Result, false); 783 } 784 785 return Result; 786} 787 788static 789SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 790 MVT::ValueType VT = N0.getValueType(); 791 SDOperand N00 = N0.getOperand(0); 792 SDOperand N01 = N0.getOperand(1); 793 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 794 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 795 isa<ConstantSDNode>(N00.getOperand(1))) { 796 N0 = DAG.getNode(ISD::ADD, VT, 797 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 798 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 799 return DAG.getNode(ISD::ADD, VT, N0, N1); 800 } 801 return SDOperand(); 802} 803 804SDOperand DAGCombiner::visitADD(SDNode *N) { 805 SDOperand N0 = N->getOperand(0); 806 SDOperand N1 = N->getOperand(1); 807 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 808 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 809 MVT::ValueType VT = N0.getValueType(); 810 811 // fold (add c1, c2) -> c1+c2 812 if (N0C && N1C) 813 return DAG.getNode(ISD::ADD, VT, N0, N1); 814 // canonicalize constant to RHS 815 if (N0C && !N1C) 816 return DAG.getNode(ISD::ADD, VT, N1, N0); 817 // fold (add x, 0) -> x 818 if (N1C && N1C->isNullValue()) 819 return N0; 820 // fold ((c1-A)+c2) -> (c1+c2)-A 821 if (N1C && N0.getOpcode() == ISD::SUB) 822 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 823 return DAG.getNode(ISD::SUB, VT, 824 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 825 N0.getOperand(1)); 826 // reassociate add 827 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 828 if (RADD.Val != 0) 829 return RADD; 830 // fold ((0-A) + B) -> B-A 831 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 832 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 833 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 834 // fold (A + (0-B)) -> A-B 835 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 836 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 837 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 838 // fold (A+(B-A)) -> B 839 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 840 return N1.getOperand(0); 841 842 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 843 return SDOperand(N, 0); 844 845 // fold (a+b) -> (a|b) iff a and b share no bits. 846 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 847 uint64_t LHSZero, LHSOne; 848 uint64_t RHSZero, RHSOne; 849 uint64_t Mask = MVT::getIntVTBitMask(VT); 850 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 851 if (LHSZero) { 852 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 853 854 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 855 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 856 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 857 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 858 return DAG.getNode(ISD::OR, VT, N0, N1); 859 } 860 } 861 862 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 863 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 864 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 865 if (Result.Val) return Result; 866 } 867 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 868 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 869 if (Result.Val) return Result; 870 } 871 872 return SDOperand(); 873} 874 875SDOperand DAGCombiner::visitADDC(SDNode *N) { 876 SDOperand N0 = N->getOperand(0); 877 SDOperand N1 = N->getOperand(1); 878 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 879 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 880 MVT::ValueType VT = N0.getValueType(); 881 882 // If the flag result is dead, turn this into an ADD. 883 if (N->hasNUsesOfValue(0, 1)) 884 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 885 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 886 887 // canonicalize constant to RHS. 888 if (N0C && !N1C) { 889 SDOperand Ops[] = { N1, N0 }; 890 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 891 } 892 893 // fold (addc x, 0) -> x + no carry out 894 if (N1C && N1C->isNullValue()) 895 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 896 897 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 898 uint64_t LHSZero, LHSOne; 899 uint64_t RHSZero, RHSOne; 900 uint64_t Mask = MVT::getIntVTBitMask(VT); 901 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 902 if (LHSZero) { 903 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 904 905 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 906 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 907 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 908 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 909 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 910 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 911 } 912 913 return SDOperand(); 914} 915 916SDOperand DAGCombiner::visitADDE(SDNode *N) { 917 SDOperand N0 = N->getOperand(0); 918 SDOperand N1 = N->getOperand(1); 919 SDOperand CarryIn = N->getOperand(2); 920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 922 //MVT::ValueType VT = N0.getValueType(); 923 924 // canonicalize constant to RHS 925 if (N0C && !N1C) { 926 SDOperand Ops[] = { N1, N0, CarryIn }; 927 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 928 } 929 930 // fold (adde x, y, false) -> (addc x, y) 931 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 932 SDOperand Ops[] = { N1, N0 }; 933 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 934 } 935 936 return SDOperand(); 937} 938 939 940 941SDOperand DAGCombiner::visitSUB(SDNode *N) { 942 SDOperand N0 = N->getOperand(0); 943 SDOperand N1 = N->getOperand(1); 944 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 946 MVT::ValueType VT = N0.getValueType(); 947 948 // fold (sub x, x) -> 0 949 if (N0 == N1) 950 return DAG.getConstant(0, N->getValueType(0)); 951 // fold (sub c1, c2) -> c1-c2 952 if (N0C && N1C) 953 return DAG.getNode(ISD::SUB, VT, N0, N1); 954 // fold (sub x, c) -> (add x, -c) 955 if (N1C) 956 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 957 // fold (A+B)-A -> B 958 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 959 return N0.getOperand(1); 960 // fold (A+B)-B -> A 961 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 962 return N0.getOperand(0); 963 return SDOperand(); 964} 965 966SDOperand DAGCombiner::visitMUL(SDNode *N) { 967 SDOperand N0 = N->getOperand(0); 968 SDOperand N1 = N->getOperand(1); 969 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 970 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 971 MVT::ValueType VT = N0.getValueType(); 972 973 // fold (mul c1, c2) -> c1*c2 974 if (N0C && N1C) 975 return DAG.getNode(ISD::MUL, VT, N0, N1); 976 // canonicalize constant to RHS 977 if (N0C && !N1C) 978 return DAG.getNode(ISD::MUL, VT, N1, N0); 979 // fold (mul x, 0) -> 0 980 if (N1C && N1C->isNullValue()) 981 return N1; 982 // fold (mul x, -1) -> 0-x 983 if (N1C && N1C->isAllOnesValue()) 984 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 985 // fold (mul x, (1 << c)) -> x << c 986 if (N1C && isPowerOf2_64(N1C->getValue())) 987 return DAG.getNode(ISD::SHL, VT, N0, 988 DAG.getConstant(Log2_64(N1C->getValue()), 989 TLI.getShiftAmountTy())); 990 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 991 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 992 // FIXME: If the input is something that is easily negated (e.g. a 993 // single-use add), we should put the negate there. 994 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 995 DAG.getNode(ISD::SHL, VT, N0, 996 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 997 TLI.getShiftAmountTy()))); 998 } 999 1000 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1001 if (N1C && N0.getOpcode() == ISD::SHL && 1002 isa<ConstantSDNode>(N0.getOperand(1))) { 1003 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1004 AddToWorkList(C3.Val); 1005 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1006 } 1007 1008 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1009 // use. 1010 { 1011 SDOperand Sh(0,0), Y(0,0); 1012 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1013 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1014 N0.Val->hasOneUse()) { 1015 Sh = N0; Y = N1; 1016 } else if (N1.getOpcode() == ISD::SHL && 1017 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1018 Sh = N1; Y = N0; 1019 } 1020 if (Sh.Val) { 1021 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1022 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1023 } 1024 } 1025 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1026 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1027 isa<ConstantSDNode>(N0.getOperand(1))) { 1028 return DAG.getNode(ISD::ADD, VT, 1029 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1030 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1031 } 1032 1033 // reassociate mul 1034 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1035 if (RMUL.Val != 0) 1036 return RMUL; 1037 return SDOperand(); 1038} 1039 1040SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1041 SDOperand N0 = N->getOperand(0); 1042 SDOperand N1 = N->getOperand(1); 1043 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1044 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1045 MVT::ValueType VT = N->getValueType(0); 1046 1047 // fold (sdiv c1, c2) -> c1/c2 1048 if (N0C && N1C && !N1C->isNullValue()) 1049 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1050 // fold (sdiv X, 1) -> X 1051 if (N1C && N1C->getSignExtended() == 1LL) 1052 return N0; 1053 // fold (sdiv X, -1) -> 0-X 1054 if (N1C && N1C->isAllOnesValue()) 1055 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1056 // If we know the sign bits of both operands are zero, strength reduce to a 1057 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1058 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1059 if (TLI.MaskedValueIsZero(N1, SignBit) && 1060 TLI.MaskedValueIsZero(N0, SignBit)) 1061 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1062 // fold (sdiv X, pow2) -> simple ops after legalize 1063 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1064 (isPowerOf2_64(N1C->getSignExtended()) || 1065 isPowerOf2_64(-N1C->getSignExtended()))) { 1066 // If dividing by powers of two is cheap, then don't perform the following 1067 // fold. 1068 if (TLI.isPow2DivCheap()) 1069 return SDOperand(); 1070 int64_t pow2 = N1C->getSignExtended(); 1071 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1072 unsigned lg2 = Log2_64(abs2); 1073 // Splat the sign bit into the register 1074 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1075 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1076 TLI.getShiftAmountTy())); 1077 AddToWorkList(SGN.Val); 1078 // Add (N0 < 0) ? abs2 - 1 : 0; 1079 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1080 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1081 TLI.getShiftAmountTy())); 1082 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1083 AddToWorkList(SRL.Val); 1084 AddToWorkList(ADD.Val); // Divide by pow2 1085 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1086 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1087 // If we're dividing by a positive value, we're done. Otherwise, we must 1088 // negate the result. 1089 if (pow2 > 0) 1090 return SRA; 1091 AddToWorkList(SRA.Val); 1092 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1093 } 1094 // if integer divide is expensive and we satisfy the requirements, emit an 1095 // alternate sequence. 1096 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1097 !TLI.isIntDivCheap()) { 1098 SDOperand Op = BuildSDIV(N); 1099 if (Op.Val) return Op; 1100 } 1101 return SDOperand(); 1102} 1103 1104SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1105 SDOperand N0 = N->getOperand(0); 1106 SDOperand N1 = N->getOperand(1); 1107 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1108 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1109 MVT::ValueType VT = N->getValueType(0); 1110 1111 // fold (udiv c1, c2) -> c1/c2 1112 if (N0C && N1C && !N1C->isNullValue()) 1113 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1114 // fold (udiv x, (1 << c)) -> x >>u c 1115 if (N1C && isPowerOf2_64(N1C->getValue())) 1116 return DAG.getNode(ISD::SRL, VT, N0, 1117 DAG.getConstant(Log2_64(N1C->getValue()), 1118 TLI.getShiftAmountTy())); 1119 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1120 if (N1.getOpcode() == ISD::SHL) { 1121 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1122 if (isPowerOf2_64(SHC->getValue())) { 1123 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1124 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1125 DAG.getConstant(Log2_64(SHC->getValue()), 1126 ADDVT)); 1127 AddToWorkList(Add.Val); 1128 return DAG.getNode(ISD::SRL, VT, N0, Add); 1129 } 1130 } 1131 } 1132 // fold (udiv x, c) -> alternate 1133 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1134 SDOperand Op = BuildUDIV(N); 1135 if (Op.Val) return Op; 1136 } 1137 return SDOperand(); 1138} 1139 1140SDOperand DAGCombiner::visitSREM(SDNode *N) { 1141 SDOperand N0 = N->getOperand(0); 1142 SDOperand N1 = N->getOperand(1); 1143 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1144 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1145 MVT::ValueType VT = N->getValueType(0); 1146 1147 // fold (srem c1, c2) -> c1%c2 1148 if (N0C && N1C && !N1C->isNullValue()) 1149 return DAG.getNode(ISD::SREM, VT, N0, N1); 1150 // If we know the sign bits of both operands are zero, strength reduce to a 1151 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1152 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1153 if (TLI.MaskedValueIsZero(N1, SignBit) && 1154 TLI.MaskedValueIsZero(N0, SignBit)) 1155 return DAG.getNode(ISD::UREM, VT, N0, N1); 1156 1157 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1158 // the remainder operation. 1159 if (N1C && !N1C->isNullValue()) { 1160 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1161 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1162 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1163 AddToWorkList(Div.Val); 1164 AddToWorkList(Mul.Val); 1165 return Sub; 1166 } 1167 1168 return SDOperand(); 1169} 1170 1171SDOperand DAGCombiner::visitUREM(SDNode *N) { 1172 SDOperand N0 = N->getOperand(0); 1173 SDOperand N1 = N->getOperand(1); 1174 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1175 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1176 MVT::ValueType VT = N->getValueType(0); 1177 1178 // fold (urem c1, c2) -> c1%c2 1179 if (N0C && N1C && !N1C->isNullValue()) 1180 return DAG.getNode(ISD::UREM, VT, N0, N1); 1181 // fold (urem x, pow2) -> (and x, pow2-1) 1182 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1183 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1184 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1185 if (N1.getOpcode() == ISD::SHL) { 1186 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1187 if (isPowerOf2_64(SHC->getValue())) { 1188 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1189 AddToWorkList(Add.Val); 1190 return DAG.getNode(ISD::AND, VT, N0, Add); 1191 } 1192 } 1193 } 1194 1195 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1196 // the remainder operation. 1197 if (N1C && !N1C->isNullValue()) { 1198 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1199 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1200 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1201 AddToWorkList(Div.Val); 1202 AddToWorkList(Mul.Val); 1203 return Sub; 1204 } 1205 1206 return SDOperand(); 1207} 1208 1209SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1210 SDOperand N0 = N->getOperand(0); 1211 SDOperand N1 = N->getOperand(1); 1212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1213 1214 // fold (mulhs x, 0) -> 0 1215 if (N1C && N1C->isNullValue()) 1216 return N1; 1217 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1218 if (N1C && N1C->getValue() == 1) 1219 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1220 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1221 TLI.getShiftAmountTy())); 1222 return SDOperand(); 1223} 1224 1225SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1226 SDOperand N0 = N->getOperand(0); 1227 SDOperand N1 = N->getOperand(1); 1228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1229 1230 // fold (mulhu x, 0) -> 0 1231 if (N1C && N1C->isNullValue()) 1232 return N1; 1233 // fold (mulhu x, 1) -> 0 1234 if (N1C && N1C->getValue() == 1) 1235 return DAG.getConstant(0, N0.getValueType()); 1236 return SDOperand(); 1237} 1238 1239/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1240/// two operands of the same opcode, try to simplify it. 1241SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1242 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1243 MVT::ValueType VT = N0.getValueType(); 1244 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1245 1246 // For each of OP in AND/OR/XOR: 1247 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1248 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1249 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1250 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1251 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1252 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1253 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1254 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1255 N0.getOperand(0).getValueType(), 1256 N0.getOperand(0), N1.getOperand(0)); 1257 AddToWorkList(ORNode.Val); 1258 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1259 } 1260 1261 // For each of OP in SHL/SRL/SRA/AND... 1262 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1263 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1264 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1265 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1266 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1267 N0.getOperand(1) == N1.getOperand(1)) { 1268 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1269 N0.getOperand(0).getValueType(), 1270 N0.getOperand(0), N1.getOperand(0)); 1271 AddToWorkList(ORNode.Val); 1272 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1273 } 1274 1275 return SDOperand(); 1276} 1277 1278SDOperand DAGCombiner::visitAND(SDNode *N) { 1279 SDOperand N0 = N->getOperand(0); 1280 SDOperand N1 = N->getOperand(1); 1281 SDOperand LL, LR, RL, RR, CC0, CC1; 1282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1284 MVT::ValueType VT = N1.getValueType(); 1285 1286 // fold (and c1, c2) -> c1&c2 1287 if (N0C && N1C) 1288 return DAG.getNode(ISD::AND, VT, N0, N1); 1289 // canonicalize constant to RHS 1290 if (N0C && !N1C) 1291 return DAG.getNode(ISD::AND, VT, N1, N0); 1292 // fold (and x, -1) -> x 1293 if (N1C && N1C->isAllOnesValue()) 1294 return N0; 1295 // if (and x, c) is known to be zero, return 0 1296 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1297 return DAG.getConstant(0, VT); 1298 // reassociate and 1299 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1300 if (RAND.Val != 0) 1301 return RAND; 1302 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1303 if (N1C && N0.getOpcode() == ISD::OR) 1304 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1305 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1306 return N1; 1307 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1308 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1309 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1310 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1311 ~N1C->getValue() & InMask)) { 1312 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1313 N0.getOperand(0)); 1314 1315 // Replace uses of the AND with uses of the Zero extend node. 1316 CombineTo(N, Zext); 1317 1318 // We actually want to replace all uses of the any_extend with the 1319 // zero_extend, to avoid duplicating things. This will later cause this 1320 // AND to be folded. 1321 CombineTo(N0.Val, Zext); 1322 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1323 } 1324 } 1325 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1326 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1327 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1328 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1329 1330 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1331 MVT::isInteger(LL.getValueType())) { 1332 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1333 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1334 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1335 AddToWorkList(ORNode.Val); 1336 return DAG.getSetCC(VT, ORNode, LR, Op1); 1337 } 1338 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1339 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1340 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1341 AddToWorkList(ANDNode.Val); 1342 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1343 } 1344 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1345 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1346 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1347 AddToWorkList(ORNode.Val); 1348 return DAG.getSetCC(VT, ORNode, LR, Op1); 1349 } 1350 } 1351 // canonicalize equivalent to ll == rl 1352 if (LL == RR && LR == RL) { 1353 Op1 = ISD::getSetCCSwappedOperands(Op1); 1354 std::swap(RL, RR); 1355 } 1356 if (LL == RL && LR == RR) { 1357 bool isInteger = MVT::isInteger(LL.getValueType()); 1358 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1359 if (Result != ISD::SETCC_INVALID) 1360 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1361 } 1362 } 1363 1364 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1365 if (N0.getOpcode() == N1.getOpcode()) { 1366 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1367 if (Tmp.Val) return Tmp; 1368 } 1369 1370 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1371 // fold (and (sra)) -> (and (srl)) when possible. 1372 if (!MVT::isVector(VT) && 1373 SimplifyDemandedBits(SDOperand(N, 0))) 1374 return SDOperand(N, 0); 1375 // fold (zext_inreg (extload x)) -> (zextload x) 1376 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1377 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1378 MVT::ValueType EVT = LN0->getLoadedVT(); 1379 // If we zero all the possible extended bits, then we can turn this into 1380 // a zextload if we are running before legalize or the operation is legal. 1381 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1382 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1383 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1384 LN0->getBasePtr(), LN0->getSrcValue(), 1385 LN0->getSrcValueOffset(), EVT, 1386 LN0->isVolatile(), 1387 LN0->getAlignment()); 1388 AddToWorkList(N); 1389 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1390 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1391 } 1392 } 1393 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1394 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1395 N0.hasOneUse()) { 1396 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1397 MVT::ValueType EVT = LN0->getLoadedVT(); 1398 // If we zero all the possible extended bits, then we can turn this into 1399 // a zextload if we are running before legalize or the operation is legal. 1400 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1401 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1402 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1403 LN0->getBasePtr(), LN0->getSrcValue(), 1404 LN0->getSrcValueOffset(), EVT, 1405 LN0->isVolatile(), 1406 LN0->getAlignment()); 1407 AddToWorkList(N); 1408 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1409 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1410 } 1411 } 1412 1413 // fold (and (load x), 255) -> (zextload x, i8) 1414 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1415 if (N1C && N0.getOpcode() == ISD::LOAD) { 1416 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1417 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1418 LN0->getAddressingMode() == ISD::UNINDEXED && 1419 N0.hasOneUse()) { 1420 MVT::ValueType EVT, LoadedVT; 1421 if (N1C->getValue() == 255) 1422 EVT = MVT::i8; 1423 else if (N1C->getValue() == 65535) 1424 EVT = MVT::i16; 1425 else if (N1C->getValue() == ~0U) 1426 EVT = MVT::i32; 1427 else 1428 EVT = MVT::Other; 1429 1430 LoadedVT = LN0->getLoadedVT(); 1431 if (EVT != MVT::Other && LoadedVT > EVT && 1432 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1433 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1434 // For big endian targets, we need to add an offset to the pointer to 1435 // load the correct bytes. For little endian systems, we merely need to 1436 // read fewer bytes from the same pointer. 1437 unsigned PtrOff = 1438 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1439 SDOperand NewPtr = LN0->getBasePtr(); 1440 if (!TLI.isLittleEndian()) 1441 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1442 DAG.getConstant(PtrOff, PtrType)); 1443 AddToWorkList(NewPtr.Val); 1444 SDOperand Load = 1445 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1446 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1447 LN0->isVolatile(), LN0->getAlignment()); 1448 AddToWorkList(N); 1449 CombineTo(N0.Val, Load, Load.getValue(1)); 1450 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1451 } 1452 } 1453 } 1454 1455 return SDOperand(); 1456} 1457 1458SDOperand DAGCombiner::visitOR(SDNode *N) { 1459 SDOperand N0 = N->getOperand(0); 1460 SDOperand N1 = N->getOperand(1); 1461 SDOperand LL, LR, RL, RR, CC0, CC1; 1462 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1463 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1464 MVT::ValueType VT = N1.getValueType(); 1465 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1466 1467 // fold (or c1, c2) -> c1|c2 1468 if (N0C && N1C) 1469 return DAG.getNode(ISD::OR, VT, N0, N1); 1470 // canonicalize constant to RHS 1471 if (N0C && !N1C) 1472 return DAG.getNode(ISD::OR, VT, N1, N0); 1473 // fold (or x, 0) -> x 1474 if (N1C && N1C->isNullValue()) 1475 return N0; 1476 // fold (or x, -1) -> -1 1477 if (N1C && N1C->isAllOnesValue()) 1478 return N1; 1479 // fold (or x, c) -> c iff (x & ~c) == 0 1480 if (N1C && 1481 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1482 return N1; 1483 // reassociate or 1484 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1485 if (ROR.Val != 0) 1486 return ROR; 1487 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1488 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1489 isa<ConstantSDNode>(N0.getOperand(1))) { 1490 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1491 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1492 N1), 1493 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1494 } 1495 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1496 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1497 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1498 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1499 1500 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1501 MVT::isInteger(LL.getValueType())) { 1502 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1503 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1504 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1505 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1506 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1507 AddToWorkList(ORNode.Val); 1508 return DAG.getSetCC(VT, ORNode, LR, Op1); 1509 } 1510 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1511 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1512 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1513 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1514 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1515 AddToWorkList(ANDNode.Val); 1516 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1517 } 1518 } 1519 // canonicalize equivalent to ll == rl 1520 if (LL == RR && LR == RL) { 1521 Op1 = ISD::getSetCCSwappedOperands(Op1); 1522 std::swap(RL, RR); 1523 } 1524 if (LL == RL && LR == RR) { 1525 bool isInteger = MVT::isInteger(LL.getValueType()); 1526 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1527 if (Result != ISD::SETCC_INVALID) 1528 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1529 } 1530 } 1531 1532 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1533 if (N0.getOpcode() == N1.getOpcode()) { 1534 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1535 if (Tmp.Val) return Tmp; 1536 } 1537 1538 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1539 if (N0.getOpcode() == ISD::AND && 1540 N1.getOpcode() == ISD::AND && 1541 N0.getOperand(1).getOpcode() == ISD::Constant && 1542 N1.getOperand(1).getOpcode() == ISD::Constant && 1543 // Don't increase # computations. 1544 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1545 // We can only do this xform if we know that bits from X that are set in C2 1546 // but not in C1 are already zero. Likewise for Y. 1547 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1548 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1549 1550 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1551 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1552 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1553 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1554 } 1555 } 1556 1557 1558 // See if this is some rotate idiom. 1559 if (SDNode *Rot = MatchRotate(N0, N1)) 1560 return SDOperand(Rot, 0); 1561 1562 return SDOperand(); 1563} 1564 1565 1566/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1567static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1568 if (Op.getOpcode() == ISD::AND) { 1569 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1570 Mask = Op.getOperand(1); 1571 Op = Op.getOperand(0); 1572 } else { 1573 return false; 1574 } 1575 } 1576 1577 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1578 Shift = Op; 1579 return true; 1580 } 1581 return false; 1582} 1583 1584 1585// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1586// idioms for rotate, and if the target supports rotation instructions, generate 1587// a rot[lr]. 1588SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1589 // Must be a legal type. Expanded an promoted things won't work with rotates. 1590 MVT::ValueType VT = LHS.getValueType(); 1591 if (!TLI.isTypeLegal(VT)) return 0; 1592 1593 // The target must have at least one rotate flavor. 1594 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1595 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1596 if (!HasROTL && !HasROTR) return 0; 1597 1598 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1599 SDOperand LHSShift; // The shift. 1600 SDOperand LHSMask; // AND value if any. 1601 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1602 return 0; // Not part of a rotate. 1603 1604 SDOperand RHSShift; // The shift. 1605 SDOperand RHSMask; // AND value if any. 1606 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1607 return 0; // Not part of a rotate. 1608 1609 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1610 return 0; // Not shifting the same value. 1611 1612 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1613 return 0; // Shifts must disagree. 1614 1615 // Canonicalize shl to left side in a shl/srl pair. 1616 if (RHSShift.getOpcode() == ISD::SHL) { 1617 std::swap(LHS, RHS); 1618 std::swap(LHSShift, RHSShift); 1619 std::swap(LHSMask , RHSMask ); 1620 } 1621 1622 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1623 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1624 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1625 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1626 1627 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1628 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1629 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1630 RHSShiftAmt.getOpcode() == ISD::Constant) { 1631 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1632 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1633 if ((LShVal + RShVal) != OpSizeInBits) 1634 return 0; 1635 1636 SDOperand Rot; 1637 if (HasROTL) 1638 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1639 else 1640 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1641 1642 // If there is an AND of either shifted operand, apply it to the result. 1643 if (LHSMask.Val || RHSMask.Val) { 1644 uint64_t Mask = MVT::getIntVTBitMask(VT); 1645 1646 if (LHSMask.Val) { 1647 uint64_t RHSBits = (1ULL << LShVal)-1; 1648 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1649 } 1650 if (RHSMask.Val) { 1651 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1652 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1653 } 1654 1655 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1656 } 1657 1658 return Rot.Val; 1659 } 1660 1661 // If there is a mask here, and we have a variable shift, we can't be sure 1662 // that we're masking out the right stuff. 1663 if (LHSMask.Val || RHSMask.Val) 1664 return 0; 1665 1666 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1667 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1668 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1669 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1670 if (ConstantSDNode *SUBC = 1671 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1672 if (SUBC->getValue() == OpSizeInBits) 1673 if (HasROTL) 1674 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1675 else 1676 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1677 } 1678 } 1679 1680 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1681 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1682 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1683 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1684 if (ConstantSDNode *SUBC = 1685 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1686 if (SUBC->getValue() == OpSizeInBits) 1687 if (HasROTL) 1688 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1689 else 1690 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1691 } 1692 } 1693 1694 // Look for sign/zext/any-extended cases: 1695 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1696 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1697 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1698 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1699 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1700 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1701 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1702 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1703 if (RExtOp0.getOpcode() == ISD::SUB && 1704 RExtOp0.getOperand(1) == LExtOp0) { 1705 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1706 // (rotr x, y) 1707 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1708 // (rotl x, (sub 32, y)) 1709 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 1710 if (SUBC->getValue() == OpSizeInBits) { 1711 if (HasROTL) 1712 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1713 else 1714 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1715 } 1716 } 1717 } else if (LExtOp0.getOpcode() == ISD::SUB && 1718 RExtOp0 == LExtOp0.getOperand(1)) { 1719 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1720 // (rotl x, y) 1721 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 1722 // (rotr x, (sub 32, y)) 1723 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 1724 if (SUBC->getValue() == OpSizeInBits) { 1725 if (HasROTL) 1726 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 1727 else 1728 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1729 } 1730 } 1731 } 1732 } 1733 1734 return 0; 1735} 1736 1737 1738SDOperand DAGCombiner::visitXOR(SDNode *N) { 1739 SDOperand N0 = N->getOperand(0); 1740 SDOperand N1 = N->getOperand(1); 1741 SDOperand LHS, RHS, CC; 1742 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1743 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1744 MVT::ValueType VT = N0.getValueType(); 1745 1746 // fold (xor c1, c2) -> c1^c2 1747 if (N0C && N1C) 1748 return DAG.getNode(ISD::XOR, VT, N0, N1); 1749 // canonicalize constant to RHS 1750 if (N0C && !N1C) 1751 return DAG.getNode(ISD::XOR, VT, N1, N0); 1752 // fold (xor x, 0) -> x 1753 if (N1C && N1C->isNullValue()) 1754 return N0; 1755 // reassociate xor 1756 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1757 if (RXOR.Val != 0) 1758 return RXOR; 1759 // fold !(x cc y) -> (x !cc y) 1760 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1761 bool isInt = MVT::isInteger(LHS.getValueType()); 1762 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1763 isInt); 1764 if (N0.getOpcode() == ISD::SETCC) 1765 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1766 if (N0.getOpcode() == ISD::SELECT_CC) 1767 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1768 assert(0 && "Unhandled SetCC Equivalent!"); 1769 abort(); 1770 } 1771 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1772 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1773 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1774 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1775 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1776 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1777 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1778 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1779 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1780 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1781 } 1782 } 1783 // fold !(x or y) -> (!x and !y) iff x or y are constants 1784 if (N1C && N1C->isAllOnesValue() && 1785 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1786 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1787 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1788 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1789 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1790 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1791 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1792 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1793 } 1794 } 1795 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1796 if (N1C && N0.getOpcode() == ISD::XOR) { 1797 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1798 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1799 if (N00C) 1800 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1801 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1802 if (N01C) 1803 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1804 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1805 } 1806 // fold (xor x, x) -> 0 1807 if (N0 == N1) { 1808 if (!MVT::isVector(VT)) { 1809 return DAG.getConstant(0, VT); 1810 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1811 // Produce a vector of zeros. 1812 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1813 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1814 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1815 } 1816 } 1817 1818 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1819 if (N0.getOpcode() == N1.getOpcode()) { 1820 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1821 if (Tmp.Val) return Tmp; 1822 } 1823 1824 // Simplify the expression using non-local knowledge. 1825 if (!MVT::isVector(VT) && 1826 SimplifyDemandedBits(SDOperand(N, 0))) 1827 return SDOperand(N, 0); 1828 1829 return SDOperand(); 1830} 1831 1832SDOperand DAGCombiner::visitSHL(SDNode *N) { 1833 SDOperand N0 = N->getOperand(0); 1834 SDOperand N1 = N->getOperand(1); 1835 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1837 MVT::ValueType VT = N0.getValueType(); 1838 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1839 1840 // fold (shl c1, c2) -> c1<<c2 1841 if (N0C && N1C) 1842 return DAG.getNode(ISD::SHL, VT, N0, N1); 1843 // fold (shl 0, x) -> 0 1844 if (N0C && N0C->isNullValue()) 1845 return N0; 1846 // fold (shl x, c >= size(x)) -> undef 1847 if (N1C && N1C->getValue() >= OpSizeInBits) 1848 return DAG.getNode(ISD::UNDEF, VT); 1849 // fold (shl x, 0) -> x 1850 if (N1C && N1C->isNullValue()) 1851 return N0; 1852 // if (shl x, c) is known to be zero, return 0 1853 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1854 return DAG.getConstant(0, VT); 1855 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1856 return SDOperand(N, 0); 1857 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1858 if (N1C && N0.getOpcode() == ISD::SHL && 1859 N0.getOperand(1).getOpcode() == ISD::Constant) { 1860 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1861 uint64_t c2 = N1C->getValue(); 1862 if (c1 + c2 > OpSizeInBits) 1863 return DAG.getConstant(0, VT); 1864 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1865 DAG.getConstant(c1 + c2, N1.getValueType())); 1866 } 1867 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1868 // (srl (and x, -1 << c1), c1-c2) 1869 if (N1C && N0.getOpcode() == ISD::SRL && 1870 N0.getOperand(1).getOpcode() == ISD::Constant) { 1871 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1872 uint64_t c2 = N1C->getValue(); 1873 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1874 DAG.getConstant(~0ULL << c1, VT)); 1875 if (c2 > c1) 1876 return DAG.getNode(ISD::SHL, VT, Mask, 1877 DAG.getConstant(c2-c1, N1.getValueType())); 1878 else 1879 return DAG.getNode(ISD::SRL, VT, Mask, 1880 DAG.getConstant(c1-c2, N1.getValueType())); 1881 } 1882 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1883 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1884 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1885 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1886 return SDOperand(); 1887} 1888 1889SDOperand DAGCombiner::visitSRA(SDNode *N) { 1890 SDOperand N0 = N->getOperand(0); 1891 SDOperand N1 = N->getOperand(1); 1892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1893 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1894 MVT::ValueType VT = N0.getValueType(); 1895 1896 // fold (sra c1, c2) -> c1>>c2 1897 if (N0C && N1C) 1898 return DAG.getNode(ISD::SRA, VT, N0, N1); 1899 // fold (sra 0, x) -> 0 1900 if (N0C && N0C->isNullValue()) 1901 return N0; 1902 // fold (sra -1, x) -> -1 1903 if (N0C && N0C->isAllOnesValue()) 1904 return N0; 1905 // fold (sra x, c >= size(x)) -> undef 1906 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1907 return DAG.getNode(ISD::UNDEF, VT); 1908 // fold (sra x, 0) -> x 1909 if (N1C && N1C->isNullValue()) 1910 return N0; 1911 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1912 // sext_inreg. 1913 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1914 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1915 MVT::ValueType EVT; 1916 switch (LowBits) { 1917 default: EVT = MVT::Other; break; 1918 case 1: EVT = MVT::i1; break; 1919 case 8: EVT = MVT::i8; break; 1920 case 16: EVT = MVT::i16; break; 1921 case 32: EVT = MVT::i32; break; 1922 } 1923 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1924 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1925 DAG.getValueType(EVT)); 1926 } 1927 1928 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1929 if (N1C && N0.getOpcode() == ISD::SRA) { 1930 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1931 unsigned Sum = N1C->getValue() + C1->getValue(); 1932 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1933 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1934 DAG.getConstant(Sum, N1C->getValueType(0))); 1935 } 1936 } 1937 1938 // Simplify, based on bits shifted out of the LHS. 1939 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1940 return SDOperand(N, 0); 1941 1942 1943 // If the sign bit is known to be zero, switch this to a SRL. 1944 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1945 return DAG.getNode(ISD::SRL, VT, N0, N1); 1946 return SDOperand(); 1947} 1948 1949SDOperand DAGCombiner::visitSRL(SDNode *N) { 1950 SDOperand N0 = N->getOperand(0); 1951 SDOperand N1 = N->getOperand(1); 1952 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1954 MVT::ValueType VT = N0.getValueType(); 1955 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1956 1957 // fold (srl c1, c2) -> c1 >>u c2 1958 if (N0C && N1C) 1959 return DAG.getNode(ISD::SRL, VT, N0, N1); 1960 // fold (srl 0, x) -> 0 1961 if (N0C && N0C->isNullValue()) 1962 return N0; 1963 // fold (srl x, c >= size(x)) -> undef 1964 if (N1C && N1C->getValue() >= OpSizeInBits) 1965 return DAG.getNode(ISD::UNDEF, VT); 1966 // fold (srl x, 0) -> x 1967 if (N1C && N1C->isNullValue()) 1968 return N0; 1969 // if (srl x, c) is known to be zero, return 0 1970 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1971 return DAG.getConstant(0, VT); 1972 1973 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1974 if (N1C && N0.getOpcode() == ISD::SRL && 1975 N0.getOperand(1).getOpcode() == ISD::Constant) { 1976 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1977 uint64_t c2 = N1C->getValue(); 1978 if (c1 + c2 > OpSizeInBits) 1979 return DAG.getConstant(0, VT); 1980 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1981 DAG.getConstant(c1 + c2, N1.getValueType())); 1982 } 1983 1984 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1985 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1986 // Shifting in all undef bits? 1987 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1988 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1989 return DAG.getNode(ISD::UNDEF, VT); 1990 1991 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1992 AddToWorkList(SmallShift.Val); 1993 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1994 } 1995 1996 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1997 // bit, which is unmodified by sra. 1998 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1999 if (N0.getOpcode() == ISD::SRA) 2000 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2001 } 2002 2003 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2004 if (N1C && N0.getOpcode() == ISD::CTLZ && 2005 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2006 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2007 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2008 2009 // If any of the input bits are KnownOne, then the input couldn't be all 2010 // zeros, thus the result of the srl will always be zero. 2011 if (KnownOne) return DAG.getConstant(0, VT); 2012 2013 // If all of the bits input the to ctlz node are known to be zero, then 2014 // the result of the ctlz is "32" and the result of the shift is one. 2015 uint64_t UnknownBits = ~KnownZero & Mask; 2016 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2017 2018 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2019 if ((UnknownBits & (UnknownBits-1)) == 0) { 2020 // Okay, we know that only that the single bit specified by UnknownBits 2021 // could be set on input to the CTLZ node. If this bit is set, the SRL 2022 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2023 // to an SRL,XOR pair, which is likely to simplify more. 2024 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2025 SDOperand Op = N0.getOperand(0); 2026 if (ShAmt) { 2027 Op = DAG.getNode(ISD::SRL, VT, Op, 2028 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2029 AddToWorkList(Op.Val); 2030 } 2031 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2032 } 2033 } 2034 2035 // fold operands of srl based on knowledge that the low bits are not 2036 // demanded. 2037 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2038 return SDOperand(N, 0); 2039 2040 return SDOperand(); 2041} 2042 2043SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2044 SDOperand N0 = N->getOperand(0); 2045 MVT::ValueType VT = N->getValueType(0); 2046 2047 // fold (ctlz c1) -> c2 2048 if (isa<ConstantSDNode>(N0)) 2049 return DAG.getNode(ISD::CTLZ, VT, N0); 2050 return SDOperand(); 2051} 2052 2053SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2054 SDOperand N0 = N->getOperand(0); 2055 MVT::ValueType VT = N->getValueType(0); 2056 2057 // fold (cttz c1) -> c2 2058 if (isa<ConstantSDNode>(N0)) 2059 return DAG.getNode(ISD::CTTZ, VT, N0); 2060 return SDOperand(); 2061} 2062 2063SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2064 SDOperand N0 = N->getOperand(0); 2065 MVT::ValueType VT = N->getValueType(0); 2066 2067 // fold (ctpop c1) -> c2 2068 if (isa<ConstantSDNode>(N0)) 2069 return DAG.getNode(ISD::CTPOP, VT, N0); 2070 return SDOperand(); 2071} 2072 2073SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2074 SDOperand N0 = N->getOperand(0); 2075 SDOperand N1 = N->getOperand(1); 2076 SDOperand N2 = N->getOperand(2); 2077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2079 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2080 MVT::ValueType VT = N->getValueType(0); 2081 2082 // fold select C, X, X -> X 2083 if (N1 == N2) 2084 return N1; 2085 // fold select true, X, Y -> X 2086 if (N0C && !N0C->isNullValue()) 2087 return N1; 2088 // fold select false, X, Y -> Y 2089 if (N0C && N0C->isNullValue()) 2090 return N2; 2091 // fold select C, 1, X -> C | X 2092 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2093 return DAG.getNode(ISD::OR, VT, N0, N2); 2094 // fold select C, 0, X -> ~C & X 2095 // FIXME: this should check for C type == X type, not i1? 2096 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 2097 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2098 AddToWorkList(XORNode.Val); 2099 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2100 } 2101 // fold select C, X, 1 -> ~C | X 2102 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 2103 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2104 AddToWorkList(XORNode.Val); 2105 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2106 } 2107 // fold select C, X, 0 -> C & X 2108 // FIXME: this should check for C type == X type, not i1? 2109 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2110 return DAG.getNode(ISD::AND, VT, N0, N1); 2111 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2112 if (MVT::i1 == VT && N0 == N1) 2113 return DAG.getNode(ISD::OR, VT, N0, N2); 2114 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2115 if (MVT::i1 == VT && N0 == N2) 2116 return DAG.getNode(ISD::AND, VT, N0, N1); 2117 2118 // If we can fold this based on the true/false value, do so. 2119 if (SimplifySelectOps(N, N1, N2)) 2120 return SDOperand(N, 0); // Don't revisit N. 2121 2122 // fold selects based on a setcc into other things, such as min/max/abs 2123 if (N0.getOpcode() == ISD::SETCC) 2124 // FIXME: 2125 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2126 // having to say they don't support SELECT_CC on every type the DAG knows 2127 // about, since there is no way to mark an opcode illegal at all value types 2128 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2129 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2130 N1, N2, N0.getOperand(2)); 2131 else 2132 return SimplifySelect(N0, N1, N2); 2133 return SDOperand(); 2134} 2135 2136SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2137 SDOperand N0 = N->getOperand(0); 2138 SDOperand N1 = N->getOperand(1); 2139 SDOperand N2 = N->getOperand(2); 2140 SDOperand N3 = N->getOperand(3); 2141 SDOperand N4 = N->getOperand(4); 2142 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2143 2144 // fold select_cc lhs, rhs, x, x, cc -> x 2145 if (N2 == N3) 2146 return N2; 2147 2148 // Determine if the condition we're dealing with is constant 2149 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2150 if (SCC.Val) AddToWorkList(SCC.Val); 2151 2152 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2153 if (SCCC->getValue()) 2154 return N2; // cond always true -> true val 2155 else 2156 return N3; // cond always false -> false val 2157 } 2158 2159 // Fold to a simpler select_cc 2160 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2161 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2162 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2163 SCC.getOperand(2)); 2164 2165 // If we can fold this based on the true/false value, do so. 2166 if (SimplifySelectOps(N, N2, N3)) 2167 return SDOperand(N, 0); // Don't revisit N. 2168 2169 // fold select_cc into other things, such as min/max/abs 2170 return SimplifySelectCC(N0, N1, N2, N3, CC); 2171} 2172 2173SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2174 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2175 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2176} 2177 2178SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2179 SDOperand N0 = N->getOperand(0); 2180 MVT::ValueType VT = N->getValueType(0); 2181 2182 // fold (sext c1) -> c1 2183 if (isa<ConstantSDNode>(N0)) 2184 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2185 2186 // fold (sext (sext x)) -> (sext x) 2187 // fold (sext (aext x)) -> (sext x) 2188 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2189 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2190 2191 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2192 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2193 if (N0.getOpcode() == ISD::TRUNCATE) { 2194 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2195 if (NarrowLoad.Val) { 2196 if (NarrowLoad.Val != N0.Val) 2197 CombineTo(N0.Val, NarrowLoad); 2198 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2199 } 2200 } 2201 2202 // See if the value being truncated is already sign extended. If so, just 2203 // eliminate the trunc/sext pair. 2204 if (N0.getOpcode() == ISD::TRUNCATE) { 2205 SDOperand Op = N0.getOperand(0); 2206 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2207 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2208 unsigned DestBits = MVT::getSizeInBits(VT); 2209 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 2210 2211 if (OpBits == DestBits) { 2212 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2213 // bits, it is already ready. 2214 if (NumSignBits > DestBits-MidBits) 2215 return Op; 2216 } else if (OpBits < DestBits) { 2217 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2218 // bits, just sext from i32. 2219 if (NumSignBits > OpBits-MidBits) 2220 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2221 } else { 2222 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2223 // bits, just truncate to i32. 2224 if (NumSignBits > OpBits-MidBits) 2225 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2226 } 2227 2228 // fold (sext (truncate x)) -> (sextinreg x). 2229 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2230 N0.getValueType())) { 2231 if (Op.getValueType() < VT) 2232 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2233 else if (Op.getValueType() > VT) 2234 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2235 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2236 DAG.getValueType(N0.getValueType())); 2237 } 2238 } 2239 2240 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2241 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2242 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2243 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2244 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2245 LN0->getBasePtr(), LN0->getSrcValue(), 2246 LN0->getSrcValueOffset(), 2247 N0.getValueType(), 2248 LN0->isVolatile()); 2249 CombineTo(N, ExtLoad); 2250 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2251 ExtLoad.getValue(1)); 2252 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2253 } 2254 2255 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2256 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2257 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2258 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2259 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2260 MVT::ValueType EVT = LN0->getLoadedVT(); 2261 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2262 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2263 LN0->getBasePtr(), LN0->getSrcValue(), 2264 LN0->getSrcValueOffset(), EVT, 2265 LN0->isVolatile(), 2266 LN0->getAlignment()); 2267 CombineTo(N, ExtLoad); 2268 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2269 ExtLoad.getValue(1)); 2270 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2271 } 2272 } 2273 2274 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2275 if (N0.getOpcode() == ISD::SETCC) { 2276 SDOperand SCC = 2277 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2278 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2279 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2280 if (SCC.Val) return SCC; 2281 } 2282 2283 return SDOperand(); 2284} 2285 2286SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2287 SDOperand N0 = N->getOperand(0); 2288 MVT::ValueType VT = N->getValueType(0); 2289 2290 // fold (zext c1) -> c1 2291 if (isa<ConstantSDNode>(N0)) 2292 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2293 // fold (zext (zext x)) -> (zext x) 2294 // fold (zext (aext x)) -> (zext x) 2295 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2296 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2297 2298 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2299 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2300 if (N0.getOpcode() == ISD::TRUNCATE) { 2301 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2302 if (NarrowLoad.Val) { 2303 if (NarrowLoad.Val != N0.Val) 2304 CombineTo(N0.Val, NarrowLoad); 2305 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2306 } 2307 } 2308 2309 // fold (zext (truncate x)) -> (and x, mask) 2310 if (N0.getOpcode() == ISD::TRUNCATE && 2311 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2312 SDOperand Op = N0.getOperand(0); 2313 if (Op.getValueType() < VT) { 2314 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2315 } else if (Op.getValueType() > VT) { 2316 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2317 } 2318 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2319 } 2320 2321 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2322 if (N0.getOpcode() == ISD::AND && 2323 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2324 N0.getOperand(1).getOpcode() == ISD::Constant) { 2325 SDOperand X = N0.getOperand(0).getOperand(0); 2326 if (X.getValueType() < VT) { 2327 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2328 } else if (X.getValueType() > VT) { 2329 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2330 } 2331 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2332 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2333 } 2334 2335 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2336 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2337 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2338 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2339 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2340 LN0->getBasePtr(), LN0->getSrcValue(), 2341 LN0->getSrcValueOffset(), 2342 N0.getValueType(), 2343 LN0->isVolatile(), 2344 LN0->getAlignment()); 2345 CombineTo(N, ExtLoad); 2346 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2347 ExtLoad.getValue(1)); 2348 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2349 } 2350 2351 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2352 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2353 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2354 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2355 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2356 MVT::ValueType EVT = LN0->getLoadedVT(); 2357 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2358 LN0->getBasePtr(), LN0->getSrcValue(), 2359 LN0->getSrcValueOffset(), EVT, 2360 LN0->isVolatile(), 2361 LN0->getAlignment()); 2362 CombineTo(N, ExtLoad); 2363 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2364 ExtLoad.getValue(1)); 2365 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2366 } 2367 2368 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2369 if (N0.getOpcode() == ISD::SETCC) { 2370 SDOperand SCC = 2371 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2372 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2373 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2374 if (SCC.Val) return SCC; 2375 } 2376 2377 return SDOperand(); 2378} 2379 2380SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2381 SDOperand N0 = N->getOperand(0); 2382 MVT::ValueType VT = N->getValueType(0); 2383 2384 // fold (aext c1) -> c1 2385 if (isa<ConstantSDNode>(N0)) 2386 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2387 // fold (aext (aext x)) -> (aext x) 2388 // fold (aext (zext x)) -> (zext x) 2389 // fold (aext (sext x)) -> (sext x) 2390 if (N0.getOpcode() == ISD::ANY_EXTEND || 2391 N0.getOpcode() == ISD::ZERO_EXTEND || 2392 N0.getOpcode() == ISD::SIGN_EXTEND) 2393 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2394 2395 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2396 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2397 if (N0.getOpcode() == ISD::TRUNCATE) { 2398 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2399 if (NarrowLoad.Val) { 2400 if (NarrowLoad.Val != N0.Val) 2401 CombineTo(N0.Val, NarrowLoad); 2402 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2403 } 2404 } 2405 2406 // fold (aext (truncate x)) 2407 if (N0.getOpcode() == ISD::TRUNCATE) { 2408 SDOperand TruncOp = N0.getOperand(0); 2409 if (TruncOp.getValueType() == VT) 2410 return TruncOp; // x iff x size == zext size. 2411 if (TruncOp.getValueType() > VT) 2412 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2413 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2414 } 2415 2416 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2417 if (N0.getOpcode() == ISD::AND && 2418 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2419 N0.getOperand(1).getOpcode() == ISD::Constant) { 2420 SDOperand X = N0.getOperand(0).getOperand(0); 2421 if (X.getValueType() < VT) { 2422 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2423 } else if (X.getValueType() > VT) { 2424 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2425 } 2426 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2427 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2428 } 2429 2430 // fold (aext (load x)) -> (aext (truncate (extload x))) 2431 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2432 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2433 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2434 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2435 LN0->getBasePtr(), LN0->getSrcValue(), 2436 LN0->getSrcValueOffset(), 2437 N0.getValueType(), 2438 LN0->isVolatile(), 2439 LN0->getAlignment()); 2440 CombineTo(N, ExtLoad); 2441 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2442 ExtLoad.getValue(1)); 2443 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2444 } 2445 2446 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2447 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2448 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2449 if (N0.getOpcode() == ISD::LOAD && 2450 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2451 N0.hasOneUse()) { 2452 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2453 MVT::ValueType EVT = LN0->getLoadedVT(); 2454 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2455 LN0->getChain(), LN0->getBasePtr(), 2456 LN0->getSrcValue(), 2457 LN0->getSrcValueOffset(), EVT, 2458 LN0->isVolatile(), 2459 LN0->getAlignment()); 2460 CombineTo(N, ExtLoad); 2461 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2462 ExtLoad.getValue(1)); 2463 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2464 } 2465 2466 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2467 if (N0.getOpcode() == ISD::SETCC) { 2468 SDOperand SCC = 2469 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2470 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2471 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2472 if (SCC.Val) 2473 return SCC; 2474 } 2475 2476 return SDOperand(); 2477} 2478 2479/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2480/// bits and then truncated to a narrower type and where N is a multiple 2481/// of number of bits of the narrower type, transform it to a narrower load 2482/// from address + N / num of bits of new type. If the result is to be 2483/// extended, also fold the extension to form a extending load. 2484SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2485 unsigned Opc = N->getOpcode(); 2486 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2487 SDOperand N0 = N->getOperand(0); 2488 MVT::ValueType VT = N->getValueType(0); 2489 MVT::ValueType EVT = N->getValueType(0); 2490 2491 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2492 // extended to VT. 2493 if (Opc == ISD::SIGN_EXTEND_INREG) { 2494 ExtType = ISD::SEXTLOAD; 2495 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2496 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2497 return SDOperand(); 2498 } 2499 2500 unsigned EVTBits = MVT::getSizeInBits(EVT); 2501 unsigned ShAmt = 0; 2502 bool CombineSRL = false; 2503 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2504 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2505 ShAmt = N01->getValue(); 2506 // Is the shift amount a multiple of size of VT? 2507 if ((ShAmt & (EVTBits-1)) == 0) { 2508 N0 = N0.getOperand(0); 2509 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2510 return SDOperand(); 2511 CombineSRL = true; 2512 } 2513 } 2514 } 2515 2516 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2517 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2518 // zero extended form: by shrinking the load, we lose track of the fact 2519 // that it is already zero extended. 2520 // FIXME: This should be reevaluated. 2521 VT != MVT::i1) { 2522 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2523 "Cannot truncate to larger type!"); 2524 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2525 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2526 // For big endian targets, we need to adjust the offset to the pointer to 2527 // load the correct bytes. 2528 if (!TLI.isLittleEndian()) 2529 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2530 uint64_t PtrOff = ShAmt / 8; 2531 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2532 DAG.getConstant(PtrOff, PtrType)); 2533 AddToWorkList(NewPtr.Val); 2534 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 2535 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 2536 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2537 LN0->isVolatile(), LN0->getAlignment()) 2538 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 2539 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 2540 LN0->isVolatile(), LN0->getAlignment()); 2541 AddToWorkList(N); 2542 if (CombineSRL) { 2543 std::vector<SDNode*> NowDead; 2544 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead); 2545 CombineTo(N->getOperand(0).Val, Load); 2546 } else 2547 CombineTo(N0.Val, Load, Load.getValue(1)); 2548 if (ShAmt) { 2549 if (Opc == ISD::SIGN_EXTEND_INREG) 2550 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 2551 else 2552 return DAG.getNode(Opc, VT, Load); 2553 } 2554 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2555 } 2556 2557 return SDOperand(); 2558} 2559 2560 2561SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2562 SDOperand N0 = N->getOperand(0); 2563 SDOperand N1 = N->getOperand(1); 2564 MVT::ValueType VT = N->getValueType(0); 2565 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2566 unsigned EVTBits = MVT::getSizeInBits(EVT); 2567 2568 // fold (sext_in_reg c1) -> c1 2569 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2570 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2571 2572 // If the input is already sign extended, just drop the extension. 2573 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2574 return N0; 2575 2576 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2577 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2578 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2579 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2580 } 2581 2582 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 2583 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2584 return DAG.getZeroExtendInReg(N0, EVT); 2585 2586 // fold operands of sext_in_reg based on knowledge that the top bits are not 2587 // demanded. 2588 if (SimplifyDemandedBits(SDOperand(N, 0))) 2589 return SDOperand(N, 0); 2590 2591 // fold (sext_in_reg (load x)) -> (smaller sextload x) 2592 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 2593 SDOperand NarrowLoad = ReduceLoadWidth(N); 2594 if (NarrowLoad.Val) 2595 return NarrowLoad; 2596 2597 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2598 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2599 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2600 if (N0.getOpcode() == ISD::SRL) { 2601 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2602 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2603 // We can turn this into an SRA iff the input to the SRL is already sign 2604 // extended enough. 2605 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2606 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2607 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2608 } 2609 } 2610 2611 // fold (sext_inreg (extload x)) -> (sextload x) 2612 if (ISD::isEXTLoad(N0.Val) && 2613 ISD::isUNINDEXEDLoad(N0.Val) && 2614 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2615 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2616 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2617 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2618 LN0->getBasePtr(), LN0->getSrcValue(), 2619 LN0->getSrcValueOffset(), EVT, 2620 LN0->isVolatile(), 2621 LN0->getAlignment()); 2622 CombineTo(N, ExtLoad); 2623 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2624 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2625 } 2626 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2627 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2628 N0.hasOneUse() && 2629 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2630 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2631 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2632 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2633 LN0->getBasePtr(), LN0->getSrcValue(), 2634 LN0->getSrcValueOffset(), EVT, 2635 LN0->isVolatile(), 2636 LN0->getAlignment()); 2637 CombineTo(N, ExtLoad); 2638 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2639 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2640 } 2641 return SDOperand(); 2642} 2643 2644SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2645 SDOperand N0 = N->getOperand(0); 2646 MVT::ValueType VT = N->getValueType(0); 2647 2648 // noop truncate 2649 if (N0.getValueType() == N->getValueType(0)) 2650 return N0; 2651 // fold (truncate c1) -> c1 2652 if (isa<ConstantSDNode>(N0)) 2653 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2654 // fold (truncate (truncate x)) -> (truncate x) 2655 if (N0.getOpcode() == ISD::TRUNCATE) 2656 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2657 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2658 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2659 N0.getOpcode() == ISD::ANY_EXTEND) { 2660 if (N0.getOperand(0).getValueType() < VT) 2661 // if the source is smaller than the dest, we still need an extend 2662 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2663 else if (N0.getOperand(0).getValueType() > VT) 2664 // if the source is larger than the dest, than we just need the truncate 2665 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2666 else 2667 // if the source and dest are the same type, we can drop both the extend 2668 // and the truncate 2669 return N0.getOperand(0); 2670 } 2671 2672 // fold (truncate (load x)) -> (smaller load x) 2673 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 2674 return ReduceLoadWidth(N); 2675} 2676 2677SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2678 SDOperand N0 = N->getOperand(0); 2679 MVT::ValueType VT = N->getValueType(0); 2680 2681 // If the input is a constant, let getNode() fold it. 2682 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2683 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2684 if (Res.Val != N) return Res; 2685 } 2686 2687 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2688 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2689 2690 // fold (conv (load x)) -> (load (conv*)x) 2691 // If the resultant load doesn't need a higher alignment than the original! 2692 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2693 ISD::isUNINDEXEDLoad(N0.Val) && 2694 TLI.isOperationLegal(ISD::LOAD, VT)) { 2695 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2696 unsigned Align = TLI.getTargetMachine().getTargetData()-> 2697 getABITypeAlignment(MVT::getTypeForValueType(VT)); 2698 unsigned OrigAlign = LN0->getAlignment(); 2699 if (Align <= OrigAlign) { 2700 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2701 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2702 LN0->isVolatile(), LN0->getAlignment()); 2703 AddToWorkList(N); 2704 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2705 Load.getValue(1)); 2706 return Load; 2707 } 2708 } 2709 2710 return SDOperand(); 2711} 2712 2713SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2714 SDOperand N0 = N->getOperand(0); 2715 MVT::ValueType VT = N->getValueType(0); 2716 2717 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2718 // First check to see if this is all constant. 2719 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2720 VT == MVT::Vector) { 2721 bool isSimple = true; 2722 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2723 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2724 N0.getOperand(i).getOpcode() != ISD::Constant && 2725 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2726 isSimple = false; 2727 break; 2728 } 2729 2730 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2731 if (isSimple && !MVT::isVector(DestEltVT)) { 2732 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2733 } 2734 } 2735 2736 return SDOperand(); 2737} 2738 2739/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2740/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2741/// destination element value type. 2742SDOperand DAGCombiner:: 2743ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2744 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2745 2746 // If this is already the right type, we're done. 2747 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2748 2749 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2750 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2751 2752 // If this is a conversion of N elements of one type to N elements of another 2753 // type, convert each element. This handles FP<->INT cases. 2754 if (SrcBitSize == DstBitSize) { 2755 SmallVector<SDOperand, 8> Ops; 2756 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2757 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2758 AddToWorkList(Ops.back().Val); 2759 } 2760 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2761 Ops.push_back(DAG.getValueType(DstEltVT)); 2762 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2763 } 2764 2765 // Otherwise, we're growing or shrinking the elements. To avoid having to 2766 // handle annoying details of growing/shrinking FP values, we convert them to 2767 // int first. 2768 if (MVT::isFloatingPoint(SrcEltVT)) { 2769 // Convert the input float vector to a int vector where the elements are the 2770 // same sizes. 2771 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2772 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2773 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2774 SrcEltVT = IntVT; 2775 } 2776 2777 // Now we know the input is an integer vector. If the output is a FP type, 2778 // convert to integer first, then to FP of the right size. 2779 if (MVT::isFloatingPoint(DstEltVT)) { 2780 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2781 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2782 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2783 2784 // Next, convert to FP elements of the same size. 2785 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2786 } 2787 2788 // Okay, we know the src/dst types are both integers of differing types. 2789 // Handling growing first. 2790 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2791 if (SrcBitSize < DstBitSize) { 2792 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2793 2794 SmallVector<SDOperand, 8> Ops; 2795 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2796 i += NumInputsPerOutput) { 2797 bool isLE = TLI.isLittleEndian(); 2798 uint64_t NewBits = 0; 2799 bool EltIsUndef = true; 2800 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2801 // Shift the previously computed bits over. 2802 NewBits <<= SrcBitSize; 2803 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2804 if (Op.getOpcode() == ISD::UNDEF) continue; 2805 EltIsUndef = false; 2806 2807 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2808 } 2809 2810 if (EltIsUndef) 2811 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2812 else 2813 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2814 } 2815 2816 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2817 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2818 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2819 } 2820 2821 // Finally, this must be the case where we are shrinking elements: each input 2822 // turns into multiple outputs. 2823 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2824 SmallVector<SDOperand, 8> Ops; 2825 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2826 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2827 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2828 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2829 continue; 2830 } 2831 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2832 2833 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2834 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2835 OpVal >>= DstBitSize; 2836 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2837 } 2838 2839 // For big endian targets, swap the order of the pieces of each element. 2840 if (!TLI.isLittleEndian()) 2841 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2842 } 2843 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2844 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2845 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2846} 2847 2848 2849 2850SDOperand DAGCombiner::visitFADD(SDNode *N) { 2851 SDOperand N0 = N->getOperand(0); 2852 SDOperand N1 = N->getOperand(1); 2853 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2854 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2855 MVT::ValueType VT = N->getValueType(0); 2856 2857 // fold (fadd c1, c2) -> c1+c2 2858 if (N0CFP && N1CFP) 2859 return DAG.getNode(ISD::FADD, VT, N0, N1); 2860 // canonicalize constant to RHS 2861 if (N0CFP && !N1CFP) 2862 return DAG.getNode(ISD::FADD, VT, N1, N0); 2863 // fold (A + (-B)) -> A-B 2864 if (isNegatibleForFree(N1) == 2) 2865 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 2866 // fold ((-A) + B) -> B-A 2867 if (isNegatibleForFree(N0) == 2) 2868 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 2869 2870 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2871 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2872 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2873 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2874 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2875 2876 return SDOperand(); 2877} 2878 2879SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2880 SDOperand N0 = N->getOperand(0); 2881 SDOperand N1 = N->getOperand(1); 2882 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2883 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2884 MVT::ValueType VT = N->getValueType(0); 2885 2886 // fold (fsub c1, c2) -> c1-c2 2887 if (N0CFP && N1CFP) 2888 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2889 // fold (A-(-B)) -> A+B 2890 if (isNegatibleForFree(N1)) 2891 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 2892 2893 return SDOperand(); 2894} 2895 2896SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2897 SDOperand N0 = N->getOperand(0); 2898 SDOperand N1 = N->getOperand(1); 2899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2900 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2901 MVT::ValueType VT = N->getValueType(0); 2902 2903 // fold (fmul c1, c2) -> c1*c2 2904 if (N0CFP && N1CFP) 2905 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2906 // canonicalize constant to RHS 2907 if (N0CFP && !N1CFP) 2908 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2909 // fold (fmul X, 2.0) -> (fadd X, X) 2910 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2911 return DAG.getNode(ISD::FADD, VT, N0, N0); 2912 // fold (fmul X, -1.0) -> (fneg X) 2913 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 2914 return DAG.getNode(ISD::FNEG, VT, N0); 2915 2916 // -X * -Y -> X*Y 2917 if (char LHSNeg = isNegatibleForFree(N0)) { 2918 if (char RHSNeg = isNegatibleForFree(N1)) { 2919 // Both can be negated for free, check to see if at least one is cheaper 2920 // negated. 2921 if (LHSNeg == 2 || RHSNeg == 2) 2922 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 2923 GetNegatedExpression(N1, DAG)); 2924 } 2925 } 2926 2927 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2928 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2929 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2930 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2931 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2932 2933 return SDOperand(); 2934} 2935 2936SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2937 SDOperand N0 = N->getOperand(0); 2938 SDOperand N1 = N->getOperand(1); 2939 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2940 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2941 MVT::ValueType VT = N->getValueType(0); 2942 2943 // fold (fdiv c1, c2) -> c1/c2 2944 if (N0CFP && N1CFP) 2945 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2946 2947 2948 // -X / -Y -> X*Y 2949 if (char LHSNeg = isNegatibleForFree(N0)) { 2950 if (char RHSNeg = isNegatibleForFree(N1)) { 2951 // Both can be negated for free, check to see if at least one is cheaper 2952 // negated. 2953 if (LHSNeg == 2 || RHSNeg == 2) 2954 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 2955 GetNegatedExpression(N1, DAG)); 2956 } 2957 } 2958 2959 return SDOperand(); 2960} 2961 2962SDOperand DAGCombiner::visitFREM(SDNode *N) { 2963 SDOperand N0 = N->getOperand(0); 2964 SDOperand N1 = N->getOperand(1); 2965 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2966 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2967 MVT::ValueType VT = N->getValueType(0); 2968 2969 // fold (frem c1, c2) -> fmod(c1,c2) 2970 if (N0CFP && N1CFP) 2971 return DAG.getNode(ISD::FREM, VT, N0, N1); 2972 return SDOperand(); 2973} 2974 2975SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2976 SDOperand N0 = N->getOperand(0); 2977 SDOperand N1 = N->getOperand(1); 2978 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2979 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2980 MVT::ValueType VT = N->getValueType(0); 2981 2982 if (N0CFP && N1CFP) // Constant fold 2983 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2984 2985 if (N1CFP) { 2986 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2987 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2988 union { 2989 double d; 2990 int64_t i; 2991 } u; 2992 u.d = N1CFP->getValue(); 2993 if (u.i >= 0) 2994 return DAG.getNode(ISD::FABS, VT, N0); 2995 else 2996 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2997 } 2998 2999 // copysign(fabs(x), y) -> copysign(x, y) 3000 // copysign(fneg(x), y) -> copysign(x, y) 3001 // copysign(copysign(x,z), y) -> copysign(x, y) 3002 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3003 N0.getOpcode() == ISD::FCOPYSIGN) 3004 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3005 3006 // copysign(x, abs(y)) -> abs(x) 3007 if (N1.getOpcode() == ISD::FABS) 3008 return DAG.getNode(ISD::FABS, VT, N0); 3009 3010 // copysign(x, copysign(y,z)) -> copysign(x, z) 3011 if (N1.getOpcode() == ISD::FCOPYSIGN) 3012 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3013 3014 // copysign(x, fp_extend(y)) -> copysign(x, y) 3015 // copysign(x, fp_round(y)) -> copysign(x, y) 3016 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3017 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3018 3019 return SDOperand(); 3020} 3021 3022 3023 3024SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3025 SDOperand N0 = N->getOperand(0); 3026 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3027 MVT::ValueType VT = N->getValueType(0); 3028 3029 // fold (sint_to_fp c1) -> c1fp 3030 if (N0C) 3031 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3032 return SDOperand(); 3033} 3034 3035SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3036 SDOperand N0 = N->getOperand(0); 3037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3038 MVT::ValueType VT = N->getValueType(0); 3039 3040 // fold (uint_to_fp c1) -> c1fp 3041 if (N0C) 3042 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3043 return SDOperand(); 3044} 3045 3046SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3047 SDOperand N0 = N->getOperand(0); 3048 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3049 MVT::ValueType VT = N->getValueType(0); 3050 3051 // fold (fp_to_sint c1fp) -> c1 3052 if (N0CFP) 3053 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3054 return SDOperand(); 3055} 3056 3057SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3058 SDOperand N0 = N->getOperand(0); 3059 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3060 MVT::ValueType VT = N->getValueType(0); 3061 3062 // fold (fp_to_uint c1fp) -> c1 3063 if (N0CFP) 3064 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3065 return SDOperand(); 3066} 3067 3068SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3069 SDOperand N0 = N->getOperand(0); 3070 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3071 MVT::ValueType VT = N->getValueType(0); 3072 3073 // fold (fp_round c1fp) -> c1fp 3074 if (N0CFP) 3075 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3076 3077 // fold (fp_round (fp_extend x)) -> x 3078 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3079 return N0.getOperand(0); 3080 3081 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3082 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3083 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3084 AddToWorkList(Tmp.Val); 3085 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3086 } 3087 3088 return SDOperand(); 3089} 3090 3091SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3092 SDOperand N0 = N->getOperand(0); 3093 MVT::ValueType VT = N->getValueType(0); 3094 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3096 3097 // fold (fp_round_inreg c1fp) -> c1fp 3098 if (N0CFP) { 3099 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 3100 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3101 } 3102 return SDOperand(); 3103} 3104 3105SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3106 SDOperand N0 = N->getOperand(0); 3107 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3108 MVT::ValueType VT = N->getValueType(0); 3109 3110 // fold (fp_extend c1fp) -> c1fp 3111 if (N0CFP) 3112 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3113 3114 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3115 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3116 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3117 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3118 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3119 LN0->getBasePtr(), LN0->getSrcValue(), 3120 LN0->getSrcValueOffset(), 3121 N0.getValueType(), 3122 LN0->isVolatile(), 3123 LN0->getAlignment()); 3124 CombineTo(N, ExtLoad); 3125 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3126 ExtLoad.getValue(1)); 3127 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3128 } 3129 3130 3131 return SDOperand(); 3132} 3133 3134SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3135 SDOperand N0 = N->getOperand(0); 3136 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3137 MVT::ValueType VT = N->getValueType(0); 3138 3139 // fold (fneg c1) -> -c1 3140 if (N0CFP) 3141 return DAG.getNode(ISD::FNEG, VT, N0); 3142 // fold (fneg (sub x, y)) -> (sub y, x) 3143 if (N0.getOpcode() == ISD::SUB) 3144 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 3145 // fold (fneg (fneg x)) -> x 3146 if (N0.getOpcode() == ISD::FNEG) 3147 return N0.getOperand(0); 3148 return SDOperand(); 3149} 3150 3151SDOperand DAGCombiner::visitFABS(SDNode *N) { 3152 SDOperand N0 = N->getOperand(0); 3153 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3154 MVT::ValueType VT = N->getValueType(0); 3155 3156 // fold (fabs c1) -> fabs(c1) 3157 if (N0CFP) 3158 return DAG.getNode(ISD::FABS, VT, N0); 3159 // fold (fabs (fabs x)) -> (fabs x) 3160 if (N0.getOpcode() == ISD::FABS) 3161 return N->getOperand(0); 3162 // fold (fabs (fneg x)) -> (fabs x) 3163 // fold (fabs (fcopysign x, y)) -> (fabs x) 3164 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3165 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3166 3167 return SDOperand(); 3168} 3169 3170SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3171 SDOperand Chain = N->getOperand(0); 3172 SDOperand N1 = N->getOperand(1); 3173 SDOperand N2 = N->getOperand(2); 3174 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3175 3176 // never taken branch, fold to chain 3177 if (N1C && N1C->isNullValue()) 3178 return Chain; 3179 // unconditional branch 3180 if (N1C && N1C->getValue() == 1) 3181 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3182 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3183 // on the target. 3184 if (N1.getOpcode() == ISD::SETCC && 3185 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3186 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3187 N1.getOperand(0), N1.getOperand(1), N2); 3188 } 3189 return SDOperand(); 3190} 3191 3192// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3193// 3194SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3195 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3196 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3197 3198 // Use SimplifySetCC to simplify SETCC's. 3199 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3200 if (Simp.Val) AddToWorkList(Simp.Val); 3201 3202 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3203 3204 // fold br_cc true, dest -> br dest (unconditional branch) 3205 if (SCCC && SCCC->getValue()) 3206 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3207 N->getOperand(4)); 3208 // fold br_cc false, dest -> unconditional fall through 3209 if (SCCC && SCCC->isNullValue()) 3210 return N->getOperand(0); 3211 3212 // fold to a simpler setcc 3213 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3214 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3215 Simp.getOperand(2), Simp.getOperand(0), 3216 Simp.getOperand(1), N->getOperand(4)); 3217 return SDOperand(); 3218} 3219 3220 3221/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3222/// pre-indexed load / store when the base pointer is a add or subtract 3223/// and it has other uses besides the load / store. After the 3224/// transformation, the new indexed load / store has effectively folded 3225/// the add / subtract in and all of its other uses are redirected to the 3226/// new load / store. 3227bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3228 if (!AfterLegalize) 3229 return false; 3230 3231 bool isLoad = true; 3232 SDOperand Ptr; 3233 MVT::ValueType VT; 3234 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3235 if (LD->getAddressingMode() != ISD::UNINDEXED) 3236 return false; 3237 VT = LD->getLoadedVT(); 3238 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3239 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3240 return false; 3241 Ptr = LD->getBasePtr(); 3242 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3243 if (ST->getAddressingMode() != ISD::UNINDEXED) 3244 return false; 3245 VT = ST->getStoredVT(); 3246 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3247 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3248 return false; 3249 Ptr = ST->getBasePtr(); 3250 isLoad = false; 3251 } else 3252 return false; 3253 3254 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3255 // out. There is no reason to make this a preinc/predec. 3256 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3257 Ptr.Val->hasOneUse()) 3258 return false; 3259 3260 // Ask the target to do addressing mode selection. 3261 SDOperand BasePtr; 3262 SDOperand Offset; 3263 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3264 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3265 return false; 3266 // Don't create a indexed load / store with zero offset. 3267 if (isa<ConstantSDNode>(Offset) && 3268 cast<ConstantSDNode>(Offset)->getValue() == 0) 3269 return false; 3270 3271 // Try turning it into a pre-indexed load / store except when: 3272 // 1) The new base ptr is a frame index. 3273 // 2) If N is a store and the new base ptr is either the same as or is a 3274 // predecessor of the value being stored. 3275 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3276 // that would create a cycle. 3277 // 4) All uses are load / store ops that use it as old base ptr. 3278 3279 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3280 // (plus the implicit offset) to a register to preinc anyway. 3281 if (isa<FrameIndexSDNode>(BasePtr)) 3282 return false; 3283 3284 // Check #2. 3285 if (!isLoad) { 3286 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3287 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3288 return false; 3289 } 3290 3291 // Now check for #3 and #4. 3292 bool RealUse = false; 3293 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3294 E = Ptr.Val->use_end(); I != E; ++I) { 3295 SDNode *Use = *I; 3296 if (Use == N) 3297 continue; 3298 if (Use->isPredecessor(N)) 3299 return false; 3300 3301 if (!((Use->getOpcode() == ISD::LOAD && 3302 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3303 (Use->getOpcode() == ISD::STORE) && 3304 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3305 RealUse = true; 3306 } 3307 if (!RealUse) 3308 return false; 3309 3310 SDOperand Result; 3311 if (isLoad) 3312 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3313 else 3314 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3315 ++PreIndexedNodes; 3316 ++NodesCombined; 3317 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 3318 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3319 DOUT << '\n'; 3320 std::vector<SDNode*> NowDead; 3321 if (isLoad) { 3322 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3323 NowDead); 3324 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3325 NowDead); 3326 } else { 3327 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3328 NowDead); 3329 } 3330 3331 // Nodes can end up on the worklist more than once. Make sure we do 3332 // not process a node that has been replaced. 3333 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3334 removeFromWorkList(NowDead[i]); 3335 // Finally, since the node is now dead, remove it from the graph. 3336 DAG.DeleteNode(N); 3337 3338 // Replace the uses of Ptr with uses of the updated base value. 3339 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3340 NowDead); 3341 removeFromWorkList(Ptr.Val); 3342 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3343 removeFromWorkList(NowDead[i]); 3344 DAG.DeleteNode(Ptr.Val); 3345 3346 return true; 3347} 3348 3349/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3350/// add / sub of the base pointer node into a post-indexed load / store. 3351/// The transformation folded the add / subtract into the new indexed 3352/// load / store effectively and all of its uses are redirected to the 3353/// new load / store. 3354bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3355 if (!AfterLegalize) 3356 return false; 3357 3358 bool isLoad = true; 3359 SDOperand Ptr; 3360 MVT::ValueType VT; 3361 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3362 if (LD->getAddressingMode() != ISD::UNINDEXED) 3363 return false; 3364 VT = LD->getLoadedVT(); 3365 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3366 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3367 return false; 3368 Ptr = LD->getBasePtr(); 3369 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3370 if (ST->getAddressingMode() != ISD::UNINDEXED) 3371 return false; 3372 VT = ST->getStoredVT(); 3373 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3374 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3375 return false; 3376 Ptr = ST->getBasePtr(); 3377 isLoad = false; 3378 } else 3379 return false; 3380 3381 if (Ptr.Val->hasOneUse()) 3382 return false; 3383 3384 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3385 E = Ptr.Val->use_end(); I != E; ++I) { 3386 SDNode *Op = *I; 3387 if (Op == N || 3388 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3389 continue; 3390 3391 SDOperand BasePtr; 3392 SDOperand Offset; 3393 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3394 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3395 if (Ptr == Offset) 3396 std::swap(BasePtr, Offset); 3397 if (Ptr != BasePtr) 3398 continue; 3399 // Don't create a indexed load / store with zero offset. 3400 if (isa<ConstantSDNode>(Offset) && 3401 cast<ConstantSDNode>(Offset)->getValue() == 0) 3402 continue; 3403 3404 // Try turning it into a post-indexed load / store except when 3405 // 1) All uses are load / store ops that use it as base ptr. 3406 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3407 // nor a successor of N. Otherwise, if Op is folded that would 3408 // create a cycle. 3409 3410 // Check for #1. 3411 bool TryNext = false; 3412 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3413 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3414 SDNode *Use = *II; 3415 if (Use == Ptr.Val) 3416 continue; 3417 3418 // If all the uses are load / store addresses, then don't do the 3419 // transformation. 3420 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3421 bool RealUse = false; 3422 for (SDNode::use_iterator III = Use->use_begin(), 3423 EEE = Use->use_end(); III != EEE; ++III) { 3424 SDNode *UseUse = *III; 3425 if (!((UseUse->getOpcode() == ISD::LOAD && 3426 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3427 (UseUse->getOpcode() == ISD::STORE) && 3428 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3429 RealUse = true; 3430 } 3431 3432 if (!RealUse) { 3433 TryNext = true; 3434 break; 3435 } 3436 } 3437 } 3438 if (TryNext) 3439 continue; 3440 3441 // Check for #2 3442 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3443 SDOperand Result = isLoad 3444 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3445 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3446 ++PostIndexedNodes; 3447 ++NodesCombined; 3448 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3449 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3450 DOUT << '\n'; 3451 std::vector<SDNode*> NowDead; 3452 if (isLoad) { 3453 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3454 NowDead); 3455 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3456 NowDead); 3457 } else { 3458 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3459 NowDead); 3460 } 3461 3462 // Nodes can end up on the worklist more than once. Make sure we do 3463 // not process a node that has been replaced. 3464 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3465 removeFromWorkList(NowDead[i]); 3466 // Finally, since the node is now dead, remove it from the graph. 3467 DAG.DeleteNode(N); 3468 3469 // Replace the uses of Use with uses of the updated base value. 3470 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3471 Result.getValue(isLoad ? 1 : 0), 3472 NowDead); 3473 removeFromWorkList(Op); 3474 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3475 removeFromWorkList(NowDead[i]); 3476 DAG.DeleteNode(Op); 3477 3478 return true; 3479 } 3480 } 3481 } 3482 return false; 3483} 3484 3485 3486SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3487 LoadSDNode *LD = cast<LoadSDNode>(N); 3488 SDOperand Chain = LD->getChain(); 3489 SDOperand Ptr = LD->getBasePtr(); 3490 3491 // If load is not volatile and there are no uses of the loaded value (and 3492 // the updated indexed value in case of indexed loads), change uses of the 3493 // chain value into uses of the chain input (i.e. delete the dead load). 3494 if (!LD->isVolatile()) { 3495 if (N->getValueType(1) == MVT::Other) { 3496 // Unindexed loads. 3497 if (N->hasNUsesOfValue(0, 0)) 3498 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3499 } else { 3500 // Indexed loads. 3501 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3502 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3503 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3504 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3505 SDOperand To[] = { Undef0, Undef1, Chain }; 3506 return CombineTo(N, To, 3); 3507 } 3508 } 3509 } 3510 3511 // If this load is directly stored, replace the load value with the stored 3512 // value. 3513 // TODO: Handle store large -> read small portion. 3514 // TODO: Handle TRUNCSTORE/LOADEXT 3515 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3516 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3517 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3518 if (PrevST->getBasePtr() == Ptr && 3519 PrevST->getValue().getValueType() == N->getValueType(0)) 3520 return CombineTo(N, Chain.getOperand(1), Chain); 3521 } 3522 } 3523 3524 if (CombinerAA) { 3525 // Walk up chain skipping non-aliasing memory nodes. 3526 SDOperand BetterChain = FindBetterChain(N, Chain); 3527 3528 // If there is a better chain. 3529 if (Chain != BetterChain) { 3530 SDOperand ReplLoad; 3531 3532 // Replace the chain to void dependency. 3533 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3534 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3535 LD->getSrcValue(), LD->getSrcValueOffset(), 3536 LD->isVolatile(), LD->getAlignment()); 3537 } else { 3538 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3539 LD->getValueType(0), 3540 BetterChain, Ptr, LD->getSrcValue(), 3541 LD->getSrcValueOffset(), 3542 LD->getLoadedVT(), 3543 LD->isVolatile(), 3544 LD->getAlignment()); 3545 } 3546 3547 // Create token factor to keep old chain connected. 3548 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3549 Chain, ReplLoad.getValue(1)); 3550 3551 // Replace uses with load result and token factor. Don't add users 3552 // to work list. 3553 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3554 } 3555 } 3556 3557 // Try transforming N to an indexed load. 3558 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3559 return SDOperand(N, 0); 3560 3561 return SDOperand(); 3562} 3563 3564SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3565 StoreSDNode *ST = cast<StoreSDNode>(N); 3566 SDOperand Chain = ST->getChain(); 3567 SDOperand Value = ST->getValue(); 3568 SDOperand Ptr = ST->getBasePtr(); 3569 3570 // If this is a store of a bit convert, store the input value if the 3571 // resultant store does not need a higher alignment than the original. 3572 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 3573 ST->getAddressingMode() == ISD::UNINDEXED) { 3574 unsigned Align = ST->getAlignment(); 3575 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 3576 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 3577 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 3578 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 3579 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3580 ST->getSrcValueOffset()); 3581 } 3582 3583 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3584 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3585 if (Value.getOpcode() != ISD::TargetConstantFP) { 3586 SDOperand Tmp; 3587 switch (CFP->getValueType(0)) { 3588 default: assert(0 && "Unknown FP type"); 3589 case MVT::f32: 3590 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3591 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3592 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3593 ST->getSrcValueOffset()); 3594 } 3595 break; 3596 case MVT::f64: 3597 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3598 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3599 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3600 ST->getSrcValueOffset()); 3601 } else if (TLI.isTypeLegal(MVT::i32)) { 3602 // Many FP stores are not make apparent until after legalize, e.g. for 3603 // argument passing. Since this is so common, custom legalize the 3604 // 64-bit integer store into two 32-bit stores. 3605 uint64_t Val = DoubleToBits(CFP->getValue()); 3606 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3607 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3608 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3609 3610 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3611 ST->getSrcValueOffset()); 3612 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3613 DAG.getConstant(4, Ptr.getValueType())); 3614 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3615 ST->getSrcValueOffset()+4); 3616 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3617 } 3618 break; 3619 } 3620 } 3621 } 3622 3623 if (CombinerAA) { 3624 // Walk up chain skipping non-aliasing memory nodes. 3625 SDOperand BetterChain = FindBetterChain(N, Chain); 3626 3627 // If there is a better chain. 3628 if (Chain != BetterChain) { 3629 // Replace the chain to avoid dependency. 3630 SDOperand ReplStore; 3631 if (ST->isTruncatingStore()) { 3632 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3633 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3634 } else { 3635 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3636 ST->getSrcValue(), ST->getSrcValueOffset()); 3637 } 3638 3639 // Create token to keep both nodes around. 3640 SDOperand Token = 3641 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3642 3643 // Don't add users to work list. 3644 return CombineTo(N, Token, false); 3645 } 3646 } 3647 3648 // Try transforming N to an indexed store. 3649 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3650 return SDOperand(N, 0); 3651 3652 return SDOperand(); 3653} 3654 3655SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3656 SDOperand InVec = N->getOperand(0); 3657 SDOperand InVal = N->getOperand(1); 3658 SDOperand EltNo = N->getOperand(2); 3659 3660 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3661 // vector with the inserted element. 3662 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3663 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3664 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3665 if (Elt < Ops.size()) 3666 Ops[Elt] = InVal; 3667 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3668 &Ops[0], Ops.size()); 3669 } 3670 3671 return SDOperand(); 3672} 3673 3674SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3675 SDOperand InVec = N->getOperand(0); 3676 SDOperand InVal = N->getOperand(1); 3677 SDOperand EltNo = N->getOperand(2); 3678 SDOperand NumElts = N->getOperand(3); 3679 SDOperand EltType = N->getOperand(4); 3680 3681 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3682 // vector with the inserted element. 3683 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3684 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3685 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3686 if (Elt < Ops.size()-2) 3687 Ops[Elt] = InVal; 3688 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3689 &Ops[0], Ops.size()); 3690 } 3691 3692 return SDOperand(); 3693} 3694 3695SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3696 unsigned NumInScalars = N->getNumOperands()-2; 3697 SDOperand NumElts = N->getOperand(NumInScalars); 3698 SDOperand EltType = N->getOperand(NumInScalars+1); 3699 3700 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3701 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3702 // two distinct vectors, turn this into a shuffle node. 3703 SDOperand VecIn1, VecIn2; 3704 for (unsigned i = 0; i != NumInScalars; ++i) { 3705 // Ignore undef inputs. 3706 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3707 3708 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3709 // constant index, bail out. 3710 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3711 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3712 VecIn1 = VecIn2 = SDOperand(0, 0); 3713 break; 3714 } 3715 3716 // If the input vector type disagrees with the result of the vbuild_vector, 3717 // we can't make a shuffle. 3718 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3719 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3720 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3721 VecIn1 = VecIn2 = SDOperand(0, 0); 3722 break; 3723 } 3724 3725 // Otherwise, remember this. We allow up to two distinct input vectors. 3726 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3727 continue; 3728 3729 if (VecIn1.Val == 0) { 3730 VecIn1 = ExtractedFromVec; 3731 } else if (VecIn2.Val == 0) { 3732 VecIn2 = ExtractedFromVec; 3733 } else { 3734 // Too many inputs. 3735 VecIn1 = VecIn2 = SDOperand(0, 0); 3736 break; 3737 } 3738 } 3739 3740 // If everything is good, we can make a shuffle operation. 3741 if (VecIn1.Val) { 3742 SmallVector<SDOperand, 8> BuildVecIndices; 3743 for (unsigned i = 0; i != NumInScalars; ++i) { 3744 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3745 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3746 continue; 3747 } 3748 3749 SDOperand Extract = N->getOperand(i); 3750 3751 // If extracting from the first vector, just use the index directly. 3752 if (Extract.getOperand(0) == VecIn1) { 3753 BuildVecIndices.push_back(Extract.getOperand(1)); 3754 continue; 3755 } 3756 3757 // Otherwise, use InIdx + VecSize 3758 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3759 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3760 TLI.getPointerTy())); 3761 } 3762 3763 // Add count and size info. 3764 BuildVecIndices.push_back(NumElts); 3765 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3766 3767 // Return the new VVECTOR_SHUFFLE node. 3768 SDOperand Ops[5]; 3769 Ops[0] = VecIn1; 3770 if (VecIn2.Val) { 3771 Ops[1] = VecIn2; 3772 } else { 3773 // Use an undef vbuild_vector as input for the second operand. 3774 std::vector<SDOperand> UnOps(NumInScalars, 3775 DAG.getNode(ISD::UNDEF, 3776 cast<VTSDNode>(EltType)->getVT())); 3777 UnOps.push_back(NumElts); 3778 UnOps.push_back(EltType); 3779 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3780 &UnOps[0], UnOps.size()); 3781 AddToWorkList(Ops[1].Val); 3782 } 3783 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3784 &BuildVecIndices[0], BuildVecIndices.size()); 3785 Ops[3] = NumElts; 3786 Ops[4] = EltType; 3787 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3788 } 3789 3790 return SDOperand(); 3791} 3792 3793SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3794 SDOperand ShufMask = N->getOperand(2); 3795 unsigned NumElts = ShufMask.getNumOperands(); 3796 3797 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3798 bool isIdentity = true; 3799 for (unsigned i = 0; i != NumElts; ++i) { 3800 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3801 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3802 isIdentity = false; 3803 break; 3804 } 3805 } 3806 if (isIdentity) return N->getOperand(0); 3807 3808 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3809 isIdentity = true; 3810 for (unsigned i = 0; i != NumElts; ++i) { 3811 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3812 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3813 isIdentity = false; 3814 break; 3815 } 3816 } 3817 if (isIdentity) return N->getOperand(1); 3818 3819 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3820 // needed at all. 3821 bool isUnary = true; 3822 bool isSplat = true; 3823 int VecNum = -1; 3824 unsigned BaseIdx = 0; 3825 for (unsigned i = 0; i != NumElts; ++i) 3826 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3827 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3828 int V = (Idx < NumElts) ? 0 : 1; 3829 if (VecNum == -1) { 3830 VecNum = V; 3831 BaseIdx = Idx; 3832 } else { 3833 if (BaseIdx != Idx) 3834 isSplat = false; 3835 if (VecNum != V) { 3836 isUnary = false; 3837 break; 3838 } 3839 } 3840 } 3841 3842 SDOperand N0 = N->getOperand(0); 3843 SDOperand N1 = N->getOperand(1); 3844 // Normalize unary shuffle so the RHS is undef. 3845 if (isUnary && VecNum == 1) 3846 std::swap(N0, N1); 3847 3848 // If it is a splat, check if the argument vector is a build_vector with 3849 // all scalar elements the same. 3850 if (isSplat) { 3851 SDNode *V = N0.Val; 3852 if (V->getOpcode() == ISD::BIT_CONVERT) 3853 V = V->getOperand(0).Val; 3854 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3855 unsigned NumElems = V->getNumOperands()-2; 3856 if (NumElems > BaseIdx) { 3857 SDOperand Base; 3858 bool AllSame = true; 3859 for (unsigned i = 0; i != NumElems; ++i) { 3860 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3861 Base = V->getOperand(i); 3862 break; 3863 } 3864 } 3865 // Splat of <u, u, u, u>, return <u, u, u, u> 3866 if (!Base.Val) 3867 return N0; 3868 for (unsigned i = 0; i != NumElems; ++i) { 3869 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3870 V->getOperand(i) != Base) { 3871 AllSame = false; 3872 break; 3873 } 3874 } 3875 // Splat of <x, x, x, x>, return <x, x, x, x> 3876 if (AllSame) 3877 return N0; 3878 } 3879 } 3880 } 3881 3882 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3883 // into an undef. 3884 if (isUnary || N0 == N1) { 3885 if (N0.getOpcode() == ISD::UNDEF) 3886 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3887 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3888 // first operand. 3889 SmallVector<SDOperand, 8> MappedOps; 3890 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3891 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3892 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3893 MappedOps.push_back(ShufMask.getOperand(i)); 3894 } else { 3895 unsigned NewIdx = 3896 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3897 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3898 } 3899 } 3900 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3901 &MappedOps[0], MappedOps.size()); 3902 AddToWorkList(ShufMask.Val); 3903 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3904 N0, 3905 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3906 ShufMask); 3907 } 3908 3909 return SDOperand(); 3910} 3911 3912SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3913 SDOperand ShufMask = N->getOperand(2); 3914 unsigned NumElts = ShufMask.getNumOperands()-2; 3915 3916 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3917 bool isIdentity = true; 3918 for (unsigned i = 0; i != NumElts; ++i) { 3919 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3920 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3921 isIdentity = false; 3922 break; 3923 } 3924 } 3925 if (isIdentity) return N->getOperand(0); 3926 3927 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3928 isIdentity = true; 3929 for (unsigned i = 0; i != NumElts; ++i) { 3930 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3931 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3932 isIdentity = false; 3933 break; 3934 } 3935 } 3936 if (isIdentity) return N->getOperand(1); 3937 3938 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3939 // needed at all. 3940 bool isUnary = true; 3941 bool isSplat = true; 3942 int VecNum = -1; 3943 unsigned BaseIdx = 0; 3944 for (unsigned i = 0; i != NumElts; ++i) 3945 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3946 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3947 int V = (Idx < NumElts) ? 0 : 1; 3948 if (VecNum == -1) { 3949 VecNum = V; 3950 BaseIdx = Idx; 3951 } else { 3952 if (BaseIdx != Idx) 3953 isSplat = false; 3954 if (VecNum != V) { 3955 isUnary = false; 3956 break; 3957 } 3958 } 3959 } 3960 3961 SDOperand N0 = N->getOperand(0); 3962 SDOperand N1 = N->getOperand(1); 3963 // Normalize unary shuffle so the RHS is undef. 3964 if (isUnary && VecNum == 1) 3965 std::swap(N0, N1); 3966 3967 // If it is a splat, check if the argument vector is a build_vector with 3968 // all scalar elements the same. 3969 if (isSplat) { 3970 SDNode *V = N0.Val; 3971 3972 // If this is a vbit convert that changes the element type of the vector but 3973 // not the number of vector elements, look through it. Be careful not to 3974 // look though conversions that change things like v4f32 to v2f64. 3975 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3976 SDOperand ConvInput = V->getOperand(0); 3977 if (ConvInput.getValueType() == MVT::Vector && 3978 NumElts == 3979 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3980 V = ConvInput.Val; 3981 } 3982 3983 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3984 unsigned NumElems = V->getNumOperands()-2; 3985 if (NumElems > BaseIdx) { 3986 SDOperand Base; 3987 bool AllSame = true; 3988 for (unsigned i = 0; i != NumElems; ++i) { 3989 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3990 Base = V->getOperand(i); 3991 break; 3992 } 3993 } 3994 // Splat of <u, u, u, u>, return <u, u, u, u> 3995 if (!Base.Val) 3996 return N0; 3997 for (unsigned i = 0; i != NumElems; ++i) { 3998 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3999 V->getOperand(i) != Base) { 4000 AllSame = false; 4001 break; 4002 } 4003 } 4004 // Splat of <x, x, x, x>, return <x, x, x, x> 4005 if (AllSame) 4006 return N0; 4007 } 4008 } 4009 } 4010 4011 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4012 // into an undef. 4013 if (isUnary || N0 == N1) { 4014 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4015 // first operand. 4016 SmallVector<SDOperand, 8> MappedOps; 4017 for (unsigned i = 0; i != NumElts; ++i) { 4018 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4019 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4020 MappedOps.push_back(ShufMask.getOperand(i)); 4021 } else { 4022 unsigned NewIdx = 4023 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4024 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4025 } 4026 } 4027 // Add the type/#elts values. 4028 MappedOps.push_back(ShufMask.getOperand(NumElts)); 4029 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 4030 4031 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 4032 &MappedOps[0], MappedOps.size()); 4033 AddToWorkList(ShufMask.Val); 4034 4035 // Build the undef vector. 4036 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 4037 for (unsigned i = 0; i != NumElts; ++i) 4038 MappedOps[i] = UDVal; 4039 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 4040 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 4041 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4042 &MappedOps[0], MappedOps.size()); 4043 4044 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 4045 N0, UDVal, ShufMask, 4046 MappedOps[NumElts], MappedOps[NumElts+1]); 4047 } 4048 4049 return SDOperand(); 4050} 4051 4052/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4053/// a VAND to a vector_shuffle with the destination vector and a zero vector. 4054/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4055/// vector_shuffle V, Zero, <0, 4, 2, 4> 4056SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4057 SDOperand LHS = N->getOperand(0); 4058 SDOperand RHS = N->getOperand(1); 4059 if (N->getOpcode() == ISD::VAND) { 4060 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 4061 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 4062 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 4063 RHS = RHS.getOperand(0); 4064 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 4065 std::vector<SDOperand> IdxOps; 4066 unsigned NumOps = RHS.getNumOperands(); 4067 unsigned NumElts = NumOps-2; 4068 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 4069 for (unsigned i = 0; i != NumElts; ++i) { 4070 SDOperand Elt = RHS.getOperand(i); 4071 if (!isa<ConstantSDNode>(Elt)) 4072 return SDOperand(); 4073 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4074 IdxOps.push_back(DAG.getConstant(i, EVT)); 4075 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4076 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4077 else 4078 return SDOperand(); 4079 } 4080 4081 // Let's see if the target supports this vector_shuffle. 4082 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4083 return SDOperand(); 4084 4085 // Return the new VVECTOR_SHUFFLE node. 4086 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 4087 SDOperand EVTNode = DAG.getValueType(EVT); 4088 std::vector<SDOperand> Ops; 4089 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 4090 EVTNode); 4091 Ops.push_back(LHS); 4092 AddToWorkList(LHS.Val); 4093 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4094 ZeroOps.push_back(NumEltsNode); 4095 ZeroOps.push_back(EVTNode); 4096 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4097 &ZeroOps[0], ZeroOps.size())); 4098 IdxOps.push_back(NumEltsNode); 4099 IdxOps.push_back(EVTNode); 4100 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 4101 &IdxOps[0], IdxOps.size())); 4102 Ops.push_back(NumEltsNode); 4103 Ops.push_back(EVTNode); 4104 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 4105 &Ops[0], Ops.size()); 4106 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 4107 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 4108 DstVecSize, DstVecEVT); 4109 } 4110 return Result; 4111 } 4112 } 4113 return SDOperand(); 4114} 4115 4116/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 4117/// the scalar operation of the vop if it is operating on an integer vector 4118/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 4119SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 4120 ISD::NodeType FPOp) { 4121 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 4122 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 4123 SDOperand LHS = N->getOperand(0); 4124 SDOperand RHS = N->getOperand(1); 4125 SDOperand Shuffle = XformToShuffleWithZero(N); 4126 if (Shuffle.Val) return Shuffle; 4127 4128 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 4129 // this operation. 4130 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 4131 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 4132 SmallVector<SDOperand, 8> Ops; 4133 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 4134 SDOperand LHSOp = LHS.getOperand(i); 4135 SDOperand RHSOp = RHS.getOperand(i); 4136 // If these two elements can't be folded, bail out. 4137 if ((LHSOp.getOpcode() != ISD::UNDEF && 4138 LHSOp.getOpcode() != ISD::Constant && 4139 LHSOp.getOpcode() != ISD::ConstantFP) || 4140 (RHSOp.getOpcode() != ISD::UNDEF && 4141 RHSOp.getOpcode() != ISD::Constant && 4142 RHSOp.getOpcode() != ISD::ConstantFP)) 4143 break; 4144 // Can't fold divide by zero. 4145 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 4146 if ((RHSOp.getOpcode() == ISD::Constant && 4147 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4148 (RHSOp.getOpcode() == ISD::ConstantFP && 4149 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 4150 break; 4151 } 4152 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 4153 AddToWorkList(Ops.back().Val); 4154 assert((Ops.back().getOpcode() == ISD::UNDEF || 4155 Ops.back().getOpcode() == ISD::Constant || 4156 Ops.back().getOpcode() == ISD::ConstantFP) && 4157 "Scalar binop didn't fold!"); 4158 } 4159 4160 if (Ops.size() == LHS.getNumOperands()-2) { 4161 Ops.push_back(*(LHS.Val->op_end()-2)); 4162 Ops.push_back(*(LHS.Val->op_end()-1)); 4163 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 4164 } 4165 } 4166 4167 return SDOperand(); 4168} 4169 4170SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4171 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4172 4173 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4174 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4175 // If we got a simplified select_cc node back from SimplifySelectCC, then 4176 // break it down into a new SETCC node, and a new SELECT node, and then return 4177 // the SELECT node, since we were called with a SELECT node. 4178 if (SCC.Val) { 4179 // Check to see if we got a select_cc back (to turn into setcc/select). 4180 // Otherwise, just return whatever node we got back, like fabs. 4181 if (SCC.getOpcode() == ISD::SELECT_CC) { 4182 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4183 SCC.getOperand(0), SCC.getOperand(1), 4184 SCC.getOperand(4)); 4185 AddToWorkList(SETCC.Val); 4186 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4187 SCC.getOperand(3), SETCC); 4188 } 4189 return SCC; 4190 } 4191 return SDOperand(); 4192} 4193 4194/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4195/// are the two values being selected between, see if we can simplify the 4196/// select. Callers of this should assume that TheSelect is deleted if this 4197/// returns true. As such, they should return the appropriate thing (e.g. the 4198/// node) back to the top-level of the DAG combiner loop to avoid it being 4199/// looked at. 4200/// 4201bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4202 SDOperand RHS) { 4203 4204 // If this is a select from two identical things, try to pull the operation 4205 // through the select. 4206 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4207 // If this is a load and the token chain is identical, replace the select 4208 // of two loads with a load through a select of the address to load from. 4209 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4210 // constants have been dropped into the constant pool. 4211 if (LHS.getOpcode() == ISD::LOAD && 4212 // Token chains must be identical. 4213 LHS.getOperand(0) == RHS.getOperand(0)) { 4214 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4215 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4216 4217 // If this is an EXTLOAD, the VT's must match. 4218 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4219 // FIXME: this conflates two src values, discarding one. This is not 4220 // the right thing to do, but nothing uses srcvalues now. When they do, 4221 // turn SrcValue into a list of locations. 4222 SDOperand Addr; 4223 if (TheSelect->getOpcode() == ISD::SELECT) { 4224 // Check that the condition doesn't reach either load. If so, folding 4225 // this will induce a cycle into the DAG. 4226 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4227 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4228 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4229 TheSelect->getOperand(0), LLD->getBasePtr(), 4230 RLD->getBasePtr()); 4231 } 4232 } else { 4233 // Check that the condition doesn't reach either load. If so, folding 4234 // this will induce a cycle into the DAG. 4235 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4236 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4237 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4238 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4239 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4240 TheSelect->getOperand(0), 4241 TheSelect->getOperand(1), 4242 LLD->getBasePtr(), RLD->getBasePtr(), 4243 TheSelect->getOperand(4)); 4244 } 4245 } 4246 4247 if (Addr.Val) { 4248 SDOperand Load; 4249 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4250 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4251 Addr,LLD->getSrcValue(), 4252 LLD->getSrcValueOffset(), 4253 LLD->isVolatile(), 4254 LLD->getAlignment()); 4255 else { 4256 Load = DAG.getExtLoad(LLD->getExtensionType(), 4257 TheSelect->getValueType(0), 4258 LLD->getChain(), Addr, LLD->getSrcValue(), 4259 LLD->getSrcValueOffset(), 4260 LLD->getLoadedVT(), 4261 LLD->isVolatile(), 4262 LLD->getAlignment()); 4263 } 4264 // Users of the select now use the result of the load. 4265 CombineTo(TheSelect, Load); 4266 4267 // Users of the old loads now use the new load's chain. We know the 4268 // old-load value is dead now. 4269 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4270 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4271 return true; 4272 } 4273 } 4274 } 4275 } 4276 4277 return false; 4278} 4279 4280SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4281 SDOperand N2, SDOperand N3, 4282 ISD::CondCode CC, bool NotExtCompare) { 4283 4284 MVT::ValueType VT = N2.getValueType(); 4285 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4286 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4287 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4288 4289 // Determine if the condition we're dealing with is constant 4290 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4291 if (SCC.Val) AddToWorkList(SCC.Val); 4292 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4293 4294 // fold select_cc true, x, y -> x 4295 if (SCCC && SCCC->getValue()) 4296 return N2; 4297 // fold select_cc false, x, y -> y 4298 if (SCCC && SCCC->getValue() == 0) 4299 return N3; 4300 4301 // Check to see if we can simplify the select into an fabs node 4302 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4303 // Allow either -0.0 or 0.0 4304 if (CFP->getValue() == 0.0) { 4305 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4306 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4307 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4308 N2 == N3.getOperand(0)) 4309 return DAG.getNode(ISD::FABS, VT, N0); 4310 4311 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4312 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4313 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4314 N2.getOperand(0) == N3) 4315 return DAG.getNode(ISD::FABS, VT, N3); 4316 } 4317 } 4318 4319 // Check to see if we can perform the "gzip trick", transforming 4320 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4321 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4322 MVT::isInteger(N0.getValueType()) && 4323 MVT::isInteger(N2.getValueType()) && 4324 (N1C->isNullValue() || // (a < 0) ? b : 0 4325 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4326 MVT::ValueType XType = N0.getValueType(); 4327 MVT::ValueType AType = N2.getValueType(); 4328 if (XType >= AType) { 4329 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4330 // single-bit constant. 4331 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4332 unsigned ShCtV = Log2_64(N2C->getValue()); 4333 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4334 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4335 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4336 AddToWorkList(Shift.Val); 4337 if (XType > AType) { 4338 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4339 AddToWorkList(Shift.Val); 4340 } 4341 return DAG.getNode(ISD::AND, AType, Shift, N2); 4342 } 4343 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4344 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4345 TLI.getShiftAmountTy())); 4346 AddToWorkList(Shift.Val); 4347 if (XType > AType) { 4348 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4349 AddToWorkList(Shift.Val); 4350 } 4351 return DAG.getNode(ISD::AND, AType, Shift, N2); 4352 } 4353 } 4354 4355 // fold select C, 16, 0 -> shl C, 4 4356 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4357 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4358 4359 // If the caller doesn't want us to simplify this into a zext of a compare, 4360 // don't do it. 4361 if (NotExtCompare && N2C->getValue() == 1) 4362 return SDOperand(); 4363 4364 // Get a SetCC of the condition 4365 // FIXME: Should probably make sure that setcc is legal if we ever have a 4366 // target where it isn't. 4367 SDOperand Temp, SCC; 4368 // cast from setcc result type to select result type 4369 if (AfterLegalize) { 4370 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4371 if (N2.getValueType() < SCC.getValueType()) 4372 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4373 else 4374 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4375 } else { 4376 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4377 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4378 } 4379 AddToWorkList(SCC.Val); 4380 AddToWorkList(Temp.Val); 4381 4382 if (N2C->getValue() == 1) 4383 return Temp; 4384 // shl setcc result by log2 n2c 4385 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4386 DAG.getConstant(Log2_64(N2C->getValue()), 4387 TLI.getShiftAmountTy())); 4388 } 4389 4390 // Check to see if this is the equivalent of setcc 4391 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4392 // otherwise, go ahead with the folds. 4393 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4394 MVT::ValueType XType = N0.getValueType(); 4395 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4396 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4397 if (Res.getValueType() != VT) 4398 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4399 return Res; 4400 } 4401 4402 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4403 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4404 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4405 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4406 return DAG.getNode(ISD::SRL, XType, Ctlz, 4407 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4408 TLI.getShiftAmountTy())); 4409 } 4410 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4411 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4412 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4413 N0); 4414 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4415 DAG.getConstant(~0ULL, XType)); 4416 return DAG.getNode(ISD::SRL, XType, 4417 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4418 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4419 TLI.getShiftAmountTy())); 4420 } 4421 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4422 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4423 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4424 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4425 TLI.getShiftAmountTy())); 4426 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4427 } 4428 } 4429 4430 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4431 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4432 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4433 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4434 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4435 MVT::ValueType XType = N0.getValueType(); 4436 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4437 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4438 TLI.getShiftAmountTy())); 4439 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4440 AddToWorkList(Shift.Val); 4441 AddToWorkList(Add.Val); 4442 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4443 } 4444 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4445 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4446 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4447 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4448 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4449 MVT::ValueType XType = N0.getValueType(); 4450 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4451 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4452 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4453 TLI.getShiftAmountTy())); 4454 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4455 AddToWorkList(Shift.Val); 4456 AddToWorkList(Add.Val); 4457 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4458 } 4459 } 4460 } 4461 4462 return SDOperand(); 4463} 4464 4465/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4466SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4467 SDOperand N1, ISD::CondCode Cond, 4468 bool foldBooleans) { 4469 TargetLowering::DAGCombinerInfo 4470 DagCombineInfo(DAG, !AfterLegalize, false, this); 4471 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4472} 4473 4474/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4475/// return a DAG expression to select that will generate the same value by 4476/// multiplying by a magic number. See: 4477/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4478SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4479 std::vector<SDNode*> Built; 4480 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4481 4482 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4483 ii != ee; ++ii) 4484 AddToWorkList(*ii); 4485 return S; 4486} 4487 4488/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4489/// return a DAG expression to select that will generate the same value by 4490/// multiplying by a magic number. See: 4491/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4492SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4493 std::vector<SDNode*> Built; 4494 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4495 4496 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4497 ii != ee; ++ii) 4498 AddToWorkList(*ii); 4499 return S; 4500} 4501 4502/// FindBaseOffset - Return true if base is known not to alias with anything 4503/// but itself. Provides base object and offset as results. 4504static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4505 // Assume it is a primitive operation. 4506 Base = Ptr; Offset = 0; 4507 4508 // If it's an adding a simple constant then integrate the offset. 4509 if (Base.getOpcode() == ISD::ADD) { 4510 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4511 Base = Base.getOperand(0); 4512 Offset += C->getValue(); 4513 } 4514 } 4515 4516 // If it's any of the following then it can't alias with anything but itself. 4517 return isa<FrameIndexSDNode>(Base) || 4518 isa<ConstantPoolSDNode>(Base) || 4519 isa<GlobalAddressSDNode>(Base); 4520} 4521 4522/// isAlias - Return true if there is any possibility that the two addresses 4523/// overlap. 4524bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4525 const Value *SrcValue1, int SrcValueOffset1, 4526 SDOperand Ptr2, int64_t Size2, 4527 const Value *SrcValue2, int SrcValueOffset2) 4528{ 4529 // If they are the same then they must be aliases. 4530 if (Ptr1 == Ptr2) return true; 4531 4532 // Gather base node and offset information. 4533 SDOperand Base1, Base2; 4534 int64_t Offset1, Offset2; 4535 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4536 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4537 4538 // If they have a same base address then... 4539 if (Base1 == Base2) { 4540 // Check to see if the addresses overlap. 4541 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4542 } 4543 4544 // If we know both bases then they can't alias. 4545 if (KnownBase1 && KnownBase2) return false; 4546 4547 if (CombinerGlobalAA) { 4548 // Use alias analysis information. 4549 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4550 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4551 AliasAnalysis::AliasResult AAResult = 4552 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4553 if (AAResult == AliasAnalysis::NoAlias) 4554 return false; 4555 } 4556 4557 // Otherwise we have to assume they alias. 4558 return true; 4559} 4560 4561/// FindAliasInfo - Extracts the relevant alias information from the memory 4562/// node. Returns true if the operand was a load. 4563bool DAGCombiner::FindAliasInfo(SDNode *N, 4564 SDOperand &Ptr, int64_t &Size, 4565 const Value *&SrcValue, int &SrcValueOffset) { 4566 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4567 Ptr = LD->getBasePtr(); 4568 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4569 SrcValue = LD->getSrcValue(); 4570 SrcValueOffset = LD->getSrcValueOffset(); 4571 return true; 4572 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4573 Ptr = ST->getBasePtr(); 4574 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4575 SrcValue = ST->getSrcValue(); 4576 SrcValueOffset = ST->getSrcValueOffset(); 4577 } else { 4578 assert(0 && "FindAliasInfo expected a memory operand"); 4579 } 4580 4581 return false; 4582} 4583 4584/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4585/// looking for aliasing nodes and adding them to the Aliases vector. 4586void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4587 SmallVector<SDOperand, 8> &Aliases) { 4588 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4589 std::set<SDNode *> Visited; // Visited node set. 4590 4591 // Get alias information for node. 4592 SDOperand Ptr; 4593 int64_t Size; 4594 const Value *SrcValue; 4595 int SrcValueOffset; 4596 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4597 4598 // Starting off. 4599 Chains.push_back(OriginalChain); 4600 4601 // Look at each chain and determine if it is an alias. If so, add it to the 4602 // aliases list. If not, then continue up the chain looking for the next 4603 // candidate. 4604 while (!Chains.empty()) { 4605 SDOperand Chain = Chains.back(); 4606 Chains.pop_back(); 4607 4608 // Don't bother if we've been before. 4609 if (Visited.find(Chain.Val) != Visited.end()) continue; 4610 Visited.insert(Chain.Val); 4611 4612 switch (Chain.getOpcode()) { 4613 case ISD::EntryToken: 4614 // Entry token is ideal chain operand, but handled in FindBetterChain. 4615 break; 4616 4617 case ISD::LOAD: 4618 case ISD::STORE: { 4619 // Get alias information for Chain. 4620 SDOperand OpPtr; 4621 int64_t OpSize; 4622 const Value *OpSrcValue; 4623 int OpSrcValueOffset; 4624 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4625 OpSrcValue, OpSrcValueOffset); 4626 4627 // If chain is alias then stop here. 4628 if (!(IsLoad && IsOpLoad) && 4629 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4630 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4631 Aliases.push_back(Chain); 4632 } else { 4633 // Look further up the chain. 4634 Chains.push_back(Chain.getOperand(0)); 4635 // Clean up old chain. 4636 AddToWorkList(Chain.Val); 4637 } 4638 break; 4639 } 4640 4641 case ISD::TokenFactor: 4642 // We have to check each of the operands of the token factor, so we queue 4643 // then up. Adding the operands to the queue (stack) in reverse order 4644 // maintains the original order and increases the likelihood that getNode 4645 // will find a matching token factor (CSE.) 4646 for (unsigned n = Chain.getNumOperands(); n;) 4647 Chains.push_back(Chain.getOperand(--n)); 4648 // Eliminate the token factor if we can. 4649 AddToWorkList(Chain.Val); 4650 break; 4651 4652 default: 4653 // For all other instructions we will just have to take what we can get. 4654 Aliases.push_back(Chain); 4655 break; 4656 } 4657 } 4658} 4659 4660/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4661/// for a better chain (aliasing node.) 4662SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4663 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4664 4665 // Accumulate all the aliases to this node. 4666 GatherAllAliases(N, OldChain, Aliases); 4667 4668 if (Aliases.size() == 0) { 4669 // If no operands then chain to entry token. 4670 return DAG.getEntryNode(); 4671 } else if (Aliases.size() == 1) { 4672 // If a single operand then chain to it. We don't need to revisit it. 4673 return Aliases[0]; 4674 } 4675 4676 // Construct a custom tailored token factor. 4677 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4678 &Aliases[0], Aliases.size()); 4679 4680 // Make sure the old chain gets cleaned up. 4681 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4682 4683 return NewChain; 4684} 4685 4686// SelectionDAG::Combine - This is the entry point for the file. 4687// 4688void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4689 if (!RunningAfterLegalize && ViewDAGCombine1) 4690 viewGraph(); 4691 if (RunningAfterLegalize && ViewDAGCombine2) 4692 viewGraph(); 4693 /// run - This is the main entry point to this class. 4694 /// 4695 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4696} 4697