DAGCombiner.cpp revision 5eed34d208159e02949097ec91d98d5d9eb30e27
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: make truncate see through SIGN_EXTEND and AND 26// FIXME: divide by zero is currently left unfolded. do we want to turn this 27// into an undef? 28// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 29// 30//===----------------------------------------------------------------------===// 31 32#define DEBUG_TYPE "dagcombine" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include <algorithm> 39#include <cmath> 40#include <iostream> 41using namespace llvm; 42 43namespace { 44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 45 46 class DAGCombiner { 47 SelectionDAG &DAG; 48 TargetLowering &TLI; 49 bool AfterLegalize; 50 51 // Worklist of all of the nodes that need to be simplified. 52 std::vector<SDNode*> WorkList; 53 54 /// AddUsersToWorkList - When an instruction is simplified, add all users of 55 /// the instruction to the work lists because they might get more simplified 56 /// now. 57 /// 58 void AddUsersToWorkList(SDNode *N) { 59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 60 UI != UE; ++UI) 61 WorkList.push_back(*UI); 62 } 63 64 /// removeFromWorkList - remove all instances of N from the worklist. 65 /// 66 void removeFromWorkList(SDNode *N) { 67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 68 WorkList.end()); 69 } 70 71 public: 72 void AddToWorkList(SDNode *N) { 73 WorkList.push_back(N); 74 } 75 76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 77 ++NodesCombined; 78 DEBUG(std::cerr << "\nReplacing "; N->dump(); 79 std::cerr << "\nWith: "; To[0].Val->dump(&DAG); 80 std::cerr << " and " << To.size()-1 << " other values\n"); 81 std::vector<SDNode*> NowDead; 82 DAG.ReplaceAllUsesWith(N, To, &NowDead); 83 84 // Push the new nodes and any users onto the worklist 85 for (unsigned i = 0, e = To.size(); i != e; ++i) { 86 WorkList.push_back(To[i].Val); 87 AddUsersToWorkList(To[i].Val); 88 } 89 90 // Nodes can end up on the worklist more than once. Make sure we do 91 // not process a node that has been replaced. 92 removeFromWorkList(N); 93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 94 removeFromWorkList(NowDead[i]); 95 96 // Finally, since the node is now dead, remove it from the graph. 97 DAG.DeleteNode(N); 98 return SDOperand(N, 0); 99 } 100 101 SDOperand CombineTo(SDNode *N, SDOperand Res) { 102 std::vector<SDOperand> To; 103 To.push_back(Res); 104 return CombineTo(N, To); 105 } 106 107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 108 std::vector<SDOperand> To; 109 To.push_back(Res0); 110 To.push_back(Res1); 111 return CombineTo(N, To); 112 } 113 private: 114 115 /// SimplifyDemandedBits - Check the specified integer node value to see if 116 /// it can be simplified or if things it uses can be simplified by bit 117 /// propagation. If so, return true. 118 bool SimplifyDemandedBits(SDOperand Op) { 119 TargetLowering::TargetLoweringOpt TLO(DAG); 120 uint64_t KnownZero, KnownOne; 121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 123 return false; 124 125 // Revisit the node. 126 WorkList.push_back(Op.Val); 127 128 // Replace the old value with the new one. 129 ++NodesCombined; 130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump(); 131 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG)); 132 133 std::vector<SDNode*> NowDead; 134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 135 136 // Push the new node and any (possibly new) users onto the worklist. 137 WorkList.push_back(TLO.New.Val); 138 AddUsersToWorkList(TLO.New.Val); 139 140 // Nodes can end up on the worklist more than once. Make sure we do 141 // not process a node that has been replaced. 142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 143 removeFromWorkList(NowDead[i]); 144 145 // Finally, if the node is now dead, remove it from the graph. The node 146 // may not be dead if the replacement process recursively simplified to 147 // something else needing this node. 148 if (TLO.Old.Val->use_empty()) { 149 removeFromWorkList(TLO.Old.Val); 150 DAG.DeleteNode(TLO.Old.Val); 151 } 152 return true; 153 } 154 155 /// visit - call the node-specific routine that knows how to fold each 156 /// particular type of node. 157 SDOperand visit(SDNode *N); 158 159 // Visitation implementation - Implement dag node combining for different 160 // node types. The semantics are as follows: 161 // Return Value: 162 // SDOperand.Val == 0 - No change was made 163 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 164 // otherwise - N should be replaced by the returned Operand. 165 // 166 SDOperand visitTokenFactor(SDNode *N); 167 SDOperand visitADD(SDNode *N); 168 SDOperand visitSUB(SDNode *N); 169 SDOperand visitMUL(SDNode *N); 170 SDOperand visitSDIV(SDNode *N); 171 SDOperand visitUDIV(SDNode *N); 172 SDOperand visitSREM(SDNode *N); 173 SDOperand visitUREM(SDNode *N); 174 SDOperand visitMULHU(SDNode *N); 175 SDOperand visitMULHS(SDNode *N); 176 SDOperand visitAND(SDNode *N); 177 SDOperand visitOR(SDNode *N); 178 SDOperand visitXOR(SDNode *N); 179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 180 SDOperand visitSHL(SDNode *N); 181 SDOperand visitSRA(SDNode *N); 182 SDOperand visitSRL(SDNode *N); 183 SDOperand visitCTLZ(SDNode *N); 184 SDOperand visitCTTZ(SDNode *N); 185 SDOperand visitCTPOP(SDNode *N); 186 SDOperand visitSELECT(SDNode *N); 187 SDOperand visitSELECT_CC(SDNode *N); 188 SDOperand visitSETCC(SDNode *N); 189 SDOperand visitSIGN_EXTEND(SDNode *N); 190 SDOperand visitZERO_EXTEND(SDNode *N); 191 SDOperand visitANY_EXTEND(SDNode *N); 192 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 193 SDOperand visitTRUNCATE(SDNode *N); 194 SDOperand visitBIT_CONVERT(SDNode *N); 195 SDOperand visitVBIT_CONVERT(SDNode *N); 196 SDOperand visitFADD(SDNode *N); 197 SDOperand visitFSUB(SDNode *N); 198 SDOperand visitFMUL(SDNode *N); 199 SDOperand visitFDIV(SDNode *N); 200 SDOperand visitFREM(SDNode *N); 201 SDOperand visitFCOPYSIGN(SDNode *N); 202 SDOperand visitSINT_TO_FP(SDNode *N); 203 SDOperand visitUINT_TO_FP(SDNode *N); 204 SDOperand visitFP_TO_SINT(SDNode *N); 205 SDOperand visitFP_TO_UINT(SDNode *N); 206 SDOperand visitFP_ROUND(SDNode *N); 207 SDOperand visitFP_ROUND_INREG(SDNode *N); 208 SDOperand visitFP_EXTEND(SDNode *N); 209 SDOperand visitFNEG(SDNode *N); 210 SDOperand visitFABS(SDNode *N); 211 SDOperand visitBRCOND(SDNode *N); 212 SDOperand visitBR_CC(SDNode *N); 213 SDOperand visitLOAD(SDNode *N); 214 SDOperand visitXEXTLOAD(SDNode *N); 215 SDOperand visitSTORE(SDNode *N); 216 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 217 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 218 SDOperand visitVBUILD_VECTOR(SDNode *N); 219 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 220 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 221 222 SDOperand XformToShuffleWithZero(SDNode *N); 223 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 224 225 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 226 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 227 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 228 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 229 SDOperand N3, ISD::CondCode CC); 230 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 231 ISD::CondCode Cond, bool foldBooleans = true); 232 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 233 SDOperand BuildSDIV(SDNode *N); 234 SDOperand BuildUDIV(SDNode *N); 235public: 236 DAGCombiner(SelectionDAG &D) 237 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 238 239 /// Run - runs the dag combiner on all nodes in the work list 240 void Run(bool RunningAfterLegalize); 241 }; 242} 243 244//===----------------------------------------------------------------------===// 245// TargetLowering::DAGCombinerInfo implementation 246//===----------------------------------------------------------------------===// 247 248void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 249 ((DAGCombiner*)DC)->AddToWorkList(N); 250} 251 252SDOperand TargetLowering::DAGCombinerInfo:: 253CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 254 return ((DAGCombiner*)DC)->CombineTo(N, To); 255} 256 257SDOperand TargetLowering::DAGCombinerInfo:: 258CombineTo(SDNode *N, SDOperand Res) { 259 return ((DAGCombiner*)DC)->CombineTo(N, Res); 260} 261 262 263SDOperand TargetLowering::DAGCombinerInfo:: 264CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 265 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 266} 267 268 269 270 271//===----------------------------------------------------------------------===// 272 273 274struct ms { 275 int64_t m; // magic number 276 int64_t s; // shift amount 277}; 278 279struct mu { 280 uint64_t m; // magic number 281 int64_t a; // add indicator 282 int64_t s; // shift amount 283}; 284 285/// magic - calculate the magic numbers required to codegen an integer sdiv as 286/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 287/// or -1. 288static ms magic32(int32_t d) { 289 int32_t p; 290 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 291 const uint32_t two31 = 0x80000000U; 292 struct ms mag; 293 294 ad = abs(d); 295 t = two31 + ((uint32_t)d >> 31); 296 anc = t - 1 - t%ad; // absolute value of nc 297 p = 31; // initialize p 298 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 299 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 300 q2 = two31/ad; // initialize q2 = 2p/abs(d) 301 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 302 do { 303 p = p + 1; 304 q1 = 2*q1; // update q1 = 2p/abs(nc) 305 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 306 if (r1 >= anc) { // must be unsigned comparison 307 q1 = q1 + 1; 308 r1 = r1 - anc; 309 } 310 q2 = 2*q2; // update q2 = 2p/abs(d) 311 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 312 if (r2 >= ad) { // must be unsigned comparison 313 q2 = q2 + 1; 314 r2 = r2 - ad; 315 } 316 delta = ad - r2; 317 } while (q1 < delta || (q1 == delta && r1 == 0)); 318 319 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 320 if (d < 0) mag.m = -mag.m; // resulting magic number 321 mag.s = p - 32; // resulting shift 322 return mag; 323} 324 325/// magicu - calculate the magic numbers required to codegen an integer udiv as 326/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 327static mu magicu32(uint32_t d) { 328 int32_t p; 329 uint32_t nc, delta, q1, r1, q2, r2; 330 struct mu magu; 331 magu.a = 0; // initialize "add" indicator 332 nc = - 1 - (-d)%d; 333 p = 31; // initialize p 334 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 335 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 336 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 337 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 338 do { 339 p = p + 1; 340 if (r1 >= nc - r1 ) { 341 q1 = 2*q1 + 1; // update q1 342 r1 = 2*r1 - nc; // update r1 343 } 344 else { 345 q1 = 2*q1; // update q1 346 r1 = 2*r1; // update r1 347 } 348 if (r2 + 1 >= d - r2) { 349 if (q2 >= 0x7FFFFFFF) magu.a = 1; 350 q2 = 2*q2 + 1; // update q2 351 r2 = 2*r2 + 1 - d; // update r2 352 } 353 else { 354 if (q2 >= 0x80000000) magu.a = 1; 355 q2 = 2*q2; // update q2 356 r2 = 2*r2 + 1; // update r2 357 } 358 delta = d - 1 - r2; 359 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 360 magu.m = q2 + 1; // resulting magic number 361 magu.s = p - 32; // resulting shift 362 return magu; 363} 364 365/// magic - calculate the magic numbers required to codegen an integer sdiv as 366/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 367/// or -1. 368static ms magic64(int64_t d) { 369 int64_t p; 370 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 371 const uint64_t two63 = 9223372036854775808ULL; // 2^63 372 struct ms mag; 373 374 ad = d >= 0 ? d : -d; 375 t = two63 + ((uint64_t)d >> 63); 376 anc = t - 1 - t%ad; // absolute value of nc 377 p = 63; // initialize p 378 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 379 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 380 q2 = two63/ad; // initialize q2 = 2p/abs(d) 381 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 382 do { 383 p = p + 1; 384 q1 = 2*q1; // update q1 = 2p/abs(nc) 385 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 386 if (r1 >= anc) { // must be unsigned comparison 387 q1 = q1 + 1; 388 r1 = r1 - anc; 389 } 390 q2 = 2*q2; // update q2 = 2p/abs(d) 391 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 392 if (r2 >= ad) { // must be unsigned comparison 393 q2 = q2 + 1; 394 r2 = r2 - ad; 395 } 396 delta = ad - r2; 397 } while (q1 < delta || (q1 == delta && r1 == 0)); 398 399 mag.m = q2 + 1; 400 if (d < 0) mag.m = -mag.m; // resulting magic number 401 mag.s = p - 64; // resulting shift 402 return mag; 403} 404 405/// magicu - calculate the magic numbers required to codegen an integer udiv as 406/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 407static mu magicu64(uint64_t d) 408{ 409 int64_t p; 410 uint64_t nc, delta, q1, r1, q2, r2; 411 struct mu magu; 412 magu.a = 0; // initialize "add" indicator 413 nc = - 1 - (-d)%d; 414 p = 63; // initialize p 415 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 416 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 417 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 418 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 419 do { 420 p = p + 1; 421 if (r1 >= nc - r1 ) { 422 q1 = 2*q1 + 1; // update q1 423 r1 = 2*r1 - nc; // update r1 424 } 425 else { 426 q1 = 2*q1; // update q1 427 r1 = 2*r1; // update r1 428 } 429 if (r2 + 1 >= d - r2) { 430 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 431 q2 = 2*q2 + 1; // update q2 432 r2 = 2*r2 + 1 - d; // update r2 433 } 434 else { 435 if (q2 >= 0x8000000000000000ull) magu.a = 1; 436 q2 = 2*q2; // update q2 437 r2 = 2*r2 + 1; // update r2 438 } 439 delta = d - 1 - r2; 440 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 441 magu.m = q2 + 1; // resulting magic number 442 magu.s = p - 64; // resulting shift 443 return magu; 444} 445 446// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 447// that selects between the values 1 and 0, making it equivalent to a setcc. 448// Also, set the incoming LHS, RHS, and CC references to the appropriate 449// nodes based on the type of node we are checking. This simplifies life a 450// bit for the callers. 451static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 452 SDOperand &CC) { 453 if (N.getOpcode() == ISD::SETCC) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(2); 457 return true; 458 } 459 if (N.getOpcode() == ISD::SELECT_CC && 460 N.getOperand(2).getOpcode() == ISD::Constant && 461 N.getOperand(3).getOpcode() == ISD::Constant && 462 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 464 LHS = N.getOperand(0); 465 RHS = N.getOperand(1); 466 CC = N.getOperand(4); 467 return true; 468 } 469 return false; 470} 471 472// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 473// one use. If this is true, it allows the users to invert the operation for 474// free when it is profitable to do so. 475static bool isOneUseSetCC(SDOperand N) { 476 SDOperand N0, N1, N2; 477 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 478 return true; 479 return false; 480} 481 482// FIXME: This should probably go in the ISD class rather than being duplicated 483// in several files. 484static bool isCommutativeBinOp(unsigned Opcode) { 485 switch (Opcode) { 486 case ISD::ADD: 487 case ISD::MUL: 488 case ISD::AND: 489 case ISD::OR: 490 case ISD::XOR: return true; 491 default: return false; // FIXME: Need commutative info for user ops! 492 } 493} 494 495SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 496 MVT::ValueType VT = N0.getValueType(); 497 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 498 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 500 if (isa<ConstantSDNode>(N1)) { 501 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 502 AddToWorkList(OpNode.Val); 503 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 504 } else if (N0.hasOneUse()) { 505 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 506 AddToWorkList(OpNode.Val); 507 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 508 } 509 } 510 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 511 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 512 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 513 if (isa<ConstantSDNode>(N0)) { 514 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 515 AddToWorkList(OpNode.Val); 516 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 517 } else if (N1.hasOneUse()) { 518 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 519 AddToWorkList(OpNode.Val); 520 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 521 } 522 } 523 return SDOperand(); 524} 525 526void DAGCombiner::Run(bool RunningAfterLegalize) { 527 // set the instance variable, so that the various visit routines may use it. 528 AfterLegalize = RunningAfterLegalize; 529 530 // Add all the dag nodes to the worklist. 531 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 532 E = DAG.allnodes_end(); I != E; ++I) 533 WorkList.push_back(I); 534 535 // Create a dummy node (which is not added to allnodes), that adds a reference 536 // to the root node, preventing it from being deleted, and tracking any 537 // changes of the root. 538 HandleSDNode Dummy(DAG.getRoot()); 539 540 541 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 542 TargetLowering::DAGCombinerInfo 543 DagCombineInfo(DAG, !RunningAfterLegalize, this); 544 545 // while the worklist isn't empty, inspect the node on the end of it and 546 // try and combine it. 547 while (!WorkList.empty()) { 548 SDNode *N = WorkList.back(); 549 WorkList.pop_back(); 550 551 // If N has no uses, it is dead. Make sure to revisit all N's operands once 552 // N is deleted from the DAG, since they too may now be dead or may have a 553 // reduced number of uses, allowing other xforms. 554 if (N->use_empty() && N != &Dummy) { 555 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 556 WorkList.push_back(N->getOperand(i).Val); 557 558 removeFromWorkList(N); 559 DAG.DeleteNode(N); 560 continue; 561 } 562 563 SDOperand RV = visit(N); 564 565 // If nothing happened, try a target-specific DAG combine. 566 if (RV.Val == 0) { 567 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 568 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 569 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 570 } 571 572 if (RV.Val) { 573 ++NodesCombined; 574 // If we get back the same node we passed in, rather than a new node or 575 // zero, we know that the node must have defined multiple values and 576 // CombineTo was used. Since CombineTo takes care of the worklist 577 // mechanics for us, we have no work to do in this case. 578 if (RV.Val != N) { 579 DEBUG(std::cerr << "\nReplacing "; N->dump(); 580 std::cerr << "\nWith: "; RV.Val->dump(&DAG); 581 std::cerr << '\n'); 582 std::vector<SDNode*> NowDead; 583 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 584 585 // Push the new node and any users onto the worklist 586 WorkList.push_back(RV.Val); 587 AddUsersToWorkList(RV.Val); 588 589 // Nodes can end up on the worklist more than once. Make sure we do 590 // not process a node that has been replaced. 591 removeFromWorkList(N); 592 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 593 removeFromWorkList(NowDead[i]); 594 595 // Finally, since the node is now dead, remove it from the graph. 596 DAG.DeleteNode(N); 597 } 598 } 599 } 600 601 // If the root changed (e.g. it was a dead load, update the root). 602 DAG.setRoot(Dummy.getValue()); 603} 604 605SDOperand DAGCombiner::visit(SDNode *N) { 606 switch(N->getOpcode()) { 607 default: break; 608 case ISD::TokenFactor: return visitTokenFactor(N); 609 case ISD::ADD: return visitADD(N); 610 case ISD::SUB: return visitSUB(N); 611 case ISD::MUL: return visitMUL(N); 612 case ISD::SDIV: return visitSDIV(N); 613 case ISD::UDIV: return visitUDIV(N); 614 case ISD::SREM: return visitSREM(N); 615 case ISD::UREM: return visitUREM(N); 616 case ISD::MULHU: return visitMULHU(N); 617 case ISD::MULHS: return visitMULHS(N); 618 case ISD::AND: return visitAND(N); 619 case ISD::OR: return visitOR(N); 620 case ISD::XOR: return visitXOR(N); 621 case ISD::SHL: return visitSHL(N); 622 case ISD::SRA: return visitSRA(N); 623 case ISD::SRL: return visitSRL(N); 624 case ISD::CTLZ: return visitCTLZ(N); 625 case ISD::CTTZ: return visitCTTZ(N); 626 case ISD::CTPOP: return visitCTPOP(N); 627 case ISD::SELECT: return visitSELECT(N); 628 case ISD::SELECT_CC: return visitSELECT_CC(N); 629 case ISD::SETCC: return visitSETCC(N); 630 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 631 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 632 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 633 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 634 case ISD::TRUNCATE: return visitTRUNCATE(N); 635 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 636 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 637 case ISD::FADD: return visitFADD(N); 638 case ISD::FSUB: return visitFSUB(N); 639 case ISD::FMUL: return visitFMUL(N); 640 case ISD::FDIV: return visitFDIV(N); 641 case ISD::FREM: return visitFREM(N); 642 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 643 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 644 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 645 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 646 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 647 case ISD::FP_ROUND: return visitFP_ROUND(N); 648 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 649 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 650 case ISD::FNEG: return visitFNEG(N); 651 case ISD::FABS: return visitFABS(N); 652 case ISD::BRCOND: return visitBRCOND(N); 653 case ISD::BR_CC: return visitBR_CC(N); 654 case ISD::LOAD: return visitLOAD(N); 655 case ISD::EXTLOAD: 656 case ISD::SEXTLOAD: 657 case ISD::ZEXTLOAD: return visitXEXTLOAD(N); 658 case ISD::STORE: return visitSTORE(N); 659 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 660 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 661 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 662 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 663 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 664 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 665 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 666 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 667 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 668 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 669 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 670 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 671 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 672 } 673 return SDOperand(); 674} 675 676SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 677 std::vector<SDOperand> Ops; 678 bool Changed = false; 679 680 // If the token factor has two operands and one is the entry token, replace 681 // the token factor with the other operand. 682 if (N->getNumOperands() == 2) { 683 if (N->getOperand(0).getOpcode() == ISD::EntryToken || 684 N->getOperand(0) == N->getOperand(1)) 685 return N->getOperand(1); 686 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 687 return N->getOperand(0); 688 } 689 690 // fold (tokenfactor (tokenfactor)) -> tokenfactor 691 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 692 SDOperand Op = N->getOperand(i); 693 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 694 AddToWorkList(Op.Val); // Remove dead node. 695 Changed = true; 696 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 697 Ops.push_back(Op.getOperand(j)); 698 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) { 699 Ops.push_back(Op); 700 } else { 701 // Deleted an operand that was the same as the last one. 702 Changed = true; 703 } 704 } 705 if (Changed) 706 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 707 return SDOperand(); 708} 709 710SDOperand DAGCombiner::visitADD(SDNode *N) { 711 SDOperand N0 = N->getOperand(0); 712 SDOperand N1 = N->getOperand(1); 713 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 714 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 715 MVT::ValueType VT = N0.getValueType(); 716 717 // fold (add c1, c2) -> c1+c2 718 if (N0C && N1C) 719 return DAG.getNode(ISD::ADD, VT, N0, N1); 720 // canonicalize constant to RHS 721 if (N0C && !N1C) 722 return DAG.getNode(ISD::ADD, VT, N1, N0); 723 // fold (add x, 0) -> x 724 if (N1C && N1C->isNullValue()) 725 return N0; 726 // fold ((c1-A)+c2) -> (c1+c2)-A 727 if (N1C && N0.getOpcode() == ISD::SUB) 728 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 729 return DAG.getNode(ISD::SUB, VT, 730 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 731 N0.getOperand(1)); 732 // reassociate add 733 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 734 if (RADD.Val != 0) 735 return RADD; 736 // fold ((0-A) + B) -> B-A 737 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 738 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 739 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 740 // fold (A + (0-B)) -> A-B 741 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 742 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 743 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 744 // fold (A+(B-A)) -> B 745 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 746 return N1.getOperand(0); 747 748 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 749 return SDOperand(N, 0); 750 751 // fold (a+b) -> (a|b) iff a and b share no bits. 752 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 753 uint64_t LHSZero, LHSOne; 754 uint64_t RHSZero, RHSOne; 755 uint64_t Mask = MVT::getIntVTBitMask(VT); 756 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 757 if (LHSZero) { 758 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 759 760 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 761 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 762 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 763 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 764 return DAG.getNode(ISD::OR, VT, N0, N1); 765 } 766 } 767 768 return SDOperand(); 769} 770 771SDOperand DAGCombiner::visitSUB(SDNode *N) { 772 SDOperand N0 = N->getOperand(0); 773 SDOperand N1 = N->getOperand(1); 774 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 775 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 776 MVT::ValueType VT = N0.getValueType(); 777 778 // fold (sub x, x) -> 0 779 if (N0 == N1) 780 return DAG.getConstant(0, N->getValueType(0)); 781 // fold (sub c1, c2) -> c1-c2 782 if (N0C && N1C) 783 return DAG.getNode(ISD::SUB, VT, N0, N1); 784 // fold (sub x, c) -> (add x, -c) 785 if (N1C) 786 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 787 // fold (A+B)-A -> B 788 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 789 return N0.getOperand(1); 790 // fold (A+B)-B -> A 791 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 792 return N0.getOperand(0); 793 return SDOperand(); 794} 795 796SDOperand DAGCombiner::visitMUL(SDNode *N) { 797 SDOperand N0 = N->getOperand(0); 798 SDOperand N1 = N->getOperand(1); 799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 800 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 801 MVT::ValueType VT = N0.getValueType(); 802 803 // fold (mul c1, c2) -> c1*c2 804 if (N0C && N1C) 805 return DAG.getNode(ISD::MUL, VT, N0, N1); 806 // canonicalize constant to RHS 807 if (N0C && !N1C) 808 return DAG.getNode(ISD::MUL, VT, N1, N0); 809 // fold (mul x, 0) -> 0 810 if (N1C && N1C->isNullValue()) 811 return N1; 812 // fold (mul x, -1) -> 0-x 813 if (N1C && N1C->isAllOnesValue()) 814 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 815 // fold (mul x, (1 << c)) -> x << c 816 if (N1C && isPowerOf2_64(N1C->getValue())) 817 return DAG.getNode(ISD::SHL, VT, N0, 818 DAG.getConstant(Log2_64(N1C->getValue()), 819 TLI.getShiftAmountTy())); 820 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 821 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 822 // FIXME: If the input is something that is easily negated (e.g. a 823 // single-use add), we should put the negate there. 824 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 825 DAG.getNode(ISD::SHL, VT, N0, 826 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 827 TLI.getShiftAmountTy()))); 828 } 829 830 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 831 if (N1C && N0.getOpcode() == ISD::SHL && 832 isa<ConstantSDNode>(N0.getOperand(1))) { 833 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 834 AddToWorkList(C3.Val); 835 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 836 } 837 838 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 839 // use. 840 { 841 SDOperand Sh(0,0), Y(0,0); 842 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 843 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 844 N0.Val->hasOneUse()) { 845 Sh = N0; Y = N1; 846 } else if (N1.getOpcode() == ISD::SHL && 847 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 848 Sh = N1; Y = N0; 849 } 850 if (Sh.Val) { 851 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 852 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 853 } 854 } 855 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 856 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 857 isa<ConstantSDNode>(N0.getOperand(1))) { 858 return DAG.getNode(ISD::ADD, VT, 859 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 860 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 861 } 862 863 // reassociate mul 864 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 865 if (RMUL.Val != 0) 866 return RMUL; 867 return SDOperand(); 868} 869 870SDOperand DAGCombiner::visitSDIV(SDNode *N) { 871 SDOperand N0 = N->getOperand(0); 872 SDOperand N1 = N->getOperand(1); 873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 875 MVT::ValueType VT = N->getValueType(0); 876 877 // fold (sdiv c1, c2) -> c1/c2 878 if (N0C && N1C && !N1C->isNullValue()) 879 return DAG.getNode(ISD::SDIV, VT, N0, N1); 880 // fold (sdiv X, 1) -> X 881 if (N1C && N1C->getSignExtended() == 1LL) 882 return N0; 883 // fold (sdiv X, -1) -> 0-X 884 if (N1C && N1C->isAllOnesValue()) 885 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 886 // If we know the sign bits of both operands are zero, strength reduce to a 887 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 888 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 889 if (TLI.MaskedValueIsZero(N1, SignBit) && 890 TLI.MaskedValueIsZero(N0, SignBit)) 891 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 892 // fold (sdiv X, pow2) -> simple ops after legalize 893 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 894 (isPowerOf2_64(N1C->getSignExtended()) || 895 isPowerOf2_64(-N1C->getSignExtended()))) { 896 // If dividing by powers of two is cheap, then don't perform the following 897 // fold. 898 if (TLI.isPow2DivCheap()) 899 return SDOperand(); 900 int64_t pow2 = N1C->getSignExtended(); 901 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 902 unsigned lg2 = Log2_64(abs2); 903 // Splat the sign bit into the register 904 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 905 DAG.getConstant(MVT::getSizeInBits(VT)-1, 906 TLI.getShiftAmountTy())); 907 AddToWorkList(SGN.Val); 908 // Add (N0 < 0) ? abs2 - 1 : 0; 909 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 910 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 911 TLI.getShiftAmountTy())); 912 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 913 AddToWorkList(SRL.Val); 914 AddToWorkList(ADD.Val); // Divide by pow2 915 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 916 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 917 // If we're dividing by a positive value, we're done. Otherwise, we must 918 // negate the result. 919 if (pow2 > 0) 920 return SRA; 921 AddToWorkList(SRA.Val); 922 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 923 } 924 // if integer divide is expensive and we satisfy the requirements, emit an 925 // alternate sequence. 926 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 927 !TLI.isIntDivCheap()) { 928 SDOperand Op = BuildSDIV(N); 929 if (Op.Val) return Op; 930 } 931 return SDOperand(); 932} 933 934SDOperand DAGCombiner::visitUDIV(SDNode *N) { 935 SDOperand N0 = N->getOperand(0); 936 SDOperand N1 = N->getOperand(1); 937 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 939 MVT::ValueType VT = N->getValueType(0); 940 941 // fold (udiv c1, c2) -> c1/c2 942 if (N0C && N1C && !N1C->isNullValue()) 943 return DAG.getNode(ISD::UDIV, VT, N0, N1); 944 // fold (udiv x, (1 << c)) -> x >>u c 945 if (N1C && isPowerOf2_64(N1C->getValue())) 946 return DAG.getNode(ISD::SRL, VT, N0, 947 DAG.getConstant(Log2_64(N1C->getValue()), 948 TLI.getShiftAmountTy())); 949 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 950 if (N1.getOpcode() == ISD::SHL) { 951 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 952 if (isPowerOf2_64(SHC->getValue())) { 953 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 954 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 955 DAG.getConstant(Log2_64(SHC->getValue()), 956 ADDVT)); 957 AddToWorkList(Add.Val); 958 return DAG.getNode(ISD::SRL, VT, N0, Add); 959 } 960 } 961 } 962 // fold (udiv x, c) -> alternate 963 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 964 SDOperand Op = BuildUDIV(N); 965 if (Op.Val) return Op; 966 } 967 return SDOperand(); 968} 969 970SDOperand DAGCombiner::visitSREM(SDNode *N) { 971 SDOperand N0 = N->getOperand(0); 972 SDOperand N1 = N->getOperand(1); 973 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 974 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 975 MVT::ValueType VT = N->getValueType(0); 976 977 // fold (srem c1, c2) -> c1%c2 978 if (N0C && N1C && !N1C->isNullValue()) 979 return DAG.getNode(ISD::SREM, VT, N0, N1); 980 // If we know the sign bits of both operands are zero, strength reduce to a 981 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 982 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 983 if (TLI.MaskedValueIsZero(N1, SignBit) && 984 TLI.MaskedValueIsZero(N0, SignBit)) 985 return DAG.getNode(ISD::UREM, VT, N0, N1); 986 return SDOperand(); 987} 988 989SDOperand DAGCombiner::visitUREM(SDNode *N) { 990 SDOperand N0 = N->getOperand(0); 991 SDOperand N1 = N->getOperand(1); 992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 994 MVT::ValueType VT = N->getValueType(0); 995 996 // fold (urem c1, c2) -> c1%c2 997 if (N0C && N1C && !N1C->isNullValue()) 998 return DAG.getNode(ISD::UREM, VT, N0, N1); 999 // fold (urem x, pow2) -> (and x, pow2-1) 1000 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1001 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1002 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1003 if (N1.getOpcode() == ISD::SHL) { 1004 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1005 if (isPowerOf2_64(SHC->getValue())) { 1006 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1007 AddToWorkList(Add.Val); 1008 return DAG.getNode(ISD::AND, VT, N0, Add); 1009 } 1010 } 1011 } 1012 return SDOperand(); 1013} 1014 1015SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1016 SDOperand N0 = N->getOperand(0); 1017 SDOperand N1 = N->getOperand(1); 1018 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1019 1020 // fold (mulhs x, 0) -> 0 1021 if (N1C && N1C->isNullValue()) 1022 return N1; 1023 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1024 if (N1C && N1C->getValue() == 1) 1025 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1026 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1027 TLI.getShiftAmountTy())); 1028 return SDOperand(); 1029} 1030 1031SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1032 SDOperand N0 = N->getOperand(0); 1033 SDOperand N1 = N->getOperand(1); 1034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1035 1036 // fold (mulhu x, 0) -> 0 1037 if (N1C && N1C->isNullValue()) 1038 return N1; 1039 // fold (mulhu x, 1) -> 0 1040 if (N1C && N1C->getValue() == 1) 1041 return DAG.getConstant(0, N0.getValueType()); 1042 return SDOperand(); 1043} 1044 1045/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1046/// two operands of the same opcode, try to simplify it. 1047SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1048 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1049 MVT::ValueType VT = N0.getValueType(); 1050 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1051 1052 // For each of OP in AND/OR/XOR: 1053 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1054 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1055 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1056 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1057 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1058 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1059 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1060 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1061 N0.getOperand(0).getValueType(), 1062 N0.getOperand(0), N1.getOperand(0)); 1063 AddToWorkList(ORNode.Val); 1064 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1065 } 1066 1067 // For each of OP in SHL/SRL/SRA/AND... 1068 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1069 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1070 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1071 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1072 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1073 N0.getOperand(1) == N1.getOperand(1)) { 1074 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1075 N0.getOperand(0).getValueType(), 1076 N0.getOperand(0), N1.getOperand(0)); 1077 AddToWorkList(ORNode.Val); 1078 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1079 } 1080 1081 return SDOperand(); 1082} 1083 1084SDOperand DAGCombiner::visitAND(SDNode *N) { 1085 SDOperand N0 = N->getOperand(0); 1086 SDOperand N1 = N->getOperand(1); 1087 SDOperand LL, LR, RL, RR, CC0, CC1; 1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1090 MVT::ValueType VT = N1.getValueType(); 1091 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1092 1093 // fold (and c1, c2) -> c1&c2 1094 if (N0C && N1C) 1095 return DAG.getNode(ISD::AND, VT, N0, N1); 1096 // canonicalize constant to RHS 1097 if (N0C && !N1C) 1098 return DAG.getNode(ISD::AND, VT, N1, N0); 1099 // fold (and x, -1) -> x 1100 if (N1C && N1C->isAllOnesValue()) 1101 return N0; 1102 // if (and x, c) is known to be zero, return 0 1103 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1104 return DAG.getConstant(0, VT); 1105 // reassociate and 1106 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1107 if (RAND.Val != 0) 1108 return RAND; 1109 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1110 if (N1C && N0.getOpcode() == ISD::OR) 1111 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1112 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1113 return N1; 1114 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1115 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1116 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1117 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1118 ~N1C->getValue() & InMask)) { 1119 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1120 N0.getOperand(0)); 1121 1122 // Replace uses of the AND with uses of the Zero extend node. 1123 CombineTo(N, Zext); 1124 1125 // We actually want to replace all uses of the any_extend with the 1126 // zero_extend, to avoid duplicating things. This will later cause this 1127 // AND to be folded. 1128 CombineTo(N0.Val, Zext); 1129 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1130 } 1131 } 1132 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1133 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1134 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1135 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1136 1137 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1138 MVT::isInteger(LL.getValueType())) { 1139 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1140 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1141 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1142 AddToWorkList(ORNode.Val); 1143 return DAG.getSetCC(VT, ORNode, LR, Op1); 1144 } 1145 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1146 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1147 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1148 AddToWorkList(ANDNode.Val); 1149 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1150 } 1151 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1152 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1153 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1154 AddToWorkList(ORNode.Val); 1155 return DAG.getSetCC(VT, ORNode, LR, Op1); 1156 } 1157 } 1158 // canonicalize equivalent to ll == rl 1159 if (LL == RR && LR == RL) { 1160 Op1 = ISD::getSetCCSwappedOperands(Op1); 1161 std::swap(RL, RR); 1162 } 1163 if (LL == RL && LR == RR) { 1164 bool isInteger = MVT::isInteger(LL.getValueType()); 1165 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1166 if (Result != ISD::SETCC_INVALID) 1167 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1168 } 1169 } 1170 1171 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1172 if (N0.getOpcode() == N1.getOpcode()) { 1173 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1174 if (Tmp.Val) return Tmp; 1175 } 1176 1177 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1178 // fold (and (sra)) -> (and (srl)) when possible. 1179 if (!MVT::isVector(VT) && 1180 SimplifyDemandedBits(SDOperand(N, 0))) 1181 return SDOperand(N, 0); 1182 // fold (zext_inreg (extload x)) -> (zextload x) 1183 if (N0.getOpcode() == ISD::EXTLOAD) { 1184 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1185 // If we zero all the possible extended bits, then we can turn this into 1186 // a zextload if we are running before legalize or the operation is legal. 1187 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1188 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1189 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1190 N0.getOperand(1), N0.getOperand(2), 1191 EVT); 1192 AddToWorkList(N); 1193 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1194 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1195 } 1196 } 1197 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1198 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1199 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1200 // If we zero all the possible extended bits, then we can turn this into 1201 // a zextload if we are running before legalize or the operation is legal. 1202 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1203 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1204 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1205 N0.getOperand(1), N0.getOperand(2), 1206 EVT); 1207 AddToWorkList(N); 1208 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1209 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1210 } 1211 } 1212 1213 // fold (and (load x), 255) -> (zextload x, i8) 1214 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1215 if (N1C && 1216 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD || 1217 N0.getOpcode() == ISD::ZEXTLOAD) && 1218 N0.hasOneUse()) { 1219 MVT::ValueType EVT, LoadedVT; 1220 if (N1C->getValue() == 255) 1221 EVT = MVT::i8; 1222 else if (N1C->getValue() == 65535) 1223 EVT = MVT::i16; 1224 else if (N1C->getValue() == ~0U) 1225 EVT = MVT::i32; 1226 else 1227 EVT = MVT::Other; 1228 1229 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT : 1230 cast<VTSDNode>(N0.getOperand(3))->getVT(); 1231 if (EVT != MVT::Other && LoadedVT > EVT && 1232 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1233 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1234 // For big endian targets, we need to add an offset to the pointer to load 1235 // the correct bytes. For little endian systems, we merely need to read 1236 // fewer bytes from the same pointer. 1237 unsigned PtrOff = 1238 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1239 SDOperand NewPtr = N0.getOperand(1); 1240 if (!TLI.isLittleEndian()) 1241 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1242 DAG.getConstant(PtrOff, PtrType)); 1243 AddToWorkList(NewPtr.Val); 1244 SDOperand Load = 1245 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr, 1246 N0.getOperand(2), EVT); 1247 AddToWorkList(N); 1248 CombineTo(N0.Val, Load, Load.getValue(1)); 1249 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1250 } 1251 } 1252 1253 return SDOperand(); 1254} 1255 1256SDOperand DAGCombiner::visitOR(SDNode *N) { 1257 SDOperand N0 = N->getOperand(0); 1258 SDOperand N1 = N->getOperand(1); 1259 SDOperand LL, LR, RL, RR, CC0, CC1; 1260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1261 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1262 MVT::ValueType VT = N1.getValueType(); 1263 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1264 1265 // fold (or c1, c2) -> c1|c2 1266 if (N0C && N1C) 1267 return DAG.getNode(ISD::OR, VT, N0, N1); 1268 // canonicalize constant to RHS 1269 if (N0C && !N1C) 1270 return DAG.getNode(ISD::OR, VT, N1, N0); 1271 // fold (or x, 0) -> x 1272 if (N1C && N1C->isNullValue()) 1273 return N0; 1274 // fold (or x, -1) -> -1 1275 if (N1C && N1C->isAllOnesValue()) 1276 return N1; 1277 // fold (or x, c) -> c iff (x & ~c) == 0 1278 if (N1C && 1279 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1280 return N1; 1281 // reassociate or 1282 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1283 if (ROR.Val != 0) 1284 return ROR; 1285 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1286 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1287 isa<ConstantSDNode>(N0.getOperand(1))) { 1288 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1289 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1290 N1), 1291 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1292 } 1293 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1294 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1295 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1296 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1297 1298 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1299 MVT::isInteger(LL.getValueType())) { 1300 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1301 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1302 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1303 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1304 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1305 AddToWorkList(ORNode.Val); 1306 return DAG.getSetCC(VT, ORNode, LR, Op1); 1307 } 1308 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1309 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1310 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1311 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1312 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1313 AddToWorkList(ANDNode.Val); 1314 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1315 } 1316 } 1317 // canonicalize equivalent to ll == rl 1318 if (LL == RR && LR == RL) { 1319 Op1 = ISD::getSetCCSwappedOperands(Op1); 1320 std::swap(RL, RR); 1321 } 1322 if (LL == RL && LR == RR) { 1323 bool isInteger = MVT::isInteger(LL.getValueType()); 1324 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1325 if (Result != ISD::SETCC_INVALID) 1326 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1327 } 1328 } 1329 1330 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1331 if (N0.getOpcode() == N1.getOpcode()) { 1332 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1333 if (Tmp.Val) return Tmp; 1334 } 1335 1336 // canonicalize shl to left side in a shl/srl pair, to match rotate 1337 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1338 std::swap(N0, N1); 1339 // check for rotl, rotr 1340 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1341 N0.getOperand(0) == N1.getOperand(0) && 1342 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1343 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1344 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1345 N1.getOperand(1).getOpcode() == ISD::Constant) { 1346 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1347 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1348 if ((c1val + c2val) == OpSizeInBits) 1349 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1350 } 1351 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1352 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1353 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1354 if (ConstantSDNode *SUBC = 1355 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1356 if (SUBC->getValue() == OpSizeInBits) 1357 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1358 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1359 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1360 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1361 if (ConstantSDNode *SUBC = 1362 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1363 if (SUBC->getValue() == OpSizeInBits) { 1364 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1365 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1366 N1.getOperand(1)); 1367 else 1368 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1369 N0.getOperand(1)); 1370 } 1371 } 1372 return SDOperand(); 1373} 1374 1375SDOperand DAGCombiner::visitXOR(SDNode *N) { 1376 SDOperand N0 = N->getOperand(0); 1377 SDOperand N1 = N->getOperand(1); 1378 SDOperand LHS, RHS, CC; 1379 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1380 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1381 MVT::ValueType VT = N0.getValueType(); 1382 1383 // fold (xor c1, c2) -> c1^c2 1384 if (N0C && N1C) 1385 return DAG.getNode(ISD::XOR, VT, N0, N1); 1386 // canonicalize constant to RHS 1387 if (N0C && !N1C) 1388 return DAG.getNode(ISD::XOR, VT, N1, N0); 1389 // fold (xor x, 0) -> x 1390 if (N1C && N1C->isNullValue()) 1391 return N0; 1392 // reassociate xor 1393 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1394 if (RXOR.Val != 0) 1395 return RXOR; 1396 // fold !(x cc y) -> (x !cc y) 1397 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1398 bool isInt = MVT::isInteger(LHS.getValueType()); 1399 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1400 isInt); 1401 if (N0.getOpcode() == ISD::SETCC) 1402 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1403 if (N0.getOpcode() == ISD::SELECT_CC) 1404 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1405 assert(0 && "Unhandled SetCC Equivalent!"); 1406 abort(); 1407 } 1408 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1409 if (N1C && N1C->getValue() == 1 && 1410 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1411 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1412 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1413 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1414 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1415 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1416 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1417 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1418 } 1419 } 1420 // fold !(x or y) -> (!x and !y) iff x or y are constants 1421 if (N1C && N1C->isAllOnesValue() && 1422 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1423 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1424 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1425 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1426 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1427 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1428 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1429 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1430 } 1431 } 1432 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1433 if (N1C && N0.getOpcode() == ISD::XOR) { 1434 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1435 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1436 if (N00C) 1437 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1438 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1439 if (N01C) 1440 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1441 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1442 } 1443 // fold (xor x, x) -> 0 1444 if (N0 == N1) { 1445 if (!MVT::isVector(VT)) { 1446 return DAG.getConstant(0, VT); 1447 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1448 // Produce a vector of zeros. 1449 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1450 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1451 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops); 1452 } 1453 } 1454 1455 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1456 if (N0.getOpcode() == N1.getOpcode()) { 1457 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1458 if (Tmp.Val) return Tmp; 1459 } 1460 1461 // Simplify the expression using non-local knowledge. 1462 if (!MVT::isVector(VT) && 1463 SimplifyDemandedBits(SDOperand(N, 0))) 1464 return SDOperand(N, 0); 1465 1466 return SDOperand(); 1467} 1468 1469SDOperand DAGCombiner::visitSHL(SDNode *N) { 1470 SDOperand N0 = N->getOperand(0); 1471 SDOperand N1 = N->getOperand(1); 1472 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1473 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1474 MVT::ValueType VT = N0.getValueType(); 1475 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1476 1477 // fold (shl c1, c2) -> c1<<c2 1478 if (N0C && N1C) 1479 return DAG.getNode(ISD::SHL, VT, N0, N1); 1480 // fold (shl 0, x) -> 0 1481 if (N0C && N0C->isNullValue()) 1482 return N0; 1483 // fold (shl x, c >= size(x)) -> undef 1484 if (N1C && N1C->getValue() >= OpSizeInBits) 1485 return DAG.getNode(ISD::UNDEF, VT); 1486 // fold (shl x, 0) -> x 1487 if (N1C && N1C->isNullValue()) 1488 return N0; 1489 // if (shl x, c) is known to be zero, return 0 1490 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1491 return DAG.getConstant(0, VT); 1492 if (SimplifyDemandedBits(SDOperand(N, 0))) 1493 return SDOperand(N, 0); 1494 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1495 if (N1C && N0.getOpcode() == ISD::SHL && 1496 N0.getOperand(1).getOpcode() == ISD::Constant) { 1497 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1498 uint64_t c2 = N1C->getValue(); 1499 if (c1 + c2 > OpSizeInBits) 1500 return DAG.getConstant(0, VT); 1501 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1502 DAG.getConstant(c1 + c2, N1.getValueType())); 1503 } 1504 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1505 // (srl (and x, -1 << c1), c1-c2) 1506 if (N1C && N0.getOpcode() == ISD::SRL && 1507 N0.getOperand(1).getOpcode() == ISD::Constant) { 1508 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1509 uint64_t c2 = N1C->getValue(); 1510 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1511 DAG.getConstant(~0ULL << c1, VT)); 1512 if (c2 > c1) 1513 return DAG.getNode(ISD::SHL, VT, Mask, 1514 DAG.getConstant(c2-c1, N1.getValueType())); 1515 else 1516 return DAG.getNode(ISD::SRL, VT, Mask, 1517 DAG.getConstant(c1-c2, N1.getValueType())); 1518 } 1519 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1520 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1521 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1522 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1523 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2) 1524 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1525 isa<ConstantSDNode>(N0.getOperand(1))) { 1526 return DAG.getNode(ISD::ADD, VT, 1527 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1), 1528 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1)); 1529 } 1530 return SDOperand(); 1531} 1532 1533SDOperand DAGCombiner::visitSRA(SDNode *N) { 1534 SDOperand N0 = N->getOperand(0); 1535 SDOperand N1 = N->getOperand(1); 1536 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1538 MVT::ValueType VT = N0.getValueType(); 1539 1540 // fold (sra c1, c2) -> c1>>c2 1541 if (N0C && N1C) 1542 return DAG.getNode(ISD::SRA, VT, N0, N1); 1543 // fold (sra 0, x) -> 0 1544 if (N0C && N0C->isNullValue()) 1545 return N0; 1546 // fold (sra -1, x) -> -1 1547 if (N0C && N0C->isAllOnesValue()) 1548 return N0; 1549 // fold (sra x, c >= size(x)) -> undef 1550 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1551 return DAG.getNode(ISD::UNDEF, VT); 1552 // fold (sra x, 0) -> x 1553 if (N1C && N1C->isNullValue()) 1554 return N0; 1555 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1556 // sext_inreg. 1557 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1558 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1559 MVT::ValueType EVT; 1560 switch (LowBits) { 1561 default: EVT = MVT::Other; break; 1562 case 1: EVT = MVT::i1; break; 1563 case 8: EVT = MVT::i8; break; 1564 case 16: EVT = MVT::i16; break; 1565 case 32: EVT = MVT::i32; break; 1566 } 1567 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1568 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1569 DAG.getValueType(EVT)); 1570 } 1571 1572 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1573 if (N1C && N0.getOpcode() == ISD::SRA) { 1574 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1575 unsigned Sum = N1C->getValue() + C1->getValue(); 1576 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1577 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1578 DAG.getConstant(Sum, N1C->getValueType(0))); 1579 } 1580 } 1581 1582 // Simplify, based on bits shifted out of the LHS. 1583 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1584 return SDOperand(N, 0); 1585 1586 1587 // If the sign bit is known to be zero, switch this to a SRL. 1588 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1589 return DAG.getNode(ISD::SRL, VT, N0, N1); 1590 return SDOperand(); 1591} 1592 1593SDOperand DAGCombiner::visitSRL(SDNode *N) { 1594 SDOperand N0 = N->getOperand(0); 1595 SDOperand N1 = N->getOperand(1); 1596 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1597 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1598 MVT::ValueType VT = N0.getValueType(); 1599 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1600 1601 // fold (srl c1, c2) -> c1 >>u c2 1602 if (N0C && N1C) 1603 return DAG.getNode(ISD::SRL, VT, N0, N1); 1604 // fold (srl 0, x) -> 0 1605 if (N0C && N0C->isNullValue()) 1606 return N0; 1607 // fold (srl x, c >= size(x)) -> undef 1608 if (N1C && N1C->getValue() >= OpSizeInBits) 1609 return DAG.getNode(ISD::UNDEF, VT); 1610 // fold (srl x, 0) -> x 1611 if (N1C && N1C->isNullValue()) 1612 return N0; 1613 // if (srl x, c) is known to be zero, return 0 1614 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1615 return DAG.getConstant(0, VT); 1616 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1617 if (N1C && N0.getOpcode() == ISD::SRL && 1618 N0.getOperand(1).getOpcode() == ISD::Constant) { 1619 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1620 uint64_t c2 = N1C->getValue(); 1621 if (c1 + c2 > OpSizeInBits) 1622 return DAG.getConstant(0, VT); 1623 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1624 DAG.getConstant(c1 + c2, N1.getValueType())); 1625 } 1626 1627 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1628 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1629 // Shifting in all undef bits? 1630 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1631 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1632 return DAG.getNode(ISD::UNDEF, VT); 1633 1634 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1635 AddToWorkList(SmallShift.Val); 1636 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1637 } 1638 1639 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1640 if (N1C && N0.getOpcode() == ISD::CTLZ && 1641 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1642 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1643 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1644 1645 // If any of the input bits are KnownOne, then the input couldn't be all 1646 // zeros, thus the result of the srl will always be zero. 1647 if (KnownOne) return DAG.getConstant(0, VT); 1648 1649 // If all of the bits input the to ctlz node are known to be zero, then 1650 // the result of the ctlz is "32" and the result of the shift is one. 1651 uint64_t UnknownBits = ~KnownZero & Mask; 1652 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1653 1654 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1655 if ((UnknownBits & (UnknownBits-1)) == 0) { 1656 // Okay, we know that only that the single bit specified by UnknownBits 1657 // could be set on input to the CTLZ node. If this bit is set, the SRL 1658 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1659 // to an SRL,XOR pair, which is likely to simplify more. 1660 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1661 SDOperand Op = N0.getOperand(0); 1662 if (ShAmt) { 1663 Op = DAG.getNode(ISD::SRL, VT, Op, 1664 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1665 AddToWorkList(Op.Val); 1666 } 1667 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1668 } 1669 } 1670 1671 return SDOperand(); 1672} 1673 1674SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1675 SDOperand N0 = N->getOperand(0); 1676 MVT::ValueType VT = N->getValueType(0); 1677 1678 // fold (ctlz c1) -> c2 1679 if (isa<ConstantSDNode>(N0)) 1680 return DAG.getNode(ISD::CTLZ, VT, N0); 1681 return SDOperand(); 1682} 1683 1684SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1685 SDOperand N0 = N->getOperand(0); 1686 MVT::ValueType VT = N->getValueType(0); 1687 1688 // fold (cttz c1) -> c2 1689 if (isa<ConstantSDNode>(N0)) 1690 return DAG.getNode(ISD::CTTZ, VT, N0); 1691 return SDOperand(); 1692} 1693 1694SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1695 SDOperand N0 = N->getOperand(0); 1696 MVT::ValueType VT = N->getValueType(0); 1697 1698 // fold (ctpop c1) -> c2 1699 if (isa<ConstantSDNode>(N0)) 1700 return DAG.getNode(ISD::CTPOP, VT, N0); 1701 return SDOperand(); 1702} 1703 1704SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1705 SDOperand N0 = N->getOperand(0); 1706 SDOperand N1 = N->getOperand(1); 1707 SDOperand N2 = N->getOperand(2); 1708 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1709 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1710 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1711 MVT::ValueType VT = N->getValueType(0); 1712 1713 // fold select C, X, X -> X 1714 if (N1 == N2) 1715 return N1; 1716 // fold select true, X, Y -> X 1717 if (N0C && !N0C->isNullValue()) 1718 return N1; 1719 // fold select false, X, Y -> Y 1720 if (N0C && N0C->isNullValue()) 1721 return N2; 1722 // fold select C, 1, X -> C | X 1723 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1724 return DAG.getNode(ISD::OR, VT, N0, N2); 1725 // fold select C, 0, X -> ~C & X 1726 // FIXME: this should check for C type == X type, not i1? 1727 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1728 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1729 AddToWorkList(XORNode.Val); 1730 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1731 } 1732 // fold select C, X, 1 -> ~C | X 1733 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1734 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1735 AddToWorkList(XORNode.Val); 1736 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1737 } 1738 // fold select C, X, 0 -> C & X 1739 // FIXME: this should check for C type == X type, not i1? 1740 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1741 return DAG.getNode(ISD::AND, VT, N0, N1); 1742 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1743 if (MVT::i1 == VT && N0 == N1) 1744 return DAG.getNode(ISD::OR, VT, N0, N2); 1745 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1746 if (MVT::i1 == VT && N0 == N2) 1747 return DAG.getNode(ISD::AND, VT, N0, N1); 1748 // If we can fold this based on the true/false value, do so. 1749 if (SimplifySelectOps(N, N1, N2)) 1750 return SDOperand(); 1751 // fold selects based on a setcc into other things, such as min/max/abs 1752 if (N0.getOpcode() == ISD::SETCC) 1753 // FIXME: 1754 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1755 // having to say they don't support SELECT_CC on every type the DAG knows 1756 // about, since there is no way to mark an opcode illegal at all value types 1757 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1758 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1759 N1, N2, N0.getOperand(2)); 1760 else 1761 return SimplifySelect(N0, N1, N2); 1762 return SDOperand(); 1763} 1764 1765SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1766 SDOperand N0 = N->getOperand(0); 1767 SDOperand N1 = N->getOperand(1); 1768 SDOperand N2 = N->getOperand(2); 1769 SDOperand N3 = N->getOperand(3); 1770 SDOperand N4 = N->getOperand(4); 1771 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1772 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1773 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1774 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1775 1776 // Determine if the condition we're dealing with is constant 1777 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1778 //ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1779 1780 // fold select_cc lhs, rhs, x, x, cc -> x 1781 if (N2 == N3) 1782 return N2; 1783 1784 // If we can fold this based on the true/false value, do so. 1785 if (SimplifySelectOps(N, N2, N3)) 1786 return SDOperand(); 1787 1788 // fold select_cc into other things, such as min/max/abs 1789 return SimplifySelectCC(N0, N1, N2, N3, CC); 1790} 1791 1792SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1793 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1794 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1795} 1796 1797SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1798 SDOperand N0 = N->getOperand(0); 1799 MVT::ValueType VT = N->getValueType(0); 1800 1801 // fold (sext c1) -> c1 1802 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1803 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1804 1805 // fold (sext (sext x)) -> (sext x) 1806 // fold (sext (aext x)) -> (sext x) 1807 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1808 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1809 1810 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1811 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1812 (!AfterLegalize || 1813 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1814 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1815 DAG.getValueType(N0.getValueType())); 1816 1817 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1818 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1819 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1820 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1821 N0.getOperand(1), N0.getOperand(2), 1822 N0.getValueType()); 1823 CombineTo(N, ExtLoad); 1824 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1825 ExtLoad.getValue(1)); 1826 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1827 } 1828 1829 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1830 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1831 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1832 N0.hasOneUse()) { 1833 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1834 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1835 N0.getOperand(1), N0.getOperand(2), EVT); 1836 CombineTo(N, ExtLoad); 1837 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1838 ExtLoad.getValue(1)); 1839 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1840 } 1841 1842 return SDOperand(); 1843} 1844 1845SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1846 SDOperand N0 = N->getOperand(0); 1847 MVT::ValueType VT = N->getValueType(0); 1848 1849 // fold (zext c1) -> c1 1850 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0)) 1851 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1852 // fold (zext (zext x)) -> (zext x) 1853 // fold (zext (aext x)) -> (zext x) 1854 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1855 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1856 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1857 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1858 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1859 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1860 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1861 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1862 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1863 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1864 N0.getOperand(1), N0.getOperand(2), 1865 N0.getValueType()); 1866 CombineTo(N, ExtLoad); 1867 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1868 ExtLoad.getValue(1)); 1869 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1870 } 1871 1872 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1873 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1874 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1875 N0.hasOneUse()) { 1876 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1877 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1878 N0.getOperand(1), N0.getOperand(2), EVT); 1879 CombineTo(N, ExtLoad); 1880 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1881 ExtLoad.getValue(1)); 1882 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1883 } 1884 return SDOperand(); 1885} 1886 1887SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 1888 SDOperand N0 = N->getOperand(0); 1889 MVT::ValueType VT = N->getValueType(0); 1890 1891 // fold (aext c1) -> c1 1892 if (isa<ConstantSDNode>(N0)) 1893 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 1894 // fold (aext (aext x)) -> (aext x) 1895 // fold (aext (zext x)) -> (zext x) 1896 // fold (aext (sext x)) -> (sext x) 1897 if (N0.getOpcode() == ISD::ANY_EXTEND || 1898 N0.getOpcode() == ISD::ZERO_EXTEND || 1899 N0.getOpcode() == ISD::SIGN_EXTEND) 1900 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1901 1902 // fold (aext (truncate x)) -> x iff x size == zext size. 1903 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT) 1904 return N0.getOperand(0); 1905 // fold (aext (load x)) -> (aext (truncate (extload x))) 1906 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1907 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 1908 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 1909 N0.getOperand(1), N0.getOperand(2), 1910 N0.getValueType()); 1911 CombineTo(N, ExtLoad); 1912 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1913 ExtLoad.getValue(1)); 1914 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1915 } 1916 1917 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 1918 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 1919 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 1920 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD || 1921 N0.getOpcode() == ISD::SEXTLOAD) && 1922 N0.hasOneUse()) { 1923 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1924 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0), 1925 N0.getOperand(1), N0.getOperand(2), EVT); 1926 CombineTo(N, ExtLoad); 1927 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1928 ExtLoad.getValue(1)); 1929 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1930 } 1931 return SDOperand(); 1932} 1933 1934 1935SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1936 SDOperand N0 = N->getOperand(0); 1937 SDOperand N1 = N->getOperand(1); 1938 MVT::ValueType VT = N->getValueType(0); 1939 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1940 unsigned EVTBits = MVT::getSizeInBits(EVT); 1941 1942 // fold (sext_in_reg c1) -> c1 1943 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 1944 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 1945 1946 // If the input is already sign extended, just drop the extension. 1947 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 1948 return N0; 1949 1950 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1951 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1952 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1953 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1954 } 1955 1956 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1957 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1958 return DAG.getZeroExtendInReg(N0, EVT); 1959 1960 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 1961 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 1962 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 1963 if (N0.getOpcode() == ISD::SRL) { 1964 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1965 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 1966 // We can turn this into an SRA iff the input to the SRL is already sign 1967 // extended enough. 1968 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 1969 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 1970 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 1971 } 1972 } 1973 1974 // fold (sext_inreg (extload x)) -> (sextload x) 1975 if (N0.getOpcode() == ISD::EXTLOAD && 1976 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1977 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1978 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1979 N0.getOperand(1), N0.getOperand(2), 1980 EVT); 1981 CombineTo(N, ExtLoad); 1982 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1983 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1984 } 1985 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1986 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1987 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1988 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1989 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1990 N0.getOperand(1), N0.getOperand(2), 1991 EVT); 1992 CombineTo(N, ExtLoad); 1993 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1994 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1995 } 1996 return SDOperand(); 1997} 1998 1999SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2000 SDOperand N0 = N->getOperand(0); 2001 MVT::ValueType VT = N->getValueType(0); 2002 2003 // noop truncate 2004 if (N0.getValueType() == N->getValueType(0)) 2005 return N0; 2006 // fold (truncate c1) -> c1 2007 if (isa<ConstantSDNode>(N0)) 2008 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2009 // fold (truncate (truncate x)) -> (truncate x) 2010 if (N0.getOpcode() == ISD::TRUNCATE) 2011 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2012 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2013 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2014 N0.getOpcode() == ISD::ANY_EXTEND) { 2015 if (N0.getValueType() < VT) 2016 // if the source is smaller than the dest, we still need an extend 2017 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2018 else if (N0.getValueType() > VT) 2019 // if the source is larger than the dest, than we just need the truncate 2020 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2021 else 2022 // if the source and dest are the same type, we can drop both the extend 2023 // and the truncate 2024 return N0.getOperand(0); 2025 } 2026 // fold (truncate (load x)) -> (smaller load x) 2027 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2028 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2029 "Cannot truncate to larger type!"); 2030 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2031 // For big endian targets, we need to add an offset to the pointer to load 2032 // the correct bytes. For little endian systems, we merely need to read 2033 // fewer bytes from the same pointer. 2034 uint64_t PtrOff = 2035 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2036 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 2037 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 2038 DAG.getConstant(PtrOff, PtrType)); 2039 AddToWorkList(NewPtr.Val); 2040 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 2041 AddToWorkList(N); 2042 CombineTo(N0.Val, Load, Load.getValue(1)); 2043 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2044 } 2045 return SDOperand(); 2046} 2047 2048SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2049 SDOperand N0 = N->getOperand(0); 2050 MVT::ValueType VT = N->getValueType(0); 2051 2052 // If the input is a constant, let getNode() fold it. 2053 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2054 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2055 if (Res.Val != N) return Res; 2056 } 2057 2058 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2059 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2060 2061 // fold (conv (load x)) -> (load (conv*)x) 2062 // FIXME: These xforms need to know that the resultant load doesn't need a 2063 // higher alignment than the original! 2064 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 2065 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 2066 N0.getOperand(2)); 2067 AddToWorkList(N); 2068 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2069 Load.getValue(1)); 2070 return Load; 2071 } 2072 2073 return SDOperand(); 2074} 2075 2076SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2077 SDOperand N0 = N->getOperand(0); 2078 MVT::ValueType VT = N->getValueType(0); 2079 2080 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2081 // First check to see if this is all constant. 2082 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2083 VT == MVT::Vector) { 2084 bool isSimple = true; 2085 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2086 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2087 N0.getOperand(i).getOpcode() != ISD::Constant && 2088 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2089 isSimple = false; 2090 break; 2091 } 2092 2093 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2094 if (isSimple && !MVT::isVector(DestEltVT)) { 2095 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2096 } 2097 } 2098 2099 return SDOperand(); 2100} 2101 2102/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2103/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2104/// destination element value type. 2105SDOperand DAGCombiner:: 2106ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2107 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2108 2109 // If this is already the right type, we're done. 2110 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2111 2112 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2113 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2114 2115 // If this is a conversion of N elements of one type to N elements of another 2116 // type, convert each element. This handles FP<->INT cases. 2117 if (SrcBitSize == DstBitSize) { 2118 std::vector<SDOperand> Ops; 2119 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2120 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2121 AddToWorkList(Ops.back().Val); 2122 } 2123 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2124 Ops.push_back(DAG.getValueType(DstEltVT)); 2125 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2126 } 2127 2128 // Otherwise, we're growing or shrinking the elements. To avoid having to 2129 // handle annoying details of growing/shrinking FP values, we convert them to 2130 // int first. 2131 if (MVT::isFloatingPoint(SrcEltVT)) { 2132 // Convert the input float vector to a int vector where the elements are the 2133 // same sizes. 2134 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2135 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2136 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2137 SrcEltVT = IntVT; 2138 } 2139 2140 // Now we know the input is an integer vector. If the output is a FP type, 2141 // convert to integer first, then to FP of the right size. 2142 if (MVT::isFloatingPoint(DstEltVT)) { 2143 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2144 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2145 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2146 2147 // Next, convert to FP elements of the same size. 2148 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2149 } 2150 2151 // Okay, we know the src/dst types are both integers of differing types. 2152 // Handling growing first. 2153 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2154 if (SrcBitSize < DstBitSize) { 2155 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2156 2157 std::vector<SDOperand> Ops; 2158 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2159 i += NumInputsPerOutput) { 2160 bool isLE = TLI.isLittleEndian(); 2161 uint64_t NewBits = 0; 2162 bool EltIsUndef = true; 2163 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2164 // Shift the previously computed bits over. 2165 NewBits <<= SrcBitSize; 2166 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2167 if (Op.getOpcode() == ISD::UNDEF) continue; 2168 EltIsUndef = false; 2169 2170 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2171 } 2172 2173 if (EltIsUndef) 2174 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2175 else 2176 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2177 } 2178 2179 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2180 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2181 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2182 } 2183 2184 // Finally, this must be the case where we are shrinking elements: each input 2185 // turns into multiple outputs. 2186 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2187 std::vector<SDOperand> Ops; 2188 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2189 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2190 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2191 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2192 continue; 2193 } 2194 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2195 2196 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2197 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2198 OpVal >>= DstBitSize; 2199 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2200 } 2201 2202 // For big endian targets, swap the order of the pieces of each element. 2203 if (!TLI.isLittleEndian()) 2204 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2205 } 2206 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2207 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2208 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2209} 2210 2211 2212 2213SDOperand DAGCombiner::visitFADD(SDNode *N) { 2214 SDOperand N0 = N->getOperand(0); 2215 SDOperand N1 = N->getOperand(1); 2216 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2217 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2218 MVT::ValueType VT = N->getValueType(0); 2219 2220 // fold (fadd c1, c2) -> c1+c2 2221 if (N0CFP && N1CFP) 2222 return DAG.getNode(ISD::FADD, VT, N0, N1); 2223 // canonicalize constant to RHS 2224 if (N0CFP && !N1CFP) 2225 return DAG.getNode(ISD::FADD, VT, N1, N0); 2226 // fold (A + (-B)) -> A-B 2227 if (N1.getOpcode() == ISD::FNEG) 2228 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2229 // fold ((-A) + B) -> B-A 2230 if (N0.getOpcode() == ISD::FNEG) 2231 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2232 return SDOperand(); 2233} 2234 2235SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2236 SDOperand N0 = N->getOperand(0); 2237 SDOperand N1 = N->getOperand(1); 2238 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2239 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2240 MVT::ValueType VT = N->getValueType(0); 2241 2242 // fold (fsub c1, c2) -> c1-c2 2243 if (N0CFP && N1CFP) 2244 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2245 // fold (A-(-B)) -> A+B 2246 if (N1.getOpcode() == ISD::FNEG) 2247 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2248 return SDOperand(); 2249} 2250 2251SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2252 SDOperand N0 = N->getOperand(0); 2253 SDOperand N1 = N->getOperand(1); 2254 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2255 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2256 MVT::ValueType VT = N->getValueType(0); 2257 2258 // fold (fmul c1, c2) -> c1*c2 2259 if (N0CFP && N1CFP) 2260 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2261 // canonicalize constant to RHS 2262 if (N0CFP && !N1CFP) 2263 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2264 // fold (fmul X, 2.0) -> (fadd X, X) 2265 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2266 return DAG.getNode(ISD::FADD, VT, N0, N0); 2267 return SDOperand(); 2268} 2269 2270SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2271 SDOperand N0 = N->getOperand(0); 2272 SDOperand N1 = N->getOperand(1); 2273 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2274 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2275 MVT::ValueType VT = N->getValueType(0); 2276 2277 // fold (fdiv c1, c2) -> c1/c2 2278 if (N0CFP && N1CFP) 2279 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2280 return SDOperand(); 2281} 2282 2283SDOperand DAGCombiner::visitFREM(SDNode *N) { 2284 SDOperand N0 = N->getOperand(0); 2285 SDOperand N1 = N->getOperand(1); 2286 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2287 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2288 MVT::ValueType VT = N->getValueType(0); 2289 2290 // fold (frem c1, c2) -> fmod(c1,c2) 2291 if (N0CFP && N1CFP) 2292 return DAG.getNode(ISD::FREM, VT, N0, N1); 2293 return SDOperand(); 2294} 2295 2296SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2297 SDOperand N0 = N->getOperand(0); 2298 SDOperand N1 = N->getOperand(1); 2299 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2300 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2301 MVT::ValueType VT = N->getValueType(0); 2302 2303 if (N0CFP && N1CFP) // Constant fold 2304 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2305 2306 if (N1CFP) { 2307 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2308 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2309 union { 2310 double d; 2311 int64_t i; 2312 } u; 2313 u.d = N1CFP->getValue(); 2314 if (u.i >= 0) 2315 return DAG.getNode(ISD::FABS, VT, N0); 2316 else 2317 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2318 } 2319 2320 // copysign(fabs(x), y) -> copysign(x, y) 2321 // copysign(fneg(x), y) -> copysign(x, y) 2322 // copysign(copysign(x,z), y) -> copysign(x, y) 2323 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2324 N0.getOpcode() == ISD::FCOPYSIGN) 2325 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2326 2327 // copysign(x, abs(y)) -> abs(x) 2328 if (N1.getOpcode() == ISD::FABS) 2329 return DAG.getNode(ISD::FABS, VT, N0); 2330 2331 // copysign(x, copysign(y,z)) -> copysign(x, z) 2332 if (N1.getOpcode() == ISD::FCOPYSIGN) 2333 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2334 2335 // copysign(x, fp_extend(y)) -> copysign(x, y) 2336 // copysign(x, fp_round(y)) -> copysign(x, y) 2337 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2338 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2339 2340 return SDOperand(); 2341} 2342 2343 2344 2345SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2346 SDOperand N0 = N->getOperand(0); 2347 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2348 MVT::ValueType VT = N->getValueType(0); 2349 2350 // fold (sint_to_fp c1) -> c1fp 2351 if (N0C) 2352 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2353 return SDOperand(); 2354} 2355 2356SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2357 SDOperand N0 = N->getOperand(0); 2358 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2359 MVT::ValueType VT = N->getValueType(0); 2360 2361 // fold (uint_to_fp c1) -> c1fp 2362 if (N0C) 2363 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2364 return SDOperand(); 2365} 2366 2367SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2368 SDOperand N0 = N->getOperand(0); 2369 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2370 MVT::ValueType VT = N->getValueType(0); 2371 2372 // fold (fp_to_sint c1fp) -> c1 2373 if (N0CFP) 2374 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2375 return SDOperand(); 2376} 2377 2378SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2379 SDOperand N0 = N->getOperand(0); 2380 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2381 MVT::ValueType VT = N->getValueType(0); 2382 2383 // fold (fp_to_uint c1fp) -> c1 2384 if (N0CFP) 2385 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2386 return SDOperand(); 2387} 2388 2389SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2390 SDOperand N0 = N->getOperand(0); 2391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2392 MVT::ValueType VT = N->getValueType(0); 2393 2394 // fold (fp_round c1fp) -> c1fp 2395 if (N0CFP) 2396 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2397 2398 // fold (fp_round (fp_extend x)) -> x 2399 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2400 return N0.getOperand(0); 2401 2402 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2403 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2404 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2405 AddToWorkList(Tmp.Val); 2406 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2407 } 2408 2409 return SDOperand(); 2410} 2411 2412SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2413 SDOperand N0 = N->getOperand(0); 2414 MVT::ValueType VT = N->getValueType(0); 2415 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2416 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2417 2418 // fold (fp_round_inreg c1fp) -> c1fp 2419 if (N0CFP) { 2420 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2421 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2422 } 2423 return SDOperand(); 2424} 2425 2426SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2427 SDOperand N0 = N->getOperand(0); 2428 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2429 MVT::ValueType VT = N->getValueType(0); 2430 2431 // fold (fp_extend c1fp) -> c1fp 2432 if (N0CFP) 2433 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2434 2435 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2436 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 2437 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) { 2438 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0), 2439 N0.getOperand(1), N0.getOperand(2), 2440 N0.getValueType()); 2441 CombineTo(N, ExtLoad); 2442 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2443 ExtLoad.getValue(1)); 2444 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2445 } 2446 2447 2448 return SDOperand(); 2449} 2450 2451SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2452 SDOperand N0 = N->getOperand(0); 2453 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2454 MVT::ValueType VT = N->getValueType(0); 2455 2456 // fold (fneg c1) -> -c1 2457 if (N0CFP) 2458 return DAG.getNode(ISD::FNEG, VT, N0); 2459 // fold (fneg (sub x, y)) -> (sub y, x) 2460 if (N0.getOpcode() == ISD::SUB) 2461 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2462 // fold (fneg (fneg x)) -> x 2463 if (N0.getOpcode() == ISD::FNEG) 2464 return N0.getOperand(0); 2465 return SDOperand(); 2466} 2467 2468SDOperand DAGCombiner::visitFABS(SDNode *N) { 2469 SDOperand N0 = N->getOperand(0); 2470 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2471 MVT::ValueType VT = N->getValueType(0); 2472 2473 // fold (fabs c1) -> fabs(c1) 2474 if (N0CFP) 2475 return DAG.getNode(ISD::FABS, VT, N0); 2476 // fold (fabs (fabs x)) -> (fabs x) 2477 if (N0.getOpcode() == ISD::FABS) 2478 return N->getOperand(0); 2479 // fold (fabs (fneg x)) -> (fabs x) 2480 // fold (fabs (fcopysign x, y)) -> (fabs x) 2481 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2482 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2483 2484 return SDOperand(); 2485} 2486 2487SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2488 SDOperand Chain = N->getOperand(0); 2489 SDOperand N1 = N->getOperand(1); 2490 SDOperand N2 = N->getOperand(2); 2491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2492 2493 // never taken branch, fold to chain 2494 if (N1C && N1C->isNullValue()) 2495 return Chain; 2496 // unconditional branch 2497 if (N1C && N1C->getValue() == 1) 2498 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2499 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2500 // on the target. 2501 if (N1.getOpcode() == ISD::SETCC && 2502 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2503 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2504 N1.getOperand(0), N1.getOperand(1), N2); 2505 } 2506 return SDOperand(); 2507} 2508 2509// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2510// 2511SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2512 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2513 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2514 2515 // Use SimplifySetCC to simplify SETCC's. 2516 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2517 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2518 2519 // fold br_cc true, dest -> br dest (unconditional branch) 2520 if (SCCC && SCCC->getValue()) 2521 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2522 N->getOperand(4)); 2523 // fold br_cc false, dest -> unconditional fall through 2524 if (SCCC && SCCC->isNullValue()) 2525 return N->getOperand(0); 2526 // fold to a simpler setcc 2527 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2528 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2529 Simp.getOperand(2), Simp.getOperand(0), 2530 Simp.getOperand(1), N->getOperand(4)); 2531 return SDOperand(); 2532} 2533 2534SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2535 SDOperand Chain = N->getOperand(0); 2536 SDOperand Ptr = N->getOperand(1); 2537 SDOperand SrcValue = N->getOperand(2); 2538 2539 // If there are no uses of the loaded value, change uses of the chain value 2540 // into uses of the chain input (i.e. delete the dead load). 2541 if (N->hasNUsesOfValue(0, 0)) 2542 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2543 2544 // If this load is directly stored, replace the load value with the stored 2545 // value. 2546 // TODO: Handle store large -> read small portion. 2547 // TODO: Handle TRUNCSTORE/EXTLOAD 2548 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2549 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2550 return CombineTo(N, Chain.getOperand(1), Chain); 2551 2552 return SDOperand(); 2553} 2554 2555/// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD. 2556SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) { 2557 SDOperand Chain = N->getOperand(0); 2558 SDOperand Ptr = N->getOperand(1); 2559 SDOperand SrcValue = N->getOperand(2); 2560 SDOperand EVT = N->getOperand(3); 2561 2562 // If there are no uses of the loaded value, change uses of the chain value 2563 // into uses of the chain input (i.e. delete the dead load). 2564 if (N->hasNUsesOfValue(0, 0)) 2565 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 2566 2567 return SDOperand(); 2568} 2569 2570SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2571 SDOperand Chain = N->getOperand(0); 2572 SDOperand Value = N->getOperand(1); 2573 SDOperand Ptr = N->getOperand(2); 2574 SDOperand SrcValue = N->getOperand(3); 2575 2576 // If this is a store that kills a previous store, remove the previous store. 2577 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2578 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2579 // Make sure that these stores are the same value type: 2580 // FIXME: we really care that the second store is >= size of the first. 2581 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2582 // Create a new store of Value that replaces both stores. 2583 SDNode *PrevStore = Chain.Val; 2584 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2585 return Chain; 2586 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2587 PrevStore->getOperand(0), Value, Ptr, 2588 SrcValue); 2589 CombineTo(N, NewStore); // Nuke this store. 2590 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2591 return SDOperand(N, 0); 2592 } 2593 2594 // If this is a store of a bit convert, store the input value. 2595 // FIXME: This needs to know that the resultant store does not need a 2596 // higher alignment than the original. 2597 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2598 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2599 Ptr, SrcValue); 2600 2601 return SDOperand(); 2602} 2603 2604SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 2605 SDOperand InVec = N->getOperand(0); 2606 SDOperand InVal = N->getOperand(1); 2607 SDOperand EltNo = N->getOperand(2); 2608 2609 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 2610 // vector with the inserted element. 2611 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2612 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2613 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2614 if (Elt < Ops.size()) 2615 Ops[Elt] = InVal; 2616 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops); 2617 } 2618 2619 return SDOperand(); 2620} 2621 2622SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 2623 SDOperand InVec = N->getOperand(0); 2624 SDOperand InVal = N->getOperand(1); 2625 SDOperand EltNo = N->getOperand(2); 2626 SDOperand NumElts = N->getOperand(3); 2627 SDOperand EltType = N->getOperand(4); 2628 2629 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 2630 // vector with the inserted element. 2631 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 2632 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 2633 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 2634 if (Elt < Ops.size()-2) 2635 Ops[Elt] = InVal; 2636 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops); 2637 } 2638 2639 return SDOperand(); 2640} 2641 2642SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 2643 unsigned NumInScalars = N->getNumOperands()-2; 2644 SDOperand NumElts = N->getOperand(NumInScalars); 2645 SDOperand EltType = N->getOperand(NumInScalars+1); 2646 2647 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 2648 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 2649 // two distinct vectors, turn this into a shuffle node. 2650 SDOperand VecIn1, VecIn2; 2651 for (unsigned i = 0; i != NumInScalars; ++i) { 2652 // Ignore undef inputs. 2653 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 2654 2655 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 2656 // constant index, bail out. 2657 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 2658 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 2659 VecIn1 = VecIn2 = SDOperand(0, 0); 2660 break; 2661 } 2662 2663 // If the input vector type disagrees with the result of the vbuild_vector, 2664 // we can't make a shuffle. 2665 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 2666 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 2667 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 2668 VecIn1 = VecIn2 = SDOperand(0, 0); 2669 break; 2670 } 2671 2672 // Otherwise, remember this. We allow up to two distinct input vectors. 2673 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 2674 continue; 2675 2676 if (VecIn1.Val == 0) { 2677 VecIn1 = ExtractedFromVec; 2678 } else if (VecIn2.Val == 0) { 2679 VecIn2 = ExtractedFromVec; 2680 } else { 2681 // Too many inputs. 2682 VecIn1 = VecIn2 = SDOperand(0, 0); 2683 break; 2684 } 2685 } 2686 2687 // If everything is good, we can make a shuffle operation. 2688 if (VecIn1.Val) { 2689 std::vector<SDOperand> BuildVecIndices; 2690 for (unsigned i = 0; i != NumInScalars; ++i) { 2691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 2692 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32)); 2693 continue; 2694 } 2695 2696 SDOperand Extract = N->getOperand(i); 2697 2698 // If extracting from the first vector, just use the index directly. 2699 if (Extract.getOperand(0) == VecIn1) { 2700 BuildVecIndices.push_back(Extract.getOperand(1)); 2701 continue; 2702 } 2703 2704 // Otherwise, use InIdx + VecSize 2705 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 2706 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32)); 2707 } 2708 2709 // Add count and size info. 2710 BuildVecIndices.push_back(NumElts); 2711 BuildVecIndices.push_back(DAG.getValueType(MVT::i32)); 2712 2713 // Return the new VVECTOR_SHUFFLE node. 2714 std::vector<SDOperand> Ops; 2715 Ops.push_back(VecIn1); 2716 if (VecIn2.Val) { 2717 Ops.push_back(VecIn2); 2718 } else { 2719 // Use an undef vbuild_vector as input for the second operand. 2720 std::vector<SDOperand> UnOps(NumInScalars, 2721 DAG.getNode(ISD::UNDEF, 2722 cast<VTSDNode>(EltType)->getVT())); 2723 UnOps.push_back(NumElts); 2724 UnOps.push_back(EltType); 2725 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps)); 2726 AddToWorkList(Ops.back().Val); 2727 } 2728 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices)); 2729 Ops.push_back(NumElts); 2730 Ops.push_back(EltType); 2731 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2732 } 2733 2734 return SDOperand(); 2735} 2736 2737SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 2738 SDOperand ShufMask = N->getOperand(2); 2739 unsigned NumElts = ShufMask.getNumOperands(); 2740 2741 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2742 bool isIdentity = true; 2743 for (unsigned i = 0; i != NumElts; ++i) { 2744 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2745 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2746 isIdentity = false; 2747 break; 2748 } 2749 } 2750 if (isIdentity) return N->getOperand(0); 2751 2752 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2753 isIdentity = true; 2754 for (unsigned i = 0; i != NumElts; ++i) { 2755 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2756 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2757 isIdentity = false; 2758 break; 2759 } 2760 } 2761 if (isIdentity) return N->getOperand(1); 2762 2763 // If the LHS and the RHS are the same node, turn the RHS into an undef. 2764 if (N->getOperand(0) == N->getOperand(1)) { 2765 if (N->getOperand(0).getOpcode() == ISD::UNDEF) 2766 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 2767 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2768 // first operand. 2769 std::vector<SDOperand> MappedOps; 2770 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 2771 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2772 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2773 MappedOps.push_back(ShufMask.getOperand(i)); 2774 } else { 2775 unsigned NewIdx = 2776 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2777 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2778 } 2779 } 2780 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 2781 MappedOps); 2782 AddToWorkList(ShufMask.Val); 2783 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 2784 N->getOperand(0), 2785 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 2786 ShufMask); 2787 } 2788 2789 return SDOperand(); 2790} 2791 2792SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 2793 SDOperand ShufMask = N->getOperand(2); 2794 unsigned NumElts = ShufMask.getNumOperands()-2; 2795 2796 // If the shuffle mask is an identity operation on the LHS, return the LHS. 2797 bool isIdentity = true; 2798 for (unsigned i = 0; i != NumElts; ++i) { 2799 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2800 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 2801 isIdentity = false; 2802 break; 2803 } 2804 } 2805 if (isIdentity) return N->getOperand(0); 2806 2807 // If the shuffle mask is an identity operation on the RHS, return the RHS. 2808 isIdentity = true; 2809 for (unsigned i = 0; i != NumElts; ++i) { 2810 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 2811 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 2812 isIdentity = false; 2813 break; 2814 } 2815 } 2816 if (isIdentity) return N->getOperand(1); 2817 2818 // If the LHS and the RHS are the same node, turn the RHS into an undef. 2819 if (N->getOperand(0) == N->getOperand(1)) { 2820 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 2821 // first operand. 2822 std::vector<SDOperand> MappedOps; 2823 for (unsigned i = 0; i != NumElts; ++i) { 2824 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 2825 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 2826 MappedOps.push_back(ShufMask.getOperand(i)); 2827 } else { 2828 unsigned NewIdx = 2829 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 2830 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 2831 } 2832 } 2833 // Add the type/#elts values. 2834 MappedOps.push_back(ShufMask.getOperand(NumElts)); 2835 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 2836 2837 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 2838 MappedOps); 2839 AddToWorkList(ShufMask.Val); 2840 2841 // Build the undef vector. 2842 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 2843 for (unsigned i = 0; i != NumElts; ++i) 2844 MappedOps[i] = UDVal; 2845 MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2); 2846 MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1); 2847 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps); 2848 2849 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 2850 N->getOperand(0), UDVal, ShufMask, 2851 MappedOps[NumElts], MappedOps[NumElts+1]); 2852 } 2853 2854 return SDOperand(); 2855} 2856 2857/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 2858/// a VAND to a vector_shuffle with the destination vector and a zero vector. 2859/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 2860/// vector_shuffle V, Zero, <0, 4, 2, 4> 2861SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 2862 SDOperand LHS = N->getOperand(0); 2863 SDOperand RHS = N->getOperand(1); 2864 if (N->getOpcode() == ISD::VAND) { 2865 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 2866 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 2867 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 2868 RHS = RHS.getOperand(0); 2869 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2870 std::vector<SDOperand> IdxOps; 2871 unsigned NumOps = RHS.getNumOperands(); 2872 unsigned NumElts = NumOps-2; 2873 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 2874 for (unsigned i = 0; i != NumElts; ++i) { 2875 SDOperand Elt = RHS.getOperand(i); 2876 if (!isa<ConstantSDNode>(Elt)) 2877 return SDOperand(); 2878 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 2879 IdxOps.push_back(DAG.getConstant(i, EVT)); 2880 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 2881 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 2882 else 2883 return SDOperand(); 2884 } 2885 2886 // Let's see if the target supports this vector_shuffle. 2887 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 2888 return SDOperand(); 2889 2890 // Return the new VVECTOR_SHUFFLE node. 2891 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 2892 SDOperand EVTNode = DAG.getValueType(EVT); 2893 std::vector<SDOperand> Ops; 2894 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode); 2895 Ops.push_back(LHS); 2896 AddToWorkList(LHS.Val); 2897 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 2898 ZeroOps.push_back(NumEltsNode); 2899 ZeroOps.push_back(EVTNode); 2900 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps)); 2901 IdxOps.push_back(NumEltsNode); 2902 IdxOps.push_back(EVTNode); 2903 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps)); 2904 Ops.push_back(NumEltsNode); 2905 Ops.push_back(EVTNode); 2906 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops); 2907 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 2908 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 2909 DstVecSize, DstVecEVT); 2910 } 2911 return Result; 2912 } 2913 } 2914 return SDOperand(); 2915} 2916 2917/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 2918/// the scalar operation of the vop if it is operating on an integer vector 2919/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 2920SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 2921 ISD::NodeType FPOp) { 2922 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 2923 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 2924 SDOperand LHS = N->getOperand(0); 2925 SDOperand RHS = N->getOperand(1); 2926 SDOperand Shuffle = XformToShuffleWithZero(N); 2927 if (Shuffle.Val) return Shuffle; 2928 2929 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 2930 // this operation. 2931 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 2932 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 2933 std::vector<SDOperand> Ops; 2934 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 2935 SDOperand LHSOp = LHS.getOperand(i); 2936 SDOperand RHSOp = RHS.getOperand(i); 2937 // If these two elements can't be folded, bail out. 2938 if ((LHSOp.getOpcode() != ISD::UNDEF && 2939 LHSOp.getOpcode() != ISD::Constant && 2940 LHSOp.getOpcode() != ISD::ConstantFP) || 2941 (RHSOp.getOpcode() != ISD::UNDEF && 2942 RHSOp.getOpcode() != ISD::Constant && 2943 RHSOp.getOpcode() != ISD::ConstantFP)) 2944 break; 2945 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 2946 AddToWorkList(Ops.back().Val); 2947 assert((Ops.back().getOpcode() == ISD::UNDEF || 2948 Ops.back().getOpcode() == ISD::Constant || 2949 Ops.back().getOpcode() == ISD::ConstantFP) && 2950 "Scalar binop didn't fold!"); 2951 } 2952 2953 if (Ops.size() == LHS.getNumOperands()-2) { 2954 Ops.push_back(*(LHS.Val->op_end()-2)); 2955 Ops.push_back(*(LHS.Val->op_end()-1)); 2956 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops); 2957 } 2958 } 2959 2960 return SDOperand(); 2961} 2962 2963SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2964 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2965 2966 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2967 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2968 // If we got a simplified select_cc node back from SimplifySelectCC, then 2969 // break it down into a new SETCC node, and a new SELECT node, and then return 2970 // the SELECT node, since we were called with a SELECT node. 2971 if (SCC.Val) { 2972 // Check to see if we got a select_cc back (to turn into setcc/select). 2973 // Otherwise, just return whatever node we got back, like fabs. 2974 if (SCC.getOpcode() == ISD::SELECT_CC) { 2975 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2976 SCC.getOperand(0), SCC.getOperand(1), 2977 SCC.getOperand(4)); 2978 AddToWorkList(SETCC.Val); 2979 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2980 SCC.getOperand(3), SETCC); 2981 } 2982 return SCC; 2983 } 2984 return SDOperand(); 2985} 2986 2987/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2988/// are the two values being selected between, see if we can simplify the 2989/// select. 2990/// 2991bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2992 SDOperand RHS) { 2993 2994 // If this is a select from two identical things, try to pull the operation 2995 // through the select. 2996 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2997#if 0 2998 std::cerr << "SELECT: ["; LHS.Val->dump(); 2999 std::cerr << "] ["; RHS.Val->dump(); 3000 std::cerr << "]\n"; 3001#endif 3002 3003 // If this is a load and the token chain is identical, replace the select 3004 // of two loads with a load through a select of the address to load from. 3005 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3006 // constants have been dropped into the constant pool. 3007 if ((LHS.getOpcode() == ISD::LOAD || 3008 LHS.getOpcode() == ISD::EXTLOAD || 3009 LHS.getOpcode() == ISD::ZEXTLOAD || 3010 LHS.getOpcode() == ISD::SEXTLOAD) && 3011 // Token chains must be identical. 3012 LHS.getOperand(0) == RHS.getOperand(0) && 3013 // If this is an EXTLOAD, the VT's must match. 3014 (LHS.getOpcode() == ISD::LOAD || 3015 LHS.getOperand(3) == RHS.getOperand(3))) { 3016 // FIXME: this conflates two src values, discarding one. This is not 3017 // the right thing to do, but nothing uses srcvalues now. When they do, 3018 // turn SrcValue into a list of locations. 3019 SDOperand Addr; 3020 if (TheSelect->getOpcode() == ISD::SELECT) 3021 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 3022 TheSelect->getOperand(0), LHS.getOperand(1), 3023 RHS.getOperand(1)); 3024 else 3025 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 3026 TheSelect->getOperand(0), 3027 TheSelect->getOperand(1), 3028 LHS.getOperand(1), RHS.getOperand(1), 3029 TheSelect->getOperand(4)); 3030 3031 SDOperand Load; 3032 if (LHS.getOpcode() == ISD::LOAD) 3033 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 3034 Addr, LHS.getOperand(2)); 3035 else 3036 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 3037 LHS.getOperand(0), Addr, LHS.getOperand(2), 3038 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 3039 // Users of the select now use the result of the load. 3040 CombineTo(TheSelect, Load); 3041 3042 // Users of the old loads now use the new load's chain. We know the 3043 // old-load value is dead now. 3044 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3045 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3046 return true; 3047 } 3048 } 3049 3050 return false; 3051} 3052 3053SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3054 SDOperand N2, SDOperand N3, 3055 ISD::CondCode CC) { 3056 3057 MVT::ValueType VT = N2.getValueType(); 3058 //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 3059 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3060 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3061 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3062 3063 // Determine if the condition we're dealing with is constant 3064 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3065 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3066 3067 // fold select_cc true, x, y -> x 3068 if (SCCC && SCCC->getValue()) 3069 return N2; 3070 // fold select_cc false, x, y -> y 3071 if (SCCC && SCCC->getValue() == 0) 3072 return N3; 3073 3074 // Check to see if we can simplify the select into an fabs node 3075 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3076 // Allow either -0.0 or 0.0 3077 if (CFP->getValue() == 0.0) { 3078 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3079 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3080 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3081 N2 == N3.getOperand(0)) 3082 return DAG.getNode(ISD::FABS, VT, N0); 3083 3084 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3085 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3086 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3087 N2.getOperand(0) == N3) 3088 return DAG.getNode(ISD::FABS, VT, N3); 3089 } 3090 } 3091 3092 // Check to see if we can perform the "gzip trick", transforming 3093 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3094 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 3095 MVT::isInteger(N0.getValueType()) && 3096 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 3097 MVT::ValueType XType = N0.getValueType(); 3098 MVT::ValueType AType = N2.getValueType(); 3099 if (XType >= AType) { 3100 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3101 // single-bit constant. 3102 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3103 unsigned ShCtV = Log2_64(N2C->getValue()); 3104 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3105 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3106 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3107 AddToWorkList(Shift.Val); 3108 if (XType > AType) { 3109 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3110 AddToWorkList(Shift.Val); 3111 } 3112 return DAG.getNode(ISD::AND, AType, Shift, N2); 3113 } 3114 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3115 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3116 TLI.getShiftAmountTy())); 3117 AddToWorkList(Shift.Val); 3118 if (XType > AType) { 3119 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3120 AddToWorkList(Shift.Val); 3121 } 3122 return DAG.getNode(ISD::AND, AType, Shift, N2); 3123 } 3124 } 3125 3126 // fold select C, 16, 0 -> shl C, 4 3127 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3128 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3129 // Get a SetCC of the condition 3130 // FIXME: Should probably make sure that setcc is legal if we ever have a 3131 // target where it isn't. 3132 SDOperand Temp, SCC; 3133 // cast from setcc result type to select result type 3134 if (AfterLegalize) { 3135 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3136 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3137 } else { 3138 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3139 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3140 } 3141 AddToWorkList(SCC.Val); 3142 AddToWorkList(Temp.Val); 3143 // shl setcc result by log2 n2c 3144 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3145 DAG.getConstant(Log2_64(N2C->getValue()), 3146 TLI.getShiftAmountTy())); 3147 } 3148 3149 // Check to see if this is the equivalent of setcc 3150 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3151 // otherwise, go ahead with the folds. 3152 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3153 MVT::ValueType XType = N0.getValueType(); 3154 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3155 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3156 if (Res.getValueType() != VT) 3157 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3158 return Res; 3159 } 3160 3161 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3162 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3163 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3164 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3165 return DAG.getNode(ISD::SRL, XType, Ctlz, 3166 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3167 TLI.getShiftAmountTy())); 3168 } 3169 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3170 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3171 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3172 N0); 3173 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3174 DAG.getConstant(~0ULL, XType)); 3175 return DAG.getNode(ISD::SRL, XType, 3176 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3177 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3178 TLI.getShiftAmountTy())); 3179 } 3180 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3181 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3182 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3183 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3184 TLI.getShiftAmountTy())); 3185 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3186 } 3187 } 3188 3189 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3190 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3191 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 3192 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 3193 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 3194 MVT::ValueType XType = N0.getValueType(); 3195 if (SubC->isNullValue() && MVT::isInteger(XType)) { 3196 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3197 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3198 TLI.getShiftAmountTy())); 3199 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 3200 AddToWorkList(Shift.Val); 3201 AddToWorkList(Add.Val); 3202 return DAG.getNode(ISD::XOR, XType, Add, Shift); 3203 } 3204 } 3205 } 3206 3207 return SDOperand(); 3208} 3209 3210SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 3211 SDOperand N1, ISD::CondCode Cond, 3212 bool foldBooleans) { 3213 // These setcc operations always fold. 3214 switch (Cond) { 3215 default: break; 3216 case ISD::SETFALSE: 3217 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 3218 case ISD::SETTRUE: 3219 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 3220 } 3221 3222 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 3223 uint64_t C1 = N1C->getValue(); 3224 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 3225 uint64_t C0 = N0C->getValue(); 3226 3227 // Sign extend the operands if required 3228 if (ISD::isSignedIntSetCC(Cond)) { 3229 C0 = N0C->getSignExtended(); 3230 C1 = N1C->getSignExtended(); 3231 } 3232 3233 switch (Cond) { 3234 default: assert(0 && "Unknown integer setcc!"); 3235 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3236 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3237 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 3238 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 3239 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 3240 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 3241 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 3242 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 3243 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 3244 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 3245 } 3246 } else { 3247 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 3248 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 3249 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 3250 3251 // If the comparison constant has bits in the upper part, the 3252 // zero-extended value could never match. 3253 if (C1 & (~0ULL << InSize)) { 3254 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 3255 switch (Cond) { 3256 case ISD::SETUGT: 3257 case ISD::SETUGE: 3258 case ISD::SETEQ: return DAG.getConstant(0, VT); 3259 case ISD::SETULT: 3260 case ISD::SETULE: 3261 case ISD::SETNE: return DAG.getConstant(1, VT); 3262 case ISD::SETGT: 3263 case ISD::SETGE: 3264 // True if the sign bit of C1 is set. 3265 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 3266 case ISD::SETLT: 3267 case ISD::SETLE: 3268 // True if the sign bit of C1 isn't set. 3269 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 3270 default: 3271 break; 3272 } 3273 } 3274 3275 // Otherwise, we can perform the comparison with the low bits. 3276 switch (Cond) { 3277 case ISD::SETEQ: 3278 case ISD::SETNE: 3279 case ISD::SETUGT: 3280 case ISD::SETUGE: 3281 case ISD::SETULT: 3282 case ISD::SETULE: 3283 return DAG.getSetCC(VT, N0.getOperand(0), 3284 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 3285 Cond); 3286 default: 3287 break; // todo, be more careful with signed comparisons 3288 } 3289 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3290 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 3291 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 3292 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 3293 MVT::ValueType ExtDstTy = N0.getValueType(); 3294 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 3295 3296 // If the extended part has any inconsistent bits, it cannot ever 3297 // compare equal. In other words, they have to be all ones or all 3298 // zeros. 3299 uint64_t ExtBits = 3300 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 3301 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 3302 return DAG.getConstant(Cond == ISD::SETNE, VT); 3303 3304 SDOperand ZextOp; 3305 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 3306 if (Op0Ty == ExtSrcTy) { 3307 ZextOp = N0.getOperand(0); 3308 } else { 3309 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 3310 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 3311 DAG.getConstant(Imm, Op0Ty)); 3312 } 3313 AddToWorkList(ZextOp.Val); 3314 // Otherwise, make this a use of a zext. 3315 return DAG.getSetCC(VT, ZextOp, 3316 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 3317 ExtDstTy), 3318 Cond); 3319 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) && 3320 (Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3321 (N0.getOpcode() == ISD::XOR || 3322 (N0.getOpcode() == ISD::AND && 3323 N0.getOperand(0).getOpcode() == ISD::XOR && 3324 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) && 3325 isa<ConstantSDNode>(N0.getOperand(1)) && 3326 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) { 3327 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can 3328 // only do this if the top bits are known zero. 3329 if (TLI.MaskedValueIsZero(N1, 3330 MVT::getIntVTBitMask(N0.getValueType())-1)) { 3331 // Okay, get the un-inverted input value. 3332 SDOperand Val; 3333 if (N0.getOpcode() == ISD::XOR) 3334 Val = N0.getOperand(0); 3335 else { 3336 assert(N0.getOpcode() == ISD::AND && 3337 N0.getOperand(0).getOpcode() == ISD::XOR); 3338 // ((X^1)&1)^1 -> X & 1 3339 Val = DAG.getNode(ISD::AND, N0.getValueType(), 3340 N0.getOperand(0).getOperand(0), N0.getOperand(1)); 3341 } 3342 return DAG.getSetCC(VT, Val, N1, 3343 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); 3344 } 3345 } 3346 3347 uint64_t MinVal, MaxVal; 3348 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 3349 if (ISD::isSignedIntSetCC(Cond)) { 3350 MinVal = 1ULL << (OperandBitSize-1); 3351 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 3352 MaxVal = ~0ULL >> (65-OperandBitSize); 3353 else 3354 MaxVal = 0; 3355 } else { 3356 MinVal = 0; 3357 MaxVal = ~0ULL >> (64-OperandBitSize); 3358 } 3359 3360 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 3361 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 3362 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 3363 --C1; // X >= C0 --> X > (C0-1) 3364 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3365 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 3366 } 3367 3368 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 3369 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 3370 ++C1; // X <= C0 --> X < (C0+1) 3371 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 3372 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 3373 } 3374 3375 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 3376 return DAG.getConstant(0, VT); // X < MIN --> false 3377 3378 // Canonicalize setgt X, Min --> setne X, Min 3379 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 3380 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3381 // Canonicalize setlt X, Max --> setne X, Max 3382 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 3383 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 3384 3385 // If we have setult X, 1, turn it into seteq X, 0 3386 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 3387 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 3388 ISD::SETEQ); 3389 // If we have setugt X, Max-1, turn it into seteq X, Max 3390 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 3391 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 3392 ISD::SETEQ); 3393 3394 // If we have "setcc X, C0", check to see if we can shrink the immediate 3395 // by changing cc. 3396 3397 // SETUGT X, SINTMAX -> SETLT X, 0 3398 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 3399 C1 == (~0ULL >> (65-OperandBitSize))) 3400 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 3401 ISD::SETLT); 3402 3403 // FIXME: Implement the rest of these. 3404 3405 // Fold bit comparisons when we can. 3406 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3407 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 3408 if (ConstantSDNode *AndRHS = 3409 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3410 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 3411 // Perform the xform if the AND RHS is a single bit. 3412 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 3413 return DAG.getNode(ISD::SRL, VT, N0, 3414 DAG.getConstant(Log2_64(AndRHS->getValue()), 3415 TLI.getShiftAmountTy())); 3416 } 3417 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 3418 // (X & 8) == 8 --> (X & 8) >> 3 3419 // Perform the xform if C1 is a single bit. 3420 if ((C1 & (C1-1)) == 0) { 3421 return DAG.getNode(ISD::SRL, VT, N0, 3422 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 3423 } 3424 } 3425 } 3426 } 3427 } else if (isa<ConstantSDNode>(N0.Val)) { 3428 // Ensure that the constant occurs on the RHS. 3429 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3430 } 3431 3432 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 3433 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 3434 double C0 = N0C->getValue(), C1 = N1C->getValue(); 3435 3436 switch (Cond) { 3437 default: break; // FIXME: Implement the rest of these! 3438 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 3439 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 3440 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 3441 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 3442 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 3443 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 3444 } 3445 } else { 3446 // Ensure that the constant occurs on the RHS. 3447 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 3448 } 3449 3450 if (N0 == N1) { 3451 // We can always fold X == Y for integer setcc's. 3452 if (MVT::isInteger(N0.getValueType())) 3453 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3454 unsigned UOF = ISD::getUnorderedFlavor(Cond); 3455 if (UOF == 2) // FP operators that are undefined on NaNs. 3456 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 3457 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 3458 return DAG.getConstant(UOF, VT); 3459 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 3460 // if it is not already. 3461 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 3462 if (NewCond != Cond) 3463 return DAG.getSetCC(VT, N0, N1, NewCond); 3464 } 3465 3466 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 3467 MVT::isInteger(N0.getValueType())) { 3468 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 3469 N0.getOpcode() == ISD::XOR) { 3470 // Simplify (X+Y) == (X+Z) --> Y == Z 3471 if (N0.getOpcode() == N1.getOpcode()) { 3472 if (N0.getOperand(0) == N1.getOperand(0)) 3473 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 3474 if (N0.getOperand(1) == N1.getOperand(1)) 3475 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 3476 if (isCommutativeBinOp(N0.getOpcode())) { 3477 // If X op Y == Y op X, try other combinations. 3478 if (N0.getOperand(0) == N1.getOperand(1)) 3479 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 3480 if (N0.getOperand(1) == N1.getOperand(0)) 3481 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 3482 } 3483 } 3484 3485 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 3486 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3487 // Turn (X+C1) == C2 --> X == C2-C1 3488 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 3489 return DAG.getSetCC(VT, N0.getOperand(0), 3490 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 3491 N0.getValueType()), Cond); 3492 } 3493 3494 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 3495 if (N0.getOpcode() == ISD::XOR) 3496 // If we know that all of the inverted bits are zero, don't bother 3497 // performing the inversion. 3498 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 3499 return DAG.getSetCC(VT, N0.getOperand(0), 3500 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 3501 N0.getValueType()), Cond); 3502 } 3503 3504 // Turn (C1-X) == C2 --> X == C1-C2 3505 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 3506 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 3507 return DAG.getSetCC(VT, N0.getOperand(1), 3508 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 3509 N0.getValueType()), Cond); 3510 } 3511 } 3512 } 3513 3514 // Simplify (X+Z) == X --> Z == 0 3515 if (N0.getOperand(0) == N1) 3516 return DAG.getSetCC(VT, N0.getOperand(1), 3517 DAG.getConstant(0, N0.getValueType()), Cond); 3518 if (N0.getOperand(1) == N1) { 3519 if (isCommutativeBinOp(N0.getOpcode())) 3520 return DAG.getSetCC(VT, N0.getOperand(0), 3521 DAG.getConstant(0, N0.getValueType()), Cond); 3522 else { 3523 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 3524 // (Z-X) == X --> Z == X<<1 3525 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 3526 N1, 3527 DAG.getConstant(1,TLI.getShiftAmountTy())); 3528 AddToWorkList(SH.Val); 3529 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 3530 } 3531 } 3532 } 3533 3534 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 3535 N1.getOpcode() == ISD::XOR) { 3536 // Simplify X == (X+Z) --> Z == 0 3537 if (N1.getOperand(0) == N0) { 3538 return DAG.getSetCC(VT, N1.getOperand(1), 3539 DAG.getConstant(0, N1.getValueType()), Cond); 3540 } else if (N1.getOperand(1) == N0) { 3541 if (isCommutativeBinOp(N1.getOpcode())) { 3542 return DAG.getSetCC(VT, N1.getOperand(0), 3543 DAG.getConstant(0, N1.getValueType()), Cond); 3544 } else { 3545 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3546 // X == (Z-X) --> X<<1 == Z 3547 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 3548 DAG.getConstant(1,TLI.getShiftAmountTy())); 3549 AddToWorkList(SH.Val); 3550 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 3551 } 3552 } 3553 } 3554 } 3555 3556 // Fold away ALL boolean setcc's. 3557 SDOperand Temp; 3558 if (N0.getValueType() == MVT::i1 && foldBooleans) { 3559 switch (Cond) { 3560 default: assert(0 && "Unknown integer setcc!"); 3561 case ISD::SETEQ: // X == Y -> (X^Y)^1 3562 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3563 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 3564 AddToWorkList(Temp.Val); 3565 break; 3566 case ISD::SETNE: // X != Y --> (X^Y) 3567 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 3568 break; 3569 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 3570 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 3571 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3572 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 3573 AddToWorkList(Temp.Val); 3574 break; 3575 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 3576 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 3577 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3578 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 3579 AddToWorkList(Temp.Val); 3580 break; 3581 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 3582 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 3583 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 3584 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 3585 AddToWorkList(Temp.Val); 3586 break; 3587 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 3588 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 3589 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 3590 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 3591 break; 3592 } 3593 if (VT != MVT::i1) { 3594 AddToWorkList(N0.Val); 3595 // FIXME: If running after legalize, we probably can't do this. 3596 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3597 } 3598 return N0; 3599 } 3600 3601 // Could not fold it. 3602 return SDOperand(); 3603} 3604 3605/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 3606/// return a DAG expression to select that will generate the same value by 3607/// multiplying by a magic number. See: 3608/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3609SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 3610 MVT::ValueType VT = N->getValueType(0); 3611 3612 // Check to see if we can do this. 3613 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3614 return SDOperand(); // BuildSDIV only operates on i32 or i64 3615 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 3616 return SDOperand(); // Make sure the target supports MULHS. 3617 3618 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 3619 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 3620 3621 // Multiply the numerator (operand 0) by the magic value 3622 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 3623 DAG.getConstant(magics.m, VT)); 3624 // If d > 0 and m < 0, add the numerator 3625 if (d > 0 && magics.m < 0) { 3626 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 3627 AddToWorkList(Q.Val); 3628 } 3629 // If d < 0 and m > 0, subtract the numerator. 3630 if (d < 0 && magics.m > 0) { 3631 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 3632 AddToWorkList(Q.Val); 3633 } 3634 // Shift right algebraic if shift value is nonzero 3635 if (magics.s > 0) { 3636 Q = DAG.getNode(ISD::SRA, VT, Q, 3637 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3638 AddToWorkList(Q.Val); 3639 } 3640 // Extract the sign bit and add it to the quotient 3641 SDOperand T = 3642 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 3643 TLI.getShiftAmountTy())); 3644 AddToWorkList(T.Val); 3645 return DAG.getNode(ISD::ADD, VT, Q, T); 3646} 3647 3648/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 3649/// return a DAG expression to select that will generate the same value by 3650/// multiplying by a magic number. See: 3651/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 3652SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 3653 MVT::ValueType VT = N->getValueType(0); 3654 3655 // Check to see if we can do this. 3656 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 3657 return SDOperand(); // BuildUDIV only operates on i32 or i64 3658 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 3659 return SDOperand(); // Make sure the target supports MULHU. 3660 3661 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 3662 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 3663 3664 // Multiply the numerator (operand 0) by the magic value 3665 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 3666 DAG.getConstant(magics.m, VT)); 3667 AddToWorkList(Q.Val); 3668 3669 if (magics.a == 0) { 3670 return DAG.getNode(ISD::SRL, VT, Q, 3671 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 3672 } else { 3673 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 3674 AddToWorkList(NPQ.Val); 3675 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 3676 DAG.getConstant(1, TLI.getShiftAmountTy())); 3677 AddToWorkList(NPQ.Val); 3678 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 3679 AddToWorkList(NPQ.Val); 3680 return DAG.getNode(ISD::SRL, VT, NPQ, 3681 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 3682 } 3683} 3684 3685// SelectionDAG::Combine - This is the entry point for the file. 3686// 3687void SelectionDAG::Combine(bool RunningAfterLegalize) { 3688 /// run - This is the main entry point to this class. 3689 /// 3690 DAGCombiner(*this).Run(RunningAfterLegalize); 3691} 3692