DAGCombiner.cpp revision 6e1c6231ba93ed7590c62ef0f94d0d9443b598ed
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.getNode() == 0 - No change was made 129 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 194 SDValue XformToShuffleWithZero(SDNode *N); 195 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 196 197 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 198 199 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 200 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 201 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 202 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 203 SDValue N3, ISD::CondCode CC, 204 bool NotExtCompare = false); 205 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 206 ISD::CondCode Cond, bool foldBooleans = true); 207 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 208 unsigned HiOp); 209 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 210 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 211 SDValue BuildSDIV(SDNode *N); 212 SDValue BuildUDIV(SDNode *N); 213 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 214 SDValue ReduceLoadWidth(SDNode *N); 215 216 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 217 218 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 219 /// looking for aliasing nodes and adding them to the Aliases vector. 220 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 221 SmallVector<SDValue, 8> &Aliases); 222 223 /// isAlias - Return true if there is any possibility that the two addresses 224 /// overlap. 225 bool isAlias(SDValue Ptr1, int64_t Size1, 226 const Value *SrcValue1, int SrcValueOffset1, 227 SDValue Ptr2, int64_t Size2, 228 const Value *SrcValue2, int SrcValueOffset2); 229 230 /// FindAliasInfo - Extracts the relevant alias information from the memory 231 /// node. Returns true if the operand was a load. 232 bool FindAliasInfo(SDNode *N, 233 SDValue &Ptr, int64_t &Size, 234 const Value *&SrcValue, int &SrcValueOffset); 235 236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 237 /// looking for a better chain (aliasing node.) 238 SDValue FindBetterChain(SDNode *N, SDValue Chain); 239 240public: 241 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 242 : DAG(D), 243 TLI(D.getTargetLoweringInfo()), 244 AfterLegalize(false), 245 Fast(fast), 246 AA(A) {} 247 248 /// Run - runs the dag combiner on all nodes in the work list 249 void Run(bool RunningAfterLegalize); 250 }; 251} 252 253 254namespace { 255/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 256/// nodes from the worklist. 257class VISIBILITY_HIDDEN WorkListRemover : 258 public SelectionDAG::DAGUpdateListener { 259 DAGCombiner &DC; 260public: 261 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 262 263 virtual void NodeDeleted(SDNode *N, SDNode *E) { 264 DC.removeFromWorkList(N); 265 } 266 267 virtual void NodeUpdated(SDNode *N) { 268 // Ignore updates. 269 } 270}; 271} 272 273//===----------------------------------------------------------------------===// 274// TargetLowering::DAGCombinerInfo implementation 275//===----------------------------------------------------------------------===// 276 277void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 278 ((DAGCombiner*)DC)->AddToWorkList(N); 279} 280 281SDValue TargetLowering::DAGCombinerInfo:: 282CombineTo(SDNode *N, const std::vector<SDValue> &To) { 283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 284} 285 286SDValue TargetLowering::DAGCombinerInfo:: 287CombineTo(SDNode *N, SDValue Res) { 288 return ((DAGCombiner*)DC)->CombineTo(N, Res); 289} 290 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 295} 296 297 298//===----------------------------------------------------------------------===// 299// Helper Functions 300//===----------------------------------------------------------------------===// 301 302/// isNegatibleForFree - Return 1 if we can compute the negated form of the 303/// specified expression for the same cost as the expression itself, or 2 if we 304/// can compute the negated form more cheaply than the expression itself. 305static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 306 unsigned Depth = 0) { 307 // No compile time optimizations on this type. 308 if (Op.getValueType() == MVT::ppcf128) 309 return 0; 310 311 // fneg is removable even if it has multiple uses. 312 if (Op.getOpcode() == ISD::FNEG) return 2; 313 314 // Don't allow anything with multiple uses. 315 if (!Op.hasOneUse()) return 0; 316 317 // Don't recurse exponentially. 318 if (Depth > 6) return 0; 319 320 switch (Op.getOpcode()) { 321 default: return false; 322 case ISD::ConstantFP: 323 // Don't invert constant FP values after legalize. The negated constant 324 // isn't necessarily legal. 325 return AfterLegalize ? 0 : 1; 326 case ISD::FADD: 327 // FIXME: determine better conditions for this xform. 328 if (!UnsafeFPMath) return 0; 329 330 // -(A+B) -> -A - B 331 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 332 return V; 333 // -(A+B) -> -B - A 334 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 335 case ISD::FSUB: 336 // We can't turn -(A-B) into B-A when we honor signed zeros. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A-B) -> B-A 340 return 1; 341 342 case ISD::FMUL: 343 case ISD::FDIV: 344 if (HonorSignDependentRoundingFPMath()) return 0; 345 346 // -(X*Y) -> (-X * Y) or (X*-Y) 347 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 348 return V; 349 350 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 351 352 case ISD::FP_EXTEND: 353 case ISD::FP_ROUND: 354 case ISD::FSIN: 355 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 356 } 357} 358 359/// GetNegatedExpression - If isNegatibleForFree returns true, this function 360/// returns the newly negated expression. 361static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 362 bool AfterLegalize, unsigned Depth = 0) { 363 // fneg is removable even if it has multiple uses. 364 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 365 366 // Don't allow anything with multiple uses. 367 assert(Op.hasOneUse() && "Unknown reuse!"); 368 369 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 370 switch (Op.getOpcode()) { 371 default: assert(0 && "Unknown code"); 372 case ISD::ConstantFP: { 373 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 374 V.changeSign(); 375 return DAG.getConstantFP(V, Op.getValueType()); 376 } 377 case ISD::FADD: 378 // FIXME: determine better conditions for this xform. 379 assert(UnsafeFPMath); 380 381 // -(A+B) -> -A - B 382 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 383 return DAG.getNode(ISD::FSUB, Op.getValueType(), 384 GetNegatedExpression(Op.getOperand(0), DAG, 385 AfterLegalize, Depth+1), 386 Op.getOperand(1)); 387 // -(A+B) -> -B - A 388 return DAG.getNode(ISD::FSUB, Op.getValueType(), 389 GetNegatedExpression(Op.getOperand(1), DAG, 390 AfterLegalize, Depth+1), 391 Op.getOperand(0)); 392 case ISD::FSUB: 393 // We can't turn -(A-B) into B-A when we honor signed zeros. 394 assert(UnsafeFPMath); 395 396 // -(0-B) -> B 397 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 398 if (N0CFP->getValueAPF().isZero()) 399 return Op.getOperand(1); 400 401 // -(A-B) -> B-A 402 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 403 Op.getOperand(0)); 404 405 case ISD::FMUL: 406 case ISD::FDIV: 407 assert(!HonorSignDependentRoundingFPMath()); 408 409 // -(X*Y) -> -X * Y 410 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 411 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 AfterLegalize, Depth+1), 414 Op.getOperand(1)); 415 416 // -(X*Y) -> X * -Y 417 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 418 Op.getOperand(0), 419 GetNegatedExpression(Op.getOperand(1), DAG, 420 AfterLegalize, Depth+1)); 421 422 case ISD::FP_EXTEND: 423 case ISD::FSIN: 424 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 AfterLegalize, Depth+1)); 427 case ISD::FP_ROUND: 428 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 AfterLegalize, Depth+1), 431 Op.getOperand(1)); 432 } 433} 434 435 436// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 437// that selects between the values 1 and 0, making it equivalent to a setcc. 438// Also, set the incoming LHS, RHS, and CC references to the appropriate 439// nodes based on the type of node we are checking. This simplifies life a 440// bit for the callers. 441static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 442 SDValue &CC) { 443 if (N.getOpcode() == ISD::SETCC) { 444 LHS = N.getOperand(0); 445 RHS = N.getOperand(1); 446 CC = N.getOperand(2); 447 return true; 448 } 449 if (N.getOpcode() == ISD::SELECT_CC && 450 N.getOperand(2).getOpcode() == ISD::Constant && 451 N.getOperand(3).getOpcode() == ISD::Constant && 452 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(4); 457 return true; 458 } 459 return false; 460} 461 462// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 463// one use. If this is true, it allows the users to invert the operation for 464// free when it is profitable to do so. 465static bool isOneUseSetCC(SDValue N) { 466 SDValue N0, N1, N2; 467 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 468 return true; 469 return false; 470} 471 472SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 473 MVT VT = N0.getValueType(); 474 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 475 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 476 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 477 if (isa<ConstantSDNode>(N1)) { 478 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 479 AddToWorkList(OpNode.getNode()); 480 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 481 } else if (N0.hasOneUse()) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 485 } 486 } 487 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 488 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 489 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 490 if (isa<ConstantSDNode>(N0)) { 491 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 492 AddToWorkList(OpNode.getNode()); 493 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 494 } else if (N1.hasOneUse()) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 498 } 499 } 500 return SDValue(); 501} 502 503SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 504 bool AddTo) { 505 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 506 ++NodesCombined; 507 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 508 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 509 DOUT << " and " << NumTo-1 << " other values\n"; 510 WorkListRemover DeadNodes(*this); 511 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 512 513 if (AddTo) { 514 // Push the new nodes and any users onto the worklist 515 for (unsigned i = 0, e = NumTo; i != e; ++i) { 516 AddToWorkList(To[i].getNode()); 517 AddUsersToWorkList(To[i].getNode()); 518 } 519 } 520 521 // Nodes can be reintroduced into the worklist. Make sure we do not 522 // process a node that has been replaced. 523 removeFromWorkList(N); 524 525 // Finally, since the node is now dead, remove it from the graph. 526 DAG.DeleteNode(N); 527 return SDValue(N, 0); 528} 529 530/// SimplifyDemandedBits - Check the specified integer node value to see if 531/// it can be simplified or if things it uses can be simplified by bit 532/// propagation. If so, return true. 533bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 534 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 535 APInt KnownZero, KnownOne; 536 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 537 return false; 538 539 // Revisit the node. 540 AddToWorkList(Op.getNode()); 541 542 // Replace the old value with the new one. 543 ++NodesCombined; 544 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 545 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 546 DOUT << '\n'; 547 548 // Replace all uses. If any nodes become isomorphic to other nodes and 549 // are deleted, make sure to remove them from our worklist. 550 WorkListRemover DeadNodes(*this); 551 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 552 553 // Push the new node and any (possibly new) users onto the worklist. 554 AddToWorkList(TLO.New.getNode()); 555 AddUsersToWorkList(TLO.New.getNode()); 556 557 // Finally, if the node is now dead, remove it from the graph. The node 558 // may not be dead if the replacement process recursively simplified to 559 // something else needing this node. 560 if (TLO.Old.getNode()->use_empty()) { 561 removeFromWorkList(TLO.Old.getNode()); 562 563 // If the operands of this node are only used by the node, they will now 564 // be dead. Make sure to visit them first to delete dead nodes early. 565 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 566 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 567 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 568 569 DAG.DeleteNode(TLO.Old.getNode()); 570 } 571 return true; 572} 573 574//===----------------------------------------------------------------------===// 575// Main DAG Combiner implementation 576//===----------------------------------------------------------------------===// 577 578void DAGCombiner::Run(bool RunningAfterLegalize) { 579 // set the instance variable, so that the various visit routines may use it. 580 AfterLegalize = RunningAfterLegalize; 581 582 // Add all the dag nodes to the worklist. 583 WorkList.reserve(DAG.allnodes_size()); 584 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 585 E = DAG.allnodes_end(); I != E; ++I) 586 WorkList.push_back(I); 587 588 // Create a dummy node (which is not added to allnodes), that adds a reference 589 // to the root node, preventing it from being deleted, and tracking any 590 // changes of the root. 591 HandleSDNode Dummy(DAG.getRoot()); 592 593 // The root of the dag may dangle to deleted nodes until the dag combiner is 594 // done. Set it to null to avoid confusion. 595 DAG.setRoot(SDValue()); 596 597 // while the worklist isn't empty, inspect the node on the end of it and 598 // try and combine it. 599 while (!WorkList.empty()) { 600 SDNode *N = WorkList.back(); 601 WorkList.pop_back(); 602 603 // If N has no uses, it is dead. Make sure to revisit all N's operands once 604 // N is deleted from the DAG, since they too may now be dead or may have a 605 // reduced number of uses, allowing other xforms. 606 if (N->use_empty() && N != &Dummy) { 607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 608 AddToWorkList(N->getOperand(i).getNode()); 609 610 DAG.DeleteNode(N); 611 continue; 612 } 613 614 SDValue RV = combine(N); 615 616 if (RV.getNode() == 0) 617 continue; 618 619 ++NodesCombined; 620 621 // If we get back the same node we passed in, rather than a new node or 622 // zero, we know that the node must have defined multiple values and 623 // CombineTo was used. Since CombineTo takes care of the worklist 624 // mechanics for us, we have no work to do in this case. 625 if (RV.getNode() == N) 626 continue; 627 628 assert(N->getOpcode() != ISD::DELETED_NODE && 629 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 630 "Node was deleted but visit returned new node!"); 631 632 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 633 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 634 DOUT << '\n'; 635 WorkListRemover DeadNodes(*this); 636 if (N->getNumValues() == RV.getNode()->getNumValues()) 637 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 638 else { 639 assert(N->getValueType(0) == RV.getValueType() && 640 N->getNumValues() == 1 && "Type mismatch"); 641 SDValue OpV = RV; 642 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 643 } 644 645 // Push the new node and any users onto the worklist 646 AddToWorkList(RV.getNode()); 647 AddUsersToWorkList(RV.getNode()); 648 649 // Add any uses of the old node to the worklist in case this node is the 650 // last one that uses them. They may become dead after this node is 651 // deleted. 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).getNode()); 654 655 // Nodes can be reintroduced into the worklist. Make sure we do not 656 // process a node that has been replaced. 657 removeFromWorkList(N); 658 659 // Finally, since the node is now dead, remove it from the graph. 660 DAG.DeleteNode(N); 661 } 662 663 // If the root changed (e.g. it was a dead load, update the root). 664 DAG.setRoot(Dummy.getValue()); 665} 666 667SDValue DAGCombiner::visit(SDNode *N) { 668 switch(N->getOpcode()) { 669 default: break; 670 case ISD::TokenFactor: return visitTokenFactor(N); 671 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 672 case ISD::ADD: return visitADD(N); 673 case ISD::SUB: return visitSUB(N); 674 case ISD::ADDC: return visitADDC(N); 675 case ISD::ADDE: return visitADDE(N); 676 case ISD::MUL: return visitMUL(N); 677 case ISD::SDIV: return visitSDIV(N); 678 case ISD::UDIV: return visitUDIV(N); 679 case ISD::SREM: return visitSREM(N); 680 case ISD::UREM: return visitUREM(N); 681 case ISD::MULHU: return visitMULHU(N); 682 case ISD::MULHS: return visitMULHS(N); 683 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 684 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 685 case ISD::SDIVREM: return visitSDIVREM(N); 686 case ISD::UDIVREM: return visitUDIVREM(N); 687 case ISD::AND: return visitAND(N); 688 case ISD::OR: return visitOR(N); 689 case ISD::XOR: return visitXOR(N); 690 case ISD::SHL: return visitSHL(N); 691 case ISD::SRA: return visitSRA(N); 692 case ISD::SRL: return visitSRL(N); 693 case ISD::CTLZ: return visitCTLZ(N); 694 case ISD::CTTZ: return visitCTTZ(N); 695 case ISD::CTPOP: return visitCTPOP(N); 696 case ISD::SELECT: return visitSELECT(N); 697 case ISD::SELECT_CC: return visitSELECT_CC(N); 698 case ISD::SETCC: return visitSETCC(N); 699 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 700 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 701 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 702 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 703 case ISD::TRUNCATE: return visitTRUNCATE(N); 704 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 705 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 706 case ISD::FADD: return visitFADD(N); 707 case ISD::FSUB: return visitFSUB(N); 708 case ISD::FMUL: return visitFMUL(N); 709 case ISD::FDIV: return visitFDIV(N); 710 case ISD::FREM: return visitFREM(N); 711 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 712 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 713 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 714 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 715 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 716 case ISD::FP_ROUND: return visitFP_ROUND(N); 717 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 718 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 719 case ISD::FNEG: return visitFNEG(N); 720 case ISD::FABS: return visitFABS(N); 721 case ISD::BRCOND: return visitBRCOND(N); 722 case ISD::BR_CC: return visitBR_CC(N); 723 case ISD::LOAD: return visitLOAD(N); 724 case ISD::STORE: return visitSTORE(N); 725 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 726 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 727 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 728 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 729 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 730 } 731 return SDValue(); 732} 733 734SDValue DAGCombiner::combine(SDNode *N) { 735 736 SDValue RV = visit(N); 737 738 // If nothing happened, try a target-specific DAG combine. 739 if (RV.getNode() == 0) { 740 assert(N->getOpcode() != ISD::DELETED_NODE && 741 "Node was deleted but visit returned NULL!"); 742 743 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 744 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 745 746 // Expose the DAG combiner to the target combiner impls. 747 TargetLowering::DAGCombinerInfo 748 DagCombineInfo(DAG, !AfterLegalize, false, this); 749 750 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 751 } 752 } 753 754 // If N is a commutative binary node, try commuting it to enable more 755 // sdisel CSE. 756 if (RV.getNode() == 0 && 757 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 758 N->getNumValues() == 1) { 759 SDValue N0 = N->getOperand(0); 760 SDValue N1 = N->getOperand(1); 761 // Constant operands are canonicalized to RHS. 762 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 763 SDValue Ops[] = { N1, N0 }; 764 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 765 Ops, 2); 766 if (CSENode) 767 return SDValue(CSENode, 0); 768 } 769 } 770 771 return RV; 772} 773 774/// getInputChainForNode - Given a node, return its input chain if it has one, 775/// otherwise return a null sd operand. 776static SDValue getInputChainForNode(SDNode *N) { 777 if (unsigned NumOps = N->getNumOperands()) { 778 if (N->getOperand(0).getValueType() == MVT::Other) 779 return N->getOperand(0); 780 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 781 return N->getOperand(NumOps-1); 782 for (unsigned i = 1; i < NumOps-1; ++i) 783 if (N->getOperand(i).getValueType() == MVT::Other) 784 return N->getOperand(i); 785 } 786 return SDValue(0, 0); 787} 788 789SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 790 // If N has two operands, where one has an input chain equal to the other, 791 // the 'other' chain is redundant. 792 if (N->getNumOperands() == 2) { 793 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 794 return N->getOperand(0); 795 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 796 return N->getOperand(1); 797 } 798 799 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 800 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 801 SmallPtrSet<SDNode*, 16> SeenOps; 802 bool Changed = false; // If we should replace this token factor. 803 804 // Start out with this token factor. 805 TFs.push_back(N); 806 807 // Iterate through token factors. The TFs grows when new token factors are 808 // encountered. 809 for (unsigned i = 0; i < TFs.size(); ++i) { 810 SDNode *TF = TFs[i]; 811 812 // Check each of the operands. 813 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 814 SDValue Op = TF->getOperand(i); 815 816 switch (Op.getOpcode()) { 817 case ISD::EntryToken: 818 // Entry tokens don't need to be added to the list. They are 819 // rededundant. 820 Changed = true; 821 break; 822 823 case ISD::TokenFactor: 824 if ((CombinerAA || Op.hasOneUse()) && 825 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 826 // Queue up for processing. 827 TFs.push_back(Op.getNode()); 828 // Clean up in case the token factor is removed. 829 AddToWorkList(Op.getNode()); 830 Changed = true; 831 break; 832 } 833 // Fall thru 834 835 default: 836 // Only add if it isn't already in the list. 837 if (SeenOps.insert(Op.getNode())) 838 Ops.push_back(Op); 839 else 840 Changed = true; 841 break; 842 } 843 } 844 } 845 846 SDValue Result; 847 848 // If we've change things around then replace token factor. 849 if (Changed) { 850 if (Ops.empty()) { 851 // The entry token is the only possible outcome. 852 Result = DAG.getEntryNode(); 853 } else { 854 // New and improved token factor. 855 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 856 } 857 858 // Don't add users to work list. 859 return CombineTo(N, Result, false); 860 } 861 862 return Result; 863} 864 865/// MERGE_VALUES can always be eliminated. 866SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 867 WorkListRemover DeadNodes(*this); 868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 869 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 870 &DeadNodes); 871 removeFromWorkList(N); 872 DAG.DeleteNode(N); 873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 874} 875 876 877static 878SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 879 MVT VT = N0.getValueType(); 880 SDValue N00 = N0.getOperand(0); 881 SDValue N01 = N0.getOperand(1); 882 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 883 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 884 isa<ConstantSDNode>(N00.getOperand(1))) { 885 N0 = DAG.getNode(ISD::ADD, VT, 886 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 887 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 888 return DAG.getNode(ISD::ADD, VT, N0, N1); 889 } 890 return SDValue(); 891} 892 893static 894SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 895 SelectionDAG &DAG) { 896 MVT VT = N->getValueType(0); 897 unsigned Opc = N->getOpcode(); 898 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 899 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 900 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 901 ISD::CondCode CC = ISD::SETCC_INVALID; 902 if (isSlctCC) 903 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 904 else { 905 SDValue CCOp = Slct.getOperand(0); 906 if (CCOp.getOpcode() == ISD::SETCC) 907 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 908 } 909 910 bool DoXform = false; 911 bool InvCC = false; 912 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 913 "Bad input!"); 914 if (LHS.getOpcode() == ISD::Constant && 915 cast<ConstantSDNode>(LHS)->isNullValue()) 916 DoXform = true; 917 else if (CC != ISD::SETCC_INVALID && 918 RHS.getOpcode() == ISD::Constant && 919 cast<ConstantSDNode>(RHS)->isNullValue()) { 920 std::swap(LHS, RHS); 921 SDValue Op0 = Slct.getOperand(0); 922 bool isInt = (isSlctCC ? Op0.getValueType() : 923 Op0.getOperand(0).getValueType()).isInteger(); 924 CC = ISD::getSetCCInverse(CC, isInt); 925 DoXform = true; 926 InvCC = true; 927 } 928 929 if (DoXform) { 930 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 931 if (isSlctCC) 932 return DAG.getSelectCC(OtherOp, Result, 933 Slct.getOperand(0), Slct.getOperand(1), CC); 934 SDValue CCOp = Slct.getOperand(0); 935 if (InvCC) 936 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 937 CCOp.getOperand(1), CC); 938 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 939 } 940 return SDValue(); 941} 942 943SDValue DAGCombiner::visitADD(SDNode *N) { 944 SDValue N0 = N->getOperand(0); 945 SDValue N1 = N->getOperand(1); 946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 948 MVT VT = N0.getValueType(); 949 950 // fold vector ops 951 if (VT.isVector()) { 952 SDValue FoldedVOp = SimplifyVBinOp(N); 953 if (FoldedVOp.getNode()) return FoldedVOp; 954 } 955 956 // fold (add x, undef) -> undef 957 if (N0.getOpcode() == ISD::UNDEF) 958 return N0; 959 if (N1.getOpcode() == ISD::UNDEF) 960 return N1; 961 // fold (add c1, c2) -> c1+c2 962 if (N0C && N1C) 963 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 964 // canonicalize constant to RHS 965 if (N0C && !N1C) 966 return DAG.getNode(ISD::ADD, VT, N1, N0); 967 // fold (add x, 0) -> x 968 if (N1C && N1C->isNullValue()) 969 return N0; 970 // fold (add Sym, c) -> Sym+c 971 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 972 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA) && N1C && 973 GA->getOpcode() == ISD::GlobalAddress) 974 return DAG.getGlobalAddress(GA->getGlobal(), VT, 975 GA->getOffset() + 976 (uint64_t)N1C->getSExtValue()); 977 // fold ((c1-A)+c2) -> (c1+c2)-A 978 if (N1C && N0.getOpcode() == ISD::SUB) 979 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 980 return DAG.getNode(ISD::SUB, VT, 981 DAG.getConstant(N1C->getAPIntValue()+ 982 N0C->getAPIntValue(), VT), 983 N0.getOperand(1)); 984 // reassociate add 985 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 986 if (RADD.getNode() != 0) 987 return RADD; 988 // fold ((0-A) + B) -> B-A 989 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 990 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 991 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 992 // fold (A + (0-B)) -> A-B 993 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 994 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 995 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 996 // fold (A+(B-A)) -> B 997 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 998 return N1.getOperand(0); 999 1000 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1001 return SDValue(N, 0); 1002 1003 // fold (a+b) -> (a|b) iff a and b share no bits. 1004 if (VT.isInteger() && !VT.isVector()) { 1005 APInt LHSZero, LHSOne; 1006 APInt RHSZero, RHSOne; 1007 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1008 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1009 if (LHSZero.getBoolValue()) { 1010 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1011 1012 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1013 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1014 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1015 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1016 return DAG.getNode(ISD::OR, VT, N0, N1); 1017 } 1018 } 1019 1020 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1021 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1022 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1023 if (Result.getNode()) return Result; 1024 } 1025 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1026 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1027 if (Result.getNode()) return Result; 1028 } 1029 1030 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1031 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1032 SDValue Result = combineSelectAndUse(N, N0, N1, DAG); 1033 if (Result.getNode()) return Result; 1034 } 1035 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1036 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1037 if (Result.getNode()) return Result; 1038 } 1039 1040 return SDValue(); 1041} 1042 1043SDValue DAGCombiner::visitADDC(SDNode *N) { 1044 SDValue N0 = N->getOperand(0); 1045 SDValue N1 = N->getOperand(1); 1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1048 MVT VT = N0.getValueType(); 1049 1050 // If the flag result is dead, turn this into an ADD. 1051 if (N->hasNUsesOfValue(0, 1)) 1052 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1053 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1054 1055 // canonicalize constant to RHS. 1056 if (N0C && !N1C) 1057 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1058 1059 // fold (addc x, 0) -> x + no carry out 1060 if (N1C && N1C->isNullValue()) 1061 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1062 1063 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1064 APInt LHSZero, LHSOne; 1065 APInt RHSZero, RHSOne; 1066 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1067 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1068 if (LHSZero.getBoolValue()) { 1069 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1070 1071 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1072 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1073 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1074 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1075 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1076 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1077 } 1078 1079 return SDValue(); 1080} 1081 1082SDValue DAGCombiner::visitADDE(SDNode *N) { 1083 SDValue N0 = N->getOperand(0); 1084 SDValue N1 = N->getOperand(1); 1085 SDValue CarryIn = N->getOperand(2); 1086 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1087 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1088 //MVT VT = N0.getValueType(); 1089 1090 // canonicalize constant to RHS 1091 if (N0C && !N1C) 1092 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1093 1094 // fold (adde x, y, false) -> (addc x, y) 1095 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1096 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1097 1098 return SDValue(); 1099} 1100 1101 1102 1103SDValue DAGCombiner::visitSUB(SDNode *N) { 1104 SDValue N0 = N->getOperand(0); 1105 SDValue N1 = N->getOperand(1); 1106 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1107 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1108 MVT VT = N0.getValueType(); 1109 1110 // fold vector ops 1111 if (VT.isVector()) { 1112 SDValue FoldedVOp = SimplifyVBinOp(N); 1113 if (FoldedVOp.getNode()) return FoldedVOp; 1114 } 1115 1116 // fold (sub x, x) -> 0 1117 if (N0 == N1) 1118 return DAG.getConstant(0, N->getValueType(0)); 1119 // fold (sub c1, c2) -> c1-c2 1120 if (N0C && N1C) 1121 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1122 // fold (sub x, c) -> (add x, -c) 1123 if (N1C) 1124 return DAG.getNode(ISD::ADD, VT, N0, 1125 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1126 // fold (A+B)-A -> B 1127 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1128 return N0.getOperand(1); 1129 // fold (A+B)-B -> A 1130 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1131 return N0.getOperand(0); 1132 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1133 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1134 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1135 if (Result.getNode()) return Result; 1136 } 1137 // If either operand of a sub is undef, the result is undef 1138 if (N0.getOpcode() == ISD::UNDEF) 1139 return N0; 1140 if (N1.getOpcode() == ISD::UNDEF) 1141 return N1; 1142 1143 // If the relocation model supports it, consider symbol offsets. 1144 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1145 if (!AfterLegalize && TLI.isOffsetFoldingLegal(GA)) { 1146 // fold (sub Sym, c) -> Sym-c 1147 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1148 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1149 GA->getOffset() - 1150 (uint64_t)N1C->getSExtValue()); 1151 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1152 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1153 if (GA->getGlobal() == GB->getGlobal()) 1154 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1155 VT); 1156 } 1157 1158 return SDValue(); 1159} 1160 1161SDValue DAGCombiner::visitMUL(SDNode *N) { 1162 SDValue N0 = N->getOperand(0); 1163 SDValue N1 = N->getOperand(1); 1164 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1165 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1166 MVT VT = N0.getValueType(); 1167 1168 // fold vector ops 1169 if (VT.isVector()) { 1170 SDValue FoldedVOp = SimplifyVBinOp(N); 1171 if (FoldedVOp.getNode()) return FoldedVOp; 1172 } 1173 1174 // fold (mul x, undef) -> 0 1175 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1176 return DAG.getConstant(0, VT); 1177 // fold (mul c1, c2) -> c1*c2 1178 if (N0C && N1C) 1179 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1180 // canonicalize constant to RHS 1181 if (N0C && !N1C) 1182 return DAG.getNode(ISD::MUL, VT, N1, N0); 1183 // fold (mul x, 0) -> 0 1184 if (N1C && N1C->isNullValue()) 1185 return N1; 1186 // fold (mul x, -1) -> 0-x 1187 if (N1C && N1C->isAllOnesValue()) 1188 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1189 // fold (mul x, (1 << c)) -> x << c 1190 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1191 return DAG.getNode(ISD::SHL, VT, N0, 1192 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1193 TLI.getShiftAmountTy())); 1194 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1195 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1196 // FIXME: If the input is something that is easily negated (e.g. a 1197 // single-use add), we should put the negate there. 1198 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1199 DAG.getNode(ISD::SHL, VT, N0, 1200 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1201 TLI.getShiftAmountTy()))); 1202 } 1203 1204 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1205 if (N1C && N0.getOpcode() == ISD::SHL && 1206 isa<ConstantSDNode>(N0.getOperand(1))) { 1207 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1208 AddToWorkList(C3.getNode()); 1209 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1210 } 1211 1212 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1213 // use. 1214 { 1215 SDValue Sh(0,0), Y(0,0); 1216 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1217 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1218 N0.getNode()->hasOneUse()) { 1219 Sh = N0; Y = N1; 1220 } else if (N1.getOpcode() == ISD::SHL && 1221 isa<ConstantSDNode>(N1.getOperand(1)) && 1222 N1.getNode()->hasOneUse()) { 1223 Sh = N1; Y = N0; 1224 } 1225 if (Sh.getNode()) { 1226 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1227 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1228 } 1229 } 1230 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1231 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1232 isa<ConstantSDNode>(N0.getOperand(1))) { 1233 return DAG.getNode(ISD::ADD, VT, 1234 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1235 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1236 } 1237 1238 // reassociate mul 1239 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1240 if (RMUL.getNode() != 0) 1241 return RMUL; 1242 1243 return SDValue(); 1244} 1245 1246SDValue DAGCombiner::visitSDIV(SDNode *N) { 1247 SDValue N0 = N->getOperand(0); 1248 SDValue N1 = N->getOperand(1); 1249 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1250 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1251 MVT VT = N->getValueType(0); 1252 1253 // fold vector ops 1254 if (VT.isVector()) { 1255 SDValue FoldedVOp = SimplifyVBinOp(N); 1256 if (FoldedVOp.getNode()) return FoldedVOp; 1257 } 1258 1259 // fold (sdiv c1, c2) -> c1/c2 1260 if (N0C && N1C && !N1C->isNullValue()) 1261 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1262 // fold (sdiv X, 1) -> X 1263 if (N1C && N1C->getSExtValue() == 1LL) 1264 return N0; 1265 // fold (sdiv X, -1) -> 0-X 1266 if (N1C && N1C->isAllOnesValue()) 1267 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1268 // If we know the sign bits of both operands are zero, strength reduce to a 1269 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1270 if (!VT.isVector()) { 1271 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1272 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1273 } 1274 // fold (sdiv X, pow2) -> simple ops after legalize 1275 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1276 (isPowerOf2_64(N1C->getSExtValue()) || 1277 isPowerOf2_64(-N1C->getSExtValue()))) { 1278 // If dividing by powers of two is cheap, then don't perform the following 1279 // fold. 1280 if (TLI.isPow2DivCheap()) 1281 return SDValue(); 1282 int64_t pow2 = N1C->getSExtValue(); 1283 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1284 unsigned lg2 = Log2_64(abs2); 1285 // Splat the sign bit into the register 1286 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1287 DAG.getConstant(VT.getSizeInBits()-1, 1288 TLI.getShiftAmountTy())); 1289 AddToWorkList(SGN.getNode()); 1290 // Add (N0 < 0) ? abs2 - 1 : 0; 1291 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1292 DAG.getConstant(VT.getSizeInBits()-lg2, 1293 TLI.getShiftAmountTy())); 1294 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1295 AddToWorkList(SRL.getNode()); 1296 AddToWorkList(ADD.getNode()); // Divide by pow2 1297 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1298 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1299 // If we're dividing by a positive value, we're done. Otherwise, we must 1300 // negate the result. 1301 if (pow2 > 0) 1302 return SRA; 1303 AddToWorkList(SRA.getNode()); 1304 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1305 } 1306 // if integer divide is expensive and we satisfy the requirements, emit an 1307 // alternate sequence. 1308 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1309 !TLI.isIntDivCheap()) { 1310 SDValue Op = BuildSDIV(N); 1311 if (Op.getNode()) return Op; 1312 } 1313 1314 // undef / X -> 0 1315 if (N0.getOpcode() == ISD::UNDEF) 1316 return DAG.getConstant(0, VT); 1317 // X / undef -> undef 1318 if (N1.getOpcode() == ISD::UNDEF) 1319 return N1; 1320 1321 return SDValue(); 1322} 1323 1324SDValue DAGCombiner::visitUDIV(SDNode *N) { 1325 SDValue N0 = N->getOperand(0); 1326 SDValue N1 = N->getOperand(1); 1327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1329 MVT VT = N->getValueType(0); 1330 1331 // fold vector ops 1332 if (VT.isVector()) { 1333 SDValue FoldedVOp = SimplifyVBinOp(N); 1334 if (FoldedVOp.getNode()) return FoldedVOp; 1335 } 1336 1337 // fold (udiv c1, c2) -> c1/c2 1338 if (N0C && N1C && !N1C->isNullValue()) 1339 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1340 // fold (udiv x, (1 << c)) -> x >>u c 1341 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1342 return DAG.getNode(ISD::SRL, VT, N0, 1343 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1344 TLI.getShiftAmountTy())); 1345 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1346 if (N1.getOpcode() == ISD::SHL) { 1347 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1348 if (SHC->getAPIntValue().isPowerOf2()) { 1349 MVT ADDVT = N1.getOperand(1).getValueType(); 1350 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1351 DAG.getConstant(SHC->getAPIntValue() 1352 .logBase2(), 1353 ADDVT)); 1354 AddToWorkList(Add.getNode()); 1355 return DAG.getNode(ISD::SRL, VT, N0, Add); 1356 } 1357 } 1358 } 1359 // fold (udiv x, c) -> alternate 1360 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1361 SDValue Op = BuildUDIV(N); 1362 if (Op.getNode()) return Op; 1363 } 1364 1365 // undef / X -> 0 1366 if (N0.getOpcode() == ISD::UNDEF) 1367 return DAG.getConstant(0, VT); 1368 // X / undef -> undef 1369 if (N1.getOpcode() == ISD::UNDEF) 1370 return N1; 1371 1372 return SDValue(); 1373} 1374 1375SDValue DAGCombiner::visitSREM(SDNode *N) { 1376 SDValue N0 = N->getOperand(0); 1377 SDValue N1 = N->getOperand(1); 1378 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1379 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1380 MVT VT = N->getValueType(0); 1381 1382 // fold (srem c1, c2) -> c1%c2 1383 if (N0C && N1C && !N1C->isNullValue()) 1384 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1385 // If we know the sign bits of both operands are zero, strength reduce to a 1386 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1387 if (!VT.isVector()) { 1388 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1389 return DAG.getNode(ISD::UREM, VT, N0, N1); 1390 } 1391 1392 // If X/C can be simplified by the division-by-constant logic, lower 1393 // X%C to the equivalent of X-X/C*C. 1394 if (N1C && !N1C->isNullValue()) { 1395 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1396 AddToWorkList(Div.getNode()); 1397 SDValue OptimizedDiv = combine(Div.getNode()); 1398 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1399 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1400 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1401 AddToWorkList(Mul.getNode()); 1402 return Sub; 1403 } 1404 } 1405 1406 // undef % X -> 0 1407 if (N0.getOpcode() == ISD::UNDEF) 1408 return DAG.getConstant(0, VT); 1409 // X % undef -> undef 1410 if (N1.getOpcode() == ISD::UNDEF) 1411 return N1; 1412 1413 return SDValue(); 1414} 1415 1416SDValue DAGCombiner::visitUREM(SDNode *N) { 1417 SDValue N0 = N->getOperand(0); 1418 SDValue N1 = N->getOperand(1); 1419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1421 MVT VT = N->getValueType(0); 1422 1423 // fold (urem c1, c2) -> c1%c2 1424 if (N0C && N1C && !N1C->isNullValue()) 1425 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1426 // fold (urem x, pow2) -> (and x, pow2-1) 1427 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1428 return DAG.getNode(ISD::AND, VT, N0, 1429 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1430 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1431 if (N1.getOpcode() == ISD::SHL) { 1432 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1433 if (SHC->getAPIntValue().isPowerOf2()) { 1434 SDValue Add = 1435 DAG.getNode(ISD::ADD, VT, N1, 1436 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1437 VT)); 1438 AddToWorkList(Add.getNode()); 1439 return DAG.getNode(ISD::AND, VT, N0, Add); 1440 } 1441 } 1442 } 1443 1444 // If X/C can be simplified by the division-by-constant logic, lower 1445 // X%C to the equivalent of X-X/C*C. 1446 if (N1C && !N1C->isNullValue()) { 1447 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1448 AddToWorkList(Div.getNode()); 1449 SDValue OptimizedDiv = combine(Div.getNode()); 1450 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1451 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1452 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1453 AddToWorkList(Mul.getNode()); 1454 return Sub; 1455 } 1456 } 1457 1458 // undef % X -> 0 1459 if (N0.getOpcode() == ISD::UNDEF) 1460 return DAG.getConstant(0, VT); 1461 // X % undef -> undef 1462 if (N1.getOpcode() == ISD::UNDEF) 1463 return N1; 1464 1465 return SDValue(); 1466} 1467 1468SDValue DAGCombiner::visitMULHS(SDNode *N) { 1469 SDValue N0 = N->getOperand(0); 1470 SDValue N1 = N->getOperand(1); 1471 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1472 MVT VT = N->getValueType(0); 1473 1474 // fold (mulhs x, 0) -> 0 1475 if (N1C && N1C->isNullValue()) 1476 return N1; 1477 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1478 if (N1C && N1C->getAPIntValue() == 1) 1479 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1480 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1481 TLI.getShiftAmountTy())); 1482 // fold (mulhs x, undef) -> 0 1483 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1484 return DAG.getConstant(0, VT); 1485 1486 return SDValue(); 1487} 1488 1489SDValue DAGCombiner::visitMULHU(SDNode *N) { 1490 SDValue N0 = N->getOperand(0); 1491 SDValue N1 = N->getOperand(1); 1492 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1493 MVT VT = N->getValueType(0); 1494 1495 // fold (mulhu x, 0) -> 0 1496 if (N1C && N1C->isNullValue()) 1497 return N1; 1498 // fold (mulhu x, 1) -> 0 1499 if (N1C && N1C->getAPIntValue() == 1) 1500 return DAG.getConstant(0, N0.getValueType()); 1501 // fold (mulhu x, undef) -> 0 1502 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1503 return DAG.getConstant(0, VT); 1504 1505 return SDValue(); 1506} 1507 1508/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1509/// compute two values. LoOp and HiOp give the opcodes for the two computations 1510/// that are being performed. Return true if a simplification was made. 1511/// 1512SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1513 unsigned HiOp) { 1514 // If the high half is not needed, just compute the low half. 1515 bool HiExists = N->hasAnyUseOfValue(1); 1516 if (!HiExists && 1517 (!AfterLegalize || 1518 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1519 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1520 N->getNumOperands()); 1521 return CombineTo(N, Res, Res); 1522 } 1523 1524 // If the low half is not needed, just compute the high half. 1525 bool LoExists = N->hasAnyUseOfValue(0); 1526 if (!LoExists && 1527 (!AfterLegalize || 1528 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1529 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1530 N->getNumOperands()); 1531 return CombineTo(N, Res, Res); 1532 } 1533 1534 // If both halves are used, return as it is. 1535 if (LoExists && HiExists) 1536 return SDValue(); 1537 1538 // If the two computed results can be simplified separately, separate them. 1539 if (LoExists) { 1540 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1541 N->op_begin(), N->getNumOperands()); 1542 AddToWorkList(Lo.getNode()); 1543 SDValue LoOpt = combine(Lo.getNode()); 1544 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1545 (!AfterLegalize || 1546 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1547 return CombineTo(N, LoOpt, LoOpt); 1548 } 1549 1550 if (HiExists) { 1551 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1552 N->op_begin(), N->getNumOperands()); 1553 AddToWorkList(Hi.getNode()); 1554 SDValue HiOpt = combine(Hi.getNode()); 1555 if (HiOpt.getNode() && HiOpt != Hi && 1556 (!AfterLegalize || 1557 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1558 return CombineTo(N, HiOpt, HiOpt); 1559 } 1560 return SDValue(); 1561} 1562 1563SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1564 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1565 if (Res.getNode()) return Res; 1566 1567 return SDValue(); 1568} 1569 1570SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1571 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1572 if (Res.getNode()) return Res; 1573 1574 return SDValue(); 1575} 1576 1577SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1578 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1579 if (Res.getNode()) return Res; 1580 1581 return SDValue(); 1582} 1583 1584SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1585 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1586 if (Res.getNode()) return Res; 1587 1588 return SDValue(); 1589} 1590 1591/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1592/// two operands of the same opcode, try to simplify it. 1593SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1594 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1595 MVT VT = N0.getValueType(); 1596 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1597 1598 // For each of OP in AND/OR/XOR: 1599 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1600 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1601 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1602 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1603 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1604 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1605 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1606 SDValue ORNode = DAG.getNode(N->getOpcode(), 1607 N0.getOperand(0).getValueType(), 1608 N0.getOperand(0), N1.getOperand(0)); 1609 AddToWorkList(ORNode.getNode()); 1610 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1611 } 1612 1613 // For each of OP in SHL/SRL/SRA/AND... 1614 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1615 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1616 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1617 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1618 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1619 N0.getOperand(1) == N1.getOperand(1)) { 1620 SDValue ORNode = DAG.getNode(N->getOpcode(), 1621 N0.getOperand(0).getValueType(), 1622 N0.getOperand(0), N1.getOperand(0)); 1623 AddToWorkList(ORNode.getNode()); 1624 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1625 } 1626 1627 return SDValue(); 1628} 1629 1630SDValue DAGCombiner::visitAND(SDNode *N) { 1631 SDValue N0 = N->getOperand(0); 1632 SDValue N1 = N->getOperand(1); 1633 SDValue LL, LR, RL, RR, CC0, CC1; 1634 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1636 MVT VT = N1.getValueType(); 1637 unsigned BitWidth = VT.getSizeInBits(); 1638 1639 // fold vector ops 1640 if (VT.isVector()) { 1641 SDValue FoldedVOp = SimplifyVBinOp(N); 1642 if (FoldedVOp.getNode()) return FoldedVOp; 1643 } 1644 1645 // fold (and x, undef) -> 0 1646 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1647 return DAG.getConstant(0, VT); 1648 // fold (and c1, c2) -> c1&c2 1649 if (N0C && N1C) 1650 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1651 // canonicalize constant to RHS 1652 if (N0C && !N1C) 1653 return DAG.getNode(ISD::AND, VT, N1, N0); 1654 // fold (and x, -1) -> x 1655 if (N1C && N1C->isAllOnesValue()) 1656 return N0; 1657 // if (and x, c) is known to be zero, return 0 1658 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1659 APInt::getAllOnesValue(BitWidth))) 1660 return DAG.getConstant(0, VT); 1661 // reassociate and 1662 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1663 if (RAND.getNode() != 0) 1664 return RAND; 1665 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1666 if (N1C && N0.getOpcode() == ISD::OR) 1667 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1668 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1669 return N1; 1670 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1671 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1672 SDValue N0Op0 = N0.getOperand(0); 1673 APInt Mask = ~N1C->getAPIntValue(); 1674 Mask.trunc(N0Op0.getValueSizeInBits()); 1675 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1676 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1677 N0Op0); 1678 1679 // Replace uses of the AND with uses of the Zero extend node. 1680 CombineTo(N, Zext); 1681 1682 // We actually want to replace all uses of the any_extend with the 1683 // zero_extend, to avoid duplicating things. This will later cause this 1684 // AND to be folded. 1685 CombineTo(N0.getNode(), Zext); 1686 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1687 } 1688 } 1689 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1690 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1691 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1692 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1693 1694 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1695 LL.getValueType().isInteger()) { 1696 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1697 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1698 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1699 AddToWorkList(ORNode.getNode()); 1700 return DAG.getSetCC(VT, ORNode, LR, Op1); 1701 } 1702 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1703 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1704 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1705 AddToWorkList(ANDNode.getNode()); 1706 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1707 } 1708 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1709 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1710 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1711 AddToWorkList(ORNode.getNode()); 1712 return DAG.getSetCC(VT, ORNode, LR, Op1); 1713 } 1714 } 1715 // canonicalize equivalent to ll == rl 1716 if (LL == RR && LR == RL) { 1717 Op1 = ISD::getSetCCSwappedOperands(Op1); 1718 std::swap(RL, RR); 1719 } 1720 if (LL == RL && LR == RR) { 1721 bool isInteger = LL.getValueType().isInteger(); 1722 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1723 if (Result != ISD::SETCC_INVALID && 1724 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1725 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1726 } 1727 } 1728 1729 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1730 if (N0.getOpcode() == N1.getOpcode()) { 1731 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1732 if (Tmp.getNode()) return Tmp; 1733 } 1734 1735 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1736 // fold (and (sra)) -> (and (srl)) when possible. 1737 if (!VT.isVector() && 1738 SimplifyDemandedBits(SDValue(N, 0))) 1739 return SDValue(N, 0); 1740 // fold (zext_inreg (extload x)) -> (zextload x) 1741 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1742 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1743 MVT EVT = LN0->getMemoryVT(); 1744 // If we zero all the possible extended bits, then we can turn this into 1745 // a zextload if we are running before legalize or the operation is legal. 1746 unsigned BitWidth = N1.getValueSizeInBits(); 1747 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1748 BitWidth - EVT.getSizeInBits())) && 1749 ((!AfterLegalize && !LN0->isVolatile()) || 1750 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1751 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1752 LN0->getBasePtr(), LN0->getSrcValue(), 1753 LN0->getSrcValueOffset(), EVT, 1754 LN0->isVolatile(), 1755 LN0->getAlignment()); 1756 AddToWorkList(N); 1757 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1758 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1759 } 1760 } 1761 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1762 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1763 N0.hasOneUse()) { 1764 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1765 MVT EVT = LN0->getMemoryVT(); 1766 // If we zero all the possible extended bits, then we can turn this into 1767 // a zextload if we are running before legalize or the operation is legal. 1768 unsigned BitWidth = N1.getValueSizeInBits(); 1769 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1770 BitWidth - EVT.getSizeInBits())) && 1771 ((!AfterLegalize && !LN0->isVolatile()) || 1772 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1773 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1774 LN0->getBasePtr(), LN0->getSrcValue(), 1775 LN0->getSrcValueOffset(), EVT, 1776 LN0->isVolatile(), 1777 LN0->getAlignment()); 1778 AddToWorkList(N); 1779 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1780 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1781 } 1782 } 1783 1784 // fold (and (load x), 255) -> (zextload x, i8) 1785 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1786 if (N1C && N0.getOpcode() == ISD::LOAD) { 1787 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1788 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1789 LN0->isUnindexed() && N0.hasOneUse() && 1790 // Do not change the width of a volatile load. 1791 !LN0->isVolatile()) { 1792 MVT EVT = MVT::Other; 1793 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1794 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1795 EVT = MVT::getIntegerVT(ActiveBits); 1796 1797 MVT LoadedVT = LN0->getMemoryVT(); 1798 // Do not generate loads of non-round integer types since these can 1799 // be expensive (and would be wrong if the type is not byte sized). 1800 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1801 (!AfterLegalize || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1802 MVT PtrType = N0.getOperand(1).getValueType(); 1803 // For big endian targets, we need to add an offset to the pointer to 1804 // load the correct bytes. For little endian systems, we merely need to 1805 // read fewer bytes from the same pointer. 1806 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1807 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1808 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1809 unsigned Alignment = LN0->getAlignment(); 1810 SDValue NewPtr = LN0->getBasePtr(); 1811 if (TLI.isBigEndian()) { 1812 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1813 DAG.getConstant(PtrOff, PtrType)); 1814 Alignment = MinAlign(Alignment, PtrOff); 1815 } 1816 AddToWorkList(NewPtr.getNode()); 1817 SDValue Load = 1818 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1819 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1820 LN0->isVolatile(), Alignment); 1821 AddToWorkList(N); 1822 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1823 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1824 } 1825 } 1826 } 1827 1828 return SDValue(); 1829} 1830 1831SDValue DAGCombiner::visitOR(SDNode *N) { 1832 SDValue N0 = N->getOperand(0); 1833 SDValue N1 = N->getOperand(1); 1834 SDValue LL, LR, RL, RR, CC0, CC1; 1835 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1837 MVT VT = N1.getValueType(); 1838 1839 // fold vector ops 1840 if (VT.isVector()) { 1841 SDValue FoldedVOp = SimplifyVBinOp(N); 1842 if (FoldedVOp.getNode()) return FoldedVOp; 1843 } 1844 1845 // fold (or x, undef) -> -1 1846 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1847 return DAG.getConstant(~0ULL, VT); 1848 // fold (or c1, c2) -> c1|c2 1849 if (N0C && N1C) 1850 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1851 // canonicalize constant to RHS 1852 if (N0C && !N1C) 1853 return DAG.getNode(ISD::OR, VT, N1, N0); 1854 // fold (or x, 0) -> x 1855 if (N1C && N1C->isNullValue()) 1856 return N0; 1857 // fold (or x, -1) -> -1 1858 if (N1C && N1C->isAllOnesValue()) 1859 return N1; 1860 // fold (or x, c) -> c iff (x & ~c) == 0 1861 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1862 return N1; 1863 // reassociate or 1864 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1865 if (ROR.getNode() != 0) 1866 return ROR; 1867 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1868 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1869 isa<ConstantSDNode>(N0.getOperand(1))) { 1870 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1871 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1872 N1), 1873 DAG.getConstant(N1C->getAPIntValue() | 1874 C1->getAPIntValue(), VT)); 1875 } 1876 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1877 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1878 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1879 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1880 1881 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1882 LL.getValueType().isInteger()) { 1883 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1884 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1885 if (cast<ConstantSDNode>(LR)->isNullValue() && 1886 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1887 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1888 AddToWorkList(ORNode.getNode()); 1889 return DAG.getSetCC(VT, ORNode, LR, Op1); 1890 } 1891 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1892 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1893 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1894 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1895 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1896 AddToWorkList(ANDNode.getNode()); 1897 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1898 } 1899 } 1900 // canonicalize equivalent to ll == rl 1901 if (LL == RR && LR == RL) { 1902 Op1 = ISD::getSetCCSwappedOperands(Op1); 1903 std::swap(RL, RR); 1904 } 1905 if (LL == RL && LR == RR) { 1906 bool isInteger = LL.getValueType().isInteger(); 1907 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1908 if (Result != ISD::SETCC_INVALID && 1909 (!AfterLegalize || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1910 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1911 } 1912 } 1913 1914 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1915 if (N0.getOpcode() == N1.getOpcode()) { 1916 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1917 if (Tmp.getNode()) return Tmp; 1918 } 1919 1920 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1921 if (N0.getOpcode() == ISD::AND && 1922 N1.getOpcode() == ISD::AND && 1923 N0.getOperand(1).getOpcode() == ISD::Constant && 1924 N1.getOperand(1).getOpcode() == ISD::Constant && 1925 // Don't increase # computations. 1926 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1927 // We can only do this xform if we know that bits from X that are set in C2 1928 // but not in C1 are already zero. Likewise for Y. 1929 const APInt &LHSMask = 1930 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1931 const APInt &RHSMask = 1932 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1933 1934 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1935 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1936 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1937 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1938 } 1939 } 1940 1941 1942 // See if this is some rotate idiom. 1943 if (SDNode *Rot = MatchRotate(N0, N1)) 1944 return SDValue(Rot, 0); 1945 1946 return SDValue(); 1947} 1948 1949 1950/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1951static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1952 if (Op.getOpcode() == ISD::AND) { 1953 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1954 Mask = Op.getOperand(1); 1955 Op = Op.getOperand(0); 1956 } else { 1957 return false; 1958 } 1959 } 1960 1961 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1962 Shift = Op; 1963 return true; 1964 } 1965 return false; 1966} 1967 1968 1969// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1970// idioms for rotate, and if the target supports rotation instructions, generate 1971// a rot[lr]. 1972SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1973 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1974 MVT VT = LHS.getValueType(); 1975 if (!TLI.isTypeLegal(VT)) return 0; 1976 1977 // The target must have at least one rotate flavor. 1978 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1979 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1980 if (!HasROTL && !HasROTR) return 0; 1981 1982 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1983 SDValue LHSShift; // The shift. 1984 SDValue LHSMask; // AND value if any. 1985 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1986 return 0; // Not part of a rotate. 1987 1988 SDValue RHSShift; // The shift. 1989 SDValue RHSMask; // AND value if any. 1990 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1991 return 0; // Not part of a rotate. 1992 1993 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1994 return 0; // Not shifting the same value. 1995 1996 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1997 return 0; // Shifts must disagree. 1998 1999 // Canonicalize shl to left side in a shl/srl pair. 2000 if (RHSShift.getOpcode() == ISD::SHL) { 2001 std::swap(LHS, RHS); 2002 std::swap(LHSShift, RHSShift); 2003 std::swap(LHSMask , RHSMask ); 2004 } 2005 2006 unsigned OpSizeInBits = VT.getSizeInBits(); 2007 SDValue LHSShiftArg = LHSShift.getOperand(0); 2008 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2009 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2010 2011 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2012 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2013 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2014 RHSShiftAmt.getOpcode() == ISD::Constant) { 2015 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2016 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2017 if ((LShVal + RShVal) != OpSizeInBits) 2018 return 0; 2019 2020 SDValue Rot; 2021 if (HasROTL) 2022 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2023 else 2024 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2025 2026 // If there is an AND of either shifted operand, apply it to the result. 2027 if (LHSMask.getNode() || RHSMask.getNode()) { 2028 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2029 2030 if (LHSMask.getNode()) { 2031 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2032 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2033 } 2034 if (RHSMask.getNode()) { 2035 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2036 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2037 } 2038 2039 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2040 } 2041 2042 return Rot.getNode(); 2043 } 2044 2045 // If there is a mask here, and we have a variable shift, we can't be sure 2046 // that we're masking out the right stuff. 2047 if (LHSMask.getNode() || RHSMask.getNode()) 2048 return 0; 2049 2050 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2051 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2052 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2053 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2054 if (ConstantSDNode *SUBC = 2055 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2056 if (SUBC->getAPIntValue() == OpSizeInBits) { 2057 if (HasROTL) 2058 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2059 else 2060 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2061 } 2062 } 2063 } 2064 2065 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2066 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2067 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2068 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2069 if (ConstantSDNode *SUBC = 2070 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2071 if (SUBC->getAPIntValue() == OpSizeInBits) { 2072 if (HasROTR) 2073 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2074 else 2075 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2076 } 2077 } 2078 } 2079 2080 // Look for sign/zext/any-extended or truncate cases: 2081 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2082 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2083 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2084 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2085 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2086 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2087 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2088 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2089 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2090 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2091 if (RExtOp0.getOpcode() == ISD::SUB && 2092 RExtOp0.getOperand(1) == LExtOp0) { 2093 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2094 // (rotl x, y) 2095 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2096 // (rotr x, (sub 32, y)) 2097 if (ConstantSDNode *SUBC = 2098 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2099 if (SUBC->getAPIntValue() == OpSizeInBits) { 2100 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2101 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2102 } 2103 } 2104 } else if (LExtOp0.getOpcode() == ISD::SUB && 2105 RExtOp0 == LExtOp0.getOperand(1)) { 2106 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2107 // (rotr x, y) 2108 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2109 // (rotl x, (sub 32, y)) 2110 if (ConstantSDNode *SUBC = 2111 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2112 if (SUBC->getAPIntValue() == OpSizeInBits) { 2113 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2114 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2115 } 2116 } 2117 } 2118 } 2119 2120 return 0; 2121} 2122 2123 2124SDValue DAGCombiner::visitXOR(SDNode *N) { 2125 SDValue N0 = N->getOperand(0); 2126 SDValue N1 = N->getOperand(1); 2127 SDValue LHS, RHS, CC; 2128 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2129 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2130 MVT VT = N0.getValueType(); 2131 2132 // fold vector ops 2133 if (VT.isVector()) { 2134 SDValue FoldedVOp = SimplifyVBinOp(N); 2135 if (FoldedVOp.getNode()) return FoldedVOp; 2136 } 2137 2138 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2139 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2140 return DAG.getConstant(0, VT); 2141 // fold (xor x, undef) -> undef 2142 if (N0.getOpcode() == ISD::UNDEF) 2143 return N0; 2144 if (N1.getOpcode() == ISD::UNDEF) 2145 return N1; 2146 // fold (xor c1, c2) -> c1^c2 2147 if (N0C && N1C) 2148 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2149 // canonicalize constant to RHS 2150 if (N0C && !N1C) 2151 return DAG.getNode(ISD::XOR, VT, N1, N0); 2152 // fold (xor x, 0) -> x 2153 if (N1C && N1C->isNullValue()) 2154 return N0; 2155 // reassociate xor 2156 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2157 if (RXOR.getNode() != 0) 2158 return RXOR; 2159 // fold !(x cc y) -> (x !cc y) 2160 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2161 bool isInt = LHS.getValueType().isInteger(); 2162 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2163 isInt); 2164 if (N0.getOpcode() == ISD::SETCC) 2165 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2166 if (N0.getOpcode() == ISD::SELECT_CC) 2167 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2168 assert(0 && "Unhandled SetCC Equivalent!"); 2169 abort(); 2170 } 2171 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2172 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2173 N0.getNode()->hasOneUse() && 2174 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2175 SDValue V = N0.getOperand(0); 2176 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2177 DAG.getConstant(1, V.getValueType())); 2178 AddToWorkList(V.getNode()); 2179 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2180 } 2181 2182 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2183 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2184 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2185 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2186 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2187 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2188 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2189 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2190 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2191 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2192 } 2193 } 2194 // fold !(x or y) -> (!x and !y) iff x or y are constants 2195 if (N1C && N1C->isAllOnesValue() && 2196 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2197 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2198 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2199 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2200 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2201 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2202 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2203 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2204 } 2205 } 2206 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2207 if (N1C && N0.getOpcode() == ISD::XOR) { 2208 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2209 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2210 if (N00C) 2211 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2212 DAG.getConstant(N1C->getAPIntValue()^ 2213 N00C->getAPIntValue(), VT)); 2214 if (N01C) 2215 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2216 DAG.getConstant(N1C->getAPIntValue()^ 2217 N01C->getAPIntValue(), VT)); 2218 } 2219 // fold (xor x, x) -> 0 2220 if (N0 == N1) { 2221 if (!VT.isVector()) { 2222 return DAG.getConstant(0, VT); 2223 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2224 // Produce a vector of zeros. 2225 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2226 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2227 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2228 } 2229 } 2230 2231 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2232 if (N0.getOpcode() == N1.getOpcode()) { 2233 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2234 if (Tmp.getNode()) return Tmp; 2235 } 2236 2237 // Simplify the expression using non-local knowledge. 2238 if (!VT.isVector() && 2239 SimplifyDemandedBits(SDValue(N, 0))) 2240 return SDValue(N, 0); 2241 2242 return SDValue(); 2243} 2244 2245/// visitShiftByConstant - Handle transforms common to the three shifts, when 2246/// the shift amount is a constant. 2247SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2248 SDNode *LHS = N->getOperand(0).getNode(); 2249 if (!LHS->hasOneUse()) return SDValue(); 2250 2251 // We want to pull some binops through shifts, so that we have (and (shift)) 2252 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2253 // thing happens with address calculations, so it's important to canonicalize 2254 // it. 2255 bool HighBitSet = false; // Can we transform this if the high bit is set? 2256 2257 switch (LHS->getOpcode()) { 2258 default: return SDValue(); 2259 case ISD::OR: 2260 case ISD::XOR: 2261 HighBitSet = false; // We can only transform sra if the high bit is clear. 2262 break; 2263 case ISD::AND: 2264 HighBitSet = true; // We can only transform sra if the high bit is set. 2265 break; 2266 case ISD::ADD: 2267 if (N->getOpcode() != ISD::SHL) 2268 return SDValue(); // only shl(add) not sr[al](add). 2269 HighBitSet = false; // We can only transform sra if the high bit is clear. 2270 break; 2271 } 2272 2273 // We require the RHS of the binop to be a constant as well. 2274 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2275 if (!BinOpCst) return SDValue(); 2276 2277 2278 // FIXME: disable this for unless the input to the binop is a shift by a 2279 // constant. If it is not a shift, it pessimizes some common cases like: 2280 // 2281 //void foo(int *X, int i) { X[i & 1235] = 1; } 2282 //int bar(int *X, int i) { return X[i & 255]; } 2283 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2284 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2285 BinOpLHSVal->getOpcode() != ISD::SRA && 2286 BinOpLHSVal->getOpcode() != ISD::SRL) || 2287 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2288 return SDValue(); 2289 2290 MVT VT = N->getValueType(0); 2291 2292 // If this is a signed shift right, and the high bit is modified 2293 // by the logical operation, do not perform the transformation. 2294 // The highBitSet boolean indicates the value of the high bit of 2295 // the constant which would cause it to be modified for this 2296 // operation. 2297 if (N->getOpcode() == ISD::SRA) { 2298 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2299 if (BinOpRHSSignSet != HighBitSet) 2300 return SDValue(); 2301 } 2302 2303 // Fold the constants, shifting the binop RHS by the shift amount. 2304 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2305 LHS->getOperand(1), N->getOperand(1)); 2306 2307 // Create the new shift. 2308 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2309 N->getOperand(1)); 2310 2311 // Create the new binop. 2312 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2313} 2314 2315 2316SDValue DAGCombiner::visitSHL(SDNode *N) { 2317 SDValue N0 = N->getOperand(0); 2318 SDValue N1 = N->getOperand(1); 2319 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2320 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2321 MVT VT = N0.getValueType(); 2322 unsigned OpSizeInBits = VT.getSizeInBits(); 2323 2324 // fold (shl c1, c2) -> c1<<c2 2325 if (N0C && N1C) 2326 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2327 // fold (shl 0, x) -> 0 2328 if (N0C && N0C->isNullValue()) 2329 return N0; 2330 // fold (shl x, c >= size(x)) -> undef 2331 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2332 return DAG.getNode(ISD::UNDEF, VT); 2333 // fold (shl x, 0) -> x 2334 if (N1C && N1C->isNullValue()) 2335 return N0; 2336 // if (shl x, c) is known to be zero, return 0 2337 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2338 APInt::getAllOnesValue(VT.getSizeInBits()))) 2339 return DAG.getConstant(0, VT); 2340 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2341 // iff (trunc c) == c 2342 if (N1.getOpcode() == ISD::TRUNCATE && 2343 N1.getOperand(0).getOpcode() == ISD::AND && 2344 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2345 SDValue N101 = N1.getOperand(0).getOperand(1); 2346 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2347 MVT TruncVT = N1.getValueType(); 2348 SDValue N100 = N1.getOperand(0).getOperand(0); 2349 return DAG.getNode(ISD::SHL, VT, N0, 2350 DAG.getNode(ISD::AND, TruncVT, 2351 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2352 DAG.getConstant(N101C->getZExtValue(), 2353 TruncVT))); 2354 } 2355 } 2356 2357 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2358 return SDValue(N, 0); 2359 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2360 if (N1C && N0.getOpcode() == ISD::SHL && 2361 N0.getOperand(1).getOpcode() == ISD::Constant) { 2362 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2363 uint64_t c2 = N1C->getZExtValue(); 2364 if (c1 + c2 > OpSizeInBits) 2365 return DAG.getConstant(0, VT); 2366 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2367 DAG.getConstant(c1 + c2, N1.getValueType())); 2368 } 2369 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2370 // (srl (and x, -1 << c1), c1-c2) 2371 if (N1C && N0.getOpcode() == ISD::SRL && 2372 N0.getOperand(1).getOpcode() == ISD::Constant) { 2373 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2374 uint64_t c2 = N1C->getZExtValue(); 2375 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2376 DAG.getConstant(~0ULL << c1, VT)); 2377 if (c2 > c1) 2378 return DAG.getNode(ISD::SHL, VT, Mask, 2379 DAG.getConstant(c2-c1, N1.getValueType())); 2380 else 2381 return DAG.getNode(ISD::SRL, VT, Mask, 2382 DAG.getConstant(c1-c2, N1.getValueType())); 2383 } 2384 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2385 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2386 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2387 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2388 2389 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2390} 2391 2392SDValue DAGCombiner::visitSRA(SDNode *N) { 2393 SDValue N0 = N->getOperand(0); 2394 SDValue N1 = N->getOperand(1); 2395 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2396 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2397 MVT VT = N0.getValueType(); 2398 2399 // fold (sra c1, c2) -> c1>>c2 2400 if (N0C && N1C) 2401 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2402 // fold (sra 0, x) -> 0 2403 if (N0C && N0C->isNullValue()) 2404 return N0; 2405 // fold (sra -1, x) -> -1 2406 if (N0C && N0C->isAllOnesValue()) 2407 return N0; 2408 // fold (sra x, c >= size(x)) -> undef 2409 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2410 return DAG.getNode(ISD::UNDEF, VT); 2411 // fold (sra x, 0) -> x 2412 if (N1C && N1C->isNullValue()) 2413 return N0; 2414 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2415 // sext_inreg. 2416 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2417 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2418 MVT EVT = MVT::getIntegerVT(LowBits); 2419 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2420 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2421 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2422 DAG.getValueType(EVT)); 2423 } 2424 2425 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2426 if (N1C && N0.getOpcode() == ISD::SRA) { 2427 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2428 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2429 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2430 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2431 DAG.getConstant(Sum, N1C->getValueType(0))); 2432 } 2433 } 2434 2435 // fold sra (shl X, m), result_size - n 2436 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2437 // result_size - n != m. 2438 // If truncate is free for the target sext(shl) is likely to result in better 2439 // code. 2440 if (N0.getOpcode() == ISD::SHL) { 2441 // Get the two constanst of the shifts, CN0 = m, CN = n. 2442 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2443 if (N01C && N1C) { 2444 // Determine what the truncate's result bitsize and type would be. 2445 unsigned VTValSize = VT.getSizeInBits(); 2446 MVT TruncVT = 2447 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2448 // Determine the residual right-shift amount. 2449 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2450 2451 // If the shift is not a no-op (in which case this should be just a sign 2452 // extend already), the truncated to type is legal, sign_extend is legal 2453 // on that type, and the the truncate to that type is both legal and free, 2454 // perform the transform. 2455 if (ShiftAmt && 2456 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2457 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2458 TLI.isTruncateFree(VT, TruncVT)) { 2459 2460 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2461 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2462 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2463 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2464 } 2465 } 2466 } 2467 2468 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2469 // iff (trunc c) == c 2470 if (N1.getOpcode() == ISD::TRUNCATE && 2471 N1.getOperand(0).getOpcode() == ISD::AND && 2472 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2473 SDValue N101 = N1.getOperand(0).getOperand(1); 2474 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2475 MVT TruncVT = N1.getValueType(); 2476 SDValue N100 = N1.getOperand(0).getOperand(0); 2477 return DAG.getNode(ISD::SRA, VT, N0, 2478 DAG.getNode(ISD::AND, TruncVT, 2479 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2480 DAG.getConstant(N101C->getZExtValue(), 2481 TruncVT))); 2482 } 2483 } 2484 2485 // Simplify, based on bits shifted out of the LHS. 2486 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2487 return SDValue(N, 0); 2488 2489 2490 // If the sign bit is known to be zero, switch this to a SRL. 2491 if (DAG.SignBitIsZero(N0)) 2492 return DAG.getNode(ISD::SRL, VT, N0, N1); 2493 2494 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2495} 2496 2497SDValue DAGCombiner::visitSRL(SDNode *N) { 2498 SDValue N0 = N->getOperand(0); 2499 SDValue N1 = N->getOperand(1); 2500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2502 MVT VT = N0.getValueType(); 2503 unsigned OpSizeInBits = VT.getSizeInBits(); 2504 2505 // fold (srl c1, c2) -> c1 >>u c2 2506 if (N0C && N1C) 2507 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2508 // fold (srl 0, x) -> 0 2509 if (N0C && N0C->isNullValue()) 2510 return N0; 2511 // fold (srl x, c >= size(x)) -> undef 2512 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2513 return DAG.getNode(ISD::UNDEF, VT); 2514 // fold (srl x, 0) -> x 2515 if (N1C && N1C->isNullValue()) 2516 return N0; 2517 // if (srl x, c) is known to be zero, return 0 2518 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2519 APInt::getAllOnesValue(OpSizeInBits))) 2520 return DAG.getConstant(0, VT); 2521 2522 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2523 if (N1C && N0.getOpcode() == ISD::SRL && 2524 N0.getOperand(1).getOpcode() == ISD::Constant) { 2525 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2526 uint64_t c2 = N1C->getZExtValue(); 2527 if (c1 + c2 > OpSizeInBits) 2528 return DAG.getConstant(0, VT); 2529 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2530 DAG.getConstant(c1 + c2, N1.getValueType())); 2531 } 2532 2533 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2534 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2535 // Shifting in all undef bits? 2536 MVT SmallVT = N0.getOperand(0).getValueType(); 2537 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2538 return DAG.getNode(ISD::UNDEF, VT); 2539 2540 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2541 AddToWorkList(SmallShift.getNode()); 2542 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2543 } 2544 2545 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2546 // bit, which is unmodified by sra. 2547 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2548 if (N0.getOpcode() == ISD::SRA) 2549 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2550 } 2551 2552 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2553 if (N1C && N0.getOpcode() == ISD::CTLZ && 2554 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2555 APInt KnownZero, KnownOne; 2556 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2557 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2558 2559 // If any of the input bits are KnownOne, then the input couldn't be all 2560 // zeros, thus the result of the srl will always be zero. 2561 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2562 2563 // If all of the bits input the to ctlz node are known to be zero, then 2564 // the result of the ctlz is "32" and the result of the shift is one. 2565 APInt UnknownBits = ~KnownZero & Mask; 2566 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2567 2568 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2569 if ((UnknownBits & (UnknownBits-1)) == 0) { 2570 // Okay, we know that only that the single bit specified by UnknownBits 2571 // could be set on input to the CTLZ node. If this bit is set, the SRL 2572 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2573 // to an SRL,XOR pair, which is likely to simplify more. 2574 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2575 SDValue Op = N0.getOperand(0); 2576 if (ShAmt) { 2577 Op = DAG.getNode(ISD::SRL, VT, Op, 2578 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2579 AddToWorkList(Op.getNode()); 2580 } 2581 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2582 } 2583 } 2584 2585 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2586 // iff (trunc c) == c 2587 if (N1.getOpcode() == ISD::TRUNCATE && 2588 N1.getOperand(0).getOpcode() == ISD::AND && 2589 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2590 SDValue N101 = N1.getOperand(0).getOperand(1); 2591 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2592 MVT TruncVT = N1.getValueType(); 2593 SDValue N100 = N1.getOperand(0).getOperand(0); 2594 return DAG.getNode(ISD::SRL, VT, N0, 2595 DAG.getNode(ISD::AND, TruncVT, 2596 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2597 DAG.getConstant(N101C->getZExtValue(), 2598 TruncVT))); 2599 } 2600 } 2601 2602 // fold operands of srl based on knowledge that the low bits are not 2603 // demanded. 2604 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2605 return SDValue(N, 0); 2606 2607 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2608} 2609 2610SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2611 SDValue N0 = N->getOperand(0); 2612 MVT VT = N->getValueType(0); 2613 2614 // fold (ctlz c1) -> c2 2615 if (isa<ConstantSDNode>(N0)) 2616 return DAG.getNode(ISD::CTLZ, VT, N0); 2617 return SDValue(); 2618} 2619 2620SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2621 SDValue N0 = N->getOperand(0); 2622 MVT VT = N->getValueType(0); 2623 2624 // fold (cttz c1) -> c2 2625 if (isa<ConstantSDNode>(N0)) 2626 return DAG.getNode(ISD::CTTZ, VT, N0); 2627 return SDValue(); 2628} 2629 2630SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2631 SDValue N0 = N->getOperand(0); 2632 MVT VT = N->getValueType(0); 2633 2634 // fold (ctpop c1) -> c2 2635 if (isa<ConstantSDNode>(N0)) 2636 return DAG.getNode(ISD::CTPOP, VT, N0); 2637 return SDValue(); 2638} 2639 2640SDValue DAGCombiner::visitSELECT(SDNode *N) { 2641 SDValue N0 = N->getOperand(0); 2642 SDValue N1 = N->getOperand(1); 2643 SDValue N2 = N->getOperand(2); 2644 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2645 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2646 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2647 MVT VT = N->getValueType(0); 2648 MVT VT0 = N0.getValueType(); 2649 2650 // fold select C, X, X -> X 2651 if (N1 == N2) 2652 return N1; 2653 // fold select true, X, Y -> X 2654 if (N0C && !N0C->isNullValue()) 2655 return N1; 2656 // fold select false, X, Y -> Y 2657 if (N0C && N0C->isNullValue()) 2658 return N2; 2659 // fold select C, 1, X -> C | X 2660 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2661 return DAG.getNode(ISD::OR, VT, N0, N2); 2662 // fold select C, 0, 1 -> ~C 2663 if (VT.isInteger() && VT0.isInteger() && 2664 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2665 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2666 if (VT == VT0) 2667 return XORNode; 2668 AddToWorkList(XORNode.getNode()); 2669 if (VT.bitsGT(VT0)) 2670 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2671 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2672 } 2673 // fold select C, 0, X -> ~C & X 2674 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2675 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2676 AddToWorkList(XORNode.getNode()); 2677 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2678 } 2679 // fold select C, X, 1 -> ~C | X 2680 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2681 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2682 AddToWorkList(XORNode.getNode()); 2683 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2684 } 2685 // fold select C, X, 0 -> C & X 2686 // FIXME: this should check for C type == X type, not i1? 2687 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2688 return DAG.getNode(ISD::AND, VT, N0, N1); 2689 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2690 if (VT == MVT::i1 && N0 == N1) 2691 return DAG.getNode(ISD::OR, VT, N0, N2); 2692 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2693 if (VT == MVT::i1 && N0 == N2) 2694 return DAG.getNode(ISD::AND, VT, N0, N1); 2695 2696 // If we can fold this based on the true/false value, do so. 2697 if (SimplifySelectOps(N, N1, N2)) 2698 return SDValue(N, 0); // Don't revisit N. 2699 2700 // fold selects based on a setcc into other things, such as min/max/abs 2701 if (N0.getOpcode() == ISD::SETCC) { 2702 // FIXME: 2703 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2704 // having to say they don't support SELECT_CC on every type the DAG knows 2705 // about, since there is no way to mark an opcode illegal at all value types 2706 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2707 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2708 N1, N2, N0.getOperand(2)); 2709 else 2710 return SimplifySelect(N0, N1, N2); 2711 } 2712 return SDValue(); 2713} 2714 2715SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2716 SDValue N0 = N->getOperand(0); 2717 SDValue N1 = N->getOperand(1); 2718 SDValue N2 = N->getOperand(2); 2719 SDValue N3 = N->getOperand(3); 2720 SDValue N4 = N->getOperand(4); 2721 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2722 2723 // fold select_cc lhs, rhs, x, x, cc -> x 2724 if (N2 == N3) 2725 return N2; 2726 2727 // Determine if the condition we're dealing with is constant 2728 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2729 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2730 2731 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2732 if (!SCCC->isNullValue()) 2733 return N2; // cond always true -> true val 2734 else 2735 return N3; // cond always false -> false val 2736 } 2737 2738 // Fold to a simpler select_cc 2739 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2740 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2741 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2742 SCC.getOperand(2)); 2743 2744 // If we can fold this based on the true/false value, do so. 2745 if (SimplifySelectOps(N, N2, N3)) 2746 return SDValue(N, 0); // Don't revisit N. 2747 2748 // fold select_cc into other things, such as min/max/abs 2749 return SimplifySelectCC(N0, N1, N2, N3, CC); 2750} 2751 2752SDValue DAGCombiner::visitSETCC(SDNode *N) { 2753 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2754 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2755} 2756 2757// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2758// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2759// transformation. Returns true if extension are possible and the above 2760// mentioned transformation is profitable. 2761static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2762 unsigned ExtOpc, 2763 SmallVector<SDNode*, 4> &ExtendNodes, 2764 TargetLowering &TLI) { 2765 bool HasCopyToRegUses = false; 2766 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2767 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2768 UE = N0.getNode()->use_end(); 2769 UI != UE; ++UI) { 2770 SDNode *User = *UI; 2771 if (User == N) 2772 continue; 2773 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2774 if (User->getOpcode() == ISD::SETCC) { 2775 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2776 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2777 // Sign bits will be lost after a zext. 2778 return false; 2779 bool Add = false; 2780 for (unsigned i = 0; i != 2; ++i) { 2781 SDValue UseOp = User->getOperand(i); 2782 if (UseOp == N0) 2783 continue; 2784 if (!isa<ConstantSDNode>(UseOp)) 2785 return false; 2786 Add = true; 2787 } 2788 if (Add) 2789 ExtendNodes.push_back(User); 2790 } else { 2791 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2792 SDValue UseOp = User->getOperand(i); 2793 if (UseOp == N0) { 2794 // If truncate from extended type to original load type is free 2795 // on this target, then it's ok to extend a CopyToReg. 2796 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2797 HasCopyToRegUses = true; 2798 else 2799 return false; 2800 } 2801 } 2802 } 2803 } 2804 2805 if (HasCopyToRegUses) { 2806 bool BothLiveOut = false; 2807 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2808 UI != UE; ++UI) { 2809 SDNode *User = *UI; 2810 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2811 SDValue UseOp = User->getOperand(i); 2812 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2813 BothLiveOut = true; 2814 break; 2815 } 2816 } 2817 } 2818 if (BothLiveOut) 2819 // Both unextended and extended values are live out. There had better be 2820 // good a reason for the transformation. 2821 return ExtendNodes.size(); 2822 } 2823 return true; 2824} 2825 2826SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2827 SDValue N0 = N->getOperand(0); 2828 MVT VT = N->getValueType(0); 2829 2830 // fold (sext c1) -> c1 2831 if (isa<ConstantSDNode>(N0)) 2832 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2833 2834 // fold (sext (sext x)) -> (sext x) 2835 // fold (sext (aext x)) -> (sext x) 2836 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2837 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2838 2839 if (N0.getOpcode() == ISD::TRUNCATE) { 2840 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2841 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2842 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2843 if (NarrowLoad.getNode()) { 2844 if (NarrowLoad.getNode() != N0.getNode()) 2845 CombineTo(N0.getNode(), NarrowLoad); 2846 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2847 } 2848 2849 // See if the value being truncated is already sign extended. If so, just 2850 // eliminate the trunc/sext pair. 2851 SDValue Op = N0.getOperand(0); 2852 unsigned OpBits = Op.getValueType().getSizeInBits(); 2853 unsigned MidBits = N0.getValueType().getSizeInBits(); 2854 unsigned DestBits = VT.getSizeInBits(); 2855 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2856 2857 if (OpBits == DestBits) { 2858 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2859 // bits, it is already ready. 2860 if (NumSignBits > DestBits-MidBits) 2861 return Op; 2862 } else if (OpBits < DestBits) { 2863 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2864 // bits, just sext from i32. 2865 if (NumSignBits > OpBits-MidBits) 2866 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2867 } else { 2868 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2869 // bits, just truncate to i32. 2870 if (NumSignBits > OpBits-MidBits) 2871 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2872 } 2873 2874 // fold (sext (truncate x)) -> (sextinreg x). 2875 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2876 N0.getValueType())) { 2877 if (Op.getValueType().bitsLT(VT)) 2878 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2879 else if (Op.getValueType().bitsGT(VT)) 2880 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2881 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2882 DAG.getValueType(N0.getValueType())); 2883 } 2884 } 2885 2886 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2887 if (ISD::isNON_EXTLoad(N0.getNode()) && 2888 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2889 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2890 bool DoXform = true; 2891 SmallVector<SDNode*, 4> SetCCs; 2892 if (!N0.hasOneUse()) 2893 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2894 if (DoXform) { 2895 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2896 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2897 LN0->getBasePtr(), LN0->getSrcValue(), 2898 LN0->getSrcValueOffset(), 2899 N0.getValueType(), 2900 LN0->isVolatile(), 2901 LN0->getAlignment()); 2902 CombineTo(N, ExtLoad); 2903 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2904 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2905 // Extend SetCC uses if necessary. 2906 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2907 SDNode *SetCC = SetCCs[i]; 2908 SmallVector<SDValue, 4> Ops; 2909 for (unsigned j = 0; j != 2; ++j) { 2910 SDValue SOp = SetCC->getOperand(j); 2911 if (SOp == Trunc) 2912 Ops.push_back(ExtLoad); 2913 else 2914 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2915 } 2916 Ops.push_back(SetCC->getOperand(2)); 2917 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2918 &Ops[0], Ops.size())); 2919 } 2920 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2921 } 2922 } 2923 2924 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2925 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2926 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2927 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2928 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2929 MVT EVT = LN0->getMemoryVT(); 2930 if ((!AfterLegalize && !LN0->isVolatile()) || 2931 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 2932 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2933 LN0->getBasePtr(), LN0->getSrcValue(), 2934 LN0->getSrcValueOffset(), EVT, 2935 LN0->isVolatile(), 2936 LN0->getAlignment()); 2937 CombineTo(N, ExtLoad); 2938 CombineTo(N0.getNode(), 2939 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2940 ExtLoad.getValue(1)); 2941 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2942 } 2943 } 2944 2945 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2946 if (N0.getOpcode() == ISD::SETCC) { 2947 SDValue SCC = 2948 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2949 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2950 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2951 if (SCC.getNode()) return SCC; 2952 } 2953 2954 // fold (sext x) -> (zext x) if the sign bit is known zero. 2955 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2956 DAG.SignBitIsZero(N0)) 2957 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2958 2959 return SDValue(); 2960} 2961 2962SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2963 SDValue N0 = N->getOperand(0); 2964 MVT VT = N->getValueType(0); 2965 2966 // fold (zext c1) -> c1 2967 if (isa<ConstantSDNode>(N0)) 2968 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2969 // fold (zext (zext x)) -> (zext x) 2970 // fold (zext (aext x)) -> (zext x) 2971 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2972 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2973 2974 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2975 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2976 if (N0.getOpcode() == ISD::TRUNCATE) { 2977 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2978 if (NarrowLoad.getNode()) { 2979 if (NarrowLoad.getNode() != N0.getNode()) 2980 CombineTo(N0.getNode(), NarrowLoad); 2981 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2982 } 2983 } 2984 2985 // fold (zext (truncate x)) -> (and x, mask) 2986 if (N0.getOpcode() == ISD::TRUNCATE && 2987 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2988 SDValue Op = N0.getOperand(0); 2989 if (Op.getValueType().bitsLT(VT)) { 2990 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2991 } else if (Op.getValueType().bitsGT(VT)) { 2992 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2993 } 2994 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2995 } 2996 2997 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2998 if (N0.getOpcode() == ISD::AND && 2999 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3000 N0.getOperand(1).getOpcode() == ISD::Constant) { 3001 SDValue X = N0.getOperand(0).getOperand(0); 3002 if (X.getValueType().bitsLT(VT)) { 3003 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3004 } else if (X.getValueType().bitsGT(VT)) { 3005 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3006 } 3007 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3008 Mask.zext(VT.getSizeInBits()); 3009 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3010 } 3011 3012 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3013 if (ISD::isNON_EXTLoad(N0.getNode()) && 3014 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3015 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3016 bool DoXform = true; 3017 SmallVector<SDNode*, 4> SetCCs; 3018 if (!N0.hasOneUse()) 3019 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3020 if (DoXform) { 3021 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3022 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3023 LN0->getBasePtr(), LN0->getSrcValue(), 3024 LN0->getSrcValueOffset(), 3025 N0.getValueType(), 3026 LN0->isVolatile(), 3027 LN0->getAlignment()); 3028 CombineTo(N, ExtLoad); 3029 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3030 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3031 // Extend SetCC uses if necessary. 3032 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3033 SDNode *SetCC = SetCCs[i]; 3034 SmallVector<SDValue, 4> Ops; 3035 for (unsigned j = 0; j != 2; ++j) { 3036 SDValue SOp = SetCC->getOperand(j); 3037 if (SOp == Trunc) 3038 Ops.push_back(ExtLoad); 3039 else 3040 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3041 } 3042 Ops.push_back(SetCC->getOperand(2)); 3043 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3044 &Ops[0], Ops.size())); 3045 } 3046 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3047 } 3048 } 3049 3050 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3051 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3052 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3053 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3054 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3055 MVT EVT = LN0->getMemoryVT(); 3056 if ((!AfterLegalize && !LN0->isVolatile()) || 3057 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3058 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3059 LN0->getBasePtr(), LN0->getSrcValue(), 3060 LN0->getSrcValueOffset(), EVT, 3061 LN0->isVolatile(), 3062 LN0->getAlignment()); 3063 CombineTo(N, ExtLoad); 3064 CombineTo(N0.getNode(), 3065 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3066 ExtLoad.getValue(1)); 3067 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3068 } 3069 } 3070 3071 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3072 if (N0.getOpcode() == ISD::SETCC) { 3073 SDValue SCC = 3074 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3075 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3076 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3077 if (SCC.getNode()) return SCC; 3078 } 3079 3080 return SDValue(); 3081} 3082 3083SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3084 SDValue N0 = N->getOperand(0); 3085 MVT VT = N->getValueType(0); 3086 3087 // fold (aext c1) -> c1 3088 if (isa<ConstantSDNode>(N0)) 3089 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3090 // fold (aext (aext x)) -> (aext x) 3091 // fold (aext (zext x)) -> (zext x) 3092 // fold (aext (sext x)) -> (sext x) 3093 if (N0.getOpcode() == ISD::ANY_EXTEND || 3094 N0.getOpcode() == ISD::ZERO_EXTEND || 3095 N0.getOpcode() == ISD::SIGN_EXTEND) 3096 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3097 3098 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3099 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3100 if (N0.getOpcode() == ISD::TRUNCATE) { 3101 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3102 if (NarrowLoad.getNode()) { 3103 if (NarrowLoad.getNode() != N0.getNode()) 3104 CombineTo(N0.getNode(), NarrowLoad); 3105 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3106 } 3107 } 3108 3109 // fold (aext (truncate x)) 3110 if (N0.getOpcode() == ISD::TRUNCATE) { 3111 SDValue TruncOp = N0.getOperand(0); 3112 if (TruncOp.getValueType() == VT) 3113 return TruncOp; // x iff x size == zext size. 3114 if (TruncOp.getValueType().bitsGT(VT)) 3115 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3116 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3117 } 3118 3119 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3120 if (N0.getOpcode() == ISD::AND && 3121 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3122 N0.getOperand(1).getOpcode() == ISD::Constant) { 3123 SDValue X = N0.getOperand(0).getOperand(0); 3124 if (X.getValueType().bitsLT(VT)) { 3125 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3126 } else if (X.getValueType().bitsGT(VT)) { 3127 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3128 } 3129 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3130 Mask.zext(VT.getSizeInBits()); 3131 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3132 } 3133 3134 // fold (aext (load x)) -> (aext (truncate (extload x))) 3135 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3136 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3137 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3138 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3139 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3140 LN0->getBasePtr(), LN0->getSrcValue(), 3141 LN0->getSrcValueOffset(), 3142 N0.getValueType(), 3143 LN0->isVolatile(), 3144 LN0->getAlignment()); 3145 CombineTo(N, ExtLoad); 3146 // Redirect any chain users to the new load. 3147 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3148 SDValue(ExtLoad.getNode(), 1)); 3149 // If any node needs the original loaded value, recompute it. 3150 if (!LN0->use_empty()) 3151 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3152 ExtLoad.getValue(1)); 3153 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3154 } 3155 3156 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3157 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3158 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3159 if (N0.getOpcode() == ISD::LOAD && 3160 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3161 N0.hasOneUse()) { 3162 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3163 MVT EVT = LN0->getMemoryVT(); 3164 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3165 LN0->getChain(), LN0->getBasePtr(), 3166 LN0->getSrcValue(), 3167 LN0->getSrcValueOffset(), EVT, 3168 LN0->isVolatile(), 3169 LN0->getAlignment()); 3170 CombineTo(N, ExtLoad); 3171 CombineTo(N0.getNode(), 3172 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3173 ExtLoad.getValue(1)); 3174 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3175 } 3176 3177 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3178 if (N0.getOpcode() == ISD::SETCC) { 3179 SDValue SCC = 3180 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3181 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3182 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3183 if (SCC.getNode()) 3184 return SCC; 3185 } 3186 3187 return SDValue(); 3188} 3189 3190/// GetDemandedBits - See if the specified operand can be simplified with the 3191/// knowledge that only the bits specified by Mask are used. If so, return the 3192/// simpler operand, otherwise return a null SDValue. 3193SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3194 switch (V.getOpcode()) { 3195 default: break; 3196 case ISD::OR: 3197 case ISD::XOR: 3198 // If the LHS or RHS don't contribute bits to the or, drop them. 3199 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3200 return V.getOperand(1); 3201 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3202 return V.getOperand(0); 3203 break; 3204 case ISD::SRL: 3205 // Only look at single-use SRLs. 3206 if (!V.getNode()->hasOneUse()) 3207 break; 3208 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3209 // See if we can recursively simplify the LHS. 3210 unsigned Amt = RHSC->getZExtValue(); 3211 APInt NewMask = Mask << Amt; 3212 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3213 if (SimplifyLHS.getNode()) { 3214 return DAG.getNode(ISD::SRL, V.getValueType(), 3215 SimplifyLHS, V.getOperand(1)); 3216 } 3217 } 3218 } 3219 return SDValue(); 3220} 3221 3222/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3223/// bits and then truncated to a narrower type and where N is a multiple 3224/// of number of bits of the narrower type, transform it to a narrower load 3225/// from address + N / num of bits of new type. If the result is to be 3226/// extended, also fold the extension to form a extending load. 3227SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3228 unsigned Opc = N->getOpcode(); 3229 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3230 SDValue N0 = N->getOperand(0); 3231 MVT VT = N->getValueType(0); 3232 MVT EVT = N->getValueType(0); 3233 3234 // This transformation isn't valid for vector loads. 3235 if (VT.isVector()) 3236 return SDValue(); 3237 3238 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3239 // extended to VT. 3240 if (Opc == ISD::SIGN_EXTEND_INREG) { 3241 ExtType = ISD::SEXTLOAD; 3242 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3243 if (AfterLegalize && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3244 return SDValue(); 3245 } 3246 3247 unsigned EVTBits = EVT.getSizeInBits(); 3248 unsigned ShAmt = 0; 3249 bool CombineSRL = false; 3250 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3251 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3252 ShAmt = N01->getZExtValue(); 3253 // Is the shift amount a multiple of size of VT? 3254 if ((ShAmt & (EVTBits-1)) == 0) { 3255 N0 = N0.getOperand(0); 3256 if (N0.getValueType().getSizeInBits() <= EVTBits) 3257 return SDValue(); 3258 CombineSRL = true; 3259 } 3260 } 3261 } 3262 3263 // Do not generate loads of non-round integer types since these can 3264 // be expensive (and would be wrong if the type is not byte sized). 3265 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3266 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3267 // Do not change the width of a volatile load. 3268 !cast<LoadSDNode>(N0)->isVolatile()) { 3269 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3270 MVT PtrType = N0.getOperand(1).getValueType(); 3271 // For big endian targets, we need to adjust the offset to the pointer to 3272 // load the correct bytes. 3273 if (TLI.isBigEndian()) { 3274 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3275 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3276 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3277 } 3278 uint64_t PtrOff = ShAmt / 8; 3279 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3280 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3281 DAG.getConstant(PtrOff, PtrType)); 3282 AddToWorkList(NewPtr.getNode()); 3283 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3284 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3285 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3286 LN0->isVolatile(), NewAlign) 3287 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3288 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3289 EVT, LN0->isVolatile(), NewAlign); 3290 AddToWorkList(N); 3291 if (CombineSRL) { 3292 WorkListRemover DeadNodes(*this); 3293 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3294 &DeadNodes); 3295 CombineTo(N->getOperand(0).getNode(), Load); 3296 } else 3297 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3298 if (ShAmt) { 3299 if (Opc == ISD::SIGN_EXTEND_INREG) 3300 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3301 else 3302 return DAG.getNode(Opc, VT, Load); 3303 } 3304 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3305 } 3306 3307 return SDValue(); 3308} 3309 3310 3311SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3312 SDValue N0 = N->getOperand(0); 3313 SDValue N1 = N->getOperand(1); 3314 MVT VT = N->getValueType(0); 3315 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3316 unsigned VTBits = VT.getSizeInBits(); 3317 unsigned EVTBits = EVT.getSizeInBits(); 3318 3319 // fold (sext_in_reg c1) -> c1 3320 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3321 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3322 3323 // If the input is already sign extended, just drop the extension. 3324 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3325 return N0; 3326 3327 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3328 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3329 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3330 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3331 } 3332 3333 // fold (sext_in_reg (sext x)) -> (sext x) 3334 // fold (sext_in_reg (aext x)) -> (sext x) 3335 // if x is small enough. 3336 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3337 SDValue N00 = N0.getOperand(0); 3338 if (N00.getValueType().getSizeInBits() < EVTBits) 3339 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3340 } 3341 3342 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3343 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3344 return DAG.getZeroExtendInReg(N0, EVT); 3345 3346 // fold operands of sext_in_reg based on knowledge that the top bits are not 3347 // demanded. 3348 if (SimplifyDemandedBits(SDValue(N, 0))) 3349 return SDValue(N, 0); 3350 3351 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3352 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3353 SDValue NarrowLoad = ReduceLoadWidth(N); 3354 if (NarrowLoad.getNode()) 3355 return NarrowLoad; 3356 3357 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3358 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3359 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3360 if (N0.getOpcode() == ISD::SRL) { 3361 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3362 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3363 // We can turn this into an SRA iff the input to the SRL is already sign 3364 // extended enough. 3365 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3366 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3367 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3368 } 3369 } 3370 3371 // fold (sext_inreg (extload x)) -> (sextload x) 3372 if (ISD::isEXTLoad(N0.getNode()) && 3373 ISD::isUNINDEXEDLoad(N0.getNode()) && 3374 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3375 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3376 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3377 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3378 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3379 LN0->getBasePtr(), LN0->getSrcValue(), 3380 LN0->getSrcValueOffset(), EVT, 3381 LN0->isVolatile(), 3382 LN0->getAlignment()); 3383 CombineTo(N, ExtLoad); 3384 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3385 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3386 } 3387 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3388 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3389 N0.hasOneUse() && 3390 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3391 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3392 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3393 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3394 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3395 LN0->getBasePtr(), LN0->getSrcValue(), 3396 LN0->getSrcValueOffset(), EVT, 3397 LN0->isVolatile(), 3398 LN0->getAlignment()); 3399 CombineTo(N, ExtLoad); 3400 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3401 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3402 } 3403 return SDValue(); 3404} 3405 3406SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3407 SDValue N0 = N->getOperand(0); 3408 MVT VT = N->getValueType(0); 3409 3410 // noop truncate 3411 if (N0.getValueType() == N->getValueType(0)) 3412 return N0; 3413 // fold (truncate c1) -> c1 3414 if (isa<ConstantSDNode>(N0)) 3415 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3416 // fold (truncate (truncate x)) -> (truncate x) 3417 if (N0.getOpcode() == ISD::TRUNCATE) 3418 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3419 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3420 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3421 N0.getOpcode() == ISD::ANY_EXTEND) { 3422 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3423 // if the source is smaller than the dest, we still need an extend 3424 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3425 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3426 // if the source is larger than the dest, than we just need the truncate 3427 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3428 else 3429 // if the source and dest are the same type, we can drop both the extend 3430 // and the truncate 3431 return N0.getOperand(0); 3432 } 3433 3434 // See if we can simplify the input to this truncate through knowledge that 3435 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3436 // -> trunc y 3437 SDValue Shorter = 3438 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3439 VT.getSizeInBits())); 3440 if (Shorter.getNode()) 3441 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3442 3443 // fold (truncate (load x)) -> (smaller load x) 3444 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3445 return ReduceLoadWidth(N); 3446} 3447 3448static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3449 SDValue Elt = N->getOperand(i); 3450 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3451 return Elt.getNode(); 3452 return Elt.getOperand(Elt.getResNo()).getNode(); 3453} 3454 3455/// CombineConsecutiveLoads - build_pair (load, load) -> load 3456/// if load locations are consecutive. 3457SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3458 assert(N->getOpcode() == ISD::BUILD_PAIR); 3459 3460 SDNode *LD1 = getBuildPairElt(N, 0); 3461 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3462 return SDValue(); 3463 MVT LD1VT = LD1->getValueType(0); 3464 SDNode *LD2 = getBuildPairElt(N, 1); 3465 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3466 if (ISD::isNON_EXTLoad(LD2) && 3467 LD2->hasOneUse() && 3468 // If both are volatile this would reduce the number of volatile loads. 3469 // If one is volatile it might be ok, but play conservative and bail out. 3470 !cast<LoadSDNode>(LD1)->isVolatile() && 3471 !cast<LoadSDNode>(LD2)->isVolatile() && 3472 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3473 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3474 unsigned Align = LD->getAlignment(); 3475 unsigned NewAlign = TLI.getTargetData()-> 3476 getABITypeAlignment(VT.getTypeForMVT()); 3477 if (NewAlign <= Align && 3478 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3479 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3480 LD->getSrcValue(), LD->getSrcValueOffset(), 3481 false, Align); 3482 } 3483 return SDValue(); 3484} 3485 3486SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3487 SDValue N0 = N->getOperand(0); 3488 MVT VT = N->getValueType(0); 3489 3490 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3491 // Only do this before legalize, since afterward the target may be depending 3492 // on the bitconvert. 3493 // First check to see if this is all constant. 3494 if (!AfterLegalize && 3495 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3496 VT.isVector()) { 3497 bool isSimple = true; 3498 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3499 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3500 N0.getOperand(i).getOpcode() != ISD::Constant && 3501 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3502 isSimple = false; 3503 break; 3504 } 3505 3506 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3507 assert(!DestEltVT.isVector() && 3508 "Element type of vector ValueType must not be vector!"); 3509 if (isSimple) { 3510 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3511 } 3512 } 3513 3514 // If the input is a constant, let getNode fold it. 3515 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3516 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3517 if (Res.getNode() != N) return Res; 3518 } 3519 3520 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3521 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3522 3523 // fold (conv (load x)) -> (load (conv*)x) 3524 // If the resultant load doesn't need a higher alignment than the original! 3525 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3526 // Do not change the width of a volatile load. 3527 !cast<LoadSDNode>(N0)->isVolatile() && 3528 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3529 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3530 unsigned Align = TLI.getTargetData()-> 3531 getABITypeAlignment(VT.getTypeForMVT()); 3532 unsigned OrigAlign = LN0->getAlignment(); 3533 if (Align <= OrigAlign) { 3534 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3535 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3536 LN0->isVolatile(), OrigAlign); 3537 AddToWorkList(N); 3538 CombineTo(N0.getNode(), 3539 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3540 Load.getValue(1)); 3541 return Load; 3542 } 3543 } 3544 3545 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3546 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3547 // This often reduces constant pool loads. 3548 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3549 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3550 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3551 AddToWorkList(NewConv.getNode()); 3552 3553 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3554 if (N0.getOpcode() == ISD::FNEG) 3555 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3556 assert(N0.getOpcode() == ISD::FABS); 3557 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3558 } 3559 3560 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3561 // Note that we don't handle copysign(x,cst) because this can always be folded 3562 // to an fneg or fabs. 3563 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3564 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3565 VT.isInteger() && !VT.isVector()) { 3566 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3567 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3568 MVT::getIntegerVT(OrigXWidth), 3569 N0.getOperand(1)); 3570 AddToWorkList(X.getNode()); 3571 3572 // If X has a different width than the result/lhs, sext it or truncate it. 3573 unsigned VTWidth = VT.getSizeInBits(); 3574 if (OrigXWidth < VTWidth) { 3575 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3576 AddToWorkList(X.getNode()); 3577 } else if (OrigXWidth > VTWidth) { 3578 // To get the sign bit in the right place, we have to shift it right 3579 // before truncating. 3580 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3581 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3582 AddToWorkList(X.getNode()); 3583 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3584 AddToWorkList(X.getNode()); 3585 } 3586 3587 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3588 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3589 AddToWorkList(X.getNode()); 3590 3591 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3592 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3593 AddToWorkList(Cst.getNode()); 3594 3595 return DAG.getNode(ISD::OR, VT, X, Cst); 3596 } 3597 3598 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3599 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3600 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3601 if (CombineLD.getNode()) 3602 return CombineLD; 3603 } 3604 3605 return SDValue(); 3606} 3607 3608SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3609 MVT VT = N->getValueType(0); 3610 return CombineConsecutiveLoads(N, VT); 3611} 3612 3613/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3614/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3615/// destination element value type. 3616SDValue DAGCombiner:: 3617ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3618 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3619 3620 // If this is already the right type, we're done. 3621 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3622 3623 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3624 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3625 3626 // If this is a conversion of N elements of one type to N elements of another 3627 // type, convert each element. This handles FP<->INT cases. 3628 if (SrcBitSize == DstBitSize) { 3629 SmallVector<SDValue, 8> Ops; 3630 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3631 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3632 AddToWorkList(Ops.back().getNode()); 3633 } 3634 MVT VT = MVT::getVectorVT(DstEltVT, 3635 BV->getValueType(0).getVectorNumElements()); 3636 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3637 } 3638 3639 // Otherwise, we're growing or shrinking the elements. To avoid having to 3640 // handle annoying details of growing/shrinking FP values, we convert them to 3641 // int first. 3642 if (SrcEltVT.isFloatingPoint()) { 3643 // Convert the input float vector to a int vector where the elements are the 3644 // same sizes. 3645 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3646 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3647 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3648 SrcEltVT = IntVT; 3649 } 3650 3651 // Now we know the input is an integer vector. If the output is a FP type, 3652 // convert to integer first, then to FP of the right size. 3653 if (DstEltVT.isFloatingPoint()) { 3654 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3655 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3656 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3657 3658 // Next, convert to FP elements of the same size. 3659 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3660 } 3661 3662 // Okay, we know the src/dst types are both integers of differing types. 3663 // Handling growing first. 3664 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3665 if (SrcBitSize < DstBitSize) { 3666 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3667 3668 SmallVector<SDValue, 8> Ops; 3669 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3670 i += NumInputsPerOutput) { 3671 bool isLE = TLI.isLittleEndian(); 3672 APInt NewBits = APInt(DstBitSize, 0); 3673 bool EltIsUndef = true; 3674 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3675 // Shift the previously computed bits over. 3676 NewBits <<= SrcBitSize; 3677 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3678 if (Op.getOpcode() == ISD::UNDEF) continue; 3679 EltIsUndef = false; 3680 3681 NewBits |= 3682 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3683 } 3684 3685 if (EltIsUndef) 3686 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3687 else 3688 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3689 } 3690 3691 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3692 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3693 } 3694 3695 // Finally, this must be the case where we are shrinking elements: each input 3696 // turns into multiple outputs. 3697 bool isS2V = ISD::isScalarToVector(BV); 3698 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3699 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3700 SmallVector<SDValue, 8> Ops; 3701 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3702 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3703 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3704 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3705 continue; 3706 } 3707 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3708 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3709 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3710 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3711 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3712 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3713 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3714 OpVal = OpVal.lshr(DstBitSize); 3715 } 3716 3717 // For big endian targets, swap the order of the pieces of each element. 3718 if (TLI.isBigEndian()) 3719 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3720 } 3721 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3722} 3723 3724 3725 3726SDValue DAGCombiner::visitFADD(SDNode *N) { 3727 SDValue N0 = N->getOperand(0); 3728 SDValue N1 = N->getOperand(1); 3729 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3730 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3731 MVT VT = N->getValueType(0); 3732 3733 // fold vector ops 3734 if (VT.isVector()) { 3735 SDValue FoldedVOp = SimplifyVBinOp(N); 3736 if (FoldedVOp.getNode()) return FoldedVOp; 3737 } 3738 3739 // fold (fadd c1, c2) -> c1+c2 3740 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3741 return DAG.getNode(ISD::FADD, VT, N0, N1); 3742 // canonicalize constant to RHS 3743 if (N0CFP && !N1CFP) 3744 return DAG.getNode(ISD::FADD, VT, N1, N0); 3745 // fold (A + (-B)) -> A-B 3746 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3747 return DAG.getNode(ISD::FSUB, VT, N0, 3748 GetNegatedExpression(N1, DAG, AfterLegalize)); 3749 // fold ((-A) + B) -> B-A 3750 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3751 return DAG.getNode(ISD::FSUB, VT, N1, 3752 GetNegatedExpression(N0, DAG, AfterLegalize)); 3753 3754 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3755 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3756 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3757 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3758 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3759 3760 return SDValue(); 3761} 3762 3763SDValue DAGCombiner::visitFSUB(SDNode *N) { 3764 SDValue N0 = N->getOperand(0); 3765 SDValue N1 = N->getOperand(1); 3766 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3767 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3768 MVT VT = N->getValueType(0); 3769 3770 // fold vector ops 3771 if (VT.isVector()) { 3772 SDValue FoldedVOp = SimplifyVBinOp(N); 3773 if (FoldedVOp.getNode()) return FoldedVOp; 3774 } 3775 3776 // fold (fsub c1, c2) -> c1-c2 3777 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3778 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3779 // fold (0-B) -> -B 3780 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3781 if (isNegatibleForFree(N1, AfterLegalize)) 3782 return GetNegatedExpression(N1, DAG, AfterLegalize); 3783 return DAG.getNode(ISD::FNEG, VT, N1); 3784 } 3785 // fold (A-(-B)) -> A+B 3786 if (isNegatibleForFree(N1, AfterLegalize)) 3787 return DAG.getNode(ISD::FADD, VT, N0, 3788 GetNegatedExpression(N1, DAG, AfterLegalize)); 3789 3790 return SDValue(); 3791} 3792 3793SDValue DAGCombiner::visitFMUL(SDNode *N) { 3794 SDValue N0 = N->getOperand(0); 3795 SDValue N1 = N->getOperand(1); 3796 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3797 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3798 MVT VT = N->getValueType(0); 3799 3800 // fold vector ops 3801 if (VT.isVector()) { 3802 SDValue FoldedVOp = SimplifyVBinOp(N); 3803 if (FoldedVOp.getNode()) return FoldedVOp; 3804 } 3805 3806 // fold (fmul c1, c2) -> c1*c2 3807 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3808 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3809 // canonicalize constant to RHS 3810 if (N0CFP && !N1CFP) 3811 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3812 // fold (fmul X, 2.0) -> (fadd X, X) 3813 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3814 return DAG.getNode(ISD::FADD, VT, N0, N0); 3815 // fold (fmul X, -1.0) -> (fneg X) 3816 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3817 return DAG.getNode(ISD::FNEG, VT, N0); 3818 3819 // -X * -Y -> X*Y 3820 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3821 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3822 // Both can be negated for free, check to see if at least one is cheaper 3823 // negated. 3824 if (LHSNeg == 2 || RHSNeg == 2) 3825 return DAG.getNode(ISD::FMUL, VT, 3826 GetNegatedExpression(N0, DAG, AfterLegalize), 3827 GetNegatedExpression(N1, DAG, AfterLegalize)); 3828 } 3829 } 3830 3831 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3832 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3833 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3834 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3835 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3836 3837 return SDValue(); 3838} 3839 3840SDValue DAGCombiner::visitFDIV(SDNode *N) { 3841 SDValue N0 = N->getOperand(0); 3842 SDValue N1 = N->getOperand(1); 3843 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3844 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3845 MVT VT = N->getValueType(0); 3846 3847 // fold vector ops 3848 if (VT.isVector()) { 3849 SDValue FoldedVOp = SimplifyVBinOp(N); 3850 if (FoldedVOp.getNode()) return FoldedVOp; 3851 } 3852 3853 // fold (fdiv c1, c2) -> c1/c2 3854 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3855 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3856 3857 3858 // -X / -Y -> X*Y 3859 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3860 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3861 // Both can be negated for free, check to see if at least one is cheaper 3862 // negated. 3863 if (LHSNeg == 2 || RHSNeg == 2) 3864 return DAG.getNode(ISD::FDIV, VT, 3865 GetNegatedExpression(N0, DAG, AfterLegalize), 3866 GetNegatedExpression(N1, DAG, AfterLegalize)); 3867 } 3868 } 3869 3870 return SDValue(); 3871} 3872 3873SDValue DAGCombiner::visitFREM(SDNode *N) { 3874 SDValue N0 = N->getOperand(0); 3875 SDValue N1 = N->getOperand(1); 3876 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3877 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3878 MVT VT = N->getValueType(0); 3879 3880 // fold (frem c1, c2) -> fmod(c1,c2) 3881 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3882 return DAG.getNode(ISD::FREM, VT, N0, N1); 3883 3884 return SDValue(); 3885} 3886 3887SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3888 SDValue N0 = N->getOperand(0); 3889 SDValue N1 = N->getOperand(1); 3890 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3891 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3892 MVT VT = N->getValueType(0); 3893 3894 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3895 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3896 3897 if (N1CFP) { 3898 const APFloat& V = N1CFP->getValueAPF(); 3899 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3900 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3901 if (!V.isNegative()) 3902 return DAG.getNode(ISD::FABS, VT, N0); 3903 else 3904 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3905 } 3906 3907 // copysign(fabs(x), y) -> copysign(x, y) 3908 // copysign(fneg(x), y) -> copysign(x, y) 3909 // copysign(copysign(x,z), y) -> copysign(x, y) 3910 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3911 N0.getOpcode() == ISD::FCOPYSIGN) 3912 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3913 3914 // copysign(x, abs(y)) -> abs(x) 3915 if (N1.getOpcode() == ISD::FABS) 3916 return DAG.getNode(ISD::FABS, VT, N0); 3917 3918 // copysign(x, copysign(y,z)) -> copysign(x, z) 3919 if (N1.getOpcode() == ISD::FCOPYSIGN) 3920 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3921 3922 // copysign(x, fp_extend(y)) -> copysign(x, y) 3923 // copysign(x, fp_round(y)) -> copysign(x, y) 3924 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3925 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3926 3927 return SDValue(); 3928} 3929 3930 3931 3932SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3933 SDValue N0 = N->getOperand(0); 3934 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3935 MVT VT = N->getValueType(0); 3936 MVT OpVT = N0.getValueType(); 3937 3938 // fold (sint_to_fp c1) -> c1fp 3939 if (N0C && OpVT != MVT::ppcf128) 3940 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3941 3942 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3943 // but UINT_TO_FP is legal on this target, try to convert. 3944 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3945 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3946 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3947 if (DAG.SignBitIsZero(N0)) 3948 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3949 } 3950 3951 3952 return SDValue(); 3953} 3954 3955SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3956 SDValue N0 = N->getOperand(0); 3957 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3958 MVT VT = N->getValueType(0); 3959 MVT OpVT = N0.getValueType(); 3960 3961 // fold (uint_to_fp c1) -> c1fp 3962 if (N0C && OpVT != MVT::ppcf128) 3963 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3964 3965 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3966 // but SINT_TO_FP is legal on this target, try to convert. 3967 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3968 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3969 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3970 if (DAG.SignBitIsZero(N0)) 3971 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3972 } 3973 3974 return SDValue(); 3975} 3976 3977SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3978 SDValue N0 = N->getOperand(0); 3979 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3980 MVT VT = N->getValueType(0); 3981 3982 // fold (fp_to_sint c1fp) -> c1 3983 if (N0CFP) 3984 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3985 return SDValue(); 3986} 3987 3988SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3989 SDValue N0 = N->getOperand(0); 3990 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3991 MVT VT = N->getValueType(0); 3992 3993 // fold (fp_to_uint c1fp) -> c1 3994 if (N0CFP && VT != MVT::ppcf128) 3995 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3996 return SDValue(); 3997} 3998 3999SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4000 SDValue N0 = N->getOperand(0); 4001 SDValue N1 = N->getOperand(1); 4002 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4003 MVT VT = N->getValueType(0); 4004 4005 // fold (fp_round c1fp) -> c1fp 4006 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4007 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4008 4009 // fold (fp_round (fp_extend x)) -> x 4010 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4011 return N0.getOperand(0); 4012 4013 // fold (fp_round (fp_round x)) -> (fp_round x) 4014 if (N0.getOpcode() == ISD::FP_ROUND) { 4015 // This is a value preserving truncation if both round's are. 4016 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4017 N0.getNode()->getConstantOperandVal(1) == 1; 4018 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4019 DAG.getIntPtrConstant(IsTrunc)); 4020 } 4021 4022 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4023 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4024 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4025 AddToWorkList(Tmp.getNode()); 4026 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4027 } 4028 4029 return SDValue(); 4030} 4031 4032SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4033 SDValue N0 = N->getOperand(0); 4034 MVT VT = N->getValueType(0); 4035 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4036 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4037 4038 // fold (fp_round_inreg c1fp) -> c1fp 4039 if (N0CFP) { 4040 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4041 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4042 } 4043 return SDValue(); 4044} 4045 4046SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4047 SDValue N0 = N->getOperand(0); 4048 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4049 MVT VT = N->getValueType(0); 4050 4051 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4052 if (N->hasOneUse() && 4053 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4054 return SDValue(); 4055 4056 // fold (fp_extend c1fp) -> c1fp 4057 if (N0CFP && VT != MVT::ppcf128) 4058 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4059 4060 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4061 // value of X. 4062 if (N0.getOpcode() == ISD::FP_ROUND 4063 && N0.getNode()->getConstantOperandVal(1) == 1) { 4064 SDValue In = N0.getOperand(0); 4065 if (In.getValueType() == VT) return In; 4066 if (VT.bitsLT(In.getValueType())) 4067 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4068 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4069 } 4070 4071 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4072 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4073 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 4074 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4075 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4076 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4077 LN0->getBasePtr(), LN0->getSrcValue(), 4078 LN0->getSrcValueOffset(), 4079 N0.getValueType(), 4080 LN0->isVolatile(), 4081 LN0->getAlignment()); 4082 CombineTo(N, ExtLoad); 4083 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4084 ExtLoad, DAG.getIntPtrConstant(1)), 4085 ExtLoad.getValue(1)); 4086 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4087 } 4088 4089 return SDValue(); 4090} 4091 4092SDValue DAGCombiner::visitFNEG(SDNode *N) { 4093 SDValue N0 = N->getOperand(0); 4094 4095 if (isNegatibleForFree(N0, AfterLegalize)) 4096 return GetNegatedExpression(N0, DAG, AfterLegalize); 4097 4098 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4099 // constant pool values. 4100 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4101 N0.getOperand(0).getValueType().isInteger() && 4102 !N0.getOperand(0).getValueType().isVector()) { 4103 SDValue Int = N0.getOperand(0); 4104 MVT IntVT = Int.getValueType(); 4105 if (IntVT.isInteger() && !IntVT.isVector()) { 4106 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4107 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4108 AddToWorkList(Int.getNode()); 4109 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4110 } 4111 } 4112 4113 return SDValue(); 4114} 4115 4116SDValue DAGCombiner::visitFABS(SDNode *N) { 4117 SDValue N0 = N->getOperand(0); 4118 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4119 MVT VT = N->getValueType(0); 4120 4121 // fold (fabs c1) -> fabs(c1) 4122 if (N0CFP && VT != MVT::ppcf128) 4123 return DAG.getNode(ISD::FABS, VT, N0); 4124 // fold (fabs (fabs x)) -> (fabs x) 4125 if (N0.getOpcode() == ISD::FABS) 4126 return N->getOperand(0); 4127 // fold (fabs (fneg x)) -> (fabs x) 4128 // fold (fabs (fcopysign x, y)) -> (fabs x) 4129 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4130 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4131 4132 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4133 // constant pool values. 4134 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4135 N0.getOperand(0).getValueType().isInteger() && 4136 !N0.getOperand(0).getValueType().isVector()) { 4137 SDValue Int = N0.getOperand(0); 4138 MVT IntVT = Int.getValueType(); 4139 if (IntVT.isInteger() && !IntVT.isVector()) { 4140 Int = DAG.getNode(ISD::AND, IntVT, Int, 4141 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4142 AddToWorkList(Int.getNode()); 4143 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4144 } 4145 } 4146 4147 return SDValue(); 4148} 4149 4150SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4151 SDValue Chain = N->getOperand(0); 4152 SDValue N1 = N->getOperand(1); 4153 SDValue N2 = N->getOperand(2); 4154 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4155 4156 // never taken branch, fold to chain 4157 if (N1C && N1C->isNullValue()) 4158 return Chain; 4159 // unconditional branch 4160 if (N1C && N1C->getAPIntValue() == 1) 4161 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4162 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4163 // on the target. 4164 if (N1.getOpcode() == ISD::SETCC && 4165 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4166 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4167 N1.getOperand(0), N1.getOperand(1), N2); 4168 } 4169 return SDValue(); 4170} 4171 4172// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4173// 4174SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4175 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4176 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4177 4178 // Use SimplifySetCC to simplify SETCC's. 4179 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4180 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4181 4182 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4183 4184 // fold br_cc true, dest -> br dest (unconditional branch) 4185 if (SCCC && !SCCC->isNullValue()) 4186 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4187 N->getOperand(4)); 4188 // fold br_cc false, dest -> unconditional fall through 4189 if (SCCC && SCCC->isNullValue()) 4190 return N->getOperand(0); 4191 4192 // fold to a simpler setcc 4193 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4194 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4195 Simp.getOperand(2), Simp.getOperand(0), 4196 Simp.getOperand(1), N->getOperand(4)); 4197 return SDValue(); 4198} 4199 4200 4201/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4202/// pre-indexed load / store when the base pointer is an add or subtract 4203/// and it has other uses besides the load / store. After the 4204/// transformation, the new indexed load / store has effectively folded 4205/// the add / subtract in and all of its other uses are redirected to the 4206/// new load / store. 4207bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4208 if (!AfterLegalize) 4209 return false; 4210 4211 bool isLoad = true; 4212 SDValue Ptr; 4213 MVT VT; 4214 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4215 if (LD->isIndexed()) 4216 return false; 4217 VT = LD->getMemoryVT(); 4218 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4219 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4220 return false; 4221 Ptr = LD->getBasePtr(); 4222 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4223 if (ST->isIndexed()) 4224 return false; 4225 VT = ST->getMemoryVT(); 4226 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4227 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4228 return false; 4229 Ptr = ST->getBasePtr(); 4230 isLoad = false; 4231 } else 4232 return false; 4233 4234 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4235 // out. There is no reason to make this a preinc/predec. 4236 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4237 Ptr.getNode()->hasOneUse()) 4238 return false; 4239 4240 // Ask the target to do addressing mode selection. 4241 SDValue BasePtr; 4242 SDValue Offset; 4243 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4244 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4245 return false; 4246 // Don't create a indexed load / store with zero offset. 4247 if (isa<ConstantSDNode>(Offset) && 4248 cast<ConstantSDNode>(Offset)->isNullValue()) 4249 return false; 4250 4251 // Try turning it into a pre-indexed load / store except when: 4252 // 1) The new base ptr is a frame index. 4253 // 2) If N is a store and the new base ptr is either the same as or is a 4254 // predecessor of the value being stored. 4255 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4256 // that would create a cycle. 4257 // 4) All uses are load / store ops that use it as old base ptr. 4258 4259 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4260 // (plus the implicit offset) to a register to preinc anyway. 4261 if (isa<FrameIndexSDNode>(BasePtr)) 4262 return false; 4263 4264 // Check #2. 4265 if (!isLoad) { 4266 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4267 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4268 return false; 4269 } 4270 4271 // Now check for #3 and #4. 4272 bool RealUse = false; 4273 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4274 E = Ptr.getNode()->use_end(); I != E; ++I) { 4275 SDNode *Use = *I; 4276 if (Use == N) 4277 continue; 4278 if (Use->isPredecessorOf(N)) 4279 return false; 4280 4281 if (!((Use->getOpcode() == ISD::LOAD && 4282 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4283 (Use->getOpcode() == ISD::STORE && 4284 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4285 RealUse = true; 4286 } 4287 if (!RealUse) 4288 return false; 4289 4290 SDValue Result; 4291 if (isLoad) 4292 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4293 else 4294 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4295 ++PreIndexedNodes; 4296 ++NodesCombined; 4297 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4298 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4299 DOUT << '\n'; 4300 WorkListRemover DeadNodes(*this); 4301 if (isLoad) { 4302 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4303 &DeadNodes); 4304 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4305 &DeadNodes); 4306 } else { 4307 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4308 &DeadNodes); 4309 } 4310 4311 // Finally, since the node is now dead, remove it from the graph. 4312 DAG.DeleteNode(N); 4313 4314 // Replace the uses of Ptr with uses of the updated base value. 4315 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4316 &DeadNodes); 4317 removeFromWorkList(Ptr.getNode()); 4318 DAG.DeleteNode(Ptr.getNode()); 4319 4320 return true; 4321} 4322 4323/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4324/// add / sub of the base pointer node into a post-indexed load / store. 4325/// The transformation folded the add / subtract into the new indexed 4326/// load / store effectively and all of its uses are redirected to the 4327/// new load / store. 4328bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4329 if (!AfterLegalize) 4330 return false; 4331 4332 bool isLoad = true; 4333 SDValue Ptr; 4334 MVT VT; 4335 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4336 if (LD->isIndexed()) 4337 return false; 4338 VT = LD->getMemoryVT(); 4339 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4340 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4341 return false; 4342 Ptr = LD->getBasePtr(); 4343 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4344 if (ST->isIndexed()) 4345 return false; 4346 VT = ST->getMemoryVT(); 4347 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4348 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4349 return false; 4350 Ptr = ST->getBasePtr(); 4351 isLoad = false; 4352 } else 4353 return false; 4354 4355 if (Ptr.getNode()->hasOneUse()) 4356 return false; 4357 4358 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4359 E = Ptr.getNode()->use_end(); I != E; ++I) { 4360 SDNode *Op = *I; 4361 if (Op == N || 4362 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4363 continue; 4364 4365 SDValue BasePtr; 4366 SDValue Offset; 4367 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4368 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4369 if (Ptr == Offset) 4370 std::swap(BasePtr, Offset); 4371 if (Ptr != BasePtr) 4372 continue; 4373 // Don't create a indexed load / store with zero offset. 4374 if (isa<ConstantSDNode>(Offset) && 4375 cast<ConstantSDNode>(Offset)->isNullValue()) 4376 continue; 4377 4378 // Try turning it into a post-indexed load / store except when 4379 // 1) All uses are load / store ops that use it as base ptr. 4380 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4381 // nor a successor of N. Otherwise, if Op is folded that would 4382 // create a cycle. 4383 4384 // Check for #1. 4385 bool TryNext = false; 4386 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4387 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4388 SDNode *Use = *II; 4389 if (Use == Ptr.getNode()) 4390 continue; 4391 4392 // If all the uses are load / store addresses, then don't do the 4393 // transformation. 4394 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4395 bool RealUse = false; 4396 for (SDNode::use_iterator III = Use->use_begin(), 4397 EEE = Use->use_end(); III != EEE; ++III) { 4398 SDNode *UseUse = *III; 4399 if (!((UseUse->getOpcode() == ISD::LOAD && 4400 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4401 (UseUse->getOpcode() == ISD::STORE && 4402 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4403 RealUse = true; 4404 } 4405 4406 if (!RealUse) { 4407 TryNext = true; 4408 break; 4409 } 4410 } 4411 } 4412 if (TryNext) 4413 continue; 4414 4415 // Check for #2 4416 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4417 SDValue Result = isLoad 4418 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4419 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4420 ++PostIndexedNodes; 4421 ++NodesCombined; 4422 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4423 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4424 DOUT << '\n'; 4425 WorkListRemover DeadNodes(*this); 4426 if (isLoad) { 4427 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4428 &DeadNodes); 4429 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4430 &DeadNodes); 4431 } else { 4432 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4433 &DeadNodes); 4434 } 4435 4436 // Finally, since the node is now dead, remove it from the graph. 4437 DAG.DeleteNode(N); 4438 4439 // Replace the uses of Use with uses of the updated base value. 4440 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4441 Result.getValue(isLoad ? 1 : 0), 4442 &DeadNodes); 4443 removeFromWorkList(Op); 4444 DAG.DeleteNode(Op); 4445 return true; 4446 } 4447 } 4448 } 4449 return false; 4450} 4451 4452/// InferAlignment - If we can infer some alignment information from this 4453/// pointer, return it. 4454static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4455 // If this is a direct reference to a stack slot, use information about the 4456 // stack slot's alignment. 4457 int FrameIdx = 1 << 31; 4458 int64_t FrameOffset = 0; 4459 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4460 FrameIdx = FI->getIndex(); 4461 } else if (Ptr.getOpcode() == ISD::ADD && 4462 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4463 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4464 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4465 FrameOffset = Ptr.getConstantOperandVal(1); 4466 } 4467 4468 if (FrameIdx != (1 << 31)) { 4469 // FIXME: Handle FI+CST. 4470 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4471 if (MFI.isFixedObjectIndex(FrameIdx)) { 4472 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4473 4474 // The alignment of the frame index can be determined from its offset from 4475 // the incoming frame position. If the frame object is at offset 32 and 4476 // the stack is guaranteed to be 16-byte aligned, then we know that the 4477 // object is 16-byte aligned. 4478 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4479 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4480 4481 // Finally, the frame object itself may have a known alignment. Factor 4482 // the alignment + offset into a new alignment. For example, if we know 4483 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4484 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4485 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4486 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4487 FrameOffset); 4488 return std::max(Align, FIInfoAlign); 4489 } 4490 } 4491 4492 return 0; 4493} 4494 4495SDValue DAGCombiner::visitLOAD(SDNode *N) { 4496 LoadSDNode *LD = cast<LoadSDNode>(N); 4497 SDValue Chain = LD->getChain(); 4498 SDValue Ptr = LD->getBasePtr(); 4499 4500 // Try to infer better alignment information than the load already has. 4501 if (!Fast && LD->isUnindexed()) { 4502 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4503 if (Align > LD->getAlignment()) 4504 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4505 Chain, Ptr, LD->getSrcValue(), 4506 LD->getSrcValueOffset(), LD->getMemoryVT(), 4507 LD->isVolatile(), Align); 4508 } 4509 } 4510 4511 4512 // If load is not volatile and there are no uses of the loaded value (and 4513 // the updated indexed value in case of indexed loads), change uses of the 4514 // chain value into uses of the chain input (i.e. delete the dead load). 4515 if (!LD->isVolatile()) { 4516 if (N->getValueType(1) == MVT::Other) { 4517 // Unindexed loads. 4518 if (N->hasNUsesOfValue(0, 0)) { 4519 // It's not safe to use the two value CombineTo variant here. e.g. 4520 // v1, chain2 = load chain1, loc 4521 // v2, chain3 = load chain2, loc 4522 // v3 = add v2, c 4523 // Now we replace use of chain2 with chain1. This makes the second load 4524 // isomorphic to the one we are deleting, and thus makes this load live. 4525 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4526 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4527 DOUT << "\n"; 4528 WorkListRemover DeadNodes(*this); 4529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4530 if (N->use_empty()) { 4531 removeFromWorkList(N); 4532 DAG.DeleteNode(N); 4533 } 4534 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4535 } 4536 } else { 4537 // Indexed loads. 4538 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4539 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4540 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4541 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4542 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4543 DOUT << " and 2 other values\n"; 4544 WorkListRemover DeadNodes(*this); 4545 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4546 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4547 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4548 &DeadNodes); 4549 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4550 removeFromWorkList(N); 4551 DAG.DeleteNode(N); 4552 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4553 } 4554 } 4555 } 4556 4557 // If this load is directly stored, replace the load value with the stored 4558 // value. 4559 // TODO: Handle store large -> read small portion. 4560 // TODO: Handle TRUNCSTORE/LOADEXT 4561 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4562 !LD->isVolatile()) { 4563 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4564 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4565 if (PrevST->getBasePtr() == Ptr && 4566 PrevST->getValue().getValueType() == N->getValueType(0)) 4567 return CombineTo(N, Chain.getOperand(1), Chain); 4568 } 4569 } 4570 4571 if (CombinerAA) { 4572 // Walk up chain skipping non-aliasing memory nodes. 4573 SDValue BetterChain = FindBetterChain(N, Chain); 4574 4575 // If there is a better chain. 4576 if (Chain != BetterChain) { 4577 SDValue ReplLoad; 4578 4579 // Replace the chain to void dependency. 4580 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4581 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4582 LD->getSrcValue(), LD->getSrcValueOffset(), 4583 LD->isVolatile(), LD->getAlignment()); 4584 } else { 4585 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4586 LD->getValueType(0), 4587 BetterChain, Ptr, LD->getSrcValue(), 4588 LD->getSrcValueOffset(), 4589 LD->getMemoryVT(), 4590 LD->isVolatile(), 4591 LD->getAlignment()); 4592 } 4593 4594 // Create token factor to keep old chain connected. 4595 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4596 Chain, ReplLoad.getValue(1)); 4597 4598 // Replace uses with load result and token factor. Don't add users 4599 // to work list. 4600 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4601 } 4602 } 4603 4604 // Try transforming N to an indexed load. 4605 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4606 return SDValue(N, 0); 4607 4608 return SDValue(); 4609} 4610 4611 4612SDValue DAGCombiner::visitSTORE(SDNode *N) { 4613 StoreSDNode *ST = cast<StoreSDNode>(N); 4614 SDValue Chain = ST->getChain(); 4615 SDValue Value = ST->getValue(); 4616 SDValue Ptr = ST->getBasePtr(); 4617 4618 // Try to infer better alignment information than the store already has. 4619 if (!Fast && ST->isUnindexed()) { 4620 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4621 if (Align > ST->getAlignment()) 4622 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4623 ST->getSrcValueOffset(), ST->getMemoryVT(), 4624 ST->isVolatile(), Align); 4625 } 4626 } 4627 4628 // If this is a store of a bit convert, store the input value if the 4629 // resultant store does not need a higher alignment than the original. 4630 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4631 ST->isUnindexed()) { 4632 unsigned Align = ST->getAlignment(); 4633 MVT SVT = Value.getOperand(0).getValueType(); 4634 unsigned OrigAlign = TLI.getTargetData()-> 4635 getABITypeAlignment(SVT.getTypeForMVT()); 4636 if (Align <= OrigAlign && 4637 ((!AfterLegalize && !ST->isVolatile()) || 4638 TLI.isOperationLegal(ISD::STORE, SVT))) 4639 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4640 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4641 } 4642 4643 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4644 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4645 // NOTE: If the original store is volatile, this transform must not increase 4646 // the number of stores. For example, on x86-32 an f64 can be stored in one 4647 // processor operation but an i64 (which is not legal) requires two. So the 4648 // transform should not be done in this case. 4649 if (Value.getOpcode() != ISD::TargetConstantFP) { 4650 SDValue Tmp; 4651 switch (CFP->getValueType(0).getSimpleVT()) { 4652 default: assert(0 && "Unknown FP type"); 4653 case MVT::f80: // We don't do this for these yet. 4654 case MVT::f128: 4655 case MVT::ppcf128: 4656 break; 4657 case MVT::f32: 4658 if ((!AfterLegalize && !ST->isVolatile()) || 4659 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4660 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4661 bitcastToAPInt().getZExtValue(), MVT::i32); 4662 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4663 ST->getSrcValueOffset(), ST->isVolatile(), 4664 ST->getAlignment()); 4665 } 4666 break; 4667 case MVT::f64: 4668 if ((!AfterLegalize && !ST->isVolatile()) || 4669 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4670 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4671 getZExtValue(), MVT::i64); 4672 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4673 ST->getSrcValueOffset(), ST->isVolatile(), 4674 ST->getAlignment()); 4675 } else if (!ST->isVolatile() && 4676 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4677 // Many FP stores are not made apparent until after legalize, e.g. for 4678 // argument passing. Since this is so common, custom legalize the 4679 // 64-bit integer store into two 32-bit stores. 4680 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4681 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4682 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4683 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4684 4685 int SVOffset = ST->getSrcValueOffset(); 4686 unsigned Alignment = ST->getAlignment(); 4687 bool isVolatile = ST->isVolatile(); 4688 4689 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4690 ST->getSrcValueOffset(), 4691 isVolatile, ST->getAlignment()); 4692 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4693 DAG.getConstant(4, Ptr.getValueType())); 4694 SVOffset += 4; 4695 Alignment = MinAlign(Alignment, 4U); 4696 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4697 SVOffset, isVolatile, Alignment); 4698 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4699 } 4700 break; 4701 } 4702 } 4703 } 4704 4705 if (CombinerAA) { 4706 // Walk up chain skipping non-aliasing memory nodes. 4707 SDValue BetterChain = FindBetterChain(N, Chain); 4708 4709 // If there is a better chain. 4710 if (Chain != BetterChain) { 4711 // Replace the chain to avoid dependency. 4712 SDValue ReplStore; 4713 if (ST->isTruncatingStore()) { 4714 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4715 ST->getSrcValue(),ST->getSrcValueOffset(), 4716 ST->getMemoryVT(), 4717 ST->isVolatile(), ST->getAlignment()); 4718 } else { 4719 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4720 ST->getSrcValue(), ST->getSrcValueOffset(), 4721 ST->isVolatile(), ST->getAlignment()); 4722 } 4723 4724 // Create token to keep both nodes around. 4725 SDValue Token = 4726 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4727 4728 // Don't add users to work list. 4729 return CombineTo(N, Token, false); 4730 } 4731 } 4732 4733 // Try transforming N to an indexed store. 4734 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4735 return SDValue(N, 0); 4736 4737 // FIXME: is there such a thing as a truncating indexed store? 4738 if (ST->isTruncatingStore() && ST->isUnindexed() && 4739 Value.getValueType().isInteger()) { 4740 // See if we can simplify the input to this truncstore with knowledge that 4741 // only the low bits are being used. For example: 4742 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4743 SDValue Shorter = 4744 GetDemandedBits(Value, 4745 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4746 ST->getMemoryVT().getSizeInBits())); 4747 AddToWorkList(Value.getNode()); 4748 if (Shorter.getNode()) 4749 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4750 ST->getSrcValueOffset(), ST->getMemoryVT(), 4751 ST->isVolatile(), ST->getAlignment()); 4752 4753 // Otherwise, see if we can simplify the operation with 4754 // SimplifyDemandedBits, which only works if the value has a single use. 4755 if (SimplifyDemandedBits(Value, 4756 APInt::getLowBitsSet( 4757 Value.getValueSizeInBits(), 4758 ST->getMemoryVT().getSizeInBits()))) 4759 return SDValue(N, 0); 4760 } 4761 4762 // If this is a load followed by a store to the same location, then the store 4763 // is dead/noop. 4764 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4765 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4766 ST->isUnindexed() && !ST->isVolatile() && 4767 // There can't be any side effects between the load and store, such as 4768 // a call or store. 4769 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4770 // The store is dead, remove it. 4771 return Chain; 4772 } 4773 } 4774 4775 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4776 // truncating store. We can do this even if this is already a truncstore. 4777 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4778 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4779 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4780 ST->getMemoryVT())) { 4781 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4782 ST->getSrcValueOffset(), ST->getMemoryVT(), 4783 ST->isVolatile(), ST->getAlignment()); 4784 } 4785 4786 return SDValue(); 4787} 4788 4789SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4790 SDValue InVec = N->getOperand(0); 4791 SDValue InVal = N->getOperand(1); 4792 SDValue EltNo = N->getOperand(2); 4793 4794 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4795 // vector with the inserted element. 4796 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4797 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4798 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4799 InVec.getNode()->op_end()); 4800 if (Elt < Ops.size()) 4801 Ops[Elt] = InVal; 4802 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4803 &Ops[0], Ops.size()); 4804 } 4805 4806 return SDValue(); 4807} 4808 4809SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4810 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4811 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4812 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4813 4814 // Perform only after legalization to ensure build_vector / vector_shuffle 4815 // optimizations have already been done. 4816 if (!AfterLegalize) return SDValue(); 4817 4818 SDValue InVec = N->getOperand(0); 4819 SDValue EltNo = N->getOperand(1); 4820 4821 if (isa<ConstantSDNode>(EltNo)) { 4822 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4823 bool NewLoad = false; 4824 MVT VT = InVec.getValueType(); 4825 MVT EVT = VT.getVectorElementType(); 4826 MVT LVT = EVT; 4827 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4828 MVT BCVT = InVec.getOperand(0).getValueType(); 4829 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4830 return SDValue(); 4831 InVec = InVec.getOperand(0); 4832 EVT = BCVT.getVectorElementType(); 4833 NewLoad = true; 4834 } 4835 4836 LoadSDNode *LN0 = NULL; 4837 if (ISD::isNormalLoad(InVec.getNode())) 4838 LN0 = cast<LoadSDNode>(InVec); 4839 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4840 InVec.getOperand(0).getValueType() == EVT && 4841 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4842 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4843 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4844 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4845 // => 4846 // (load $addr+1*size) 4847 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4848 getOperand(Elt))->getZExtValue(); 4849 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4850 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4851 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4852 InVec = InVec.getOperand(0); 4853 if (ISD::isNormalLoad(InVec.getNode())) { 4854 LN0 = cast<LoadSDNode>(InVec); 4855 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4856 } 4857 } 4858 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4859 return SDValue(); 4860 4861 unsigned Align = LN0->getAlignment(); 4862 if (NewLoad) { 4863 // Check the resultant load doesn't need a higher alignment than the 4864 // original load. 4865 unsigned NewAlign = TLI.getTargetData()-> 4866 getABITypeAlignment(LVT.getTypeForMVT()); 4867 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4868 return SDValue(); 4869 Align = NewAlign; 4870 } 4871 4872 SDValue NewPtr = LN0->getBasePtr(); 4873 if (Elt) { 4874 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4875 MVT PtrType = NewPtr.getValueType(); 4876 if (TLI.isBigEndian()) 4877 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4878 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4879 DAG.getConstant(PtrOff, PtrType)); 4880 } 4881 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4882 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4883 LN0->isVolatile(), Align); 4884 } 4885 return SDValue(); 4886} 4887 4888 4889SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4890 unsigned NumInScalars = N->getNumOperands(); 4891 MVT VT = N->getValueType(0); 4892 unsigned NumElts = VT.getVectorNumElements(); 4893 MVT EltType = VT.getVectorElementType(); 4894 4895 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4896 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4897 // at most two distinct vectors, turn this into a shuffle node. 4898 SDValue VecIn1, VecIn2; 4899 for (unsigned i = 0; i != NumInScalars; ++i) { 4900 // Ignore undef inputs. 4901 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4902 4903 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4904 // constant index, bail out. 4905 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4906 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4907 VecIn1 = VecIn2 = SDValue(0, 0); 4908 break; 4909 } 4910 4911 // If the input vector type disagrees with the result of the build_vector, 4912 // we can't make a shuffle. 4913 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4914 if (ExtractedFromVec.getValueType() != VT) { 4915 VecIn1 = VecIn2 = SDValue(0, 0); 4916 break; 4917 } 4918 4919 // Otherwise, remember this. We allow up to two distinct input vectors. 4920 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4921 continue; 4922 4923 if (VecIn1.getNode() == 0) { 4924 VecIn1 = ExtractedFromVec; 4925 } else if (VecIn2.getNode() == 0) { 4926 VecIn2 = ExtractedFromVec; 4927 } else { 4928 // Too many inputs. 4929 VecIn1 = VecIn2 = SDValue(0, 0); 4930 break; 4931 } 4932 } 4933 4934 // If everything is good, we can make a shuffle operation. 4935 if (VecIn1.getNode()) { 4936 SmallVector<SDValue, 8> BuildVecIndices; 4937 for (unsigned i = 0; i != NumInScalars; ++i) { 4938 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4939 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4940 continue; 4941 } 4942 4943 SDValue Extract = N->getOperand(i); 4944 4945 // If extracting from the first vector, just use the index directly. 4946 if (Extract.getOperand(0) == VecIn1) { 4947 BuildVecIndices.push_back(Extract.getOperand(1)); 4948 continue; 4949 } 4950 4951 // Otherwise, use InIdx + VecSize 4952 unsigned Idx = 4953 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4954 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4955 } 4956 4957 // Add count and size info. 4958 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4959 4960 // Return the new VECTOR_SHUFFLE node. 4961 SDValue Ops[5]; 4962 Ops[0] = VecIn1; 4963 if (VecIn2.getNode()) { 4964 Ops[1] = VecIn2; 4965 } else { 4966 // Use an undef build_vector as input for the second operand. 4967 std::vector<SDValue> UnOps(NumInScalars, 4968 DAG.getNode(ISD::UNDEF, 4969 EltType)); 4970 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4971 &UnOps[0], UnOps.size()); 4972 AddToWorkList(Ops[1].getNode()); 4973 } 4974 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4975 &BuildVecIndices[0], BuildVecIndices.size()); 4976 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4977 } 4978 4979 return SDValue(); 4980} 4981 4982SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4983 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4984 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4985 // inputs come from at most two distinct vectors, turn this into a shuffle 4986 // node. 4987 4988 // If we only have one input vector, we don't need to do any concatenation. 4989 if (N->getNumOperands() == 1) { 4990 return N->getOperand(0); 4991 } 4992 4993 return SDValue(); 4994} 4995 4996SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4997 SDValue ShufMask = N->getOperand(2); 4998 unsigned NumElts = ShufMask.getNumOperands(); 4999 5000 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5001 bool isIdentity = true; 5002 for (unsigned i = 0; i != NumElts; ++i) { 5003 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5004 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5005 isIdentity = false; 5006 break; 5007 } 5008 } 5009 if (isIdentity) return N->getOperand(0); 5010 5011 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5012 isIdentity = true; 5013 for (unsigned i = 0; i != NumElts; ++i) { 5014 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5015 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5016 i+NumElts) { 5017 isIdentity = false; 5018 break; 5019 } 5020 } 5021 if (isIdentity) return N->getOperand(1); 5022 5023 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5024 // needed at all. 5025 bool isUnary = true; 5026 bool isSplat = true; 5027 int VecNum = -1; 5028 unsigned BaseIdx = 0; 5029 for (unsigned i = 0; i != NumElts; ++i) 5030 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5031 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5032 int V = (Idx < NumElts) ? 0 : 1; 5033 if (VecNum == -1) { 5034 VecNum = V; 5035 BaseIdx = Idx; 5036 } else { 5037 if (BaseIdx != Idx) 5038 isSplat = false; 5039 if (VecNum != V) { 5040 isUnary = false; 5041 break; 5042 } 5043 } 5044 } 5045 5046 SDValue N0 = N->getOperand(0); 5047 SDValue N1 = N->getOperand(1); 5048 // Normalize unary shuffle so the RHS is undef. 5049 if (isUnary && VecNum == 1) 5050 std::swap(N0, N1); 5051 5052 // If it is a splat, check if the argument vector is a build_vector with 5053 // all scalar elements the same. 5054 if (isSplat) { 5055 SDNode *V = N0.getNode(); 5056 5057 // If this is a bit convert that changes the element type of the vector but 5058 // not the number of vector elements, look through it. Be careful not to 5059 // look though conversions that change things like v4f32 to v2f64. 5060 if (V->getOpcode() == ISD::BIT_CONVERT) { 5061 SDValue ConvInput = V->getOperand(0); 5062 if (ConvInput.getValueType().isVector() && 5063 ConvInput.getValueType().getVectorNumElements() == NumElts) 5064 V = ConvInput.getNode(); 5065 } 5066 5067 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5068 unsigned NumElems = V->getNumOperands(); 5069 if (NumElems > BaseIdx) { 5070 SDValue Base; 5071 bool AllSame = true; 5072 for (unsigned i = 0; i != NumElems; ++i) { 5073 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5074 Base = V->getOperand(i); 5075 break; 5076 } 5077 } 5078 // Splat of <u, u, u, u>, return <u, u, u, u> 5079 if (!Base.getNode()) 5080 return N0; 5081 for (unsigned i = 0; i != NumElems; ++i) { 5082 if (V->getOperand(i) != Base) { 5083 AllSame = false; 5084 break; 5085 } 5086 } 5087 // Splat of <x, x, x, x>, return <x, x, x, x> 5088 if (AllSame) 5089 return N0; 5090 } 5091 } 5092 } 5093 5094 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5095 // into an undef. 5096 if (isUnary || N0 == N1) { 5097 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5098 // first operand. 5099 SmallVector<SDValue, 8> MappedOps; 5100 for (unsigned i = 0; i != NumElts; ++i) { 5101 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5102 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5103 NumElts) { 5104 MappedOps.push_back(ShufMask.getOperand(i)); 5105 } else { 5106 unsigned NewIdx = 5107 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5108 NumElts; 5109 MappedOps.push_back(DAG.getConstant(NewIdx, 5110 ShufMask.getOperand(i).getValueType())); 5111 } 5112 } 5113 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5114 &MappedOps[0], MappedOps.size()); 5115 AddToWorkList(ShufMask.getNode()); 5116 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5117 N0, 5118 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5119 ShufMask); 5120 } 5121 5122 return SDValue(); 5123} 5124 5125/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5126/// an AND to a vector_shuffle with the destination vector and a zero vector. 5127/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5128/// vector_shuffle V, Zero, <0, 4, 2, 4> 5129SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5130 SDValue LHS = N->getOperand(0); 5131 SDValue RHS = N->getOperand(1); 5132 if (N->getOpcode() == ISD::AND) { 5133 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5134 RHS = RHS.getOperand(0); 5135 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5136 std::vector<SDValue> IdxOps; 5137 unsigned NumOps = RHS.getNumOperands(); 5138 unsigned NumElts = NumOps; 5139 for (unsigned i = 0; i != NumElts; ++i) { 5140 SDValue Elt = RHS.getOperand(i); 5141 if (!isa<ConstantSDNode>(Elt)) 5142 return SDValue(); 5143 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5144 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5145 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5146 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5147 else 5148 return SDValue(); 5149 } 5150 5151 // Let's see if the target supports this vector_shuffle. 5152 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5153 return SDValue(); 5154 5155 // Return the new VECTOR_SHUFFLE node. 5156 MVT EVT = RHS.getValueType().getVectorElementType(); 5157 MVT VT = MVT::getVectorVT(EVT, NumElts); 5158 std::vector<SDValue> Ops; 5159 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5160 Ops.push_back(LHS); 5161 AddToWorkList(LHS.getNode()); 5162 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5163 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5164 &ZeroOps[0], ZeroOps.size())); 5165 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5166 &IdxOps[0], IdxOps.size())); 5167 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5168 &Ops[0], Ops.size()); 5169 if (VT != N->getValueType(0)) 5170 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5171 return Result; 5172 } 5173 } 5174 return SDValue(); 5175} 5176 5177/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5178SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5179 // After legalize, the target may be depending on adds and other 5180 // binary ops to provide legal ways to construct constants or other 5181 // things. Simplifying them may result in a loss of legality. 5182 if (AfterLegalize) return SDValue(); 5183 5184 MVT VT = N->getValueType(0); 5185 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5186 5187 MVT EltType = VT.getVectorElementType(); 5188 SDValue LHS = N->getOperand(0); 5189 SDValue RHS = N->getOperand(1); 5190 SDValue Shuffle = XformToShuffleWithZero(N); 5191 if (Shuffle.getNode()) return Shuffle; 5192 5193 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5194 // this operation. 5195 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5196 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5197 SmallVector<SDValue, 8> Ops; 5198 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5199 SDValue LHSOp = LHS.getOperand(i); 5200 SDValue RHSOp = RHS.getOperand(i); 5201 // If these two elements can't be folded, bail out. 5202 if ((LHSOp.getOpcode() != ISD::UNDEF && 5203 LHSOp.getOpcode() != ISD::Constant && 5204 LHSOp.getOpcode() != ISD::ConstantFP) || 5205 (RHSOp.getOpcode() != ISD::UNDEF && 5206 RHSOp.getOpcode() != ISD::Constant && 5207 RHSOp.getOpcode() != ISD::ConstantFP)) 5208 break; 5209 // Can't fold divide by zero. 5210 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5211 N->getOpcode() == ISD::FDIV) { 5212 if ((RHSOp.getOpcode() == ISD::Constant && 5213 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5214 (RHSOp.getOpcode() == ISD::ConstantFP && 5215 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5216 break; 5217 } 5218 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5219 AddToWorkList(Ops.back().getNode()); 5220 assert((Ops.back().getOpcode() == ISD::UNDEF || 5221 Ops.back().getOpcode() == ISD::Constant || 5222 Ops.back().getOpcode() == ISD::ConstantFP) && 5223 "Scalar binop didn't fold!"); 5224 } 5225 5226 if (Ops.size() == LHS.getNumOperands()) { 5227 MVT VT = LHS.getValueType(); 5228 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5229 } 5230 } 5231 5232 return SDValue(); 5233} 5234 5235SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5236 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5237 5238 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5239 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5240 // If we got a simplified select_cc node back from SimplifySelectCC, then 5241 // break it down into a new SETCC node, and a new SELECT node, and then return 5242 // the SELECT node, since we were called with a SELECT node. 5243 if (SCC.getNode()) { 5244 // Check to see if we got a select_cc back (to turn into setcc/select). 5245 // Otherwise, just return whatever node we got back, like fabs. 5246 if (SCC.getOpcode() == ISD::SELECT_CC) { 5247 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5248 SCC.getOperand(0), SCC.getOperand(1), 5249 SCC.getOperand(4)); 5250 AddToWorkList(SETCC.getNode()); 5251 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5252 SCC.getOperand(3), SETCC); 5253 } 5254 return SCC; 5255 } 5256 return SDValue(); 5257} 5258 5259/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5260/// are the two values being selected between, see if we can simplify the 5261/// select. Callers of this should assume that TheSelect is deleted if this 5262/// returns true. As such, they should return the appropriate thing (e.g. the 5263/// node) back to the top-level of the DAG combiner loop to avoid it being 5264/// looked at. 5265/// 5266bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5267 SDValue RHS) { 5268 5269 // If this is a select from two identical things, try to pull the operation 5270 // through the select. 5271 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5272 // If this is a load and the token chain is identical, replace the select 5273 // of two loads with a load through a select of the address to load from. 5274 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5275 // constants have been dropped into the constant pool. 5276 if (LHS.getOpcode() == ISD::LOAD && 5277 // Do not let this transformation reduce the number of volatile loads. 5278 !cast<LoadSDNode>(LHS)->isVolatile() && 5279 !cast<LoadSDNode>(RHS)->isVolatile() && 5280 // Token chains must be identical. 5281 LHS.getOperand(0) == RHS.getOperand(0)) { 5282 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5283 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5284 5285 // If this is an EXTLOAD, the VT's must match. 5286 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5287 // FIXME: this conflates two src values, discarding one. This is not 5288 // the right thing to do, but nothing uses srcvalues now. When they do, 5289 // turn SrcValue into a list of locations. 5290 SDValue Addr; 5291 if (TheSelect->getOpcode() == ISD::SELECT) { 5292 // Check that the condition doesn't reach either load. If so, folding 5293 // this will induce a cycle into the DAG. 5294 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5295 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5296 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5297 TheSelect->getOperand(0), LLD->getBasePtr(), 5298 RLD->getBasePtr()); 5299 } 5300 } else { 5301 // Check that the condition doesn't reach either load. If so, folding 5302 // this will induce a cycle into the DAG. 5303 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5304 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5305 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5306 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5307 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5308 TheSelect->getOperand(0), 5309 TheSelect->getOperand(1), 5310 LLD->getBasePtr(), RLD->getBasePtr(), 5311 TheSelect->getOperand(4)); 5312 } 5313 } 5314 5315 if (Addr.getNode()) { 5316 SDValue Load; 5317 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5318 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5319 Addr,LLD->getSrcValue(), 5320 LLD->getSrcValueOffset(), 5321 LLD->isVolatile(), 5322 LLD->getAlignment()); 5323 else { 5324 Load = DAG.getExtLoad(LLD->getExtensionType(), 5325 TheSelect->getValueType(0), 5326 LLD->getChain(), Addr, LLD->getSrcValue(), 5327 LLD->getSrcValueOffset(), 5328 LLD->getMemoryVT(), 5329 LLD->isVolatile(), 5330 LLD->getAlignment()); 5331 } 5332 // Users of the select now use the result of the load. 5333 CombineTo(TheSelect, Load); 5334 5335 // Users of the old loads now use the new load's chain. We know the 5336 // old-load value is dead now. 5337 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5338 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5339 return true; 5340 } 5341 } 5342 } 5343 } 5344 5345 return false; 5346} 5347 5348SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5349 SDValue N2, SDValue N3, 5350 ISD::CondCode CC, bool NotExtCompare) { 5351 5352 MVT VT = N2.getValueType(); 5353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5354 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5355 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5356 5357 // Determine if the condition we're dealing with is constant 5358 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5359 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5360 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5361 5362 // fold select_cc true, x, y -> x 5363 if (SCCC && !SCCC->isNullValue()) 5364 return N2; 5365 // fold select_cc false, x, y -> y 5366 if (SCCC && SCCC->isNullValue()) 5367 return N3; 5368 5369 // Check to see if we can simplify the select into an fabs node 5370 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5371 // Allow either -0.0 or 0.0 5372 if (CFP->getValueAPF().isZero()) { 5373 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5374 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5375 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5376 N2 == N3.getOperand(0)) 5377 return DAG.getNode(ISD::FABS, VT, N0); 5378 5379 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5380 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5381 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5382 N2.getOperand(0) == N3) 5383 return DAG.getNode(ISD::FABS, VT, N3); 5384 } 5385 } 5386 5387 // Check to see if we can perform the "gzip trick", transforming 5388 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5389 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5390 N0.getValueType().isInteger() && 5391 N2.getValueType().isInteger() && 5392 (N1C->isNullValue() || // (a < 0) ? b : 0 5393 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5394 MVT XType = N0.getValueType(); 5395 MVT AType = N2.getValueType(); 5396 if (XType.bitsGE(AType)) { 5397 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5398 // single-bit constant. 5399 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5400 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5401 ShCtV = XType.getSizeInBits()-ShCtV-1; 5402 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5403 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5404 AddToWorkList(Shift.getNode()); 5405 if (XType.bitsGT(AType)) { 5406 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5407 AddToWorkList(Shift.getNode()); 5408 } 5409 return DAG.getNode(ISD::AND, AType, Shift, N2); 5410 } 5411 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5412 DAG.getConstant(XType.getSizeInBits()-1, 5413 TLI.getShiftAmountTy())); 5414 AddToWorkList(Shift.getNode()); 5415 if (XType.bitsGT(AType)) { 5416 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5417 AddToWorkList(Shift.getNode()); 5418 } 5419 return DAG.getNode(ISD::AND, AType, Shift, N2); 5420 } 5421 } 5422 5423 // fold select C, 16, 0 -> shl C, 4 5424 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5425 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5426 5427 // If the caller doesn't want us to simplify this into a zext of a compare, 5428 // don't do it. 5429 if (NotExtCompare && N2C->getAPIntValue() == 1) 5430 return SDValue(); 5431 5432 // Get a SetCC of the condition 5433 // FIXME: Should probably make sure that setcc is legal if we ever have a 5434 // target where it isn't. 5435 SDValue Temp, SCC; 5436 // cast from setcc result type to select result type 5437 if (AfterLegalize) { 5438 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5439 if (N2.getValueType().bitsLT(SCC.getValueType())) 5440 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5441 else 5442 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5443 } else { 5444 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5445 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5446 } 5447 AddToWorkList(SCC.getNode()); 5448 AddToWorkList(Temp.getNode()); 5449 5450 if (N2C->getAPIntValue() == 1) 5451 return Temp; 5452 // shl setcc result by log2 n2c 5453 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5454 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5455 TLI.getShiftAmountTy())); 5456 } 5457 5458 // Check to see if this is the equivalent of setcc 5459 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5460 // otherwise, go ahead with the folds. 5461 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5462 MVT XType = N0.getValueType(); 5463 if (!AfterLegalize || 5464 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5465 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5466 if (Res.getValueType() != VT) 5467 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5468 return Res; 5469 } 5470 5471 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5472 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5473 (!AfterLegalize || 5474 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5475 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5476 return DAG.getNode(ISD::SRL, XType, Ctlz, 5477 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5478 TLI.getShiftAmountTy())); 5479 } 5480 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5481 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5482 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5483 N0); 5484 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5485 DAG.getConstant(~0ULL, XType)); 5486 return DAG.getNode(ISD::SRL, XType, 5487 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5488 DAG.getConstant(XType.getSizeInBits()-1, 5489 TLI.getShiftAmountTy())); 5490 } 5491 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5492 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5493 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5494 DAG.getConstant(XType.getSizeInBits()-1, 5495 TLI.getShiftAmountTy())); 5496 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5497 } 5498 } 5499 5500 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5501 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5502 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5503 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5504 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5505 MVT XType = N0.getValueType(); 5506 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5507 DAG.getConstant(XType.getSizeInBits()-1, 5508 TLI.getShiftAmountTy())); 5509 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5510 AddToWorkList(Shift.getNode()); 5511 AddToWorkList(Add.getNode()); 5512 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5513 } 5514 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5515 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5516 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5517 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5518 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5519 MVT XType = N0.getValueType(); 5520 if (SubC->isNullValue() && XType.isInteger()) { 5521 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5522 DAG.getConstant(XType.getSizeInBits()-1, 5523 TLI.getShiftAmountTy())); 5524 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5525 AddToWorkList(Shift.getNode()); 5526 AddToWorkList(Add.getNode()); 5527 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5528 } 5529 } 5530 } 5531 5532 return SDValue(); 5533} 5534 5535/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5536SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5537 SDValue N1, ISD::CondCode Cond, 5538 bool foldBooleans) { 5539 TargetLowering::DAGCombinerInfo 5540 DagCombineInfo(DAG, !AfterLegalize, false, this); 5541 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5542} 5543 5544/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5545/// return a DAG expression to select that will generate the same value by 5546/// multiplying by a magic number. See: 5547/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5548SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5549 std::vector<SDNode*> Built; 5550 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5551 5552 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5553 ii != ee; ++ii) 5554 AddToWorkList(*ii); 5555 return S; 5556} 5557 5558/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5559/// return a DAG expression to select that will generate the same value by 5560/// multiplying by a magic number. See: 5561/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5562SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5563 std::vector<SDNode*> Built; 5564 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5565 5566 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5567 ii != ee; ++ii) 5568 AddToWorkList(*ii); 5569 return S; 5570} 5571 5572/// FindBaseOffset - Return true if base is known not to alias with anything 5573/// but itself. Provides base object and offset as results. 5574static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5575 // Assume it is a primitive operation. 5576 Base = Ptr; Offset = 0; 5577 5578 // If it's an adding a simple constant then integrate the offset. 5579 if (Base.getOpcode() == ISD::ADD) { 5580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5581 Base = Base.getOperand(0); 5582 Offset += C->getZExtValue(); 5583 } 5584 } 5585 5586 // If it's any of the following then it can't alias with anything but itself. 5587 return isa<FrameIndexSDNode>(Base) || 5588 isa<ConstantPoolSDNode>(Base) || 5589 isa<GlobalAddressSDNode>(Base); 5590} 5591 5592/// isAlias - Return true if there is any possibility that the two addresses 5593/// overlap. 5594bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5595 const Value *SrcValue1, int SrcValueOffset1, 5596 SDValue Ptr2, int64_t Size2, 5597 const Value *SrcValue2, int SrcValueOffset2) 5598{ 5599 // If they are the same then they must be aliases. 5600 if (Ptr1 == Ptr2) return true; 5601 5602 // Gather base node and offset information. 5603 SDValue Base1, Base2; 5604 int64_t Offset1, Offset2; 5605 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5606 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5607 5608 // If they have a same base address then... 5609 if (Base1 == Base2) { 5610 // Check to see if the addresses overlap. 5611 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5612 } 5613 5614 // If we know both bases then they can't alias. 5615 if (KnownBase1 && KnownBase2) return false; 5616 5617 if (CombinerGlobalAA) { 5618 // Use alias analysis information. 5619 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5620 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5621 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5622 AliasAnalysis::AliasResult AAResult = 5623 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5624 if (AAResult == AliasAnalysis::NoAlias) 5625 return false; 5626 } 5627 5628 // Otherwise we have to assume they alias. 5629 return true; 5630} 5631 5632/// FindAliasInfo - Extracts the relevant alias information from the memory 5633/// node. Returns true if the operand was a load. 5634bool DAGCombiner::FindAliasInfo(SDNode *N, 5635 SDValue &Ptr, int64_t &Size, 5636 const Value *&SrcValue, int &SrcValueOffset) { 5637 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5638 Ptr = LD->getBasePtr(); 5639 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5640 SrcValue = LD->getSrcValue(); 5641 SrcValueOffset = LD->getSrcValueOffset(); 5642 return true; 5643 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5644 Ptr = ST->getBasePtr(); 5645 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5646 SrcValue = ST->getSrcValue(); 5647 SrcValueOffset = ST->getSrcValueOffset(); 5648 } else { 5649 assert(0 && "FindAliasInfo expected a memory operand"); 5650 } 5651 5652 return false; 5653} 5654 5655/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5656/// looking for aliasing nodes and adding them to the Aliases vector. 5657void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5658 SmallVector<SDValue, 8> &Aliases) { 5659 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5660 std::set<SDNode *> Visited; // Visited node set. 5661 5662 // Get alias information for node. 5663 SDValue Ptr; 5664 int64_t Size; 5665 const Value *SrcValue; 5666 int SrcValueOffset; 5667 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5668 5669 // Starting off. 5670 Chains.push_back(OriginalChain); 5671 5672 // Look at each chain and determine if it is an alias. If so, add it to the 5673 // aliases list. If not, then continue up the chain looking for the next 5674 // candidate. 5675 while (!Chains.empty()) { 5676 SDValue Chain = Chains.back(); 5677 Chains.pop_back(); 5678 5679 // Don't bother if we've been before. 5680 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5681 Visited.insert(Chain.getNode()); 5682 5683 switch (Chain.getOpcode()) { 5684 case ISD::EntryToken: 5685 // Entry token is ideal chain operand, but handled in FindBetterChain. 5686 break; 5687 5688 case ISD::LOAD: 5689 case ISD::STORE: { 5690 // Get alias information for Chain. 5691 SDValue OpPtr; 5692 int64_t OpSize; 5693 const Value *OpSrcValue; 5694 int OpSrcValueOffset; 5695 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5696 OpSrcValue, OpSrcValueOffset); 5697 5698 // If chain is alias then stop here. 5699 if (!(IsLoad && IsOpLoad) && 5700 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5701 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5702 Aliases.push_back(Chain); 5703 } else { 5704 // Look further up the chain. 5705 Chains.push_back(Chain.getOperand(0)); 5706 // Clean up old chain. 5707 AddToWorkList(Chain.getNode()); 5708 } 5709 break; 5710 } 5711 5712 case ISD::TokenFactor: 5713 // We have to check each of the operands of the token factor, so we queue 5714 // then up. Adding the operands to the queue (stack) in reverse order 5715 // maintains the original order and increases the likelihood that getNode 5716 // will find a matching token factor (CSE.) 5717 for (unsigned n = Chain.getNumOperands(); n;) 5718 Chains.push_back(Chain.getOperand(--n)); 5719 // Eliminate the token factor if we can. 5720 AddToWorkList(Chain.getNode()); 5721 break; 5722 5723 default: 5724 // For all other instructions we will just have to take what we can get. 5725 Aliases.push_back(Chain); 5726 break; 5727 } 5728 } 5729} 5730 5731/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5732/// for a better chain (aliasing node.) 5733SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5734 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5735 5736 // Accumulate all the aliases to this node. 5737 GatherAllAliases(N, OldChain, Aliases); 5738 5739 if (Aliases.size() == 0) { 5740 // If no operands then chain to entry token. 5741 return DAG.getEntryNode(); 5742 } else if (Aliases.size() == 1) { 5743 // If a single operand then chain to it. We don't need to revisit it. 5744 return Aliases[0]; 5745 } 5746 5747 // Construct a custom tailored token factor. 5748 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5749 &Aliases[0], Aliases.size()); 5750 5751 // Make sure the old chain gets cleaned up. 5752 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5753 5754 return NewChain; 5755} 5756 5757// SelectionDAG::Combine - This is the entry point for the file. 5758// 5759void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5760 bool Fast) { 5761 /// run - This is the main entry point to this class. 5762 /// 5763 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5764} 5765