DAGCombiner.cpp revision 765784ad760ee6cc504d79e4966c272387c313f8
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: (select C, load A, load B) -> load (select C, A, B) 26// FIXME: Dead stores -> nuke 27// FIXME: shr X, (and Y,31) -> shr X, Y 28// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller) 29// FIXME: mul (x, const) -> shifts + adds 30// FIXME: undef values 31// FIXME: make truncate see through SIGN_EXTEND and AND 32// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 33// FIXME: verify that getNode can't return extends with an operand whose type 34// is >= to that of the extend. 35// FIXME: divide by zero is currently left unfolded. do we want to turn this 36// into an undef? 37// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 38// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "dagcombine" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/MathExtras.h" 47#include "llvm/Target/TargetLowering.h" 48#include <algorithm> 49#include <cmath> 50using namespace llvm; 51 52namespace { 53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 54 55 class DAGCombiner { 56 SelectionDAG &DAG; 57 TargetLowering &TLI; 58 bool AfterLegalize; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 /// AddUsersToWorkList - When an instruction is simplified, add all users of 64 /// the instruction to the work lists because they might get more simplified 65 /// now. 66 /// 67 void AddUsersToWorkList(SDNode *N) { 68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 69 UI != UE; ++UI) 70 WorkList.push_back(*UI); 71 } 72 73 /// removeFromWorkList - remove all instances of N from the worklist. 74 void removeFromWorkList(SDNode *N) { 75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 76 WorkList.end()); 77 } 78 79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 80 ++NodesCombined; 81 DEBUG(std::cerr << "\nReplacing "; N->dump(); 82 std::cerr << "\nWith: "; To[0].Val->dump(); 83 std::cerr << " and " << To.size()-1 << " other values\n"); 84 std::vector<SDNode*> NowDead; 85 DAG.ReplaceAllUsesWith(N, To, &NowDead); 86 87 // Push the new nodes and any users onto the worklist 88 for (unsigned i = 0, e = To.size(); i != e; ++i) { 89 WorkList.push_back(To[i].Val); 90 AddUsersToWorkList(To[i].Val); 91 } 92 93 // Nodes can end up on the worklist more than once. Make sure we do 94 // not process a node that has been replaced. 95 removeFromWorkList(N); 96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 97 removeFromWorkList(NowDead[i]); 98 99 // Finally, since the node is now dead, remove it from the graph. 100 DAG.DeleteNode(N); 101 return SDOperand(N, 0); 102 } 103 104 SDOperand CombineTo(SDNode *N, SDOperand Res) { 105 std::vector<SDOperand> To; 106 To.push_back(Res); 107 return CombineTo(N, To); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 111 std::vector<SDOperand> To; 112 To.push_back(Res0); 113 To.push_back(Res1); 114 return CombineTo(N, To); 115 } 116 117 /// visit - call the node-specific routine that knows how to fold each 118 /// particular type of node. 119 SDOperand visit(SDNode *N); 120 121 // Visitation implementation - Implement dag node combining for different 122 // node types. The semantics are as follows: 123 // Return Value: 124 // SDOperand.Val == 0 - No change was made 125 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 126 // otherwise - N should be replaced by the returned Operand. 127 // 128 SDOperand visitTokenFactor(SDNode *N); 129 SDOperand visitADD(SDNode *N); 130 SDOperand visitSUB(SDNode *N); 131 SDOperand visitMUL(SDNode *N); 132 SDOperand visitSDIV(SDNode *N); 133 SDOperand visitUDIV(SDNode *N); 134 SDOperand visitSREM(SDNode *N); 135 SDOperand visitUREM(SDNode *N); 136 SDOperand visitMULHU(SDNode *N); 137 SDOperand visitMULHS(SDNode *N); 138 SDOperand visitAND(SDNode *N); 139 SDOperand visitOR(SDNode *N); 140 SDOperand visitXOR(SDNode *N); 141 SDOperand visitSHL(SDNode *N); 142 SDOperand visitSRA(SDNode *N); 143 SDOperand visitSRL(SDNode *N); 144 SDOperand visitCTLZ(SDNode *N); 145 SDOperand visitCTTZ(SDNode *N); 146 SDOperand visitCTPOP(SDNode *N); 147 SDOperand visitSELECT(SDNode *N); 148 SDOperand visitSELECT_CC(SDNode *N); 149 SDOperand visitSETCC(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 178 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 179 SDOperand N3, ISD::CondCode CC); 180 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 181 ISD::CondCode Cond, bool foldBooleans = true); 182public: 183 DAGCombiner(SelectionDAG &D) 184 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 185 186 /// Run - runs the dag combiner on all nodes in the work list 187 void Run(bool RunningAfterLegalize); 188 }; 189} 190 191/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 192/// this predicate to simplify operations downstream. Op and Mask are known to 193/// be the same type. 194static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 195 const TargetLowering &TLI) { 196 unsigned SrcBits; 197 if (Mask == 0) return true; 198 199 // If we know the result of a setcc has the top bits zero, use this info. 200 switch (Op.getOpcode()) { 201 case ISD::Constant: 202 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 203 case ISD::SETCC: 204 return ((Mask & 1) == 0) && 205 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 206 case ISD::ZEXTLOAD: 207 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 208 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 209 case ISD::ZERO_EXTEND: 210 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 211 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 212 case ISD::AssertZext: 213 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 214 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 215 case ISD::AND: 216 // If either of the operands has zero bits, the result will too. 217 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 218 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 219 return true; 220 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 221 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 222 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 223 return false; 224 case ISD::OR: 225 case ISD::XOR: 226 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 227 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 228 case ISD::SELECT: 229 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 230 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 231 case ISD::SELECT_CC: 232 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 233 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 234 case ISD::SRL: 235 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 236 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 237 uint64_t NewVal = Mask << ShAmt->getValue(); 238 SrcBits = MVT::getSizeInBits(Op.getValueType()); 239 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 240 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 241 } 242 return false; 243 case ISD::SHL: 244 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 245 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 246 uint64_t NewVal = Mask >> ShAmt->getValue(); 247 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 248 } 249 return false; 250 case ISD::ADD: 251 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 252 if ((Mask&(Mask+1)) == 0) { // All low bits 253 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 254 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 255 return true; 256 } 257 break; 258 case ISD::SUB: 259 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 260 // We know that the top bits of C-X are clear if X contains less bits 261 // than C (i.e. no wrap-around can happen). For example, 20-X is 262 // positive if we can prove that X is >= 0 and < 16. 263 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 264 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 265 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 266 uint64_t MaskV = (1ULL << (63-NLZ))-1; 267 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 268 // High bits are clear this value is known to be >= C. 269 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 270 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 271 return true; 272 } 273 } 274 } 275 break; 276 case ISD::CTTZ: 277 case ISD::CTLZ: 278 case ISD::CTPOP: 279 // Bit counting instructions can not set the high bits of the result 280 // register. The max number of bits sets depends on the input. 281 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 282 default: break; 283 } 284 return false; 285} 286 287// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 288// that selects between the values 1 and 0, making it equivalent to a setcc. 289// Also, set the incoming LHS, RHS, and CC references to the appropriate 290// nodes based on the type of node we are checking. This simplifies life a 291// bit for the callers. 292static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 293 SDOperand &CC) { 294 if (N.getOpcode() == ISD::SETCC) { 295 LHS = N.getOperand(0); 296 RHS = N.getOperand(1); 297 CC = N.getOperand(2); 298 return true; 299 } 300 if (N.getOpcode() == ISD::SELECT_CC && 301 N.getOperand(2).getOpcode() == ISD::Constant && 302 N.getOperand(3).getOpcode() == ISD::Constant && 303 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 304 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 305 LHS = N.getOperand(0); 306 RHS = N.getOperand(1); 307 CC = N.getOperand(4); 308 return true; 309 } 310 return false; 311} 312 313// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 314// one use. If this is true, it allows the users to invert the operation for 315// free when it is profitable to do so. 316static bool isOneUseSetCC(SDOperand N) { 317 SDOperand N0, N1, N2; 318 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 319 return true; 320 return false; 321} 322 323// FIXME: This should probably go in the ISD class rather than being duplicated 324// in several files. 325static bool isCommutativeBinOp(unsigned Opcode) { 326 switch (Opcode) { 327 case ISD::ADD: 328 case ISD::MUL: 329 case ISD::AND: 330 case ISD::OR: 331 case ISD::XOR: return true; 332 default: return false; // FIXME: Need commutative info for user ops! 333 } 334} 335 336void DAGCombiner::Run(bool RunningAfterLegalize) { 337 // set the instance variable, so that the various visit routines may use it. 338 AfterLegalize = RunningAfterLegalize; 339 340 // Add all the dag nodes to the worklist. 341 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 342 343 // Create a dummy node (which is not added to allnodes), that adds a reference 344 // to the root node, preventing it from being deleted, and tracking any 345 // changes of the root. 346 HandleSDNode Dummy(DAG.getRoot()); 347 348 // while the worklist isn't empty, inspect the node on the end of it and 349 // try and combine it. 350 while (!WorkList.empty()) { 351 SDNode *N = WorkList.back(); 352 WorkList.pop_back(); 353 354 // If N has no uses, it is dead. Make sure to revisit all N's operands once 355 // N is deleted from the DAG, since they too may now be dead or may have a 356 // reduced number of uses, allowing other xforms. 357 if (N->use_empty() && N != &Dummy) { 358 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 359 WorkList.push_back(N->getOperand(i).Val); 360 361 removeFromWorkList(N); 362 DAG.DeleteNode(N); 363 continue; 364 } 365 366 SDOperand RV = visit(N); 367 if (RV.Val) { 368 ++NodesCombined; 369 // If we get back the same node we passed in, rather than a new node or 370 // zero, we know that the node must have defined multiple values and 371 // CombineTo was used. Since CombineTo takes care of the worklist 372 // mechanics for us, we have no work to do in this case. 373 if (RV.Val != N) { 374 DEBUG(std::cerr << "\nReplacing "; N->dump(); 375 std::cerr << "\nWith: "; RV.Val->dump(); 376 std::cerr << '\n'); 377 std::vector<SDNode*> NowDead; 378 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 379 380 // Push the new node and any users onto the worklist 381 WorkList.push_back(RV.Val); 382 AddUsersToWorkList(RV.Val); 383 384 // Nodes can end up on the worklist more than once. Make sure we do 385 // not process a node that has been replaced. 386 removeFromWorkList(N); 387 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 388 removeFromWorkList(NowDead[i]); 389 390 // Finally, since the node is now dead, remove it from the graph. 391 DAG.DeleteNode(N); 392 } 393 } 394 } 395 396 // If the root changed (e.g. it was a dead load, update the root). 397 DAG.setRoot(Dummy.getValue()); 398} 399 400SDOperand DAGCombiner::visit(SDNode *N) { 401 switch(N->getOpcode()) { 402 default: break; 403 case ISD::TokenFactor: return visitTokenFactor(N); 404 case ISD::ADD: return visitADD(N); 405 case ISD::SUB: return visitSUB(N); 406 case ISD::MUL: return visitMUL(N); 407 case ISD::SDIV: return visitSDIV(N); 408 case ISD::UDIV: return visitUDIV(N); 409 case ISD::SREM: return visitSREM(N); 410 case ISD::UREM: return visitUREM(N); 411 case ISD::MULHU: return visitMULHU(N); 412 case ISD::MULHS: return visitMULHS(N); 413 case ISD::AND: return visitAND(N); 414 case ISD::OR: return visitOR(N); 415 case ISD::XOR: return visitXOR(N); 416 case ISD::SHL: return visitSHL(N); 417 case ISD::SRA: return visitSRA(N); 418 case ISD::SRL: return visitSRL(N); 419 case ISD::CTLZ: return visitCTLZ(N); 420 case ISD::CTTZ: return visitCTTZ(N); 421 case ISD::CTPOP: return visitCTPOP(N); 422 case ISD::SELECT: return visitSELECT(N); 423 case ISD::SELECT_CC: return visitSELECT_CC(N); 424 case ISD::SETCC: return visitSETCC(N); 425 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 426 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 427 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 428 case ISD::TRUNCATE: return visitTRUNCATE(N); 429 case ISD::FADD: return visitFADD(N); 430 case ISD::FSUB: return visitFSUB(N); 431 case ISD::FMUL: return visitFMUL(N); 432 case ISD::FDIV: return visitFDIV(N); 433 case ISD::FREM: return visitFREM(N); 434 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 435 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 436 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 437 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 438 case ISD::FP_ROUND: return visitFP_ROUND(N); 439 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 440 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 441 case ISD::FNEG: return visitFNEG(N); 442 case ISD::FABS: return visitFABS(N); 443 case ISD::BRCOND: return visitBRCOND(N); 444 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 445 case ISD::BR_CC: return visitBR_CC(N); 446 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 447 case ISD::LOAD: return visitLOAD(N); 448 case ISD::STORE: return visitSTORE(N); 449 } 450 return SDOperand(); 451} 452 453SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 454 // If the token factor has two operands and one is the entry token, replace 455 // the token factor with the other operand. 456 if (N->getNumOperands() == 2) { 457 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 458 return N->getOperand(1); 459 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 460 return N->getOperand(0); 461 } 462 return SDOperand(); 463} 464 465SDOperand DAGCombiner::visitADD(SDNode *N) { 466 SDOperand N0 = N->getOperand(0); 467 SDOperand N1 = N->getOperand(1); 468 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 470 MVT::ValueType VT = N0.getValueType(); 471 472 // fold (add c1, c2) -> c1+c2 473 if (N0C && N1C) 474 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 475 // canonicalize constant to RHS 476 if (N0C && !N1C) { 477 std::swap(N0, N1); 478 std::swap(N0C, N1C); 479 } 480 // fold (add x, 0) -> x 481 if (N1C && N1C->isNullValue()) 482 return N0; 483 // fold (add (add x, c1), c2) -> (add x, c1+c2) 484 if (N1C && N0.getOpcode() == ISD::ADD) { 485 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 486 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 487 if (N00C) 488 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 489 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 490 if (N01C) 491 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 492 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 493 } 494 // fold ((0-A) + B) -> B-A 495 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 496 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 497 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 498 // fold (A + (0-B)) -> A-B 499 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 500 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 501 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 502 // fold (A+(B-A)) -> B 503 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 504 return N1.getOperand(0); 505 return SDOperand(); 506} 507 508SDOperand DAGCombiner::visitSUB(SDNode *N) { 509 SDOperand N0 = N->getOperand(0); 510 SDOperand N1 = N->getOperand(1); 511 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 512 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 513 514 // fold (sub c1, c2) -> c1-c2 515 if (N0C && N1C) 516 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 517 N->getValueType(0)); 518 // fold (sub x, c) -> (add x, -c) 519 if (N1C) 520 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 521 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 522 523 // fold (A+B)-A -> B 524 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 525 return N0.getOperand(1); 526 // fold (A+B)-B -> A 527 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 528 return N0.getOperand(0); 529 return SDOperand(); 530} 531 532SDOperand DAGCombiner::visitMUL(SDNode *N) { 533 SDOperand N0 = N->getOperand(0); 534 SDOperand N1 = N->getOperand(1); 535 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 536 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 537 MVT::ValueType VT = N0.getValueType(); 538 539 // fold (mul c1, c2) -> c1*c2 540 if (N0C && N1C) 541 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 542 N->getValueType(0)); 543 // canonicalize constant to RHS 544 if (N0C && !N1C) { 545 std::swap(N0, N1); 546 std::swap(N0C, N1C); 547 } 548 // fold (mul x, 0) -> 0 549 if (N1C && N1C->isNullValue()) 550 return N1; 551 // fold (mul x, -1) -> 0-x 552 if (N1C && N1C->isAllOnesValue()) 553 return DAG.getNode(ISD::SUB, N->getValueType(0), 554 DAG.getConstant(0, N->getValueType(0)), N0); 555 // fold (mul x, (1 << c)) -> x << c 556 if (N1C && isPowerOf2_64(N1C->getValue())) 557 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 558 DAG.getConstant(Log2_64(N1C->getValue()), 559 TLI.getShiftAmountTy())); 560 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 561 if (N1C && N0.getOpcode() == ISD::MUL) { 562 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 563 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 564 if (N00C) 565 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 566 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 567 if (N01C) 568 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 569 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 570 } 571 return SDOperand(); 572} 573 574SDOperand DAGCombiner::visitSDIV(SDNode *N) { 575 SDOperand N0 = N->getOperand(0); 576 SDOperand N1 = N->getOperand(1); 577 MVT::ValueType VT = N->getValueType(0); 578 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 580 581 // fold (sdiv c1, c2) -> c1/c2 582 if (N0C && N1C && !N1C->isNullValue()) 583 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 584 N->getValueType(0)); 585 // If we know the sign bits of both operands are zero, strength reduce to a 586 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 587 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 588 if (MaskedValueIsZero(N1, SignBit, TLI) && 589 MaskedValueIsZero(N0, SignBit, TLI)) 590 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 591 return SDOperand(); 592} 593 594SDOperand DAGCombiner::visitUDIV(SDNode *N) { 595 SDOperand N0 = N->getOperand(0); 596 SDOperand N1 = N->getOperand(1); 597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 599 600 // fold (udiv c1, c2) -> c1/c2 601 if (N0C && N1C && !N1C->isNullValue()) 602 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 603 N->getValueType(0)); 604 // fold (udiv x, (1 << c)) -> x >>u c 605 if (N1C && isPowerOf2_64(N1C->getValue())) 606 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 607 DAG.getConstant(Log2_64(N1C->getValue()), 608 TLI.getShiftAmountTy())); 609 return SDOperand(); 610} 611 612SDOperand DAGCombiner::visitSREM(SDNode *N) { 613 SDOperand N0 = N->getOperand(0); 614 SDOperand N1 = N->getOperand(1); 615 MVT::ValueType VT = N->getValueType(0); 616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 618 619 // fold (srem c1, c2) -> c1%c2 620 if (N0C && N1C && !N1C->isNullValue()) 621 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 622 N->getValueType(0)); 623 // If we know the sign bits of both operands are zero, strength reduce to a 624 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 625 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 626 if (MaskedValueIsZero(N1, SignBit, TLI) && 627 MaskedValueIsZero(N0, SignBit, TLI)) 628 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 629 return SDOperand(); 630} 631 632SDOperand DAGCombiner::visitUREM(SDNode *N) { 633 SDOperand N0 = N->getOperand(0); 634 SDOperand N1 = N->getOperand(1); 635 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 636 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 637 638 // fold (urem c1, c2) -> c1%c2 639 if (N0C && N1C && !N1C->isNullValue()) 640 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 641 N->getValueType(0)); 642 // fold (urem x, pow2) -> (and x, pow2-1) 643 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 644 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 645 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 646 return SDOperand(); 647} 648 649SDOperand DAGCombiner::visitMULHS(SDNode *N) { 650 SDOperand N0 = N->getOperand(0); 651 SDOperand N1 = N->getOperand(1); 652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 653 654 // fold (mulhs x, 0) -> 0 655 if (N1C && N1C->isNullValue()) 656 return N1; 657 // fold (mulhs x, 1) -> (sra x, size(x)-1) 658 if (N1C && N1C->getValue() == 1) 659 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 660 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 661 TLI.getShiftAmountTy())); 662 return SDOperand(); 663} 664 665SDOperand DAGCombiner::visitMULHU(SDNode *N) { 666 SDOperand N0 = N->getOperand(0); 667 SDOperand N1 = N->getOperand(1); 668 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 669 670 // fold (mulhu x, 0) -> 0 671 if (N1C && N1C->isNullValue()) 672 return N1; 673 // fold (mulhu x, 1) -> 0 674 if (N1C && N1C->getValue() == 1) 675 return DAG.getConstant(0, N0.getValueType()); 676 return SDOperand(); 677} 678 679SDOperand DAGCombiner::visitAND(SDNode *N) { 680 SDOperand N0 = N->getOperand(0); 681 SDOperand N1 = N->getOperand(1); 682 SDOperand LL, LR, RL, RR, CC0, CC1; 683 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 685 MVT::ValueType VT = N1.getValueType(); 686 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 687 688 // fold (and c1, c2) -> c1&c2 689 if (N0C && N1C) 690 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 691 // canonicalize constant to RHS 692 if (N0C && !N1C) { 693 std::swap(N0, N1); 694 std::swap(N0C, N1C); 695 } 696 // fold (and x, -1) -> x 697 if (N1C && N1C->isAllOnesValue()) 698 return N0; 699 // if (and x, c) is known to be zero, return 0 700 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 701 return DAG.getConstant(0, VT); 702 // fold (and x, c) -> x iff (x & ~c) == 0 703 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 704 TLI)) 705 return N0; 706 // fold (and (and x, c1), c2) -> (and x, c1^c2) 707 if (N1C && N0.getOpcode() == ISD::AND) { 708 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 709 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 710 if (N00C) 711 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 712 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 713 if (N01C) 714 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 715 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 716 } 717 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 718 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 719 unsigned ExtendBits = 720 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 721 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 722 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 723 } 724 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 725 if (N0.getOpcode() == ISD::OR && N1C) 726 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 727 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 728 return N1; 729 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 730 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 731 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 732 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 733 734 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 735 MVT::isInteger(LL.getValueType())) { 736 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 737 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 738 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 739 WorkList.push_back(ORNode.Val); 740 return DAG.getSetCC(VT, ORNode, LR, Op1); 741 } 742 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 743 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 744 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 745 WorkList.push_back(ANDNode.Val); 746 return DAG.getSetCC(VT, ANDNode, LR, Op1); 747 } 748 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 749 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 750 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 751 WorkList.push_back(ORNode.Val); 752 return DAG.getSetCC(VT, ORNode, LR, Op1); 753 } 754 } 755 // canonicalize equivalent to ll == rl 756 if (LL == RR && LR == RL) { 757 Op1 = ISD::getSetCCSwappedOperands(Op1); 758 std::swap(RL, RR); 759 } 760 if (LL == RL && LR == RR) { 761 bool isInteger = MVT::isInteger(LL.getValueType()); 762 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 763 if (Result != ISD::SETCC_INVALID) 764 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 765 } 766 } 767 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 768 if (N0.getOpcode() == ISD::ZERO_EXTEND && 769 N1.getOpcode() == ISD::ZERO_EXTEND && 770 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 771 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 772 N0.getOperand(0), N1.getOperand(0)); 773 WorkList.push_back(ANDNode.Val); 774 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 775 } 776 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 777 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 778 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 779 N0.getOperand(1) == N1.getOperand(1)) { 780 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 781 N0.getOperand(0), N1.getOperand(0)); 782 WorkList.push_back(ANDNode.Val); 783 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 784 } 785 return SDOperand(); 786} 787 788SDOperand DAGCombiner::visitOR(SDNode *N) { 789 SDOperand N0 = N->getOperand(0); 790 SDOperand N1 = N->getOperand(1); 791 SDOperand LL, LR, RL, RR, CC0, CC1; 792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 794 MVT::ValueType VT = N1.getValueType(); 795 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 796 797 // fold (or c1, c2) -> c1|c2 798 if (N0C && N1C) 799 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 800 N->getValueType(0)); 801 // canonicalize constant to RHS 802 if (N0C && !N1C) { 803 std::swap(N0, N1); 804 std::swap(N0C, N1C); 805 } 806 // fold (or x, 0) -> x 807 if (N1C && N1C->isNullValue()) 808 return N0; 809 // fold (or x, -1) -> -1 810 if (N1C && N1C->isAllOnesValue()) 811 return N1; 812 // fold (or x, c) -> c iff (x & ~c) == 0 813 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 814 TLI)) 815 return N1; 816 // fold (or (or x, c1), c2) -> (or x, c1|c2) 817 if (N1C && N0.getOpcode() == ISD::OR) { 818 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 819 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 820 if (N00C) 821 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 822 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 823 if (N01C) 824 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 825 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 826 } 827 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 828 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 829 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 830 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 831 832 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 833 MVT::isInteger(LL.getValueType())) { 834 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 835 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 836 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 837 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 838 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 839 WorkList.push_back(ORNode.Val); 840 return DAG.getSetCC(VT, ORNode, LR, Op1); 841 } 842 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 843 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 844 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 845 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 846 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 847 WorkList.push_back(ANDNode.Val); 848 return DAG.getSetCC(VT, ANDNode, LR, Op1); 849 } 850 } 851 // canonicalize equivalent to ll == rl 852 if (LL == RR && LR == RL) { 853 Op1 = ISD::getSetCCSwappedOperands(Op1); 854 std::swap(RL, RR); 855 } 856 if (LL == RL && LR == RR) { 857 bool isInteger = MVT::isInteger(LL.getValueType()); 858 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 859 if (Result != ISD::SETCC_INVALID) 860 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 861 } 862 } 863 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 864 if (N0.getOpcode() == ISD::ZERO_EXTEND && 865 N1.getOpcode() == ISD::ZERO_EXTEND && 866 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 867 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 868 N0.getOperand(0), N1.getOperand(0)); 869 WorkList.push_back(ORNode.Val); 870 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 871 } 872 return SDOperand(); 873} 874 875SDOperand DAGCombiner::visitXOR(SDNode *N) { 876 SDOperand N0 = N->getOperand(0); 877 SDOperand N1 = N->getOperand(1); 878 SDOperand LHS, RHS, CC; 879 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 881 MVT::ValueType VT = N0.getValueType(); 882 883 // fold (xor c1, c2) -> c1^c2 884 if (N0C && N1C) 885 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 886 // canonicalize constant to RHS 887 if (N0C && !N1C) { 888 std::swap(N0, N1); 889 std::swap(N0C, N1C); 890 } 891 // fold (xor x, 0) -> x 892 if (N1C && N1C->isNullValue()) 893 return N0; 894 // fold !(x cc y) -> (x !cc y) 895 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 896 bool isInt = MVT::isInteger(LHS.getValueType()); 897 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 898 isInt); 899 if (N0.getOpcode() == ISD::SETCC) 900 return DAG.getSetCC(VT, LHS, RHS, NotCC); 901 if (N0.getOpcode() == ISD::SELECT_CC) 902 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 903 assert(0 && "Unhandled SetCC Equivalent!"); 904 abort(); 905 } 906 // fold !(x or y) -> (!x and !y) iff x or y are setcc 907 if (N1C && N1C->getValue() == 1 && 908 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 909 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 910 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 911 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 912 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 913 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 914 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 915 return DAG.getNode(NewOpcode, VT, LHS, RHS); 916 } 917 } 918 // fold !(x or y) -> (!x and !y) iff x or y are constants 919 if (N1C && N1C->isAllOnesValue() && 920 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 921 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 922 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 923 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 924 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 925 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 926 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 927 return DAG.getNode(NewOpcode, VT, LHS, RHS); 928 } 929 } 930 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 931 if (N1C && N0.getOpcode() == ISD::XOR) { 932 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 933 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 934 if (N00C) 935 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 936 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 937 if (N01C) 938 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 939 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 940 } 941 // fold (xor x, x) -> 0 942 if (N0 == N1) 943 return DAG.getConstant(0, VT); 944 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 945 if (N0.getOpcode() == ISD::ZERO_EXTEND && 946 N1.getOpcode() == ISD::ZERO_EXTEND && 947 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 948 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 949 N0.getOperand(0), N1.getOperand(0)); 950 WorkList.push_back(XORNode.Val); 951 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 952 } 953 return SDOperand(); 954} 955 956SDOperand DAGCombiner::visitSHL(SDNode *N) { 957 SDOperand N0 = N->getOperand(0); 958 SDOperand N1 = N->getOperand(1); 959 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 960 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 961 MVT::ValueType VT = N0.getValueType(); 962 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 963 964 // fold (shl c1, c2) -> c1<<c2 965 if (N0C && N1C) 966 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 967 // fold (shl 0, x) -> 0 968 if (N0C && N0C->isNullValue()) 969 return N0; 970 // fold (shl x, c >= size(x)) -> undef 971 if (N1C && N1C->getValue() >= OpSizeInBits) 972 return DAG.getNode(ISD::UNDEF, VT); 973 // fold (shl x, 0) -> x 974 if (N1C && N1C->isNullValue()) 975 return N0; 976 // if (shl x, c) is known to be zero, return 0 977 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 978 return DAG.getConstant(0, VT); 979 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 980 if (N1C && N0.getOpcode() == ISD::SHL && 981 N0.getOperand(1).getOpcode() == ISD::Constant) { 982 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 983 uint64_t c2 = N1C->getValue(); 984 if (c1 + c2 > OpSizeInBits) 985 return DAG.getConstant(0, VT); 986 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 987 DAG.getConstant(c1 + c2, N1.getValueType())); 988 } 989 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 990 // (srl (and x, -1 << c1), c1-c2) 991 if (N1C && N0.getOpcode() == ISD::SRL && 992 N0.getOperand(1).getOpcode() == ISD::Constant) { 993 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 994 uint64_t c2 = N1C->getValue(); 995 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 996 DAG.getConstant(~0ULL << c1, VT)); 997 if (c2 > c1) 998 return DAG.getNode(ISD::SHL, VT, Mask, 999 DAG.getConstant(c2-c1, N1.getValueType())); 1000 else 1001 return DAG.getNode(ISD::SRL, VT, Mask, 1002 DAG.getConstant(c1-c2, N1.getValueType())); 1003 } 1004 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1005 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1006 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1007 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1008 return SDOperand(); 1009} 1010 1011SDOperand DAGCombiner::visitSRA(SDNode *N) { 1012 SDOperand N0 = N->getOperand(0); 1013 SDOperand N1 = N->getOperand(1); 1014 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1015 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1016 MVT::ValueType VT = N0.getValueType(); 1017 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1018 1019 // fold (sra c1, c2) -> c1>>c2 1020 if (N0C && N1C) 1021 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1022 // fold (sra 0, x) -> 0 1023 if (N0C && N0C->isNullValue()) 1024 return N0; 1025 // fold (sra -1, x) -> -1 1026 if (N0C && N0C->isAllOnesValue()) 1027 return N0; 1028 // fold (sra x, c >= size(x)) -> undef 1029 if (N1C && N1C->getValue() >= OpSizeInBits) 1030 return DAG.getNode(ISD::UNDEF, VT); 1031 // fold (sra x, 0) -> x 1032 if (N1C && N1C->isNullValue()) 1033 return N0; 1034 // If the sign bit is known to be zero, switch this to a SRL. 1035 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1036 return DAG.getNode(ISD::SRL, VT, N0, N1); 1037 return SDOperand(); 1038} 1039 1040SDOperand DAGCombiner::visitSRL(SDNode *N) { 1041 SDOperand N0 = N->getOperand(0); 1042 SDOperand N1 = N->getOperand(1); 1043 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1044 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1045 MVT::ValueType VT = N0.getValueType(); 1046 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1047 1048 // fold (srl c1, c2) -> c1 >>u c2 1049 if (N0C && N1C) 1050 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1051 // fold (srl 0, x) -> 0 1052 if (N0C && N0C->isNullValue()) 1053 return N0; 1054 // fold (srl x, c >= size(x)) -> undef 1055 if (N1C && N1C->getValue() >= OpSizeInBits) 1056 return DAG.getNode(ISD::UNDEF, VT); 1057 // fold (srl x, 0) -> x 1058 if (N1C && N1C->isNullValue()) 1059 return N0; 1060 // if (srl x, c) is known to be zero, return 0 1061 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1062 return DAG.getConstant(0, VT); 1063 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1064 if (N1C && N0.getOpcode() == ISD::SRL && 1065 N0.getOperand(1).getOpcode() == ISD::Constant) { 1066 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1067 uint64_t c2 = N1C->getValue(); 1068 if (c1 + c2 > OpSizeInBits) 1069 return DAG.getConstant(0, VT); 1070 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1071 DAG.getConstant(c1 + c2, N1.getValueType())); 1072 } 1073 return SDOperand(); 1074} 1075 1076SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1077 SDOperand N0 = N->getOperand(0); 1078 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1079 1080 // fold (ctlz c1) -> c2 1081 if (N0C) 1082 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1083 N0.getValueType()); 1084 return SDOperand(); 1085} 1086 1087SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1088 SDOperand N0 = N->getOperand(0); 1089 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1090 1091 // fold (cttz c1) -> c2 1092 if (N0C) 1093 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1094 N0.getValueType()); 1095 return SDOperand(); 1096} 1097 1098SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1099 SDOperand N0 = N->getOperand(0); 1100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1101 1102 // fold (ctpop c1) -> c2 1103 if (N0C) 1104 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1105 N0.getValueType()); 1106 return SDOperand(); 1107} 1108 1109SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1110 SDOperand N0 = N->getOperand(0); 1111 SDOperand N1 = N->getOperand(1); 1112 SDOperand N2 = N->getOperand(2); 1113 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1114 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1115 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1116 MVT::ValueType VT = N->getValueType(0); 1117 1118 // fold select C, X, X -> X 1119 if (N1 == N2) 1120 return N1; 1121 // fold select true, X, Y -> X 1122 if (N0C && !N0C->isNullValue()) 1123 return N1; 1124 // fold select false, X, Y -> Y 1125 if (N0C && N0C->isNullValue()) 1126 return N2; 1127 // fold select C, 1, X -> C | X 1128 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1129 return DAG.getNode(ISD::OR, VT, N0, N2); 1130 // fold select C, 0, X -> ~C & X 1131 // FIXME: this should check for C type == X type, not i1? 1132 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1133 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1134 WorkList.push_back(XORNode.Val); 1135 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1136 } 1137 // fold select C, X, 1 -> ~C | X 1138 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1139 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1140 WorkList.push_back(XORNode.Val); 1141 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1142 } 1143 // fold select C, X, 0 -> C & X 1144 // FIXME: this should check for C type == X type, not i1? 1145 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1146 return DAG.getNode(ISD::AND, VT, N0, N1); 1147 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1148 if (MVT::i1 == VT && N0 == N1) 1149 return DAG.getNode(ISD::OR, VT, N0, N2); 1150 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1151 if (MVT::i1 == VT && N0 == N2) 1152 return DAG.getNode(ISD::AND, VT, N0, N1); 1153 // fold selects based on a setcc into other things, such as min/max/abs 1154 if (N0.getOpcode() == ISD::SETCC) 1155 return SimplifySelect(N0, N1, N2); 1156 return SDOperand(); 1157} 1158 1159SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1160 SDOperand N0 = N->getOperand(0); 1161 SDOperand N1 = N->getOperand(1); 1162 SDOperand N2 = N->getOperand(2); 1163 SDOperand N3 = N->getOperand(3); 1164 SDOperand N4 = N->getOperand(4); 1165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1166 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1167 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1168 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1169 1170 // Determine if the condition we're dealing with is constant 1171 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1172 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1173 1174 // fold select_cc lhs, rhs, x, x, cc -> x 1175 if (N2 == N3) 1176 return N2; 1177 // fold select_cc into other things, such as min/max/abs 1178 return SimplifySelectCC(N0, N1, N2, N3, CC); 1179} 1180 1181SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1182 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1183 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1184} 1185 1186SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1187 SDOperand N0 = N->getOperand(0); 1188 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1189 MVT::ValueType VT = N->getValueType(0); 1190 1191 // fold (sext c1) -> c1 1192 if (N0C) 1193 return DAG.getConstant(N0C->getSignExtended(), VT); 1194 // fold (sext (sext x)) -> (sext x) 1195 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1196 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1197 // fold (sext (sextload x)) -> (sextload x) 1198 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1199 return N0; 1200 // fold (sext (load x)) -> (sextload x) 1201 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1202 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1203 N0.getOperand(1), N0.getOperand(2), 1204 N0.getValueType()); 1205 CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0)); 1206 WorkList.push_back(N); 1207 return SDOperand(); 1208 } 1209 return SDOperand(); 1210} 1211 1212SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1213 SDOperand N0 = N->getOperand(0); 1214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1215 MVT::ValueType VT = N->getValueType(0); 1216 1217 // fold (zext c1) -> c1 1218 if (N0C) 1219 return DAG.getConstant(N0C->getValue(), VT); 1220 // fold (zext (zext x)) -> (zext x) 1221 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1222 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1223 return SDOperand(); 1224} 1225 1226SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1227 SDOperand N0 = N->getOperand(0); 1228 SDOperand N1 = N->getOperand(1); 1229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1230 MVT::ValueType VT = N->getValueType(0); 1231 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1232 unsigned EVTBits = MVT::getSizeInBits(EVT); 1233 1234 // fold (sext_in_reg c1) -> c1 1235 if (N0C) { 1236 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1237 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1238 } 1239 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1240 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1241 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) { 1242 return N0; 1243 } 1244 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1245 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1246 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1247 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1248 } 1249 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1250 if (N0.getOpcode() == ISD::AssertSext && 1251 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1252 return N0; 1253 } 1254 // fold (sext_in_reg (sextload x)) -> (sextload x) 1255 if (N0.getOpcode() == ISD::SEXTLOAD && 1256 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1257 return N0; 1258 } 1259 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1260 if (N0.getOpcode() == ISD::SETCC && 1261 TLI.getSetCCResultContents() == 1262 TargetLowering::ZeroOrNegativeOneSetCCResult) 1263 return N0; 1264 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1265 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1266 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1267 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1268 // fold (sext_in_reg (srl x)) -> sra x 1269 if (N0.getOpcode() == ISD::SRL && 1270 N0.getOperand(1).getOpcode() == ISD::Constant && 1271 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1272 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1273 N0.getOperand(1)); 1274 } 1275 return SDOperand(); 1276} 1277 1278SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1279 SDOperand N0 = N->getOperand(0); 1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1281 MVT::ValueType VT = N->getValueType(0); 1282 1283 // noop truncate 1284 if (N0.getValueType() == N->getValueType(0)) 1285 return N0; 1286 // fold (truncate c1) -> c1 1287 if (N0C) 1288 return DAG.getConstant(N0C->getValue(), VT); 1289 // fold (truncate (truncate x)) -> (truncate x) 1290 if (N0.getOpcode() == ISD::TRUNCATE) 1291 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1292 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1293 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1294 if (N0.getValueType() < VT) 1295 // if the source is smaller than the dest, we still need an extend 1296 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1297 else if (N0.getValueType() > VT) 1298 // if the source is larger than the dest, than we just need the truncate 1299 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1300 else 1301 // if the source and dest are the same type, we can drop both the extend 1302 // and the truncate 1303 return N0.getOperand(0); 1304 } 1305 // fold (truncate (load x)) -> (smaller load x) 1306 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1307 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1308 "Cannot truncate to larger type!"); 1309 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1310 // For big endian targets, we need to add an offset to the pointer to load 1311 // the correct bytes. For little endian systems, we merely need to read 1312 // fewer bytes from the same pointer. 1313 uint64_t PtrOff = 1314 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1315 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1316 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1317 DAG.getConstant(PtrOff, PtrType)); 1318 WorkList.push_back(NewPtr.Val); 1319 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1320 CombineTo(N0.Val, Load, Load.getOperand(0)); 1321 WorkList.push_back(N); 1322 return SDOperand(); 1323 } 1324 return SDOperand(); 1325} 1326 1327SDOperand DAGCombiner::visitFADD(SDNode *N) { 1328 SDOperand N0 = N->getOperand(0); 1329 SDOperand N1 = N->getOperand(1); 1330 MVT::ValueType VT = N->getValueType(0); 1331 1332 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1333 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1334 // fold floating point (fadd c1, c2) 1335 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), 1336 N->getValueType(0)); 1337 } 1338 // fold (A + (-B)) -> A-B 1339 if (N1.getOpcode() == ISD::FNEG) 1340 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1341 1342 // fold ((-A) + B) -> B-A 1343 if (N0.getOpcode() == ISD::FNEG) 1344 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1345 1346 return SDOperand(); 1347} 1348 1349SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1350 SDOperand N0 = N->getOperand(0); 1351 SDOperand N1 = N->getOperand(1); 1352 MVT::ValueType VT = N->getValueType(0); 1353 1354 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1355 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1356 // fold floating point (fsub c1, c2) 1357 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), 1358 N->getValueType(0)); 1359 } 1360 // fold (A-(-B)) -> A+B 1361 if (N1.getOpcode() == ISD::FNEG) 1362 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1363 1364 return SDOperand(); 1365} 1366 1367SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1368 SDOperand N0 = N->getOperand(0); 1369 SDOperand N1 = N->getOperand(1); 1370 MVT::ValueType VT = N->getValueType(0); 1371 1372 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1373 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1374 // fold floating point (fmul c1, c2) 1375 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), 1376 N->getValueType(0)); 1377 } 1378 return SDOperand(); 1379} 1380 1381SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1382 SDOperand N0 = N->getOperand(0); 1383 SDOperand N1 = N->getOperand(1); 1384 MVT::ValueType VT = N->getValueType(0); 1385 1386 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1387 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1388 // fold floating point (fdiv c1, c2) 1389 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), 1390 N->getValueType(0)); 1391 } 1392 return SDOperand(); 1393} 1394 1395SDOperand DAGCombiner::visitFREM(SDNode *N) { 1396 SDOperand N0 = N->getOperand(0); 1397 SDOperand N1 = N->getOperand(1); 1398 MVT::ValueType VT = N->getValueType(0); 1399 1400 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1401 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1402 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1403 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), 1404 N->getValueType(0)); 1405 } 1406 return SDOperand(); 1407} 1408 1409 1410SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1411 SDOperand N0 = N->getOperand(0); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1413 1414 // fold (sint_to_fp c1) -> c1fp 1415 if (N0C) 1416 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1417 return SDOperand(); 1418} 1419 1420SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1421 SDOperand N0 = N->getOperand(0); 1422 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1423 1424 // fold (uint_to_fp c1) -> c1fp 1425 if (N0C) 1426 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1427 return SDOperand(); 1428} 1429 1430SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1431 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1432 1433 // fold (fp_to_sint c1fp) -> c1 1434 if (N0CFP) 1435 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1436 return SDOperand(); 1437} 1438 1439SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1440 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1441 1442 // fold (fp_to_uint c1fp) -> c1 1443 if (N0CFP) 1444 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1445 return SDOperand(); 1446} 1447 1448SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1450 1451 // fold (fp_round c1fp) -> c1fp 1452 if (N0CFP) 1453 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1454 return SDOperand(); 1455} 1456 1457SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1458 SDOperand N0 = N->getOperand(0); 1459 MVT::ValueType VT = N->getValueType(0); 1460 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1461 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1462 1463 // fold (fp_round_inreg c1fp) -> c1fp 1464 if (N0CFP) { 1465 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1466 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1467 } 1468 return SDOperand(); 1469} 1470 1471SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1472 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1473 1474 // fold (fp_extend c1fp) -> c1fp 1475 if (N0CFP) 1476 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1477 return SDOperand(); 1478} 1479 1480SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1481 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1482 // fold (neg c1) -> -c1 1483 if (N0CFP) 1484 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1485 // fold (neg (sub x, y)) -> (sub y, x) 1486 if (N->getOperand(0).getOpcode() == ISD::SUB) 1487 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1488 N->getOperand(0)); 1489 // fold (neg (neg x)) -> x 1490 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1491 return N->getOperand(0).getOperand(0); 1492 return SDOperand(); 1493} 1494 1495SDOperand DAGCombiner::visitFABS(SDNode *N) { 1496 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1497 // fold (fabs c1) -> fabs(c1) 1498 if (N0CFP) 1499 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1500 // fold (fabs (fabs x)) -> (fabs x) 1501 if (N->getOperand(0).getOpcode() == ISD::FABS) 1502 return N->getOperand(0); 1503 // fold (fabs (fneg x)) -> (fabs x) 1504 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1505 return DAG.getNode(ISD::FABS, N->getValueType(0), 1506 N->getOperand(0).getOperand(0)); 1507 return SDOperand(); 1508} 1509 1510SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1511 SDOperand Chain = N->getOperand(0); 1512 SDOperand N1 = N->getOperand(1); 1513 SDOperand N2 = N->getOperand(2); 1514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1515 1516 // never taken branch, fold to chain 1517 if (N1C && N1C->isNullValue()) 1518 return Chain; 1519 // unconditional branch 1520 if (N1C && N1C->getValue() == 1) 1521 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1522 return SDOperand(); 1523} 1524 1525SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1526 SDOperand Chain = N->getOperand(0); 1527 SDOperand N1 = N->getOperand(1); 1528 SDOperand N2 = N->getOperand(2); 1529 SDOperand N3 = N->getOperand(3); 1530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1531 1532 // unconditional branch to true mbb 1533 if (N1C && N1C->getValue() == 1) 1534 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1535 // unconditional branch to false mbb 1536 if (N1C && N1C->isNullValue()) 1537 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1538 return SDOperand(); 1539} 1540 1541// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1542// 1543SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1544 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1545 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1546 1547 // Use SimplifySetCC to simplify SETCC's. 1548 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1549 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1550 1551 // fold br_cc true, dest -> br dest (unconditional branch) 1552 if (SCCC && SCCC->getValue()) 1553 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1554 N->getOperand(4)); 1555 // fold br_cc false, dest -> unconditional fall through 1556 if (SCCC && SCCC->isNullValue()) 1557 return N->getOperand(0); 1558 // fold to a simpler setcc 1559 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1560 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1561 Simp.getOperand(2), Simp.getOperand(0), 1562 Simp.getOperand(1), N->getOperand(4)); 1563 return SDOperand(); 1564} 1565 1566SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1567 SDOperand Chain = N->getOperand(0); 1568 SDOperand CCN = N->getOperand(1); 1569 SDOperand LHS = N->getOperand(2); 1570 SDOperand RHS = N->getOperand(3); 1571 SDOperand N4 = N->getOperand(4); 1572 SDOperand N5 = N->getOperand(5); 1573 1574 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1575 cast<CondCodeSDNode>(CCN)->get(), false); 1576 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1577 1578 // fold select_cc lhs, rhs, x, x, cc -> x 1579 if (N4 == N5) 1580 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1581 // fold select_cc true, x, y -> x 1582 if (SCCC && SCCC->getValue()) 1583 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1584 // fold select_cc false, x, y -> y 1585 if (SCCC && SCCC->isNullValue()) 1586 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1587 // fold to a simpler setcc 1588 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1589 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1590 SCC.getOperand(1), N4, N5); 1591 return SDOperand(); 1592} 1593 1594SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1595 SDOperand Chain = N->getOperand(0); 1596 SDOperand Ptr = N->getOperand(1); 1597 SDOperand SrcValue = N->getOperand(2); 1598 1599 // If this load is directly stored, replace the load value with the stored 1600 // value. 1601 // TODO: Handle store large -> read small portion. 1602 // TODO: Handle TRUNCSTORE/EXTLOAD 1603 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1604 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1605 return CombineTo(N, Chain.getOperand(1), Chain); 1606 1607 return SDOperand(); 1608} 1609 1610SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1611 SDOperand Chain = N->getOperand(0); 1612 SDOperand Value = N->getOperand(1); 1613 SDOperand Ptr = N->getOperand(2); 1614 SDOperand SrcValue = N->getOperand(3); 1615 1616 // If this is a store that kills a previous store, remove the previous store. 1617 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1618 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1619 // Create a new store of Value that replaces both stores. 1620 SDNode *PrevStore = Chain.Val; 1621 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1622 return Chain; 1623 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1624 PrevStore->getOperand(0), Value, Ptr, 1625 SrcValue); 1626 CombineTo(N, NewStore); // Nuke this store. 1627 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1628 return SDOperand(N, 0); 1629 } 1630 1631 return SDOperand(); 1632} 1633 1634SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1635 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1636 1637 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1638 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 1639 // If we got a simplified select_cc node back from SimplifySelectCC, then 1640 // break it down into a new SETCC node, and a new SELECT node, and then return 1641 // the SELECT node, since we were called with a SELECT node. 1642 if (SCC.Val) { 1643 // Check to see if we got a select_cc back (to turn into setcc/select). 1644 // Otherwise, just return whatever node we got back, like fabs. 1645 if (SCC.getOpcode() == ISD::SELECT_CC) { 1646 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 1647 SCC.getOperand(0), SCC.getOperand(1), 1648 SCC.getOperand(4)); 1649 WorkList.push_back(SETCC.Val); 1650 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 1651 SCC.getOperand(3), SETCC); 1652 } 1653 return SCC; 1654 } 1655 return SDOperand(); 1656} 1657 1658SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 1659 SDOperand N2, SDOperand N3, 1660 ISD::CondCode CC) { 1661 1662 MVT::ValueType VT = N2.getValueType(); 1663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1665 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1666 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1667 1668 // Determine if the condition we're dealing with is constant 1669 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1670 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1671 1672 // fold select_cc true, x, y -> x 1673 if (SCCC && SCCC->getValue()) 1674 return N2; 1675 // fold select_cc false, x, y -> y 1676 if (SCCC && SCCC->getValue() == 0) 1677 return N3; 1678 1679 // Check to see if we can simplify the select into an fabs node 1680 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1681 // Allow either -0.0 or 0.0 1682 if (CFP->getValue() == 0.0) { 1683 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1684 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1685 N0 == N2 && N3.getOpcode() == ISD::FNEG && 1686 N2 == N3.getOperand(0)) 1687 return DAG.getNode(ISD::FABS, VT, N0); 1688 1689 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1690 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1691 N0 == N3 && N2.getOpcode() == ISD::FNEG && 1692 N2.getOperand(0) == N3) 1693 return DAG.getNode(ISD::FABS, VT, N3); 1694 } 1695 } 1696 1697 // Check to see if we can perform the "gzip trick", transforming 1698 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1699 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 1700 MVT::isInteger(N0.getValueType()) && 1701 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 1702 MVT::ValueType XType = N0.getValueType(); 1703 MVT::ValueType AType = N2.getValueType(); 1704 if (XType >= AType) { 1705 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1706 // single-bit constant. 1707 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 1708 unsigned ShCtV = Log2_64(N2C->getValue()); 1709 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1710 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 1711 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 1712 WorkList.push_back(Shift.Val); 1713 if (XType > AType) { 1714 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1715 WorkList.push_back(Shift.Val); 1716 } 1717 return DAG.getNode(ISD::AND, AType, Shift, N2); 1718 } 1719 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1720 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1721 TLI.getShiftAmountTy())); 1722 WorkList.push_back(Shift.Val); 1723 if (XType > AType) { 1724 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1725 WorkList.push_back(Shift.Val); 1726 } 1727 return DAG.getNode(ISD::AND, AType, Shift, N2); 1728 } 1729 } 1730 1731 // fold select C, 16, 0 -> shl C, 4 1732 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 1733 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 1734 // Get a SetCC of the condition 1735 // FIXME: Should probably make sure that setcc is legal if we ever have a 1736 // target where it isn't. 1737 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1738 WorkList.push_back(SCC.Val); 1739 // cast from setcc result type to select result type 1740 if (AfterLegalize) 1741 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 1742 else 1743 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 1744 WorkList.push_back(Temp.Val); 1745 // shl setcc result by log2 n2c 1746 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 1747 DAG.getConstant(Log2_64(N2C->getValue()), 1748 TLI.getShiftAmountTy())); 1749 } 1750 1751 // Check to see if this is the equivalent of setcc 1752 // FIXME: Turn all of these into setcc if setcc if setcc is legal 1753 // otherwise, go ahead with the folds. 1754 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 1755 MVT::ValueType XType = N0.getValueType(); 1756 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 1757 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1758 if (Res.getValueType() != VT) 1759 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 1760 return Res; 1761 } 1762 1763 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 1764 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 1765 TLI.isOperationLegal(ISD::CTLZ, XType)) { 1766 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 1767 return DAG.getNode(ISD::SRL, XType, Ctlz, 1768 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 1769 TLI.getShiftAmountTy())); 1770 } 1771 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 1772 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 1773 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 1774 N0); 1775 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 1776 DAG.getConstant(~0ULL, XType)); 1777 return DAG.getNode(ISD::SRL, XType, 1778 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 1779 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1780 TLI.getShiftAmountTy())); 1781 } 1782 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 1783 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 1784 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 1785 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1786 TLI.getShiftAmountTy())); 1787 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 1788 } 1789 } 1790 1791 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 1792 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 1793 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 1794 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 1795 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 1796 MVT::ValueType XType = N0.getValueType(); 1797 if (SubC->isNullValue() && MVT::isInteger(XType)) { 1798 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1799 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1800 TLI.getShiftAmountTy())); 1801 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 1802 WorkList.push_back(Shift.Val); 1803 WorkList.push_back(Add.Val); 1804 return DAG.getNode(ISD::XOR, XType, Add, Shift); 1805 } 1806 } 1807 } 1808 1809 return SDOperand(); 1810} 1811 1812SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 1813 SDOperand N1, ISD::CondCode Cond, 1814 bool foldBooleans) { 1815 // These setcc operations always fold. 1816 switch (Cond) { 1817 default: break; 1818 case ISD::SETFALSE: 1819 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1820 case ISD::SETTRUE: 1821 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1822 } 1823 1824 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1825 uint64_t C1 = N1C->getValue(); 1826 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 1827 uint64_t C0 = N0C->getValue(); 1828 1829 // Sign extend the operands if required 1830 if (ISD::isSignedIntSetCC(Cond)) { 1831 C0 = N0C->getSignExtended(); 1832 C1 = N1C->getSignExtended(); 1833 } 1834 1835 switch (Cond) { 1836 default: assert(0 && "Unknown integer setcc!"); 1837 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 1838 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 1839 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 1840 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 1841 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 1842 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 1843 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 1844 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 1845 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 1846 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 1847 } 1848 } else { 1849 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1850 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1851 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1852 1853 // If the comparison constant has bits in the upper part, the 1854 // zero-extended value could never match. 1855 if (C1 & (~0ULL << InSize)) { 1856 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1857 switch (Cond) { 1858 case ISD::SETUGT: 1859 case ISD::SETUGE: 1860 case ISD::SETEQ: return DAG.getConstant(0, VT); 1861 case ISD::SETULT: 1862 case ISD::SETULE: 1863 case ISD::SETNE: return DAG.getConstant(1, VT); 1864 case ISD::SETGT: 1865 case ISD::SETGE: 1866 // True if the sign bit of C1 is set. 1867 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 1868 case ISD::SETLT: 1869 case ISD::SETLE: 1870 // True if the sign bit of C1 isn't set. 1871 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 1872 default: 1873 break; 1874 } 1875 } 1876 1877 // Otherwise, we can perform the comparison with the low bits. 1878 switch (Cond) { 1879 case ISD::SETEQ: 1880 case ISD::SETNE: 1881 case ISD::SETUGT: 1882 case ISD::SETUGE: 1883 case ISD::SETULT: 1884 case ISD::SETULE: 1885 return DAG.getSetCC(VT, N0.getOperand(0), 1886 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1887 Cond); 1888 default: 1889 break; // todo, be more careful with signed comparisons 1890 } 1891 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1892 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1893 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1894 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1895 MVT::ValueType ExtDstTy = N0.getValueType(); 1896 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1897 1898 // If the extended part has any inconsistent bits, it cannot ever 1899 // compare equal. In other words, they have to be all ones or all 1900 // zeros. 1901 uint64_t ExtBits = 1902 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1903 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1904 return DAG.getConstant(Cond == ISD::SETNE, VT); 1905 1906 SDOperand ZextOp; 1907 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1908 if (Op0Ty == ExtSrcTy) { 1909 ZextOp = N0.getOperand(0); 1910 } else { 1911 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1912 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1913 DAG.getConstant(Imm, Op0Ty)); 1914 } 1915 WorkList.push_back(ZextOp.Val); 1916 // Otherwise, make this a use of a zext. 1917 return DAG.getSetCC(VT, ZextOp, 1918 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1919 ExtDstTy), 1920 Cond); 1921 } 1922 1923 uint64_t MinVal, MaxVal; 1924 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1925 if (ISD::isSignedIntSetCC(Cond)) { 1926 MinVal = 1ULL << (OperandBitSize-1); 1927 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1928 MaxVal = ~0ULL >> (65-OperandBitSize); 1929 else 1930 MaxVal = 0; 1931 } else { 1932 MinVal = 0; 1933 MaxVal = ~0ULL >> (64-OperandBitSize); 1934 } 1935 1936 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 1937 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 1938 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 1939 --C1; // X >= C0 --> X > (C0-1) 1940 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1941 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 1942 } 1943 1944 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 1945 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 1946 ++C1; // X <= C0 --> X < (C0+1) 1947 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 1948 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 1949 } 1950 1951 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 1952 return DAG.getConstant(0, VT); // X < MIN --> false 1953 1954 // Canonicalize setgt X, Min --> setne X, Min 1955 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 1956 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 1957 1958 // If we have setult X, 1, turn it into seteq X, 0 1959 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 1960 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 1961 ISD::SETEQ); 1962 // If we have setugt X, Max-1, turn it into seteq X, Max 1963 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 1964 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 1965 ISD::SETEQ); 1966 1967 // If we have "setcc X, C0", check to see if we can shrink the immediate 1968 // by changing cc. 1969 1970 // SETUGT X, SINTMAX -> SETLT X, 0 1971 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 1972 C1 == (~0ULL >> (65-OperandBitSize))) 1973 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 1974 ISD::SETLT); 1975 1976 // FIXME: Implement the rest of these. 1977 1978 // Fold bit comparisons when we can. 1979 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 1980 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 1981 if (ConstantSDNode *AndRHS = 1982 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1983 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 1984 // Perform the xform if the AND RHS is a single bit. 1985 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 1986 return DAG.getNode(ISD::SRL, VT, N0, 1987 DAG.getConstant(Log2_64(AndRHS->getValue()), 1988 TLI.getShiftAmountTy())); 1989 } 1990 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 1991 // (X & 8) == 8 --> (X & 8) >> 3 1992 // Perform the xform if C1 is a single bit. 1993 if ((C1 & (C1-1)) == 0) { 1994 return DAG.getNode(ISD::SRL, VT, N0, 1995 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 1996 } 1997 } 1998 } 1999 } 2000 } else if (isa<ConstantSDNode>(N0.Val)) { 2001 // Ensure that the constant occurs on the RHS. 2002 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2003 } 2004 2005 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2006 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2007 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2008 2009 switch (Cond) { 2010 default: break; // FIXME: Implement the rest of these! 2011 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2012 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2013 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2014 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2015 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2016 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2017 } 2018 } else { 2019 // Ensure that the constant occurs on the RHS. 2020 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2021 } 2022 2023 if (N0 == N1) { 2024 // We can always fold X == Y for integer setcc's. 2025 if (MVT::isInteger(N0.getValueType())) 2026 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2027 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2028 if (UOF == 2) // FP operators that are undefined on NaNs. 2029 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2030 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2031 return DAG.getConstant(UOF, VT); 2032 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2033 // if it is not already. 2034 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2035 if (NewCond != Cond) 2036 return DAG.getSetCC(VT, N0, N1, NewCond); 2037 } 2038 2039 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2040 MVT::isInteger(N0.getValueType())) { 2041 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2042 N0.getOpcode() == ISD::XOR) { 2043 // Simplify (X+Y) == (X+Z) --> Y == Z 2044 if (N0.getOpcode() == N1.getOpcode()) { 2045 if (N0.getOperand(0) == N1.getOperand(0)) 2046 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2047 if (N0.getOperand(1) == N1.getOperand(1)) 2048 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2049 if (isCommutativeBinOp(N0.getOpcode())) { 2050 // If X op Y == Y op X, try other combinations. 2051 if (N0.getOperand(0) == N1.getOperand(1)) 2052 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2053 if (N0.getOperand(1) == N1.getOperand(0)) 2054 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2055 } 2056 } 2057 2058 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2059 if (N0.getOpcode() == ISD::XOR) 2060 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2061 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2062 // If we know that all of the inverted bits are zero, don't bother 2063 // performing the inversion. 2064 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2065 return DAG.getSetCC(VT, N0.getOperand(0), 2066 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2067 N0.getValueType()), Cond); 2068 } 2069 2070 // Simplify (X+Z) == X --> Z == 0 2071 if (N0.getOperand(0) == N1) 2072 return DAG.getSetCC(VT, N0.getOperand(1), 2073 DAG.getConstant(0, N0.getValueType()), Cond); 2074 if (N0.getOperand(1) == N1) { 2075 if (isCommutativeBinOp(N0.getOpcode())) 2076 return DAG.getSetCC(VT, N0.getOperand(0), 2077 DAG.getConstant(0, N0.getValueType()), Cond); 2078 else { 2079 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2080 // (Z-X) == X --> Z == X<<1 2081 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2082 N1, 2083 DAG.getConstant(1,TLI.getShiftAmountTy())); 2084 WorkList.push_back(SH.Val); 2085 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2086 } 2087 } 2088 } 2089 2090 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2091 N1.getOpcode() == ISD::XOR) { 2092 // Simplify X == (X+Z) --> Z == 0 2093 if (N1.getOperand(0) == N0) { 2094 return DAG.getSetCC(VT, N1.getOperand(1), 2095 DAG.getConstant(0, N1.getValueType()), Cond); 2096 } else if (N1.getOperand(1) == N0) { 2097 if (isCommutativeBinOp(N1.getOpcode())) { 2098 return DAG.getSetCC(VT, N1.getOperand(0), 2099 DAG.getConstant(0, N1.getValueType()), Cond); 2100 } else { 2101 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2102 // X == (Z-X) --> X<<1 == Z 2103 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2104 DAG.getConstant(1,TLI.getShiftAmountTy())); 2105 WorkList.push_back(SH.Val); 2106 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2107 } 2108 } 2109 } 2110 } 2111 2112 // Fold away ALL boolean setcc's. 2113 SDOperand Temp; 2114 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2115 switch (Cond) { 2116 default: assert(0 && "Unknown integer setcc!"); 2117 case ISD::SETEQ: // X == Y -> (X^Y)^1 2118 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2119 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2120 WorkList.push_back(Temp.Val); 2121 break; 2122 case ISD::SETNE: // X != Y --> (X^Y) 2123 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2124 break; 2125 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2126 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2127 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2128 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2129 WorkList.push_back(Temp.Val); 2130 break; 2131 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2132 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2133 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2134 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2135 WorkList.push_back(Temp.Val); 2136 break; 2137 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2138 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2139 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2140 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2141 WorkList.push_back(Temp.Val); 2142 break; 2143 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2144 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2145 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2146 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2147 break; 2148 } 2149 if (VT != MVT::i1) { 2150 WorkList.push_back(N0.Val); 2151 // FIXME: If running after legalize, we probably can't do this. 2152 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2153 } 2154 return N0; 2155 } 2156 2157 // Could not fold it. 2158 return SDOperand(); 2159} 2160 2161// SelectionDAG::Combine - This is the entry point for the file. 2162// 2163void SelectionDAG::Combine(bool RunningAfterLegalize) { 2164 /// run - This is the main entry point to this class. 2165 /// 2166 DAGCombiner(*this).Run(RunningAfterLegalize); 2167} 2168