DAGCombiner.cpp revision 83e75ecd2725aed3ace0bd52945f2b5266696d00
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: zero extend when top bits are 0 -> drop it ? 26// FIXME: make truncate see through SIGN_EXTEND and AND 27// FIXME: sext_in_reg(setcc) on targets that return zero or one, and where 28// EVT != MVT::i1 can drop the sext. 29// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 30// FIXME: verify that getNode can't return extends with an operand whose type 31// is >= to that of the extend. 32// FIXME: divide by zero is currently left unfolded. do we want to turn this 33// into an undef? 34// 35//===----------------------------------------------------------------------===// 36 37#define DEBUG_TYPE "dagcombine" 38#include "llvm/ADT/Statistic.h" 39#include "llvm/CodeGen/SelectionDAG.h" 40#include "llvm/Support/MathExtras.h" 41#include "llvm/Target/TargetLowering.h" 42#include <cmath> 43using namespace llvm; 44 45namespace { 46 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 47 48 class DAGCombiner { 49 SelectionDAG &DAG; 50 TargetLowering &TLI; 51 bool AfterLegalize; 52 53 // Worklist of all of the nodes that need to be simplified. 54 std::vector<SDNode*> WorkList; 55 56 /// AddUsersToWorkList - When an instruction is simplified, add all users of 57 /// the instruction to the work lists because they might get more simplified 58 /// now. 59 /// 60 void AddUsersToWorkList(SDNode *N) { 61 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 62 UI != UE; ++UI) 63 WorkList.push_back(*UI); 64 } 65 66 /// removeFromWorkList - remove all instances of N from the worklist. 67 void removeFromWorkList(SDNode *N) { 68 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 69 WorkList.end()); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDOperand visit(SDNode *N); 75 76 // Visitation implementation - Implement dag node combining for different 77 // node types. The semantics are as follows: 78 // Return Value: 79 // null - No change was made 80 // otherwise - Node N should be replaced by the returned node. 81 // 82 SDOperand visitTokenFactor(SDNode *N); 83 SDOperand visitADD(SDNode *N); 84 SDOperand visitSUB(SDNode *N); 85 SDOperand visitMUL(SDNode *N); 86 SDOperand visitSDIV(SDNode *N); 87 SDOperand visitUDIV(SDNode *N); 88 SDOperand visitSREM(SDNode *N); 89 SDOperand visitUREM(SDNode *N); 90 SDOperand visitMULHU(SDNode *N); 91 SDOperand visitMULHS(SDNode *N); 92 SDOperand visitAND(SDNode *N); 93 SDOperand visitOR(SDNode *N); 94 SDOperand visitXOR(SDNode *N); 95 SDOperand visitSHL(SDNode *N); 96 SDOperand visitSRA(SDNode *N); 97 SDOperand visitSRL(SDNode *N); 98 SDOperand visitCTLZ(SDNode *N); 99 SDOperand visitCTTZ(SDNode *N); 100 SDOperand visitCTPOP(SDNode *N); 101 // select 102 // select_cc 103 // setcc 104 SDOperand visitSIGN_EXTEND(SDNode *N); 105 SDOperand visitZERO_EXTEND(SDNode *N); 106 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 107 SDOperand visitTRUNCATE(SDNode *N); 108 SDOperand visitSINT_TO_FP(SDNode *N); 109 SDOperand visitUINT_TO_FP(SDNode *N); 110 SDOperand visitFP_TO_SINT(SDNode *N); 111 SDOperand visitFP_TO_UINT(SDNode *N); 112 SDOperand visitFP_ROUND(SDNode *N); 113 SDOperand visitFP_ROUND_INREG(SDNode *N); 114 SDOperand visitFP_EXTEND(SDNode *N); 115 SDOperand visitFNEG(SDNode *N); 116 SDOperand visitFABS(SDNode *N); 117 // brcond 118 // brcondtwoway 119 // br_cc 120 // brtwoway_cc 121public: 122 DAGCombiner(SelectionDAG &D) 123 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 124 125 /// Run - runs the dag combiner on all nodes in the work list 126 void Run(bool RunningAfterLegalize); 127 }; 128} 129 130/// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use 131/// this predicate to simplify operations downstream. V and Mask are known to 132/// be the same type. 133static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 134 const TargetLowering &TLI) { 135 unsigned SrcBits; 136 if (Mask == 0) return true; 137 138 // If we know the result of a setcc has the top bits zero, use this info. 139 switch (Op.getOpcode()) { 140 case ISD::Constant: 141 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 142 case ISD::SETCC: 143 // FIXME: teach this about non ZeroOrOne values, such as 0 or -1 144 return ((Mask & 1) == 0) && 145 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 146 case ISD::ZEXTLOAD: 147 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 148 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 149 case ISD::ZERO_EXTEND: 150 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 151 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 152 case ISD::AssertZext: 153 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 154 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 155 case ISD::AND: 156 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 157 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 158 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 159 // FALL THROUGH 160 case ISD::OR: 161 case ISD::XOR: 162 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 163 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 164 case ISD::SELECT: 165 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 166 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 167 case ISD::SELECT_CC: 168 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 169 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 170 case ISD::SRL: 171 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 172 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 173 uint64_t NewVal = Mask << ShAmt->getValue(); 174 SrcBits = MVT::getSizeInBits(Op.getValueType()); 175 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 176 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 177 } 178 return false; 179 case ISD::SHL: 180 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 181 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 182 uint64_t NewVal = Mask >> ShAmt->getValue(); 183 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 184 } 185 return false; 186 case ISD::CTTZ: 187 case ISD::CTLZ: 188 case ISD::CTPOP: 189 // Bit counting instructions can not set the high bits of the result 190 // register. The max number of bits sets depends on the input. 191 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 192 193 // TODO we could handle some SRA cases here. 194 default: break; 195 } 196 return false; 197} 198 199// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 200// that selects between the values 1 and 0, making it equivalent to a setcc. 201// Also, set the incoming LHS, RHS, and CC references to the appropriate 202// nodes based on the type of node we are checking. This simplifies life a 203// bit for the callers. 204static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 205 SDOperand &CC) { 206 if (N.getOpcode() == ISD::SETCC) { 207 LHS = N.getOperand(0); 208 RHS = N.getOperand(1); 209 CC = N.getOperand(2); 210 return true; 211 } 212 if (N.getOpcode() == ISD::SELECT_CC && 213 N.getOperand(2).getOpcode() == ISD::Constant && 214 N.getOperand(3).getOpcode() == ISD::Constant && 215 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 216 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 217 LHS = N.getOperand(0); 218 RHS = N.getOperand(1); 219 CC = N.getOperand(4); 220 return true; 221 } 222 return false; 223} 224 225// isInvertibleForFree - Return true if there is no cost to emitting the logical 226// inverse of this node. 227static bool isInvertibleForFree(SDOperand N) { 228 SDOperand N0, N1, N2; 229 if (isa<ConstantSDNode>(N.Val)) return true; 230 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 231 return true; 232 return false; 233} 234 235void DAGCombiner::Run(bool RunningAfterLegalize) { 236 // set the instance variable, so that the various visit routines may use it. 237 AfterLegalize = RunningAfterLegalize; 238 239 // Add all the dag nodes to the worklist. 240 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 241 242 // while the worklist isn't empty, inspect the node on the end of it and 243 // try and combine it. 244 while (!WorkList.empty()) { 245 SDNode *N = WorkList.back(); 246 WorkList.pop_back(); 247 248 // If N has no uses, it is dead. Make sure to revisit all N's operands once 249 // N is deleted from the DAG, since they too may now be dead. 250 // FIXME: is there a better way to keep from deleting the dag root because 251 // we think it has no uses? This works for now... 252 if (N->use_empty() && N != DAG.getRoot().Val) { 253 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 254 WorkList.push_back(N->getOperand(i).Val); 255 256 DAG.DeleteNode(N); 257 removeFromWorkList(N); 258 continue; 259 } 260 261 SDOperand RV = visit(N); 262 if (RV.Val) { 263 ++NodesCombined; 264 // If we get back the same node we passed in, rather than a new node or 265 // zero, we know that the node must have defined multiple values and 266 // CombineTo was used. Since CombineTo takes care of the worklist 267 // mechanics for us, we have no work to do in this case. 268 if (RV.Val != N) { 269 std::cerr << "\nReplacing "; N->dump(); 270 std::cerr << "\nWith: "; RV.Val->dump(); 271 std::cerr << '\n'; 272 DAG.ReplaceAllUsesWith(SDOperand(N, 0), RV); 273 274 // Push the new node and any users onto the worklist 275 WorkList.push_back(RV.Val); 276 AddUsersToWorkList(RV.Val); 277 278 // Nodes can end up on the worklist more than once. Make sure we do 279 // not process a node that has been replaced. 280 removeFromWorkList(N); 281 } 282 } 283 } 284} 285 286SDOperand DAGCombiner::visit(SDNode *N) { 287 switch(N->getOpcode()) { 288 default: break; 289 case ISD::TokenFactor: return visitTokenFactor(N); 290 case ISD::ADD: return visitADD(N); 291 case ISD::SUB: return visitSUB(N); 292 case ISD::MUL: return visitMUL(N); 293 case ISD::SDIV: return visitSDIV(N); 294 case ISD::UDIV: return visitUDIV(N); 295 case ISD::SREM: return visitSREM(N); 296 case ISD::UREM: return visitUREM(N); 297 case ISD::MULHU: return visitMULHU(N); 298 case ISD::MULHS: return visitMULHS(N); 299 case ISD::AND: return visitAND(N); 300 case ISD::OR: return visitOR(N); 301 case ISD::XOR: return visitXOR(N); 302 case ISD::SHL: return visitSHL(N); 303 case ISD::SRA: return visitSRA(N); 304 case ISD::SRL: return visitSRL(N); 305 case ISD::CTLZ: return visitCTLZ(N); 306 case ISD::CTTZ: return visitCTTZ(N); 307 case ISD::CTPOP: return visitCTPOP(N); 308 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 309 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 310 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 311 case ISD::TRUNCATE: return visitTRUNCATE(N); 312 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 313 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 314 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 315 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 316 case ISD::FP_ROUND: return visitFP_ROUND(N); 317 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 318 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 319 case ISD::FNEG: return visitFNEG(N); 320 case ISD::FABS: return visitFABS(N); 321 } 322 return SDOperand(); 323} 324 325SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 326 // If the token factor has two operands and one is the entry token, replace 327 // the token factor with the other operand. 328 if (N->getNumOperands() == 2) { 329 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 330 return N->getOperand(1); 331 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 332 return N->getOperand(0); 333 } 334 return SDOperand(); 335} 336 337SDOperand DAGCombiner::visitADD(SDNode *N) { 338 SDOperand N0 = N->getOperand(0); 339 SDOperand N1 = N->getOperand(1); 340 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 341 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 342 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 343 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 344 345 // fold (add c1, c2) -> c1+c2 346 if (N0C && N1C) 347 return DAG.getConstant(N0C->getValue() + N1C->getValue(), 348 N->getValueType(0)); 349 // fold (add x, 0) -> x 350 if (N1C && N1C->isNullValue()) 351 return N0; 352 // fold floating point (add c1, c2) -> c1+c2 353 if (N0CFP && N1CFP) 354 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), 355 N->getValueType(0)); 356 // fold (A + (-B)) -> A-B 357 if (N1.getOpcode() == ISD::FNEG) 358 return DAG.getNode(ISD::SUB, N->getValueType(0), N0, N1.getOperand(0)); 359 // fold ((-A) + B) -> B-A 360 if (N0.getOpcode() == ISD::FNEG) 361 return DAG.getNode(ISD::SUB, N->getValueType(0), N1, N0.getOperand(0)); 362 // fold ((0-A) + B) -> B-A 363 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 364 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 365 return DAG.getNode(ISD::SUB, N->getValueType(0), N1, N0.getOperand(1)); 366 // fold (A + (0-B)) -> A-B 367 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 368 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 369 return DAG.getNode(ISD::SUB, N->getValueType(0), N0, N1.getOperand(1)); 370 // fold (A+(B-A)) -> B for non-fp types 371 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1) && 372 !MVT::isFloatingPoint(N1.getValueType())) 373 return N1.getOperand(0); 374 return SDOperand(); 375} 376 377SDOperand DAGCombiner::visitSUB(SDNode *N) { 378 SDOperand N0 = N->getOperand(0); 379 SDOperand N1 = N->getOperand(1); 380 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 382 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val); 383 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 384 385 // fold (sub c1, c2) -> c1-c2 386 if (N0C && N1C) 387 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 388 N->getValueType(0)); 389 // fold (sub x, 0) -> x 390 if (N1C && N1C->isNullValue()) 391 return N0; 392 // fold floating point (sub c1, c2) -> c1-c2 393 if (N0CFP && N1CFP) 394 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), 395 N->getValueType(0)); 396 // fold (A+B)-A -> B 397 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 && 398 !MVT::isFloatingPoint(N1.getValueType())) 399 return N0.getOperand(1); 400 // fold (A+B)-B -> A 401 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 && 402 !MVT::isFloatingPoint(N1.getValueType())) 403 return N0.getOperand(0); 404 // fold (A-(-B)) -> A+B 405 if (N1.getOpcode() == ISD::FNEG) 406 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, N1.getOperand(0)); 407 return SDOperand(); 408} 409 410SDOperand DAGCombiner::visitMUL(SDNode *N) { 411 SDOperand N0 = N->getOperand(0); 412 SDOperand N1 = N->getOperand(1); 413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 415 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 416 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 417 418 // fold (mul c1, c2) -> c1*c2 419 if (N0C && N1C) 420 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 421 N->getValueType(0)); 422 // fold (mul x, 0) -> 0 423 if (N1C && N1C->isNullValue()) 424 return N1; 425 // fold (mul x, -1) -> 0-x 426 if (N1C && N1C->isAllOnesValue()) 427 return DAG.getNode(ISD::SUB, N->getValueType(0), 428 DAG.getConstant(0, N->getValueType(0)), N0); 429 // fold (mul x, (1 << c)) -> x << c 430 if (N1C && isPowerOf2_64(N1C->getValue())) 431 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 432 DAG.getConstant(Log2_64(N1C->getValue()), 433 TLI.getShiftAmountTy())); 434 // fold floating point (mul c1, c2) -> c1*c2 435 if (N0CFP && N1CFP) 436 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), 437 N->getValueType(0)); 438 return SDOperand(); 439} 440 441SDOperand DAGCombiner::visitSDIV(SDNode *N) { 442 SDOperand N0 = N->getOperand(0); 443 SDOperand N1 = N->getOperand(1); 444 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 445 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 446 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0.Val); 447 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val); 448 449 // fold (sdiv c1, c2) -> c1/c2 450 if (N0C && N1C && !N1C->isNullValue()) 451 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 452 N->getValueType(0)); 453 // fold floating point (sdiv c1, c2) -> c1/c2 454 if (N0CFP && N1CFP) 455 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), 456 N->getValueType(0)); 457 return SDOperand(); 458} 459 460SDOperand DAGCombiner::visitUDIV(SDNode *N) { 461 SDOperand N0 = N->getOperand(0); 462 SDOperand N1 = N->getOperand(1); 463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 465 466 // fold (udiv c1, c2) -> c1/c2 467 if (N0C && N1C && !N1C->isNullValue()) 468 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 469 N->getValueType(0)); 470 // fold (udiv x, (1 << c)) -> x >>u c 471 if (N1C && isPowerOf2_64(N1C->getValue())) 472 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 473 DAG.getConstant(Log2_64(N1C->getValue()), 474 TLI.getShiftAmountTy())); 475 return SDOperand(); 476} 477 478SDOperand DAGCombiner::visitSREM(SDNode *N) { 479 SDOperand N0 = N->getOperand(0); 480 SDOperand N1 = N->getOperand(1); 481 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 482 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 483 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 484 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 485 486 // fold (srem c1, c2) -> c1%c2 487 if (N0C && N1C && !N1C->isNullValue()) 488 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 489 N->getValueType(0)); 490 // fold floating point (srem c1, c2) -> fmod(c1, c2) 491 if (N0CFP && N1CFP) 492 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), 493 N->getValueType(0)); 494 return SDOperand(); 495} 496 497SDOperand DAGCombiner::visitUREM(SDNode *N) { 498 SDOperand N0 = N->getOperand(0); 499 SDOperand N1 = N->getOperand(1); 500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 502 503 // fold (urem c1, c2) -> c1%c2 504 if (N0C && N1C && !N1C->isNullValue()) 505 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 506 N->getValueType(0)); 507 // FIXME: c2 power of 2 -> mask? 508 return SDOperand(); 509} 510 511SDOperand DAGCombiner::visitMULHS(SDNode *N) { 512 SDOperand N0 = N->getOperand(0); 513 SDOperand N1 = N->getOperand(1); 514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 515 516 // fold (mulhs x, 0) -> 0 517 if (N1C && N1C->isNullValue()) 518 return N1; 519 // fold (mulhs x, 1) -> (sra x, size(x)-1) 520 if (N1C && N1C->getValue() == 1) 521 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 522 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 523 TLI.getShiftAmountTy())); 524 return SDOperand(); 525} 526 527SDOperand DAGCombiner::visitMULHU(SDNode *N) { 528 SDOperand N0 = N->getOperand(0); 529 SDOperand N1 = N->getOperand(1); 530 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 531 532 // fold (mulhu x, 0) -> 0 533 if (N1C && N1C->isNullValue()) 534 return N1; 535 // fold (mulhu x, 1) -> 0 536 if (N1C && N1C->getValue() == 1) 537 return DAG.getConstant(0, N0.getValueType()); 538 return SDOperand(); 539} 540 541SDOperand DAGCombiner::visitAND(SDNode *N) { 542 SDOperand N0 = N->getOperand(0); 543 SDOperand N1 = N->getOperand(1); 544 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 546 MVT::ValueType VT = N1.getValueType(); 547 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 548 549 // fold (and c1, c2) -> c1&c2 550 if (N0C && N1C) 551 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 552 // fold (and x, -1) -> x 553 if (N1C && N1C->isAllOnesValue()) 554 return N0; 555 // if (and x, c) is known to be zero, return 0 556 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 557 return DAG.getConstant(0, VT); 558 // fold (and x, c) -> x iff (x & ~c) == 0 559 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 560 TLI)) 561 return N0; 562 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 563 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 564 unsigned ExtendBits = 565 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 566 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 567 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 568 } 569 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 570 if (N0.getOpcode() == ISD::OR) 571 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 572 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 573 return N1; 574 return SDOperand(); 575} 576 577SDOperand DAGCombiner::visitOR(SDNode *N) { 578 SDOperand N0 = N->getOperand(0); 579 SDOperand N1 = N->getOperand(1); 580 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 581 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 582 MVT::ValueType VT = N1.getValueType(); 583 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 584 585 // fold (or c1, c2) -> c1|c2 586 if (N0C && N1C) 587 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 588 N->getValueType(0)); 589 // fold (or x, 0) -> x 590 if (N1C && N1C->isNullValue()) 591 return N0; 592 // fold (or x, -1) -> -1 593 if (N1C && N1C->isAllOnesValue()) 594 return N1; 595 // fold (or x, c) -> c iff (x & ~c) == 0 596 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 597 TLI)) 598 return N1; 599 return SDOperand(); 600} 601 602SDOperand DAGCombiner::visitXOR(SDNode *N) { 603 SDOperand N0 = N->getOperand(0); 604 SDOperand N1 = N->getOperand(1); 605 SDOperand LHS, RHS, CC; 606 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 608 MVT::ValueType VT = N0.getValueType(); 609 610 // fold (xor c1, c2) -> c1^c2 611 if (N0C && N1C) 612 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 613 // fold (xor x, 0) -> x 614 if (N1C && N1C->isNullValue()) 615 return N0; 616 // fold !(x cc y) -> (x !cc y) 617 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 618 bool isInt = MVT::isInteger(LHS.getValueType()); 619 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 620 isInt); 621 if (N0.getOpcode() == ISD::SETCC) 622 return DAG.getSetCC(VT, LHS, RHS, NotCC); 623 if (N0.getOpcode() == ISD::SELECT_CC) 624 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 625 assert(0 && "Unhandled SetCC Equivalent!"); 626 abort(); 627 } 628 // fold !(x or y) -> (!x and !y) iff x or y are freely invertible 629 if (N1C && N1C->isAllOnesValue() && N0.getOpcode() == ISD::OR) { 630 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 631 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 632 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 633 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 634 return DAG.getNode(ISD::AND, VT, LHS, RHS); 635 } 636 } 637 // fold !(x and y) -> (!x or !y) iff x or y are freely invertible 638 if (N1C && N1C->isAllOnesValue() && N0.getOpcode() == ISD::AND) { 639 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 640 if (isInvertibleForFree(RHS) || isInvertibleForFree(LHS)) { 641 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 642 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 643 return DAG.getNode(ISD::OR, VT, LHS, RHS); 644 } 645 } 646 return SDOperand(); 647} 648 649SDOperand DAGCombiner::visitSHL(SDNode *N) { 650 SDOperand N0 = N->getOperand(0); 651 SDOperand N1 = N->getOperand(1); 652 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 653 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 654 MVT::ValueType VT = N0.getValueType(); 655 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 656 657 // fold (shl c1, c2) -> c1<<c2 658 if (N0C && N1C) 659 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 660 // fold (shl 0, x) -> 0 661 if (N0C && N0C->isNullValue()) 662 return N0; 663 // fold (shl x, c >= size(x)) -> undef 664 if (N1C && N1C->getValue() >= OpSizeInBits) 665 return DAG.getNode(ISD::UNDEF, VT); 666 // fold (shl x, 0) -> x 667 if (N1C && N1C->isNullValue()) 668 return N0; 669 // if (shl x, c) is known to be zero, return 0 670 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 671 return DAG.getConstant(0, VT); 672 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 673 if (N1C && N0.getOpcode() == ISD::SHL && 674 N0.getOperand(1).getOpcode() == ISD::Constant) { 675 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 676 uint64_t c2 = N1C->getValue(); 677 if (c1 + c2 > OpSizeInBits) 678 return DAG.getConstant(0, VT); 679 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 680 DAG.getConstant(c1 + c2, N1.getValueType())); 681 } 682 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 683 // (srl (and x, -1 << c1), c1-c2) 684 if (N1C && N0.getOpcode() == ISD::SRL && 685 N0.getOperand(1).getOpcode() == ISD::Constant) { 686 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 687 uint64_t c2 = N1C->getValue(); 688 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 689 DAG.getConstant(~0ULL << c1, VT)); 690 if (c2 > c1) 691 return DAG.getNode(ISD::SHL, VT, Mask, 692 DAG.getConstant(c2-c1, N1.getValueType())); 693 else 694 return DAG.getNode(ISD::SRL, VT, Mask, 695 DAG.getConstant(c1-c2, N1.getValueType())); 696 } 697 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 698 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 699 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 700 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 701 return SDOperand(); 702} 703 704SDOperand DAGCombiner::visitSRA(SDNode *N) { 705 SDOperand N0 = N->getOperand(0); 706 SDOperand N1 = N->getOperand(1); 707 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 708 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 709 MVT::ValueType VT = N0.getValueType(); 710 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 711 712 // fold (sra c1, c2) -> c1>>c2 713 if (N0C && N1C) 714 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 715 // fold (sra 0, x) -> 0 716 if (N0C && N0C->isNullValue()) 717 return N0; 718 // fold (sra -1, x) -> -1 719 if (N0C && N0C->isAllOnesValue()) 720 return N0; 721 // fold (sra x, c >= size(x)) -> undef 722 if (N1C && N1C->getValue() >= OpSizeInBits) 723 return DAG.getNode(ISD::UNDEF, VT); 724 // fold (sra x, 0) -> x 725 if (N1C && N1C->isNullValue()) 726 return N0; 727 // If the sign bit is known to be zero, switch this to a SRL. 728 if (N1C && MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 729 return DAG.getNode(ISD::SRL, VT, N0, N1); 730 return SDOperand(); 731} 732 733SDOperand DAGCombiner::visitSRL(SDNode *N) { 734 SDOperand N0 = N->getOperand(0); 735 SDOperand N1 = N->getOperand(1); 736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 738 MVT::ValueType VT = N0.getValueType(); 739 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 740 741 // fold (srl c1, c2) -> c1 >>u c2 742 if (N0C && N1C) 743 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 744 // fold (srl 0, x) -> 0 745 if (N0C && N0C->isNullValue()) 746 return N0; 747 // fold (srl x, c >= size(x)) -> undef 748 if (N1C && N1C->getValue() >= OpSizeInBits) 749 return DAG.getNode(ISD::UNDEF, VT); 750 // fold (srl x, 0) -> x 751 if (N1C && N1C->isNullValue()) 752 return N0; 753 // if (srl x, c) is known to be zero, return 0 754 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 755 return DAG.getConstant(0, VT); 756 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 757 if (N1C && N0.getOpcode() == ISD::SRL && 758 N0.getOperand(1).getOpcode() == ISD::Constant) { 759 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 760 uint64_t c2 = N1C->getValue(); 761 if (c1 + c2 > OpSizeInBits) 762 return DAG.getConstant(0, VT); 763 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 764 DAG.getConstant(c1 + c2, N1.getValueType())); 765 } 766 return SDOperand(); 767} 768 769SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 770 SDOperand N0 = N->getOperand(0); 771 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 772 773 // fold (ctlz c1) -> c2 774 if (N0C) 775 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 776 N0.getValueType()); 777 return SDOperand(); 778} 779 780SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 781 SDOperand N0 = N->getOperand(0); 782 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 783 784 // fold (cttz c1) -> c2 785 if (N0C) 786 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 787 N0.getValueType()); 788 return SDOperand(); 789} 790 791SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 792 SDOperand N0 = N->getOperand(0); 793 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 794 795 // fold (ctpop c1) -> c2 796 if (N0C) 797 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 798 N0.getValueType()); 799 return SDOperand(); 800} 801 802SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 803 SDOperand N0 = N->getOperand(0); 804 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 805 MVT::ValueType VT = N->getValueType(0); 806 807 // fold (sext c1) -> c1 808 if (N0C) 809 return DAG.getConstant(N0C->getSignExtended(), VT); 810 // fold (sext (sext x)) -> (sext x) 811 if (N0.getOpcode() == ISD::SIGN_EXTEND) 812 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 813 return SDOperand(); 814} 815 816SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 817 SDOperand N0 = N->getOperand(0); 818 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 819 MVT::ValueType VT = N->getValueType(0); 820 821 // fold (zext c1) -> c1 822 if (N0C) 823 return DAG.getConstant(N0C->getValue(), VT); 824 // fold (zext (zext x)) -> (zext x) 825 if (N0.getOpcode() == ISD::ZERO_EXTEND) 826 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 827 return SDOperand(); 828} 829 830SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 831 SDOperand N0 = N->getOperand(0); 832 SDOperand N1 = N->getOperand(1); 833 SDOperand LHS, RHS, CC; 834 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 835 MVT::ValueType VT = N->getValueType(0); 836 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 837 838 // fold (sext_in_reg c1) -> c1 839 if (N0C) { 840 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 841 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 842 } 843 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 844 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 845 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) { 846 return N0; 847 } 848 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 849 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 850 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 851 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 852 } 853 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 854 if (N0.getOpcode() == ISD::AssertSext && 855 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 856 return N0; 857 } 858 // fold (sext_in_reg (sextload x)) -> (sextload x) 859 if (N0.getOpcode() == ISD::SEXTLOAD && 860 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 861 return N0; 862 } 863 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 864 // FIXME: teach isSetCCEquivalent about 0, -1 and then use it here 865 if (N0.getOpcode() == ISD::SETCC && 866 TLI.getSetCCResultContents() == 867 TargetLowering::ZeroOrNegativeOneSetCCResult) 868 return N0; 869 // FIXME: this code is currently just ported over from SelectionDAG.cpp 870 // we probably actually want to handle this in two pieces. Rather than 871 // checking all the top bits for zero, just check the sign bit here and turn 872 // it into a zero extend inreg (AND with constant). 873 // then, let the code for AND figure out if the mask is superfluous rather 874 // than doing so here. 875 if (N0.getOpcode() == ISD::AND && 876 N0.getOperand(1).getOpcode() == ISD::Constant) { 877 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 878 unsigned NumBits = MVT::getSizeInBits(EVT); 879 if ((Mask & (~0ULL << (NumBits-1))) == 0) 880 return N0; 881 } 882 return SDOperand(); 883} 884 885SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 886 SDOperand N0 = N->getOperand(0); 887 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 888 MVT::ValueType VT = N->getValueType(0); 889 890 // noop truncate 891 if (N0.getValueType() == N->getValueType(0)) 892 return N0; 893 // fold (truncate c1) -> c1 894 if (N0C) 895 return DAG.getConstant(N0C->getValue(), VT); 896 // fold (truncate (truncate x)) -> (truncate x) 897 if (N0.getOpcode() == ISD::TRUNCATE) 898 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 899 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 900 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 901 if (N0.getValueType() < VT) 902 // if the source is smaller than the dest, we still need an extend 903 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 904 else if (N0.getValueType() > VT) 905 // if the source is larger than the dest, than we just need the truncate 906 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 907 else 908 // if the source and dest are the same type, we can drop both the extend 909 // and the truncate 910 return N0.getOperand(0); 911 } 912 return SDOperand(); 913} 914 915SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 916 SDOperand N0 = N->getOperand(0); 917 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 918 919 // fold (sint_to_fp c1) -> c1fp 920 if (N0C) 921 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 922 return SDOperand(); 923} 924 925SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 926 SDOperand N0 = N->getOperand(0); 927 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 928 929 // fold (uint_to_fp c1) -> c1fp 930 if (N0C) 931 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 932 return SDOperand(); 933} 934 935SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 937 938 // fold (fp_to_sint c1fp) -> c1 939 if (N0CFP) 940 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 941 return SDOperand(); 942} 943 944SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 945 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 946 947 // fold (fp_to_uint c1fp) -> c1 948 if (N0CFP) 949 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 950 return SDOperand(); 951} 952 953SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 955 956 // fold (fp_round c1fp) -> c1fp 957 if (N0CFP) 958 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 959 return SDOperand(); 960} 961 962SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 963 SDOperand N0 = N->getOperand(0); 964 MVT::ValueType VT = N->getValueType(0); 965 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 966 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 967 968 // noop fp_round_inreg 969 if (EVT == VT) 970 return N0; 971 // fold (fp_round_inreg c1fp) -> c1fp 972 if (N0CFP) { 973 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 974 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 975 } 976 return SDOperand(); 977} 978 979SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 980 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 981 982 // fold (fp_extend c1fp) -> c1fp 983 if (N0CFP) 984 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 985 return SDOperand(); 986} 987 988SDOperand DAGCombiner::visitFNEG(SDNode *N) { 989 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 990 // fold (neg c1) -> -c1 991 if (N0CFP) 992 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 993 // fold (neg (sub x, y)) -> (sub y, x) 994 if (N->getOperand(0).getOpcode() == ISD::SUB) 995 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 996 N->getOperand(0)); 997 // fold (neg (neg x)) -> x 998 if (N->getOperand(0).getOpcode() == ISD::FNEG) 999 return N->getOperand(0).getOperand(0); 1000 return SDOperand(); 1001} 1002 1003SDOperand DAGCombiner::visitFABS(SDNode *N) { 1004 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1005 // fold (fabs c1) -> fabs(c1) 1006 if (N0CFP) 1007 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1008 // fold (fabs (fabs x)) -> (fabs x) 1009 if (N->getOperand(0).getOpcode() == ISD::FABS) 1010 return N->getOperand(0); 1011 // fold (fabs (fneg x)) -> (fabs x) 1012 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1013 return DAG.getNode(ISD::FABS, N->getValueType(0), 1014 N->getOperand(0).getOperand(0)); 1015 return SDOperand(); 1016} 1017 1018// SelectionDAG::Combine - This is the entry point for the file. 1019// 1020void SelectionDAG::Combine(bool RunningAfterLegalize) { 1021 /// run - This is the main entry point to this class. 1022 /// 1023 DAGCombiner(*this).Run(RunningAfterLegalize); 1024} 1025