DAGCombiner.cpp revision 8968450305c28444edc3c272d8752a8db0c2f34a
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 55 // Worklist of all of the nodes that need to be simplified. 56 std::vector<SDNode*> WorkList; 57 58 // AA - Used for DAG load/store alias analysis. 59 AliasAnalysis &AA; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 AddToWorkList(*UI); 69 } 70 71 /// visit - call the node-specific routine that knows how to fold each 72 /// particular type of node. 73 SDOperand visit(SDNode *N); 74 75 public: 76 /// AddToWorkList - Add to the work list making sure it's instance is at the 77 /// the back (next to be processed.) 78 void AddToWorkList(SDNode *N) { 79 removeFromWorkList(N); 80 WorkList.push_back(N); 81 } 82 83 /// removeFromWorkList - remove all instances of N from the worklist. 84 /// 85 void removeFromWorkList(SDNode *N) { 86 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 87 WorkList.end()); 88 } 89 90 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 91 bool AddTo = true); 92 93 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 94 return CombineTo(N, &Res, 1, AddTo); 95 } 96 97 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 98 bool AddTo = true) { 99 SDOperand To[] = { Res0, Res1 }; 100 return CombineTo(N, To, 2, AddTo); 101 } 102 103 private: 104 105 /// SimplifyDemandedBits - Check the specified integer node value to see if 106 /// it can be simplified or if things it uses can be simplified by bit 107 /// propagation. If so, return true. 108 bool SimplifyDemandedBits(SDOperand Op) { 109 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 110 return SimplifyDemandedBits(Op, Demanded); 111 } 112 113 bool SimplifyDemandedBits(SDOperand Op, const APInt &Demanded); 114 115 bool CombineToPreIndexedLoadStore(SDNode *N); 116 bool CombineToPostIndexedLoadStore(SDNode *N); 117 118 119 /// combine - call the node-specific routine that knows how to fold each 120 /// particular type of node. If that doesn't do anything, try the 121 /// target-specific DAG combines. 122 SDOperand combine(SDNode *N); 123 124 // Visitation implementation - Implement dag node combining for different 125 // node types. The semantics are as follows: 126 // Return Value: 127 // SDOperand.Val == 0 - No change was made 128 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 129 // otherwise - N should be replaced by the returned Operand. 130 // 131 SDOperand visitTokenFactor(SDNode *N); 132 SDOperand visitMERGE_VALUES(SDNode *N); 133 SDOperand visitADD(SDNode *N); 134 SDOperand visitSUB(SDNode *N); 135 SDOperand visitADDC(SDNode *N); 136 SDOperand visitADDE(SDNode *N); 137 SDOperand visitMUL(SDNode *N); 138 SDOperand visitSDIV(SDNode *N); 139 SDOperand visitUDIV(SDNode *N); 140 SDOperand visitSREM(SDNode *N); 141 SDOperand visitUREM(SDNode *N); 142 SDOperand visitMULHU(SDNode *N); 143 SDOperand visitMULHS(SDNode *N); 144 SDOperand visitSMUL_LOHI(SDNode *N); 145 SDOperand visitUMUL_LOHI(SDNode *N); 146 SDOperand visitSDIVREM(SDNode *N); 147 SDOperand visitUDIVREM(SDNode *N); 148 SDOperand visitAND(SDNode *N); 149 SDOperand visitOR(SDNode *N); 150 SDOperand visitXOR(SDNode *N); 151 SDOperand SimplifyVBinOp(SDNode *N); 152 SDOperand visitSHL(SDNode *N); 153 SDOperand visitSRA(SDNode *N); 154 SDOperand visitSRL(SDNode *N); 155 SDOperand visitCTLZ(SDNode *N); 156 SDOperand visitCTTZ(SDNode *N); 157 SDOperand visitCTPOP(SDNode *N); 158 SDOperand visitSELECT(SDNode *N); 159 SDOperand visitSELECT_CC(SDNode *N); 160 SDOperand visitSETCC(SDNode *N); 161 SDOperand visitSIGN_EXTEND(SDNode *N); 162 SDOperand visitZERO_EXTEND(SDNode *N); 163 SDOperand visitANY_EXTEND(SDNode *N); 164 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 165 SDOperand visitTRUNCATE(SDNode *N); 166 SDOperand visitBIT_CONVERT(SDNode *N); 167 SDOperand visitBUILD_PAIR(SDNode *N); 168 SDOperand visitFADD(SDNode *N); 169 SDOperand visitFSUB(SDNode *N); 170 SDOperand visitFMUL(SDNode *N); 171 SDOperand visitFDIV(SDNode *N); 172 SDOperand visitFREM(SDNode *N); 173 SDOperand visitFCOPYSIGN(SDNode *N); 174 SDOperand visitSINT_TO_FP(SDNode *N); 175 SDOperand visitUINT_TO_FP(SDNode *N); 176 SDOperand visitFP_TO_SINT(SDNode *N); 177 SDOperand visitFP_TO_UINT(SDNode *N); 178 SDOperand visitFP_ROUND(SDNode *N); 179 SDOperand visitFP_ROUND_INREG(SDNode *N); 180 SDOperand visitFP_EXTEND(SDNode *N); 181 SDOperand visitFNEG(SDNode *N); 182 SDOperand visitFABS(SDNode *N); 183 SDOperand visitBRCOND(SDNode *N); 184 SDOperand visitBR_CC(SDNode *N); 185 SDOperand visitLOAD(SDNode *N); 186 SDOperand visitSTORE(SDNode *N); 187 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 188 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 189 SDOperand visitBUILD_VECTOR(SDNode *N); 190 SDOperand visitCONCAT_VECTORS(SDNode *N); 191 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 192 193 SDOperand XformToShuffleWithZero(SDNode *N); 194 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 195 196 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 197 198 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 199 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 200 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 201 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 202 SDOperand N3, ISD::CondCode CC, 203 bool NotExtCompare = false); 204 SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1, 205 ISD::CondCode Cond, bool foldBooleans = true); 206 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 207 unsigned HiOp); 208 SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT); 209 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 210 SDOperand BuildSDIV(SDNode *N); 211 SDOperand BuildUDIV(SDNode *N); 212 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 213 SDOperand ReduceLoadWidth(SDNode *N); 214 215 SDOperand GetDemandedBits(SDOperand V, const APInt &Mask); 216 217 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 218 /// looking for aliasing nodes and adding them to the Aliases vector. 219 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 220 SmallVector<SDOperand, 8> &Aliases); 221 222 /// isAlias - Return true if there is any possibility that the two addresses 223 /// overlap. 224 bool isAlias(SDOperand Ptr1, int64_t Size1, 225 const Value *SrcValue1, int SrcValueOffset1, 226 SDOperand Ptr2, int64_t Size2, 227 const Value *SrcValue2, int SrcValueOffset2); 228 229 /// FindAliasInfo - Extracts the relevant alias information from the memory 230 /// node. Returns true if the operand was a load. 231 bool FindAliasInfo(SDNode *N, 232 SDOperand &Ptr, int64_t &Size, 233 const Value *&SrcValue, int &SrcValueOffset); 234 235 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 236 /// looking for a better chain (aliasing node.) 237 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 238 239public: 240 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 241 : DAG(D), 242 TLI(D.getTargetLoweringInfo()), 243 AfterLegalize(false), 244 AA(A) {} 245 246 /// Run - runs the dag combiner on all nodes in the work list 247 void Run(bool RunningAfterLegalize); 248 }; 249} 250 251 252namespace { 253/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 254/// nodes from the worklist. 255class VISIBILITY_HIDDEN WorkListRemover : 256 public SelectionDAG::DAGUpdateListener { 257 DAGCombiner &DC; 258public: 259 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 260 261 virtual void NodeDeleted(SDNode *N, SDNode *E) { 262 DC.removeFromWorkList(N); 263 } 264 265 virtual void NodeUpdated(SDNode *N) { 266 // Ignore updates. 267 } 268}; 269} 270 271//===----------------------------------------------------------------------===// 272// TargetLowering::DAGCombinerInfo implementation 273//===----------------------------------------------------------------------===// 274 275void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 276 ((DAGCombiner*)DC)->AddToWorkList(N); 277} 278 279SDOperand TargetLowering::DAGCombinerInfo:: 280CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 281 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 282} 283 284SDOperand TargetLowering::DAGCombinerInfo:: 285CombineTo(SDNode *N, SDOperand Res) { 286 return ((DAGCombiner*)DC)->CombineTo(N, Res); 287} 288 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 292 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 293} 294 295 296//===----------------------------------------------------------------------===// 297// Helper Functions 298//===----------------------------------------------------------------------===// 299 300/// isNegatibleForFree - Return 1 if we can compute the negated form of the 301/// specified expression for the same cost as the expression itself, or 2 if we 302/// can compute the negated form more cheaply than the expression itself. 303static char isNegatibleForFree(SDOperand Op, bool AfterLegalize, 304 unsigned Depth = 0) { 305 // No compile time optimizations on this type. 306 if (Op.getValueType() == MVT::ppcf128) 307 return 0; 308 309 // fneg is removable even if it has multiple uses. 310 if (Op.getOpcode() == ISD::FNEG) return 2; 311 312 // Don't allow anything with multiple uses. 313 if (!Op.hasOneUse()) return 0; 314 315 // Don't recurse exponentially. 316 if (Depth > 6) return 0; 317 318 switch (Op.getOpcode()) { 319 default: return false; 320 case ISD::ConstantFP: 321 // Don't invert constant FP values after legalize. The negated constant 322 // isn't necessarily legal. 323 return AfterLegalize ? 0 : 1; 324 case ISD::FADD: 325 // FIXME: determine better conditions for this xform. 326 if (!UnsafeFPMath) return 0; 327 328 // -(A+B) -> -A - B 329 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 330 return V; 331 // -(A+B) -> -B - A 332 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 333 case ISD::FSUB: 334 // We can't turn -(A-B) into B-A when we honor signed zeros. 335 if (!UnsafeFPMath) return 0; 336 337 // -(A-B) -> B-A 338 return 1; 339 340 case ISD::FMUL: 341 case ISD::FDIV: 342 if (HonorSignDependentRoundingFPMath()) return 0; 343 344 // -(X*Y) -> (-X * Y) or (X*-Y) 345 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 346 return V; 347 348 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 349 350 case ISD::FP_EXTEND: 351 case ISD::FP_ROUND: 352 case ISD::FSIN: 353 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 354 } 355} 356 357/// GetNegatedExpression - If isNegatibleForFree returns true, this function 358/// returns the newly negated expression. 359static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 360 bool AfterLegalize, unsigned Depth = 0) { 361 // fneg is removable even if it has multiple uses. 362 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 363 364 // Don't allow anything with multiple uses. 365 assert(Op.hasOneUse() && "Unknown reuse!"); 366 367 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 368 switch (Op.getOpcode()) { 369 default: assert(0 && "Unknown code"); 370 case ISD::ConstantFP: { 371 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 372 V.changeSign(); 373 return DAG.getConstantFP(V, Op.getValueType()); 374 } 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 assert(UnsafeFPMath); 378 379 // -(A+B) -> -A - B 380 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 381 return DAG.getNode(ISD::FSUB, Op.getValueType(), 382 GetNegatedExpression(Op.getOperand(0), DAG, 383 AfterLegalize, Depth+1), 384 Op.getOperand(1)); 385 // -(A+B) -> -B - A 386 return DAG.getNode(ISD::FSUB, Op.getValueType(), 387 GetNegatedExpression(Op.getOperand(1), DAG, 388 AfterLegalize, Depth+1), 389 Op.getOperand(0)); 390 case ISD::FSUB: 391 // We can't turn -(A-B) into B-A when we honor signed zeros. 392 assert(UnsafeFPMath); 393 394 // -(0-B) -> B 395 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 396 if (N0CFP->getValueAPF().isZero()) 397 return Op.getOperand(1); 398 399 // -(A-B) -> B-A 400 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 401 Op.getOperand(0)); 402 403 case ISD::FMUL: 404 case ISD::FDIV: 405 assert(!HonorSignDependentRoundingFPMath()); 406 407 // -(X*Y) -> -X * Y 408 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 409 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 410 GetNegatedExpression(Op.getOperand(0), DAG, 411 AfterLegalize, Depth+1), 412 Op.getOperand(1)); 413 414 // -(X*Y) -> X * -Y 415 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 416 Op.getOperand(0), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 AfterLegalize, Depth+1)); 419 420 case ISD::FP_EXTEND: 421 case ISD::FSIN: 422 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 423 GetNegatedExpression(Op.getOperand(0), DAG, 424 AfterLegalize, Depth+1)); 425 case ISD::FP_ROUND: 426 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 427 GetNegatedExpression(Op.getOperand(0), DAG, 428 AfterLegalize, Depth+1), 429 Op.getOperand(1)); 430 } 431} 432 433 434// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 435// that selects between the values 1 and 0, making it equivalent to a setcc. 436// Also, set the incoming LHS, RHS, and CC references to the appropriate 437// nodes based on the type of node we are checking. This simplifies life a 438// bit for the callers. 439static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 440 SDOperand &CC) { 441 if (N.getOpcode() == ISD::SETCC) { 442 LHS = N.getOperand(0); 443 RHS = N.getOperand(1); 444 CC = N.getOperand(2); 445 return true; 446 } 447 if (N.getOpcode() == ISD::SELECT_CC && 448 N.getOperand(2).getOpcode() == ISD::Constant && 449 N.getOperand(3).getOpcode() == ISD::Constant && 450 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 451 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 452 LHS = N.getOperand(0); 453 RHS = N.getOperand(1); 454 CC = N.getOperand(4); 455 return true; 456 } 457 return false; 458} 459 460// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 461// one use. If this is true, it allows the users to invert the operation for 462// free when it is profitable to do so. 463static bool isOneUseSetCC(SDOperand N) { 464 SDOperand N0, N1, N2; 465 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 466 return true; 467 return false; 468} 469 470SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 471 MVT VT = N0.getValueType(); 472 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 473 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 474 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 475 if (isa<ConstantSDNode>(N1)) { 476 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 477 AddToWorkList(OpNode.Val); 478 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 479 } else if (N0.hasOneUse()) { 480 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 481 AddToWorkList(OpNode.Val); 482 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 483 } 484 } 485 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 486 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 487 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 488 if (isa<ConstantSDNode>(N0)) { 489 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 490 AddToWorkList(OpNode.Val); 491 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 492 } else if (N1.hasOneUse()) { 493 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 494 AddToWorkList(OpNode.Val); 495 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 496 } 497 } 498 return SDOperand(); 499} 500 501SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 502 bool AddTo) { 503 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 504 ++NodesCombined; 505 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 506 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 507 DOUT << " and " << NumTo-1 << " other values\n"; 508 WorkListRemover DeadNodes(*this); 509 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 510 511 if (AddTo) { 512 // Push the new nodes and any users onto the worklist 513 for (unsigned i = 0, e = NumTo; i != e; ++i) { 514 AddToWorkList(To[i].Val); 515 AddUsersToWorkList(To[i].Val); 516 } 517 } 518 519 // Nodes can be reintroduced into the worklist. Make sure we do not 520 // process a node that has been replaced. 521 removeFromWorkList(N); 522 523 // Finally, since the node is now dead, remove it from the graph. 524 DAG.DeleteNode(N); 525 return SDOperand(N, 0); 526} 527 528/// SimplifyDemandedBits - Check the specified integer node value to see if 529/// it can be simplified or if things it uses can be simplified by bit 530/// propagation. If so, return true. 531bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, const APInt &Demanded) { 532 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 533 APInt KnownZero, KnownOne; 534 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 535 return false; 536 537 // Revisit the node. 538 AddToWorkList(Op.Val); 539 540 // Replace the old value with the new one. 541 ++NodesCombined; 542 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 543 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 544 DOUT << '\n'; 545 546 // Replace all uses. If any nodes become isomorphic to other nodes and 547 // are deleted, make sure to remove them from our worklist. 548 WorkListRemover DeadNodes(*this); 549 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 550 551 // Push the new node and any (possibly new) users onto the worklist. 552 AddToWorkList(TLO.New.Val); 553 AddUsersToWorkList(TLO.New.Val); 554 555 // Finally, if the node is now dead, remove it from the graph. The node 556 // may not be dead if the replacement process recursively simplified to 557 // something else needing this node. 558 if (TLO.Old.Val->use_empty()) { 559 removeFromWorkList(TLO.Old.Val); 560 561 // If the operands of this node are only used by the node, they will now 562 // be dead. Make sure to visit them first to delete dead nodes early. 563 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 564 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 565 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 566 567 DAG.DeleteNode(TLO.Old.Val); 568 } 569 return true; 570} 571 572//===----------------------------------------------------------------------===// 573// Main DAG Combiner implementation 574//===----------------------------------------------------------------------===// 575 576void DAGCombiner::Run(bool RunningAfterLegalize) { 577 // set the instance variable, so that the various visit routines may use it. 578 AfterLegalize = RunningAfterLegalize; 579 580 // Add all the dag nodes to the worklist. 581 WorkList.reserve(DAG.allnodes_size()); 582 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 583 E = DAG.allnodes_end(); I != E; ++I) 584 WorkList.push_back(I); 585 586 // Create a dummy node (which is not added to allnodes), that adds a reference 587 // to the root node, preventing it from being deleted, and tracking any 588 // changes of the root. 589 HandleSDNode Dummy(DAG.getRoot()); 590 591 // The root of the dag may dangle to deleted nodes until the dag combiner is 592 // done. Set it to null to avoid confusion. 593 DAG.setRoot(SDOperand()); 594 595 // while the worklist isn't empty, inspect the node on the end of it and 596 // try and combine it. 597 while (!WorkList.empty()) { 598 SDNode *N = WorkList.back(); 599 WorkList.pop_back(); 600 601 // If N has no uses, it is dead. Make sure to revisit all N's operands once 602 // N is deleted from the DAG, since they too may now be dead or may have a 603 // reduced number of uses, allowing other xforms. 604 if (N->use_empty() && N != &Dummy) { 605 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 606 AddToWorkList(N->getOperand(i).Val); 607 608 DAG.DeleteNode(N); 609 continue; 610 } 611 612 SDOperand RV = combine(N); 613 614 if (RV.Val == 0) 615 continue; 616 617 ++NodesCombined; 618 619 // If we get back the same node we passed in, rather than a new node or 620 // zero, we know that the node must have defined multiple values and 621 // CombineTo was used. Since CombineTo takes care of the worklist 622 // mechanics for us, we have no work to do in this case. 623 if (RV.Val == N) 624 continue; 625 626 assert(N->getOpcode() != ISD::DELETED_NODE && 627 RV.Val->getOpcode() != ISD::DELETED_NODE && 628 "Node was deleted but visit returned new node!"); 629 630 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 631 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 632 DOUT << '\n'; 633 WorkListRemover DeadNodes(*this); 634 if (N->getNumValues() == RV.Val->getNumValues()) 635 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 636 else { 637 assert(N->getValueType(0) == RV.getValueType() && 638 N->getNumValues() == 1 && "Type mismatch"); 639 SDOperand OpV = RV; 640 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 641 } 642 643 // Push the new node and any users onto the worklist 644 AddToWorkList(RV.Val); 645 AddUsersToWorkList(RV.Val); 646 647 // Add any uses of the old node to the worklist in case this node is the 648 // last one that uses them. They may become dead after this node is 649 // deleted. 650 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 651 AddToWorkList(N->getOperand(i).Val); 652 653 // Nodes can be reintroduced into the worklist. Make sure we do not 654 // process a node that has been replaced. 655 removeFromWorkList(N); 656 657 // Finally, since the node is now dead, remove it from the graph. 658 DAG.DeleteNode(N); 659 } 660 661 // If the root changed (e.g. it was a dead load, update the root). 662 DAG.setRoot(Dummy.getValue()); 663} 664 665SDOperand DAGCombiner::visit(SDNode *N) { 666 switch(N->getOpcode()) { 667 default: break; 668 case ISD::TokenFactor: return visitTokenFactor(N); 669 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 670 case ISD::ADD: return visitADD(N); 671 case ISD::SUB: return visitSUB(N); 672 case ISD::ADDC: return visitADDC(N); 673 case ISD::ADDE: return visitADDE(N); 674 case ISD::MUL: return visitMUL(N); 675 case ISD::SDIV: return visitSDIV(N); 676 case ISD::UDIV: return visitUDIV(N); 677 case ISD::SREM: return visitSREM(N); 678 case ISD::UREM: return visitUREM(N); 679 case ISD::MULHU: return visitMULHU(N); 680 case ISD::MULHS: return visitMULHS(N); 681 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 682 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 683 case ISD::SDIVREM: return visitSDIVREM(N); 684 case ISD::UDIVREM: return visitUDIVREM(N); 685 case ISD::AND: return visitAND(N); 686 case ISD::OR: return visitOR(N); 687 case ISD::XOR: return visitXOR(N); 688 case ISD::SHL: return visitSHL(N); 689 case ISD::SRA: return visitSRA(N); 690 case ISD::SRL: return visitSRL(N); 691 case ISD::CTLZ: return visitCTLZ(N); 692 case ISD::CTTZ: return visitCTTZ(N); 693 case ISD::CTPOP: return visitCTPOP(N); 694 case ISD::SELECT: return visitSELECT(N); 695 case ISD::SELECT_CC: return visitSELECT_CC(N); 696 case ISD::SETCC: return visitSETCC(N); 697 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 698 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 699 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 700 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 701 case ISD::TRUNCATE: return visitTRUNCATE(N); 702 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 703 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 704 case ISD::FADD: return visitFADD(N); 705 case ISD::FSUB: return visitFSUB(N); 706 case ISD::FMUL: return visitFMUL(N); 707 case ISD::FDIV: return visitFDIV(N); 708 case ISD::FREM: return visitFREM(N); 709 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 710 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 711 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 712 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 713 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 714 case ISD::FP_ROUND: return visitFP_ROUND(N); 715 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 716 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 717 case ISD::FNEG: return visitFNEG(N); 718 case ISD::FABS: return visitFABS(N); 719 case ISD::BRCOND: return visitBRCOND(N); 720 case ISD::BR_CC: return visitBR_CC(N); 721 case ISD::LOAD: return visitLOAD(N); 722 case ISD::STORE: return visitSTORE(N); 723 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 724 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 725 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 726 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 727 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 728 } 729 return SDOperand(); 730} 731 732SDOperand DAGCombiner::combine(SDNode *N) { 733 734 SDOperand RV = visit(N); 735 736 // If nothing happened, try a target-specific DAG combine. 737 if (RV.Val == 0) { 738 assert(N->getOpcode() != ISD::DELETED_NODE && 739 "Node was deleted but visit returned NULL!"); 740 741 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 742 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 743 744 // Expose the DAG combiner to the target combiner impls. 745 TargetLowering::DAGCombinerInfo 746 DagCombineInfo(DAG, !AfterLegalize, false, this); 747 748 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 749 } 750 } 751 752 // If N is a commutative binary node, try commuting it to enable more 753 // sdisel CSE. 754 if (RV.Val == 0 && 755 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 756 N->getNumValues() == 1) { 757 SDOperand N0 = N->getOperand(0); 758 SDOperand N1 = N->getOperand(1); 759 // Constant operands are canonicalized to RHS. 760 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 761 SDOperand Ops[] = { N1, N0 }; 762 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 763 Ops, 2); 764 if (CSENode) 765 return SDOperand(CSENode, 0); 766 } 767 } 768 769 return RV; 770} 771 772/// getInputChainForNode - Given a node, return its input chain if it has one, 773/// otherwise return a null sd operand. 774static SDOperand getInputChainForNode(SDNode *N) { 775 if (unsigned NumOps = N->getNumOperands()) { 776 if (N->getOperand(0).getValueType() == MVT::Other) 777 return N->getOperand(0); 778 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 779 return N->getOperand(NumOps-1); 780 for (unsigned i = 1; i < NumOps-1; ++i) 781 if (N->getOperand(i).getValueType() == MVT::Other) 782 return N->getOperand(i); 783 } 784 return SDOperand(0, 0); 785} 786 787SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 788 // If N has two operands, where one has an input chain equal to the other, 789 // the 'other' chain is redundant. 790 if (N->getNumOperands() == 2) { 791 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 792 return N->getOperand(0); 793 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 794 return N->getOperand(1); 795 } 796 797 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 798 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 799 SmallPtrSet<SDNode*, 16> SeenOps; 800 bool Changed = false; // If we should replace this token factor. 801 802 // Start out with this token factor. 803 TFs.push_back(N); 804 805 // Iterate through token factors. The TFs grows when new token factors are 806 // encountered. 807 for (unsigned i = 0; i < TFs.size(); ++i) { 808 SDNode *TF = TFs[i]; 809 810 // Check each of the operands. 811 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 812 SDOperand Op = TF->getOperand(i); 813 814 switch (Op.getOpcode()) { 815 case ISD::EntryToken: 816 // Entry tokens don't need to be added to the list. They are 817 // rededundant. 818 Changed = true; 819 break; 820 821 case ISD::TokenFactor: 822 if ((CombinerAA || Op.hasOneUse()) && 823 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 824 // Queue up for processing. 825 TFs.push_back(Op.Val); 826 // Clean up in case the token factor is removed. 827 AddToWorkList(Op.Val); 828 Changed = true; 829 break; 830 } 831 // Fall thru 832 833 default: 834 // Only add if it isn't already in the list. 835 if (SeenOps.insert(Op.Val)) 836 Ops.push_back(Op); 837 else 838 Changed = true; 839 break; 840 } 841 } 842 } 843 844 SDOperand Result; 845 846 // If we've change things around then replace token factor. 847 if (Changed) { 848 if (Ops.empty()) { 849 // The entry token is the only possible outcome. 850 Result = DAG.getEntryNode(); 851 } else { 852 // New and improved token factor. 853 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 854 } 855 856 // Don't add users to work list. 857 return CombineTo(N, Result, false); 858 } 859 860 return Result; 861} 862 863/// MERGE_VALUES can always be eliminated. 864SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 865 WorkListRemover DeadNodes(*this); 866 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 867 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 868 &DeadNodes); 869 removeFromWorkList(N); 870 DAG.DeleteNode(N); 871 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 872} 873 874 875static 876SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 877 MVT VT = N0.getValueType(); 878 SDOperand N00 = N0.getOperand(0); 879 SDOperand N01 = N0.getOperand(1); 880 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 881 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 882 isa<ConstantSDNode>(N00.getOperand(1))) { 883 N0 = DAG.getNode(ISD::ADD, VT, 884 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 885 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 886 return DAG.getNode(ISD::ADD, VT, N0, N1); 887 } 888 return SDOperand(); 889} 890 891static 892SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 893 SelectionDAG &DAG) { 894 MVT VT = N->getValueType(0); 895 unsigned Opc = N->getOpcode(); 896 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 897 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 898 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 899 ISD::CondCode CC = ISD::SETCC_INVALID; 900 if (isSlctCC) 901 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 902 else { 903 SDOperand CCOp = Slct.getOperand(0); 904 if (CCOp.getOpcode() == ISD::SETCC) 905 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 906 } 907 908 bool DoXform = false; 909 bool InvCC = false; 910 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 911 "Bad input!"); 912 if (LHS.getOpcode() == ISD::Constant && 913 cast<ConstantSDNode>(LHS)->isNullValue()) 914 DoXform = true; 915 else if (CC != ISD::SETCC_INVALID && 916 RHS.getOpcode() == ISD::Constant && 917 cast<ConstantSDNode>(RHS)->isNullValue()) { 918 std::swap(LHS, RHS); 919 SDOperand Op0 = Slct.getOperand(0); 920 bool isInt = (isSlctCC ? Op0.getValueType() : 921 Op0.getOperand(0).getValueType()).isInteger(); 922 CC = ISD::getSetCCInverse(CC, isInt); 923 DoXform = true; 924 InvCC = true; 925 } 926 927 if (DoXform) { 928 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 929 if (isSlctCC) 930 return DAG.getSelectCC(OtherOp, Result, 931 Slct.getOperand(0), Slct.getOperand(1), CC); 932 SDOperand CCOp = Slct.getOperand(0); 933 if (InvCC) 934 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 935 CCOp.getOperand(1), CC); 936 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 937 } 938 return SDOperand(); 939} 940 941SDOperand DAGCombiner::visitADD(SDNode *N) { 942 SDOperand N0 = N->getOperand(0); 943 SDOperand N1 = N->getOperand(1); 944 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 946 MVT VT = N0.getValueType(); 947 948 // fold vector ops 949 if (VT.isVector()) { 950 SDOperand FoldedVOp = SimplifyVBinOp(N); 951 if (FoldedVOp.Val) return FoldedVOp; 952 } 953 954 // fold (add x, undef) -> undef 955 if (N0.getOpcode() == ISD::UNDEF) 956 return N0; 957 if (N1.getOpcode() == ISD::UNDEF) 958 return N1; 959 // fold (add c1, c2) -> c1+c2 960 if (N0C && N1C) 961 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 962 // canonicalize constant to RHS 963 if (N0C && !N1C) 964 return DAG.getNode(ISD::ADD, VT, N1, N0); 965 // fold (add x, 0) -> x 966 if (N1C && N1C->isNullValue()) 967 return N0; 968 // fold ((c1-A)+c2) -> (c1+c2)-A 969 if (N1C && N0.getOpcode() == ISD::SUB) 970 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 971 return DAG.getNode(ISD::SUB, VT, 972 DAG.getConstant(N1C->getAPIntValue()+ 973 N0C->getAPIntValue(), VT), 974 N0.getOperand(1)); 975 // reassociate add 976 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 977 if (RADD.Val != 0) 978 return RADD; 979 // fold ((0-A) + B) -> B-A 980 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 981 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 982 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 983 // fold (A + (0-B)) -> A-B 984 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 985 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 986 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 987 // fold (A+(B-A)) -> B 988 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 989 return N1.getOperand(0); 990 991 if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0))) 992 return SDOperand(N, 0); 993 994 // fold (a+b) -> (a|b) iff a and b share no bits. 995 if (VT.isInteger() && !VT.isVector()) { 996 APInt LHSZero, LHSOne; 997 APInt RHSZero, RHSOne; 998 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 999 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1000 if (LHSZero.getBoolValue()) { 1001 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1002 1003 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1004 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1005 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1006 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1007 return DAG.getNode(ISD::OR, VT, N0, N1); 1008 } 1009 } 1010 1011 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1012 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1013 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 1014 if (Result.Val) return Result; 1015 } 1016 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1017 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 1018 if (Result.Val) return Result; 1019 } 1020 1021 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1022 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1023 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1024 if (Result.Val) return Result; 1025 } 1026 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1027 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1028 if (Result.Val) return Result; 1029 } 1030 1031 return SDOperand(); 1032} 1033 1034SDOperand DAGCombiner::visitADDC(SDNode *N) { 1035 SDOperand N0 = N->getOperand(0); 1036 SDOperand N1 = N->getOperand(1); 1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1039 MVT VT = N0.getValueType(); 1040 1041 // If the flag result is dead, turn this into an ADD. 1042 if (N->hasNUsesOfValue(0, 1)) 1043 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1044 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1045 1046 // canonicalize constant to RHS. 1047 if (N0C && !N1C) 1048 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1049 1050 // fold (addc x, 0) -> x + no carry out 1051 if (N1C && N1C->isNullValue()) 1052 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1053 1054 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1055 APInt LHSZero, LHSOne; 1056 APInt RHSZero, RHSOne; 1057 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1058 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1059 if (LHSZero.getBoolValue()) { 1060 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1061 1062 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1063 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1064 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1065 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1066 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1067 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1068 } 1069 1070 return SDOperand(); 1071} 1072 1073SDOperand DAGCombiner::visitADDE(SDNode *N) { 1074 SDOperand N0 = N->getOperand(0); 1075 SDOperand N1 = N->getOperand(1); 1076 SDOperand CarryIn = N->getOperand(2); 1077 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1078 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1079 //MVT VT = N0.getValueType(); 1080 1081 // canonicalize constant to RHS 1082 if (N0C && !N1C) 1083 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1084 1085 // fold (adde x, y, false) -> (addc x, y) 1086 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1087 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1088 1089 return SDOperand(); 1090} 1091 1092 1093 1094SDOperand DAGCombiner::visitSUB(SDNode *N) { 1095 SDOperand N0 = N->getOperand(0); 1096 SDOperand N1 = N->getOperand(1); 1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1099 MVT VT = N0.getValueType(); 1100 1101 // fold vector ops 1102 if (VT.isVector()) { 1103 SDOperand FoldedVOp = SimplifyVBinOp(N); 1104 if (FoldedVOp.Val) return FoldedVOp; 1105 } 1106 1107 // fold (sub x, x) -> 0 1108 if (N0 == N1) 1109 return DAG.getConstant(0, N->getValueType(0)); 1110 // fold (sub c1, c2) -> c1-c2 1111 if (N0C && N1C) 1112 return DAG.getNode(ISD::SUB, VT, N0, N1); 1113 // fold (sub x, c) -> (add x, -c) 1114 if (N1C) 1115 return DAG.getNode(ISD::ADD, VT, N0, 1116 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1117 // fold (A+B)-A -> B 1118 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1119 return N0.getOperand(1); 1120 // fold (A+B)-B -> A 1121 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1122 return N0.getOperand(0); 1123 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1124 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1125 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1126 if (Result.Val) return Result; 1127 } 1128 // If either operand of a sub is undef, the result is undef 1129 if (N0.getOpcode() == ISD::UNDEF) 1130 return N0; 1131 if (N1.getOpcode() == ISD::UNDEF) 1132 return N1; 1133 1134 return SDOperand(); 1135} 1136 1137SDOperand DAGCombiner::visitMUL(SDNode *N) { 1138 SDOperand N0 = N->getOperand(0); 1139 SDOperand N1 = N->getOperand(1); 1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1141 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1142 MVT VT = N0.getValueType(); 1143 1144 // fold vector ops 1145 if (VT.isVector()) { 1146 SDOperand FoldedVOp = SimplifyVBinOp(N); 1147 if (FoldedVOp.Val) return FoldedVOp; 1148 } 1149 1150 // fold (mul x, undef) -> 0 1151 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1152 return DAG.getConstant(0, VT); 1153 // fold (mul c1, c2) -> c1*c2 1154 if (N0C && N1C) 1155 return DAG.getNode(ISD::MUL, VT, N0, N1); 1156 // canonicalize constant to RHS 1157 if (N0C && !N1C) 1158 return DAG.getNode(ISD::MUL, VT, N1, N0); 1159 // fold (mul x, 0) -> 0 1160 if (N1C && N1C->isNullValue()) 1161 return N1; 1162 // fold (mul x, -1) -> 0-x 1163 if (N1C && N1C->isAllOnesValue()) 1164 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1165 // fold (mul x, (1 << c)) -> x << c 1166 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1167 return DAG.getNode(ISD::SHL, VT, N0, 1168 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1169 TLI.getShiftAmountTy())); 1170 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1171 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1172 // FIXME: If the input is something that is easily negated (e.g. a 1173 // single-use add), we should put the negate there. 1174 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1175 DAG.getNode(ISD::SHL, VT, N0, 1176 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1177 TLI.getShiftAmountTy()))); 1178 } 1179 1180 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1181 if (N1C && N0.getOpcode() == ISD::SHL && 1182 isa<ConstantSDNode>(N0.getOperand(1))) { 1183 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1184 AddToWorkList(C3.Val); 1185 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1186 } 1187 1188 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1189 // use. 1190 { 1191 SDOperand Sh(0,0), Y(0,0); 1192 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1193 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1194 N0.Val->hasOneUse()) { 1195 Sh = N0; Y = N1; 1196 } else if (N1.getOpcode() == ISD::SHL && 1197 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1198 Sh = N1; Y = N0; 1199 } 1200 if (Sh.Val) { 1201 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1202 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1203 } 1204 } 1205 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1206 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1207 isa<ConstantSDNode>(N0.getOperand(1))) { 1208 return DAG.getNode(ISD::ADD, VT, 1209 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1210 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1211 } 1212 1213 // reassociate mul 1214 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1215 if (RMUL.Val != 0) 1216 return RMUL; 1217 1218 return SDOperand(); 1219} 1220 1221SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1222 SDOperand N0 = N->getOperand(0); 1223 SDOperand N1 = N->getOperand(1); 1224 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1225 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1226 MVT VT = N->getValueType(0); 1227 1228 // fold vector ops 1229 if (VT.isVector()) { 1230 SDOperand FoldedVOp = SimplifyVBinOp(N); 1231 if (FoldedVOp.Val) return FoldedVOp; 1232 } 1233 1234 // fold (sdiv c1, c2) -> c1/c2 1235 if (N0C && N1C && !N1C->isNullValue()) 1236 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1237 // fold (sdiv X, 1) -> X 1238 if (N1C && N1C->getSignExtended() == 1LL) 1239 return N0; 1240 // fold (sdiv X, -1) -> 0-X 1241 if (N1C && N1C->isAllOnesValue()) 1242 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1243 // If we know the sign bits of both operands are zero, strength reduce to a 1244 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1245 if (!VT.isVector()) { 1246 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1247 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1248 } 1249 // fold (sdiv X, pow2) -> simple ops after legalize 1250 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1251 (isPowerOf2_64(N1C->getSignExtended()) || 1252 isPowerOf2_64(-N1C->getSignExtended()))) { 1253 // If dividing by powers of two is cheap, then don't perform the following 1254 // fold. 1255 if (TLI.isPow2DivCheap()) 1256 return SDOperand(); 1257 int64_t pow2 = N1C->getSignExtended(); 1258 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1259 unsigned lg2 = Log2_64(abs2); 1260 // Splat the sign bit into the register 1261 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1262 DAG.getConstant(VT.getSizeInBits()-1, 1263 TLI.getShiftAmountTy())); 1264 AddToWorkList(SGN.Val); 1265 // Add (N0 < 0) ? abs2 - 1 : 0; 1266 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1267 DAG.getConstant(VT.getSizeInBits()-lg2, 1268 TLI.getShiftAmountTy())); 1269 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1270 AddToWorkList(SRL.Val); 1271 AddToWorkList(ADD.Val); // Divide by pow2 1272 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1273 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1274 // If we're dividing by a positive value, we're done. Otherwise, we must 1275 // negate the result. 1276 if (pow2 > 0) 1277 return SRA; 1278 AddToWorkList(SRA.Val); 1279 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1280 } 1281 // if integer divide is expensive and we satisfy the requirements, emit an 1282 // alternate sequence. 1283 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1284 !TLI.isIntDivCheap()) { 1285 SDOperand Op = BuildSDIV(N); 1286 if (Op.Val) return Op; 1287 } 1288 1289 // undef / X -> 0 1290 if (N0.getOpcode() == ISD::UNDEF) 1291 return DAG.getConstant(0, VT); 1292 // X / undef -> undef 1293 if (N1.getOpcode() == ISD::UNDEF) 1294 return N1; 1295 1296 return SDOperand(); 1297} 1298 1299SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1300 SDOperand N0 = N->getOperand(0); 1301 SDOperand N1 = N->getOperand(1); 1302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1304 MVT VT = N->getValueType(0); 1305 1306 // fold vector ops 1307 if (VT.isVector()) { 1308 SDOperand FoldedVOp = SimplifyVBinOp(N); 1309 if (FoldedVOp.Val) return FoldedVOp; 1310 } 1311 1312 // fold (udiv c1, c2) -> c1/c2 1313 if (N0C && N1C && !N1C->isNullValue()) 1314 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1315 // fold (udiv x, (1 << c)) -> x >>u c 1316 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1317 return DAG.getNode(ISD::SRL, VT, N0, 1318 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1319 TLI.getShiftAmountTy())); 1320 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1321 if (N1.getOpcode() == ISD::SHL) { 1322 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1323 if (SHC->getAPIntValue().isPowerOf2()) { 1324 MVT ADDVT = N1.getOperand(1).getValueType(); 1325 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1326 DAG.getConstant(SHC->getAPIntValue() 1327 .logBase2(), 1328 ADDVT)); 1329 AddToWorkList(Add.Val); 1330 return DAG.getNode(ISD::SRL, VT, N0, Add); 1331 } 1332 } 1333 } 1334 // fold (udiv x, c) -> alternate 1335 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1336 SDOperand Op = BuildUDIV(N); 1337 if (Op.Val) return Op; 1338 } 1339 1340 // undef / X -> 0 1341 if (N0.getOpcode() == ISD::UNDEF) 1342 return DAG.getConstant(0, VT); 1343 // X / undef -> undef 1344 if (N1.getOpcode() == ISD::UNDEF) 1345 return N1; 1346 1347 return SDOperand(); 1348} 1349 1350SDOperand DAGCombiner::visitSREM(SDNode *N) { 1351 SDOperand N0 = N->getOperand(0); 1352 SDOperand N1 = N->getOperand(1); 1353 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1354 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1355 MVT VT = N->getValueType(0); 1356 1357 // fold (srem c1, c2) -> c1%c2 1358 if (N0C && N1C && !N1C->isNullValue()) 1359 return DAG.getNode(ISD::SREM, VT, N0, N1); 1360 // If we know the sign bits of both operands are zero, strength reduce to a 1361 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1362 if (!VT.isVector()) { 1363 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1364 return DAG.getNode(ISD::UREM, VT, N0, N1); 1365 } 1366 1367 // If X/C can be simplified by the division-by-constant logic, lower 1368 // X%C to the equivalent of X-X/C*C. 1369 if (N1C && !N1C->isNullValue()) { 1370 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1371 AddToWorkList(Div.Val); 1372 SDOperand OptimizedDiv = combine(Div.Val); 1373 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1374 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1375 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1376 AddToWorkList(Mul.Val); 1377 return Sub; 1378 } 1379 } 1380 1381 // undef % X -> 0 1382 if (N0.getOpcode() == ISD::UNDEF) 1383 return DAG.getConstant(0, VT); 1384 // X % undef -> undef 1385 if (N1.getOpcode() == ISD::UNDEF) 1386 return N1; 1387 1388 return SDOperand(); 1389} 1390 1391SDOperand DAGCombiner::visitUREM(SDNode *N) { 1392 SDOperand N0 = N->getOperand(0); 1393 SDOperand N1 = N->getOperand(1); 1394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1395 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1396 MVT VT = N->getValueType(0); 1397 1398 // fold (urem c1, c2) -> c1%c2 1399 if (N0C && N1C && !N1C->isNullValue()) 1400 return DAG.getNode(ISD::UREM, VT, N0, N1); 1401 // fold (urem x, pow2) -> (and x, pow2-1) 1402 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1403 return DAG.getNode(ISD::AND, VT, N0, 1404 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1405 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1406 if (N1.getOpcode() == ISD::SHL) { 1407 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1408 if (SHC->getAPIntValue().isPowerOf2()) { 1409 SDOperand Add = 1410 DAG.getNode(ISD::ADD, VT, N1, 1411 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1412 VT)); 1413 AddToWorkList(Add.Val); 1414 return DAG.getNode(ISD::AND, VT, N0, Add); 1415 } 1416 } 1417 } 1418 1419 // If X/C can be simplified by the division-by-constant logic, lower 1420 // X%C to the equivalent of X-X/C*C. 1421 if (N1C && !N1C->isNullValue()) { 1422 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1423 SDOperand OptimizedDiv = combine(Div.Val); 1424 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1425 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1426 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1427 AddToWorkList(Mul.Val); 1428 return Sub; 1429 } 1430 } 1431 1432 // undef % X -> 0 1433 if (N0.getOpcode() == ISD::UNDEF) 1434 return DAG.getConstant(0, VT); 1435 // X % undef -> undef 1436 if (N1.getOpcode() == ISD::UNDEF) 1437 return N1; 1438 1439 return SDOperand(); 1440} 1441 1442SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1443 SDOperand N0 = N->getOperand(0); 1444 SDOperand N1 = N->getOperand(1); 1445 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1446 MVT VT = N->getValueType(0); 1447 1448 // fold (mulhs x, 0) -> 0 1449 if (N1C && N1C->isNullValue()) 1450 return N1; 1451 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1452 if (N1C && N1C->getAPIntValue() == 1) 1453 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1454 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1455 TLI.getShiftAmountTy())); 1456 // fold (mulhs x, undef) -> 0 1457 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1458 return DAG.getConstant(0, VT); 1459 1460 return SDOperand(); 1461} 1462 1463SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1464 SDOperand N0 = N->getOperand(0); 1465 SDOperand N1 = N->getOperand(1); 1466 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1467 MVT VT = N->getValueType(0); 1468 1469 // fold (mulhu x, 0) -> 0 1470 if (N1C && N1C->isNullValue()) 1471 return N1; 1472 // fold (mulhu x, 1) -> 0 1473 if (N1C && N1C->getAPIntValue() == 1) 1474 return DAG.getConstant(0, N0.getValueType()); 1475 // fold (mulhu x, undef) -> 0 1476 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1477 return DAG.getConstant(0, VT); 1478 1479 return SDOperand(); 1480} 1481 1482/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1483/// compute two values. LoOp and HiOp give the opcodes for the two computations 1484/// that are being performed. Return true if a simplification was made. 1485/// 1486SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1487 unsigned HiOp) { 1488 // If the high half is not needed, just compute the low half. 1489 bool HiExists = N->hasAnyUseOfValue(1); 1490 if (!HiExists && 1491 (!AfterLegalize || 1492 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1493 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1494 N->getNumOperands()); 1495 return CombineTo(N, Res, Res); 1496 } 1497 1498 // If the low half is not needed, just compute the high half. 1499 bool LoExists = N->hasAnyUseOfValue(0); 1500 if (!LoExists && 1501 (!AfterLegalize || 1502 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1503 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1504 N->getNumOperands()); 1505 return CombineTo(N, Res, Res); 1506 } 1507 1508 // If both halves are used, return as it is. 1509 if (LoExists && HiExists) 1510 return SDOperand(); 1511 1512 // If the two computed results can be simplified separately, separate them. 1513 if (LoExists) { 1514 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1515 N->op_begin(), N->getNumOperands()); 1516 AddToWorkList(Lo.Val); 1517 SDOperand LoOpt = combine(Lo.Val); 1518 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1519 (!AfterLegalize || 1520 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1521 return CombineTo(N, LoOpt, LoOpt); 1522 } 1523 1524 if (HiExists) { 1525 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1526 N->op_begin(), N->getNumOperands()); 1527 AddToWorkList(Hi.Val); 1528 SDOperand HiOpt = combine(Hi.Val); 1529 if (HiOpt.Val && HiOpt != Hi && 1530 (!AfterLegalize || 1531 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1532 return CombineTo(N, HiOpt, HiOpt); 1533 } 1534 return SDOperand(); 1535} 1536 1537SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1538 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1539 if (Res.Val) return Res; 1540 1541 return SDOperand(); 1542} 1543 1544SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1545 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1546 if (Res.Val) return Res; 1547 1548 return SDOperand(); 1549} 1550 1551SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1552 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1553 if (Res.Val) return Res; 1554 1555 return SDOperand(); 1556} 1557 1558SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1559 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1560 if (Res.Val) return Res; 1561 1562 return SDOperand(); 1563} 1564 1565/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1566/// two operands of the same opcode, try to simplify it. 1567SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1568 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1569 MVT VT = N0.getValueType(); 1570 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1571 1572 // For each of OP in AND/OR/XOR: 1573 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1574 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1575 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1576 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1577 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1578 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1579 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1580 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1581 N0.getOperand(0).getValueType(), 1582 N0.getOperand(0), N1.getOperand(0)); 1583 AddToWorkList(ORNode.Val); 1584 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1585 } 1586 1587 // For each of OP in SHL/SRL/SRA/AND... 1588 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1589 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1590 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1591 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1592 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1593 N0.getOperand(1) == N1.getOperand(1)) { 1594 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1595 N0.getOperand(0).getValueType(), 1596 N0.getOperand(0), N1.getOperand(0)); 1597 AddToWorkList(ORNode.Val); 1598 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1599 } 1600 1601 return SDOperand(); 1602} 1603 1604SDOperand DAGCombiner::visitAND(SDNode *N) { 1605 SDOperand N0 = N->getOperand(0); 1606 SDOperand N1 = N->getOperand(1); 1607 SDOperand LL, LR, RL, RR, CC0, CC1; 1608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1610 MVT VT = N1.getValueType(); 1611 unsigned BitWidth = VT.getSizeInBits(); 1612 1613 // fold vector ops 1614 if (VT.isVector()) { 1615 SDOperand FoldedVOp = SimplifyVBinOp(N); 1616 if (FoldedVOp.Val) return FoldedVOp; 1617 } 1618 1619 // fold (and x, undef) -> 0 1620 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1621 return DAG.getConstant(0, VT); 1622 // fold (and c1, c2) -> c1&c2 1623 if (N0C && N1C) 1624 return DAG.getNode(ISD::AND, VT, N0, N1); 1625 // canonicalize constant to RHS 1626 if (N0C && !N1C) 1627 return DAG.getNode(ISD::AND, VT, N1, N0); 1628 // fold (and x, -1) -> x 1629 if (N1C && N1C->isAllOnesValue()) 1630 return N0; 1631 // if (and x, c) is known to be zero, return 0 1632 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 1633 APInt::getAllOnesValue(BitWidth))) 1634 return DAG.getConstant(0, VT); 1635 // reassociate and 1636 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1637 if (RAND.Val != 0) 1638 return RAND; 1639 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1640 if (N1C && N0.getOpcode() == ISD::OR) 1641 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1642 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1643 return N1; 1644 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1645 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1646 SDOperand N0Op0 = N0.getOperand(0); 1647 APInt Mask = ~N1C->getAPIntValue(); 1648 Mask.trunc(N0Op0.getValueSizeInBits()); 1649 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1650 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1651 N0Op0); 1652 1653 // Replace uses of the AND with uses of the Zero extend node. 1654 CombineTo(N, Zext); 1655 1656 // We actually want to replace all uses of the any_extend with the 1657 // zero_extend, to avoid duplicating things. This will later cause this 1658 // AND to be folded. 1659 CombineTo(N0.Val, Zext); 1660 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1661 } 1662 } 1663 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1664 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1665 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1666 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1667 1668 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1669 LL.getValueType().isInteger()) { 1670 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1671 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1672 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1673 AddToWorkList(ORNode.Val); 1674 return DAG.getSetCC(VT, ORNode, LR, Op1); 1675 } 1676 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1677 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1678 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1679 AddToWorkList(ANDNode.Val); 1680 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1681 } 1682 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1683 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1684 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1685 AddToWorkList(ORNode.Val); 1686 return DAG.getSetCC(VT, ORNode, LR, Op1); 1687 } 1688 } 1689 // canonicalize equivalent to ll == rl 1690 if (LL == RR && LR == RL) { 1691 Op1 = ISD::getSetCCSwappedOperands(Op1); 1692 std::swap(RL, RR); 1693 } 1694 if (LL == RL && LR == RR) { 1695 bool isInteger = LL.getValueType().isInteger(); 1696 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1697 if (Result != ISD::SETCC_INVALID) 1698 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1699 } 1700 } 1701 1702 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1703 if (N0.getOpcode() == N1.getOpcode()) { 1704 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1705 if (Tmp.Val) return Tmp; 1706 } 1707 1708 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1709 // fold (and (sra)) -> (and (srl)) when possible. 1710 if (!VT.isVector() && 1711 SimplifyDemandedBits(SDOperand(N, 0))) 1712 return SDOperand(N, 0); 1713 // fold (zext_inreg (extload x)) -> (zextload x) 1714 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1715 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1716 MVT EVT = LN0->getMemoryVT(); 1717 // If we zero all the possible extended bits, then we can turn this into 1718 // a zextload if we are running before legalize or the operation is legal. 1719 unsigned BitWidth = N1.getValueSizeInBits(); 1720 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1721 BitWidth - EVT.getSizeInBits())) && 1722 ((!AfterLegalize && !LN0->isVolatile()) || 1723 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1724 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1725 LN0->getBasePtr(), LN0->getSrcValue(), 1726 LN0->getSrcValueOffset(), EVT, 1727 LN0->isVolatile(), 1728 LN0->getAlignment()); 1729 AddToWorkList(N); 1730 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1731 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1732 } 1733 } 1734 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1735 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1736 N0.hasOneUse()) { 1737 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1738 MVT EVT = LN0->getMemoryVT(); 1739 // If we zero all the possible extended bits, then we can turn this into 1740 // a zextload if we are running before legalize or the operation is legal. 1741 unsigned BitWidth = N1.getValueSizeInBits(); 1742 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1743 BitWidth - EVT.getSizeInBits())) && 1744 ((!AfterLegalize && !LN0->isVolatile()) || 1745 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1746 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1747 LN0->getBasePtr(), LN0->getSrcValue(), 1748 LN0->getSrcValueOffset(), EVT, 1749 LN0->isVolatile(), 1750 LN0->getAlignment()); 1751 AddToWorkList(N); 1752 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1753 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1754 } 1755 } 1756 1757 // fold (and (load x), 255) -> (zextload x, i8) 1758 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1759 if (N1C && N0.getOpcode() == ISD::LOAD) { 1760 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1761 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1762 LN0->isUnindexed() && N0.hasOneUse() && 1763 // Do not change the width of a volatile load. 1764 !LN0->isVolatile()) { 1765 MVT EVT = MVT::Other; 1766 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1767 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1768 EVT = MVT::getIntegerVT(ActiveBits); 1769 1770 MVT LoadedVT = LN0->getMemoryVT(); 1771 // Do not generate loads of non-round integer types since these can 1772 // be expensive (and would be wrong if the type is not byte sized). 1773 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1774 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1775 MVT PtrType = N0.getOperand(1).getValueType(); 1776 // For big endian targets, we need to add an offset to the pointer to 1777 // load the correct bytes. For little endian systems, we merely need to 1778 // read fewer bytes from the same pointer. 1779 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1780 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1781 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1782 unsigned Alignment = LN0->getAlignment(); 1783 SDOperand NewPtr = LN0->getBasePtr(); 1784 if (TLI.isBigEndian()) { 1785 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1786 DAG.getConstant(PtrOff, PtrType)); 1787 Alignment = MinAlign(Alignment, PtrOff); 1788 } 1789 AddToWorkList(NewPtr.Val); 1790 SDOperand Load = 1791 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1792 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1793 LN0->isVolatile(), Alignment); 1794 AddToWorkList(N); 1795 CombineTo(N0.Val, Load, Load.getValue(1)); 1796 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1797 } 1798 } 1799 } 1800 1801 return SDOperand(); 1802} 1803 1804SDOperand DAGCombiner::visitOR(SDNode *N) { 1805 SDOperand N0 = N->getOperand(0); 1806 SDOperand N1 = N->getOperand(1); 1807 SDOperand LL, LR, RL, RR, CC0, CC1; 1808 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1809 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1810 MVT VT = N1.getValueType(); 1811 1812 // fold vector ops 1813 if (VT.isVector()) { 1814 SDOperand FoldedVOp = SimplifyVBinOp(N); 1815 if (FoldedVOp.Val) return FoldedVOp; 1816 } 1817 1818 // fold (or x, undef) -> -1 1819 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1820 return DAG.getConstant(~0ULL, VT); 1821 // fold (or c1, c2) -> c1|c2 1822 if (N0C && N1C) 1823 return DAG.getNode(ISD::OR, VT, N0, N1); 1824 // canonicalize constant to RHS 1825 if (N0C && !N1C) 1826 return DAG.getNode(ISD::OR, VT, N1, N0); 1827 // fold (or x, 0) -> x 1828 if (N1C && N1C->isNullValue()) 1829 return N0; 1830 // fold (or x, -1) -> -1 1831 if (N1C && N1C->isAllOnesValue()) 1832 return N1; 1833 // fold (or x, c) -> c iff (x & ~c) == 0 1834 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1835 return N1; 1836 // reassociate or 1837 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1838 if (ROR.Val != 0) 1839 return ROR; 1840 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1841 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1842 isa<ConstantSDNode>(N0.getOperand(1))) { 1843 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1844 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1845 N1), 1846 DAG.getConstant(N1C->getAPIntValue() | 1847 C1->getAPIntValue(), VT)); 1848 } 1849 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1850 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1851 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1852 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1853 1854 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1855 LL.getValueType().isInteger()) { 1856 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1857 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1858 if (cast<ConstantSDNode>(LR)->isNullValue() && 1859 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1860 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1861 AddToWorkList(ORNode.Val); 1862 return DAG.getSetCC(VT, ORNode, LR, Op1); 1863 } 1864 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1865 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1866 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1867 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1868 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1869 AddToWorkList(ANDNode.Val); 1870 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1871 } 1872 } 1873 // canonicalize equivalent to ll == rl 1874 if (LL == RR && LR == RL) { 1875 Op1 = ISD::getSetCCSwappedOperands(Op1); 1876 std::swap(RL, RR); 1877 } 1878 if (LL == RL && LR == RR) { 1879 bool isInteger = LL.getValueType().isInteger(); 1880 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1881 if (Result != ISD::SETCC_INVALID) 1882 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1883 } 1884 } 1885 1886 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1887 if (N0.getOpcode() == N1.getOpcode()) { 1888 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1889 if (Tmp.Val) return Tmp; 1890 } 1891 1892 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1893 if (N0.getOpcode() == ISD::AND && 1894 N1.getOpcode() == ISD::AND && 1895 N0.getOperand(1).getOpcode() == ISD::Constant && 1896 N1.getOperand(1).getOpcode() == ISD::Constant && 1897 // Don't increase # computations. 1898 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1899 // We can only do this xform if we know that bits from X that are set in C2 1900 // but not in C1 are already zero. Likewise for Y. 1901 const APInt &LHSMask = 1902 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1903 const APInt &RHSMask = 1904 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1905 1906 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1907 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1908 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1909 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1910 } 1911 } 1912 1913 1914 // See if this is some rotate idiom. 1915 if (SDNode *Rot = MatchRotate(N0, N1)) 1916 return SDOperand(Rot, 0); 1917 1918 return SDOperand(); 1919} 1920 1921 1922/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1923static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1924 if (Op.getOpcode() == ISD::AND) { 1925 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1926 Mask = Op.getOperand(1); 1927 Op = Op.getOperand(0); 1928 } else { 1929 return false; 1930 } 1931 } 1932 1933 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1934 Shift = Op; 1935 return true; 1936 } 1937 return false; 1938} 1939 1940 1941// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1942// idioms for rotate, and if the target supports rotation instructions, generate 1943// a rot[lr]. 1944SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1945 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1946 MVT VT = LHS.getValueType(); 1947 if (!TLI.isTypeLegal(VT)) return 0; 1948 1949 // The target must have at least one rotate flavor. 1950 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1951 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1952 if (!HasROTL && !HasROTR) return 0; 1953 1954 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1955 SDOperand LHSShift; // The shift. 1956 SDOperand LHSMask; // AND value if any. 1957 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1958 return 0; // Not part of a rotate. 1959 1960 SDOperand RHSShift; // The shift. 1961 SDOperand RHSMask; // AND value if any. 1962 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1963 return 0; // Not part of a rotate. 1964 1965 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1966 return 0; // Not shifting the same value. 1967 1968 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1969 return 0; // Shifts must disagree. 1970 1971 // Canonicalize shl to left side in a shl/srl pair. 1972 if (RHSShift.getOpcode() == ISD::SHL) { 1973 std::swap(LHS, RHS); 1974 std::swap(LHSShift, RHSShift); 1975 std::swap(LHSMask , RHSMask ); 1976 } 1977 1978 unsigned OpSizeInBits = VT.getSizeInBits(); 1979 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1980 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1981 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1982 1983 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1984 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1985 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1986 RHSShiftAmt.getOpcode() == ISD::Constant) { 1987 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1988 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1989 if ((LShVal + RShVal) != OpSizeInBits) 1990 return 0; 1991 1992 SDOperand Rot; 1993 if (HasROTL) 1994 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1995 else 1996 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1997 1998 // If there is an AND of either shifted operand, apply it to the result. 1999 if (LHSMask.Val || RHSMask.Val) { 2000 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2001 2002 if (LHSMask.Val) { 2003 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2004 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2005 } 2006 if (RHSMask.Val) { 2007 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2008 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2009 } 2010 2011 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2012 } 2013 2014 return Rot.Val; 2015 } 2016 2017 // If there is a mask here, and we have a variable shift, we can't be sure 2018 // that we're masking out the right stuff. 2019 if (LHSMask.Val || RHSMask.Val) 2020 return 0; 2021 2022 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2023 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2024 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2025 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2026 if (ConstantSDNode *SUBC = 2027 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2028 if (SUBC->getAPIntValue() == OpSizeInBits) { 2029 if (HasROTL) 2030 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2031 else 2032 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2033 } 2034 } 2035 } 2036 2037 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2038 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2039 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2040 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2041 if (ConstantSDNode *SUBC = 2042 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2043 if (SUBC->getAPIntValue() == OpSizeInBits) { 2044 if (HasROTL) 2045 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2046 else 2047 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2048 } 2049 } 2050 } 2051 2052 // Look for sign/zext/any-extended cases: 2053 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2054 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2055 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2056 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2057 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2058 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2059 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2060 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2061 if (RExtOp0.getOpcode() == ISD::SUB && 2062 RExtOp0.getOperand(1) == LExtOp0) { 2063 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2064 // (rotr x, y) 2065 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2066 // (rotl x, (sub 32, y)) 2067 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2068 if (SUBC->getAPIntValue() == OpSizeInBits) { 2069 if (HasROTL) 2070 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2071 else 2072 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2073 } 2074 } 2075 } else if (LExtOp0.getOpcode() == ISD::SUB && 2076 RExtOp0 == LExtOp0.getOperand(1)) { 2077 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2078 // (rotl x, y) 2079 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2080 // (rotr x, (sub 32, y)) 2081 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2082 if (SUBC->getAPIntValue() == OpSizeInBits) { 2083 if (HasROTL) 2084 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2085 else 2086 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2087 } 2088 } 2089 } 2090 } 2091 2092 return 0; 2093} 2094 2095 2096SDOperand DAGCombiner::visitXOR(SDNode *N) { 2097 SDOperand N0 = N->getOperand(0); 2098 SDOperand N1 = N->getOperand(1); 2099 SDOperand LHS, RHS, CC; 2100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2102 MVT VT = N0.getValueType(); 2103 2104 // fold vector ops 2105 if (VT.isVector()) { 2106 SDOperand FoldedVOp = SimplifyVBinOp(N); 2107 if (FoldedVOp.Val) return FoldedVOp; 2108 } 2109 2110 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2111 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2112 return DAG.getConstant(0, VT); 2113 // fold (xor x, undef) -> undef 2114 if (N0.getOpcode() == ISD::UNDEF) 2115 return N0; 2116 if (N1.getOpcode() == ISD::UNDEF) 2117 return N1; 2118 // fold (xor c1, c2) -> c1^c2 2119 if (N0C && N1C) 2120 return DAG.getNode(ISD::XOR, VT, N0, N1); 2121 // canonicalize constant to RHS 2122 if (N0C && !N1C) 2123 return DAG.getNode(ISD::XOR, VT, N1, N0); 2124 // fold (xor x, 0) -> x 2125 if (N1C && N1C->isNullValue()) 2126 return N0; 2127 // reassociate xor 2128 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2129 if (RXOR.Val != 0) 2130 return RXOR; 2131 // fold !(x cc y) -> (x !cc y) 2132 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2133 bool isInt = LHS.getValueType().isInteger(); 2134 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2135 isInt); 2136 if (N0.getOpcode() == ISD::SETCC) 2137 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2138 if (N0.getOpcode() == ISD::SELECT_CC) 2139 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2140 assert(0 && "Unhandled SetCC Equivalent!"); 2141 abort(); 2142 } 2143 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2144 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2145 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2146 SDOperand V = N0.getOperand(0); 2147 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2148 DAG.getConstant(1, V.getValueType())); 2149 AddToWorkList(V.Val); 2150 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2151 } 2152 2153 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2154 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2155 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2156 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2157 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2158 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2159 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2160 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2161 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2162 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2163 } 2164 } 2165 // fold !(x or y) -> (!x and !y) iff x or y are constants 2166 if (N1C && N1C->isAllOnesValue() && 2167 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2168 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2169 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2170 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2171 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2172 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2173 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2174 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2175 } 2176 } 2177 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2178 if (N1C && N0.getOpcode() == ISD::XOR) { 2179 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2180 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2181 if (N00C) 2182 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2183 DAG.getConstant(N1C->getAPIntValue()^ 2184 N00C->getAPIntValue(), VT)); 2185 if (N01C) 2186 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2187 DAG.getConstant(N1C->getAPIntValue()^ 2188 N01C->getAPIntValue(), VT)); 2189 } 2190 // fold (xor x, x) -> 0 2191 if (N0 == N1) { 2192 if (!VT.isVector()) { 2193 return DAG.getConstant(0, VT); 2194 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2195 // Produce a vector of zeros. 2196 SDOperand El = DAG.getConstant(0, VT.getVectorElementType()); 2197 std::vector<SDOperand> Ops(VT.getVectorNumElements(), El); 2198 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2199 } 2200 } 2201 2202 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2203 if (N0.getOpcode() == N1.getOpcode()) { 2204 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2205 if (Tmp.Val) return Tmp; 2206 } 2207 2208 // Simplify the expression using non-local knowledge. 2209 if (!VT.isVector() && 2210 SimplifyDemandedBits(SDOperand(N, 0))) 2211 return SDOperand(N, 0); 2212 2213 return SDOperand(); 2214} 2215 2216/// visitShiftByConstant - Handle transforms common to the three shifts, when 2217/// the shift amount is a constant. 2218SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2219 SDNode *LHS = N->getOperand(0).Val; 2220 if (!LHS->hasOneUse()) return SDOperand(); 2221 2222 // We want to pull some binops through shifts, so that we have (and (shift)) 2223 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2224 // thing happens with address calculations, so it's important to canonicalize 2225 // it. 2226 bool HighBitSet = false; // Can we transform this if the high bit is set? 2227 2228 switch (LHS->getOpcode()) { 2229 default: return SDOperand(); 2230 case ISD::OR: 2231 case ISD::XOR: 2232 HighBitSet = false; // We can only transform sra if the high bit is clear. 2233 break; 2234 case ISD::AND: 2235 HighBitSet = true; // We can only transform sra if the high bit is set. 2236 break; 2237 case ISD::ADD: 2238 if (N->getOpcode() != ISD::SHL) 2239 return SDOperand(); // only shl(add) not sr[al](add). 2240 HighBitSet = false; // We can only transform sra if the high bit is clear. 2241 break; 2242 } 2243 2244 // We require the RHS of the binop to be a constant as well. 2245 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2246 if (!BinOpCst) return SDOperand(); 2247 2248 2249 // FIXME: disable this for unless the input to the binop is a shift by a 2250 // constant. If it is not a shift, it pessimizes some common cases like: 2251 // 2252 //void foo(int *X, int i) { X[i & 1235] = 1; } 2253 //int bar(int *X, int i) { return X[i & 255]; } 2254 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2255 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2256 BinOpLHSVal->getOpcode() != ISD::SRA && 2257 BinOpLHSVal->getOpcode() != ISD::SRL) || 2258 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2259 return SDOperand(); 2260 2261 MVT VT = N->getValueType(0); 2262 2263 // If this is a signed shift right, and the high bit is modified 2264 // by the logical operation, do not perform the transformation. 2265 // The highBitSet boolean indicates the value of the high bit of 2266 // the constant which would cause it to be modified for this 2267 // operation. 2268 if (N->getOpcode() == ISD::SRA) { 2269 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2270 if (BinOpRHSSignSet != HighBitSet) 2271 return SDOperand(); 2272 } 2273 2274 // Fold the constants, shifting the binop RHS by the shift amount. 2275 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2276 LHS->getOperand(1), N->getOperand(1)); 2277 2278 // Create the new shift. 2279 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2280 N->getOperand(1)); 2281 2282 // Create the new binop. 2283 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2284} 2285 2286 2287SDOperand DAGCombiner::visitSHL(SDNode *N) { 2288 SDOperand N0 = N->getOperand(0); 2289 SDOperand N1 = N->getOperand(1); 2290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2292 MVT VT = N0.getValueType(); 2293 unsigned OpSizeInBits = VT.getSizeInBits(); 2294 2295 // fold (shl c1, c2) -> c1<<c2 2296 if (N0C && N1C) 2297 return DAG.getNode(ISD::SHL, VT, N0, N1); 2298 // fold (shl 0, x) -> 0 2299 if (N0C && N0C->isNullValue()) 2300 return N0; 2301 // fold (shl x, c >= size(x)) -> undef 2302 if (N1C && N1C->getValue() >= OpSizeInBits) 2303 return DAG.getNode(ISD::UNDEF, VT); 2304 // fold (shl x, 0) -> x 2305 if (N1C && N1C->isNullValue()) 2306 return N0; 2307 // if (shl x, c) is known to be zero, return 0 2308 if (DAG.MaskedValueIsZero(SDOperand(N, 0), 2309 APInt::getAllOnesValue(VT.getSizeInBits()))) 2310 return DAG.getConstant(0, VT); 2311 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2312 return SDOperand(N, 0); 2313 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2314 if (N1C && N0.getOpcode() == ISD::SHL && 2315 N0.getOperand(1).getOpcode() == ISD::Constant) { 2316 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2317 uint64_t c2 = N1C->getValue(); 2318 if (c1 + c2 > OpSizeInBits) 2319 return DAG.getConstant(0, VT); 2320 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2321 DAG.getConstant(c1 + c2, N1.getValueType())); 2322 } 2323 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2324 // (srl (and x, -1 << c1), c1-c2) 2325 if (N1C && N0.getOpcode() == ISD::SRL && 2326 N0.getOperand(1).getOpcode() == ISD::Constant) { 2327 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2328 uint64_t c2 = N1C->getValue(); 2329 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2330 DAG.getConstant(~0ULL << c1, VT)); 2331 if (c2 > c1) 2332 return DAG.getNode(ISD::SHL, VT, Mask, 2333 DAG.getConstant(c2-c1, N1.getValueType())); 2334 else 2335 return DAG.getNode(ISD::SRL, VT, Mask, 2336 DAG.getConstant(c1-c2, N1.getValueType())); 2337 } 2338 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2339 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2340 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2341 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2342 2343 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2344} 2345 2346SDOperand DAGCombiner::visitSRA(SDNode *N) { 2347 SDOperand N0 = N->getOperand(0); 2348 SDOperand N1 = N->getOperand(1); 2349 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2350 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2351 MVT VT = N0.getValueType(); 2352 2353 // fold (sra c1, c2) -> c1>>c2 2354 if (N0C && N1C) 2355 return DAG.getNode(ISD::SRA, VT, N0, N1); 2356 // fold (sra 0, x) -> 0 2357 if (N0C && N0C->isNullValue()) 2358 return N0; 2359 // fold (sra -1, x) -> -1 2360 if (N0C && N0C->isAllOnesValue()) 2361 return N0; 2362 // fold (sra x, c >= size(x)) -> undef 2363 if (N1C && N1C->getValue() >= VT.getSizeInBits()) 2364 return DAG.getNode(ISD::UNDEF, VT); 2365 // fold (sra x, 0) -> x 2366 if (N1C && N1C->isNullValue()) 2367 return N0; 2368 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2369 // sext_inreg. 2370 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2371 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue(); 2372 MVT EVT = MVT::getIntegerVT(LowBits); 2373 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2374 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2375 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2376 DAG.getValueType(EVT)); 2377 } 2378 2379 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2380 if (N1C && N0.getOpcode() == ISD::SRA) { 2381 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2382 unsigned Sum = N1C->getValue() + C1->getValue(); 2383 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2384 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2385 DAG.getConstant(Sum, N1C->getValueType(0))); 2386 } 2387 } 2388 2389 // fold sra (shl X, m), result_size - n 2390 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2391 // result_size - n != m. 2392 // If truncate is free for the target sext(shl) is likely to result in better 2393 // code. 2394 if (N0.getOpcode() == ISD::SHL) { 2395 // Get the two constanst of the shifts, CN0 = m, CN = n. 2396 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2397 if (N01C && N1C) { 2398 // Determine what the truncate's result bitsize and type would be. 2399 unsigned VTValSize = VT.getSizeInBits(); 2400 MVT TruncVT = 2401 MVT::getIntegerVT(VTValSize - N1C->getValue()); 2402 // Determine the residual right-shift amount. 2403 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2404 2405 // If the shift is not a no-op (in which case this should be just a sign 2406 // extend already), the truncated to type is legal, sign_extend is legal 2407 // on that type, and the the truncate to that type is both legal and free, 2408 // perform the transform. 2409 if (ShiftAmt && 2410 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2411 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2412 TLI.isTruncateFree(VT, TruncVT)) { 2413 2414 SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2415 SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2416 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2417 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2418 } 2419 } 2420 } 2421 2422 // Simplify, based on bits shifted out of the LHS. 2423 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2424 return SDOperand(N, 0); 2425 2426 2427 // If the sign bit is known to be zero, switch this to a SRL. 2428 if (DAG.SignBitIsZero(N0)) 2429 return DAG.getNode(ISD::SRL, VT, N0, N1); 2430 2431 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2432} 2433 2434SDOperand DAGCombiner::visitSRL(SDNode *N) { 2435 SDOperand N0 = N->getOperand(0); 2436 SDOperand N1 = N->getOperand(1); 2437 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2438 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2439 MVT VT = N0.getValueType(); 2440 unsigned OpSizeInBits = VT.getSizeInBits(); 2441 2442 // fold (srl c1, c2) -> c1 >>u c2 2443 if (N0C && N1C) 2444 return DAG.getNode(ISD::SRL, VT, N0, N1); 2445 // fold (srl 0, x) -> 0 2446 if (N0C && N0C->isNullValue()) 2447 return N0; 2448 // fold (srl x, c >= size(x)) -> undef 2449 if (N1C && N1C->getValue() >= OpSizeInBits) 2450 return DAG.getNode(ISD::UNDEF, VT); 2451 // fold (srl x, 0) -> x 2452 if (N1C && N1C->isNullValue()) 2453 return N0; 2454 // if (srl x, c) is known to be zero, return 0 2455 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), 2456 APInt::getAllOnesValue(OpSizeInBits))) 2457 return DAG.getConstant(0, VT); 2458 2459 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2460 if (N1C && N0.getOpcode() == ISD::SRL && 2461 N0.getOperand(1).getOpcode() == ISD::Constant) { 2462 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2463 uint64_t c2 = N1C->getValue(); 2464 if (c1 + c2 > OpSizeInBits) 2465 return DAG.getConstant(0, VT); 2466 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2467 DAG.getConstant(c1 + c2, N1.getValueType())); 2468 } 2469 2470 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2471 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2472 // Shifting in all undef bits? 2473 MVT SmallVT = N0.getOperand(0).getValueType(); 2474 if (N1C->getValue() >= SmallVT.getSizeInBits()) 2475 return DAG.getNode(ISD::UNDEF, VT); 2476 2477 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2478 AddToWorkList(SmallShift.Val); 2479 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2480 } 2481 2482 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2483 // bit, which is unmodified by sra. 2484 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) { 2485 if (N0.getOpcode() == ISD::SRA) 2486 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2487 } 2488 2489 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2490 if (N1C && N0.getOpcode() == ISD::CTLZ && 2491 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2492 APInt KnownZero, KnownOne; 2493 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2494 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2495 2496 // If any of the input bits are KnownOne, then the input couldn't be all 2497 // zeros, thus the result of the srl will always be zero. 2498 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2499 2500 // If all of the bits input the to ctlz node are known to be zero, then 2501 // the result of the ctlz is "32" and the result of the shift is one. 2502 APInt UnknownBits = ~KnownZero & Mask; 2503 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2504 2505 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2506 if ((UnknownBits & (UnknownBits-1)) == 0) { 2507 // Okay, we know that only that the single bit specified by UnknownBits 2508 // could be set on input to the CTLZ node. If this bit is set, the SRL 2509 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2510 // to an SRL,XOR pair, which is likely to simplify more. 2511 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2512 SDOperand Op = N0.getOperand(0); 2513 if (ShAmt) { 2514 Op = DAG.getNode(ISD::SRL, VT, Op, 2515 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2516 AddToWorkList(Op.Val); 2517 } 2518 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2519 } 2520 } 2521 2522 // fold operands of srl based on knowledge that the low bits are not 2523 // demanded. 2524 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2525 return SDOperand(N, 0); 2526 2527 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2528} 2529 2530SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2531 SDOperand N0 = N->getOperand(0); 2532 MVT VT = N->getValueType(0); 2533 2534 // fold (ctlz c1) -> c2 2535 if (isa<ConstantSDNode>(N0)) 2536 return DAG.getNode(ISD::CTLZ, VT, N0); 2537 return SDOperand(); 2538} 2539 2540SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2541 SDOperand N0 = N->getOperand(0); 2542 MVT VT = N->getValueType(0); 2543 2544 // fold (cttz c1) -> c2 2545 if (isa<ConstantSDNode>(N0)) 2546 return DAG.getNode(ISD::CTTZ, VT, N0); 2547 return SDOperand(); 2548} 2549 2550SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2551 SDOperand N0 = N->getOperand(0); 2552 MVT VT = N->getValueType(0); 2553 2554 // fold (ctpop c1) -> c2 2555 if (isa<ConstantSDNode>(N0)) 2556 return DAG.getNode(ISD::CTPOP, VT, N0); 2557 return SDOperand(); 2558} 2559 2560SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2561 SDOperand N0 = N->getOperand(0); 2562 SDOperand N1 = N->getOperand(1); 2563 SDOperand N2 = N->getOperand(2); 2564 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2565 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2566 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2567 MVT VT = N->getValueType(0); 2568 MVT VT0 = N0.getValueType(); 2569 2570 // fold select C, X, X -> X 2571 if (N1 == N2) 2572 return N1; 2573 // fold select true, X, Y -> X 2574 if (N0C && !N0C->isNullValue()) 2575 return N1; 2576 // fold select false, X, Y -> Y 2577 if (N0C && N0C->isNullValue()) 2578 return N2; 2579 // fold select C, 1, X -> C | X 2580 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2581 return DAG.getNode(ISD::OR, VT, N0, N2); 2582 // fold select C, 0, 1 -> ~C 2583 if (VT.isInteger() && VT0.isInteger() && 2584 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2585 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2586 if (VT == VT0) 2587 return XORNode; 2588 AddToWorkList(XORNode.Val); 2589 if (VT.bitsGT(VT0)) 2590 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2591 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2592 } 2593 // fold select C, 0, X -> ~C & X 2594 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2595 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2596 AddToWorkList(XORNode.Val); 2597 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2598 } 2599 // fold select C, X, 1 -> ~C | X 2600 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2601 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2602 AddToWorkList(XORNode.Val); 2603 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2604 } 2605 // fold select C, X, 0 -> C & X 2606 // FIXME: this should check for C type == X type, not i1? 2607 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2608 return DAG.getNode(ISD::AND, VT, N0, N1); 2609 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2610 if (VT == MVT::i1 && N0 == N1) 2611 return DAG.getNode(ISD::OR, VT, N0, N2); 2612 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2613 if (VT == MVT::i1 && N0 == N2) 2614 return DAG.getNode(ISD::AND, VT, N0, N1); 2615 2616 // If we can fold this based on the true/false value, do so. 2617 if (SimplifySelectOps(N, N1, N2)) 2618 return SDOperand(N, 0); // Don't revisit N. 2619 2620 // fold selects based on a setcc into other things, such as min/max/abs 2621 if (N0.getOpcode() == ISD::SETCC) { 2622 // FIXME: 2623 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2624 // having to say they don't support SELECT_CC on every type the DAG knows 2625 // about, since there is no way to mark an opcode illegal at all value types 2626 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2627 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2628 N1, N2, N0.getOperand(2)); 2629 else 2630 return SimplifySelect(N0, N1, N2); 2631 } 2632 return SDOperand(); 2633} 2634 2635SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2636 SDOperand N0 = N->getOperand(0); 2637 SDOperand N1 = N->getOperand(1); 2638 SDOperand N2 = N->getOperand(2); 2639 SDOperand N3 = N->getOperand(3); 2640 SDOperand N4 = N->getOperand(4); 2641 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2642 2643 // fold select_cc lhs, rhs, x, x, cc -> x 2644 if (N2 == N3) 2645 return N2; 2646 2647 // Determine if the condition we're dealing with is constant 2648 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2649 if (SCC.Val) AddToWorkList(SCC.Val); 2650 2651 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2652 if (!SCCC->isNullValue()) 2653 return N2; // cond always true -> true val 2654 else 2655 return N3; // cond always false -> false val 2656 } 2657 2658 // Fold to a simpler select_cc 2659 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2660 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2661 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2662 SCC.getOperand(2)); 2663 2664 // If we can fold this based on the true/false value, do so. 2665 if (SimplifySelectOps(N, N2, N3)) 2666 return SDOperand(N, 0); // Don't revisit N. 2667 2668 // fold select_cc into other things, such as min/max/abs 2669 return SimplifySelectCC(N0, N1, N2, N3, CC); 2670} 2671 2672SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2673 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2674 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2675} 2676 2677// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2678// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2679// transformation. Returns true if extension are possible and the above 2680// mentioned transformation is profitable. 2681static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2682 unsigned ExtOpc, 2683 SmallVector<SDNode*, 4> &ExtendNodes, 2684 TargetLowering &TLI) { 2685 bool HasCopyToRegUses = false; 2686 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2687 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2688 UI != UE; ++UI) { 2689 SDNode *User = *UI; 2690 if (User == N) 2691 continue; 2692 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2693 if (User->getOpcode() == ISD::SETCC) { 2694 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2695 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2696 // Sign bits will be lost after a zext. 2697 return false; 2698 bool Add = false; 2699 for (unsigned i = 0; i != 2; ++i) { 2700 SDOperand UseOp = User->getOperand(i); 2701 if (UseOp == N0) 2702 continue; 2703 if (!isa<ConstantSDNode>(UseOp)) 2704 return false; 2705 Add = true; 2706 } 2707 if (Add) 2708 ExtendNodes.push_back(User); 2709 } else { 2710 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2711 SDOperand UseOp = User->getOperand(i); 2712 if (UseOp == N0) { 2713 // If truncate from extended type to original load type is free 2714 // on this target, then it's ok to extend a CopyToReg. 2715 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2716 HasCopyToRegUses = true; 2717 else 2718 return false; 2719 } 2720 } 2721 } 2722 } 2723 2724 if (HasCopyToRegUses) { 2725 bool BothLiveOut = false; 2726 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2727 UI != UE; ++UI) { 2728 SDNode *User = *UI; 2729 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2730 SDOperand UseOp = User->getOperand(i); 2731 if (UseOp.Val == N && UseOp.ResNo == 0) { 2732 BothLiveOut = true; 2733 break; 2734 } 2735 } 2736 } 2737 if (BothLiveOut) 2738 // Both unextended and extended values are live out. There had better be 2739 // good a reason for the transformation. 2740 return ExtendNodes.size(); 2741 } 2742 return true; 2743} 2744 2745SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2746 SDOperand N0 = N->getOperand(0); 2747 MVT VT = N->getValueType(0); 2748 2749 // fold (sext c1) -> c1 2750 if (isa<ConstantSDNode>(N0)) 2751 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2752 2753 // fold (sext (sext x)) -> (sext x) 2754 // fold (sext (aext x)) -> (sext x) 2755 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2756 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2757 2758 if (N0.getOpcode() == ISD::TRUNCATE) { 2759 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2760 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2761 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2762 if (NarrowLoad.Val) { 2763 if (NarrowLoad.Val != N0.Val) 2764 CombineTo(N0.Val, NarrowLoad); 2765 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2766 } 2767 2768 // See if the value being truncated is already sign extended. If so, just 2769 // eliminate the trunc/sext pair. 2770 SDOperand Op = N0.getOperand(0); 2771 unsigned OpBits = Op.getValueType().getSizeInBits(); 2772 unsigned MidBits = N0.getValueType().getSizeInBits(); 2773 unsigned DestBits = VT.getSizeInBits(); 2774 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2775 2776 if (OpBits == DestBits) { 2777 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2778 // bits, it is already ready. 2779 if (NumSignBits > DestBits-MidBits) 2780 return Op; 2781 } else if (OpBits < DestBits) { 2782 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2783 // bits, just sext from i32. 2784 if (NumSignBits > OpBits-MidBits) 2785 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2786 } else { 2787 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2788 // bits, just truncate to i32. 2789 if (NumSignBits > OpBits-MidBits) 2790 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2791 } 2792 2793 // fold (sext (truncate x)) -> (sextinreg x). 2794 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2795 N0.getValueType())) { 2796 if (Op.getValueType().bitsLT(VT)) 2797 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2798 else if (Op.getValueType().bitsGT(VT)) 2799 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2800 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2801 DAG.getValueType(N0.getValueType())); 2802 } 2803 } 2804 2805 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2806 if (ISD::isNON_EXTLoad(N0.Val) && 2807 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2808 TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2809 bool DoXform = true; 2810 SmallVector<SDNode*, 4> SetCCs; 2811 if (!N0.hasOneUse()) 2812 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2813 if (DoXform) { 2814 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2815 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2816 LN0->getBasePtr(), LN0->getSrcValue(), 2817 LN0->getSrcValueOffset(), 2818 N0.getValueType(), 2819 LN0->isVolatile(), 2820 LN0->getAlignment()); 2821 CombineTo(N, ExtLoad); 2822 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2823 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2824 // Extend SetCC uses if necessary. 2825 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2826 SDNode *SetCC = SetCCs[i]; 2827 SmallVector<SDOperand, 4> Ops; 2828 for (unsigned j = 0; j != 2; ++j) { 2829 SDOperand SOp = SetCC->getOperand(j); 2830 if (SOp == Trunc) 2831 Ops.push_back(ExtLoad); 2832 else 2833 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2834 } 2835 Ops.push_back(SetCC->getOperand(2)); 2836 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2837 &Ops[0], Ops.size())); 2838 } 2839 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2840 } 2841 } 2842 2843 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2844 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2845 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2846 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2847 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2848 MVT EVT = LN0->getMemoryVT(); 2849 if ((!AfterLegalize && !LN0->isVolatile()) || 2850 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2851 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2852 LN0->getBasePtr(), LN0->getSrcValue(), 2853 LN0->getSrcValueOffset(), EVT, 2854 LN0->isVolatile(), 2855 LN0->getAlignment()); 2856 CombineTo(N, ExtLoad); 2857 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2858 ExtLoad.getValue(1)); 2859 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2860 } 2861 } 2862 2863 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2864 if (N0.getOpcode() == ISD::SETCC) { 2865 SDOperand SCC = 2866 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2867 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2868 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2869 if (SCC.Val) return SCC; 2870 } 2871 2872 // fold (sext x) -> (zext x) if the sign bit is known zero. 2873 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2874 DAG.SignBitIsZero(N0)) 2875 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2876 2877 return SDOperand(); 2878} 2879 2880SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2881 SDOperand N0 = N->getOperand(0); 2882 MVT VT = N->getValueType(0); 2883 2884 // fold (zext c1) -> c1 2885 if (isa<ConstantSDNode>(N0)) 2886 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2887 // fold (zext (zext x)) -> (zext x) 2888 // fold (zext (aext x)) -> (zext x) 2889 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2890 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2891 2892 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2893 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2894 if (N0.getOpcode() == ISD::TRUNCATE) { 2895 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2896 if (NarrowLoad.Val) { 2897 if (NarrowLoad.Val != N0.Val) 2898 CombineTo(N0.Val, NarrowLoad); 2899 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2900 } 2901 } 2902 2903 // fold (zext (truncate x)) -> (and x, mask) 2904 if (N0.getOpcode() == ISD::TRUNCATE && 2905 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2906 SDOperand Op = N0.getOperand(0); 2907 if (Op.getValueType().bitsLT(VT)) { 2908 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2909 } else if (Op.getValueType().bitsGT(VT)) { 2910 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2911 } 2912 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2913 } 2914 2915 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2916 if (N0.getOpcode() == ISD::AND && 2917 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2918 N0.getOperand(1).getOpcode() == ISD::Constant) { 2919 SDOperand X = N0.getOperand(0).getOperand(0); 2920 if (X.getValueType().bitsLT(VT)) { 2921 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2922 } else if (X.getValueType().bitsGT(VT)) { 2923 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2924 } 2925 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2926 Mask.zext(VT.getSizeInBits()); 2927 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2928 } 2929 2930 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2931 if (ISD::isNON_EXTLoad(N0.Val) && 2932 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2933 TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2934 bool DoXform = true; 2935 SmallVector<SDNode*, 4> SetCCs; 2936 if (!N0.hasOneUse()) 2937 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2938 if (DoXform) { 2939 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2940 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2941 LN0->getBasePtr(), LN0->getSrcValue(), 2942 LN0->getSrcValueOffset(), 2943 N0.getValueType(), 2944 LN0->isVolatile(), 2945 LN0->getAlignment()); 2946 CombineTo(N, ExtLoad); 2947 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2948 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2949 // Extend SetCC uses if necessary. 2950 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2951 SDNode *SetCC = SetCCs[i]; 2952 SmallVector<SDOperand, 4> Ops; 2953 for (unsigned j = 0; j != 2; ++j) { 2954 SDOperand SOp = SetCC->getOperand(j); 2955 if (SOp == Trunc) 2956 Ops.push_back(ExtLoad); 2957 else 2958 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2959 } 2960 Ops.push_back(SetCC->getOperand(2)); 2961 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2962 &Ops[0], Ops.size())); 2963 } 2964 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2965 } 2966 } 2967 2968 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2969 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2970 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2971 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2972 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2973 MVT EVT = LN0->getMemoryVT(); 2974 if ((!AfterLegalize && !LN0->isVolatile()) || 2975 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) { 2976 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2977 LN0->getBasePtr(), LN0->getSrcValue(), 2978 LN0->getSrcValueOffset(), EVT, 2979 LN0->isVolatile(), 2980 LN0->getAlignment()); 2981 CombineTo(N, ExtLoad); 2982 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2983 ExtLoad.getValue(1)); 2984 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2985 } 2986 } 2987 2988 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2989 if (N0.getOpcode() == ISD::SETCC) { 2990 SDOperand SCC = 2991 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2992 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2993 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2994 if (SCC.Val) return SCC; 2995 } 2996 2997 return SDOperand(); 2998} 2999 3000SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 3001 SDOperand N0 = N->getOperand(0); 3002 MVT VT = N->getValueType(0); 3003 3004 // fold (aext c1) -> c1 3005 if (isa<ConstantSDNode>(N0)) 3006 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3007 // fold (aext (aext x)) -> (aext x) 3008 // fold (aext (zext x)) -> (zext x) 3009 // fold (aext (sext x)) -> (sext x) 3010 if (N0.getOpcode() == ISD::ANY_EXTEND || 3011 N0.getOpcode() == ISD::ZERO_EXTEND || 3012 N0.getOpcode() == ISD::SIGN_EXTEND) 3013 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3014 3015 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3016 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3017 if (N0.getOpcode() == ISD::TRUNCATE) { 3018 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 3019 if (NarrowLoad.Val) { 3020 if (NarrowLoad.Val != N0.Val) 3021 CombineTo(N0.Val, NarrowLoad); 3022 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3023 } 3024 } 3025 3026 // fold (aext (truncate x)) 3027 if (N0.getOpcode() == ISD::TRUNCATE) { 3028 SDOperand TruncOp = N0.getOperand(0); 3029 if (TruncOp.getValueType() == VT) 3030 return TruncOp; // x iff x size == zext size. 3031 if (TruncOp.getValueType().bitsGT(VT)) 3032 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3033 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3034 } 3035 3036 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3037 if (N0.getOpcode() == ISD::AND && 3038 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3039 N0.getOperand(1).getOpcode() == ISD::Constant) { 3040 SDOperand X = N0.getOperand(0).getOperand(0); 3041 if (X.getValueType().bitsLT(VT)) { 3042 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3043 } else if (X.getValueType().bitsGT(VT)) { 3044 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3045 } 3046 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3047 Mask.zext(VT.getSizeInBits()); 3048 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3049 } 3050 3051 // fold (aext (load x)) -> (aext (truncate (extload x))) 3052 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3053 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3054 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3055 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3056 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3057 LN0->getBasePtr(), LN0->getSrcValue(), 3058 LN0->getSrcValueOffset(), 3059 N0.getValueType(), 3060 LN0->isVolatile(), 3061 LN0->getAlignment()); 3062 CombineTo(N, ExtLoad); 3063 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3064 ExtLoad.getValue(1)); 3065 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3066 } 3067 3068 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3069 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3070 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3071 if (N0.getOpcode() == ISD::LOAD && 3072 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3073 N0.hasOneUse()) { 3074 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3075 MVT EVT = LN0->getMemoryVT(); 3076 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3077 LN0->getChain(), LN0->getBasePtr(), 3078 LN0->getSrcValue(), 3079 LN0->getSrcValueOffset(), EVT, 3080 LN0->isVolatile(), 3081 LN0->getAlignment()); 3082 CombineTo(N, ExtLoad); 3083 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3084 ExtLoad.getValue(1)); 3085 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3086 } 3087 3088 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3089 if (N0.getOpcode() == ISD::SETCC) { 3090 SDOperand SCC = 3091 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3092 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3093 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3094 if (SCC.Val) 3095 return SCC; 3096 } 3097 3098 return SDOperand(); 3099} 3100 3101/// GetDemandedBits - See if the specified operand can be simplified with the 3102/// knowledge that only the bits specified by Mask are used. If so, return the 3103/// simpler operand, otherwise return a null SDOperand. 3104SDOperand DAGCombiner::GetDemandedBits(SDOperand V, const APInt &Mask) { 3105 switch (V.getOpcode()) { 3106 default: break; 3107 case ISD::OR: 3108 case ISD::XOR: 3109 // If the LHS or RHS don't contribute bits to the or, drop them. 3110 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3111 return V.getOperand(1); 3112 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3113 return V.getOperand(0); 3114 break; 3115 case ISD::SRL: 3116 // Only look at single-use SRLs. 3117 if (!V.Val->hasOneUse()) 3118 break; 3119 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3120 // See if we can recursively simplify the LHS. 3121 unsigned Amt = RHSC->getValue(); 3122 APInt NewMask = Mask << Amt; 3123 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3124 if (SimplifyLHS.Val) { 3125 return DAG.getNode(ISD::SRL, V.getValueType(), 3126 SimplifyLHS, V.getOperand(1)); 3127 } 3128 } 3129 } 3130 return SDOperand(); 3131} 3132 3133/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3134/// bits and then truncated to a narrower type and where N is a multiple 3135/// of number of bits of the narrower type, transform it to a narrower load 3136/// from address + N / num of bits of new type. If the result is to be 3137/// extended, also fold the extension to form a extending load. 3138SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3139 unsigned Opc = N->getOpcode(); 3140 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3141 SDOperand N0 = N->getOperand(0); 3142 MVT VT = N->getValueType(0); 3143 MVT EVT = N->getValueType(0); 3144 3145 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3146 // extended to VT. 3147 if (Opc == ISD::SIGN_EXTEND_INREG) { 3148 ExtType = ISD::SEXTLOAD; 3149 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3150 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3151 return SDOperand(); 3152 } 3153 3154 unsigned EVTBits = EVT.getSizeInBits(); 3155 unsigned ShAmt = 0; 3156 bool CombineSRL = false; 3157 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3158 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3159 ShAmt = N01->getValue(); 3160 // Is the shift amount a multiple of size of VT? 3161 if ((ShAmt & (EVTBits-1)) == 0) { 3162 N0 = N0.getOperand(0); 3163 if (N0.getValueType().getSizeInBits() <= EVTBits) 3164 return SDOperand(); 3165 CombineSRL = true; 3166 } 3167 } 3168 } 3169 3170 // Do not generate loads of non-round integer types since these can 3171 // be expensive (and would be wrong if the type is not byte sized). 3172 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && VT.isRound() && 3173 // Do not change the width of a volatile load. 3174 !cast<LoadSDNode>(N0)->isVolatile()) { 3175 assert(N0.getValueType().getSizeInBits() > EVTBits && 3176 "Cannot truncate to larger type!"); 3177 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3178 MVT PtrType = N0.getOperand(1).getValueType(); 3179 // For big endian targets, we need to adjust the offset to the pointer to 3180 // load the correct bytes. 3181 if (TLI.isBigEndian()) { 3182 unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits(); 3183 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3184 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3185 } 3186 uint64_t PtrOff = ShAmt / 8; 3187 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3188 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3189 DAG.getConstant(PtrOff, PtrType)); 3190 AddToWorkList(NewPtr.Val); 3191 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3192 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3193 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3194 LN0->isVolatile(), NewAlign) 3195 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3196 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3197 LN0->isVolatile(), NewAlign); 3198 AddToWorkList(N); 3199 if (CombineSRL) { 3200 WorkListRemover DeadNodes(*this); 3201 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3202 &DeadNodes); 3203 CombineTo(N->getOperand(0).Val, Load); 3204 } else 3205 CombineTo(N0.Val, Load, Load.getValue(1)); 3206 if (ShAmt) { 3207 if (Opc == ISD::SIGN_EXTEND_INREG) 3208 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3209 else 3210 return DAG.getNode(Opc, VT, Load); 3211 } 3212 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3213 } 3214 3215 return SDOperand(); 3216} 3217 3218 3219SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3220 SDOperand N0 = N->getOperand(0); 3221 SDOperand N1 = N->getOperand(1); 3222 MVT VT = N->getValueType(0); 3223 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3224 unsigned VTBits = VT.getSizeInBits(); 3225 unsigned EVTBits = EVT.getSizeInBits(); 3226 3227 // fold (sext_in_reg c1) -> c1 3228 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3229 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3230 3231 // If the input is already sign extended, just drop the extension. 3232 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3233 return N0; 3234 3235 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3236 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3237 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3238 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3239 } 3240 3241 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3242 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3243 return DAG.getZeroExtendInReg(N0, EVT); 3244 3245 // fold operands of sext_in_reg based on knowledge that the top bits are not 3246 // demanded. 3247 if (SimplifyDemandedBits(SDOperand(N, 0))) 3248 return SDOperand(N, 0); 3249 3250 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3251 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3252 SDOperand NarrowLoad = ReduceLoadWidth(N); 3253 if (NarrowLoad.Val) 3254 return NarrowLoad; 3255 3256 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3257 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3258 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3259 if (N0.getOpcode() == ISD::SRL) { 3260 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3261 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) { 3262 // We can turn this into an SRA iff the input to the SRL is already sign 3263 // extended enough. 3264 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3265 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits) 3266 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3267 } 3268 } 3269 3270 // fold (sext_inreg (extload x)) -> (sextload x) 3271 if (ISD::isEXTLoad(N0.Val) && 3272 ISD::isUNINDEXEDLoad(N0.Val) && 3273 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3274 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3275 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3276 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3277 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3278 LN0->getBasePtr(), LN0->getSrcValue(), 3279 LN0->getSrcValueOffset(), EVT, 3280 LN0->isVolatile(), 3281 LN0->getAlignment()); 3282 CombineTo(N, ExtLoad); 3283 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3284 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3285 } 3286 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3287 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3288 N0.hasOneUse() && 3289 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3290 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3291 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3292 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3293 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3294 LN0->getBasePtr(), LN0->getSrcValue(), 3295 LN0->getSrcValueOffset(), EVT, 3296 LN0->isVolatile(), 3297 LN0->getAlignment()); 3298 CombineTo(N, ExtLoad); 3299 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3300 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3301 } 3302 return SDOperand(); 3303} 3304 3305SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3306 SDOperand N0 = N->getOperand(0); 3307 MVT VT = N->getValueType(0); 3308 3309 // noop truncate 3310 if (N0.getValueType() == N->getValueType(0)) 3311 return N0; 3312 // fold (truncate c1) -> c1 3313 if (isa<ConstantSDNode>(N0)) 3314 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3315 // fold (truncate (truncate x)) -> (truncate x) 3316 if (N0.getOpcode() == ISD::TRUNCATE) 3317 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3318 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3319 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3320 N0.getOpcode() == ISD::ANY_EXTEND) { 3321 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3322 // if the source is smaller than the dest, we still need an extend 3323 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3324 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3325 // if the source is larger than the dest, than we just need the truncate 3326 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3327 else 3328 // if the source and dest are the same type, we can drop both the extend 3329 // and the truncate 3330 return N0.getOperand(0); 3331 } 3332 3333 // See if we can simplify the input to this truncate through knowledge that 3334 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3335 // -> trunc y 3336 SDOperand Shorter = 3337 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3338 VT.getSizeInBits())); 3339 if (Shorter.Val) 3340 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3341 3342 // fold (truncate (load x)) -> (smaller load x) 3343 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3344 return ReduceLoadWidth(N); 3345} 3346 3347static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3348 SDOperand Elt = N->getOperand(i); 3349 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3350 return Elt.Val; 3351 return Elt.getOperand(Elt.ResNo).Val; 3352} 3353 3354/// CombineConsecutiveLoads - build_pair (load, load) -> load 3355/// if load locations are consecutive. 3356SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3357 assert(N->getOpcode() == ISD::BUILD_PAIR); 3358 3359 SDNode *LD1 = getBuildPairElt(N, 0); 3360 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3361 return SDOperand(); 3362 MVT LD1VT = LD1->getValueType(0); 3363 SDNode *LD2 = getBuildPairElt(N, 1); 3364 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3365 if (ISD::isNON_EXTLoad(LD2) && 3366 LD2->hasOneUse() && 3367 // If both are volatile this would reduce the number of volatile loads. 3368 // If one is volatile it might be ok, but play conservative and bail out. 3369 !cast<LoadSDNode>(LD1)->isVolatile() && 3370 !cast<LoadSDNode>(LD2)->isVolatile() && 3371 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3372 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3373 unsigned Align = LD->getAlignment(); 3374 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 3375 getABITypeAlignment(VT.getTypeForMVT()); 3376 if (NewAlign <= Align && 3377 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3378 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3379 LD->getSrcValue(), LD->getSrcValueOffset(), 3380 false, Align); 3381 } 3382 return SDOperand(); 3383} 3384 3385SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3386 SDOperand N0 = N->getOperand(0); 3387 MVT VT = N->getValueType(0); 3388 3389 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3390 // Only do this before legalize, since afterward the target may be depending 3391 // on the bitconvert. 3392 // First check to see if this is all constant. 3393 if (!AfterLegalize && 3394 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3395 VT.isVector()) { 3396 bool isSimple = true; 3397 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3398 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3399 N0.getOperand(i).getOpcode() != ISD::Constant && 3400 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3401 isSimple = false; 3402 break; 3403 } 3404 3405 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3406 assert(!DestEltVT.isVector() && 3407 "Element type of vector ValueType must not be vector!"); 3408 if (isSimple) { 3409 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3410 } 3411 } 3412 3413 // If the input is a constant, let getNode() fold it. 3414 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3415 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3416 if (Res.Val != N) return Res; 3417 } 3418 3419 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3420 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3421 3422 // fold (conv (load x)) -> (load (conv*)x) 3423 // If the resultant load doesn't need a higher alignment than the original! 3424 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3425 // Do not change the width of a volatile load. 3426 !cast<LoadSDNode>(N0)->isVolatile() && 3427 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3428 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3429 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3430 getABITypeAlignment(VT.getTypeForMVT()); 3431 unsigned OrigAlign = LN0->getAlignment(); 3432 if (Align <= OrigAlign) { 3433 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3434 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3435 LN0->isVolatile(), OrigAlign); 3436 AddToWorkList(N); 3437 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3438 Load.getValue(1)); 3439 return Load; 3440 } 3441 } 3442 3443 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3444 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3445 // This often reduces constant pool loads. 3446 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3447 N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3448 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3449 AddToWorkList(NewConv.Val); 3450 3451 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3452 if (N0.getOpcode() == ISD::FNEG) 3453 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3454 assert(N0.getOpcode() == ISD::FABS); 3455 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3456 } 3457 3458 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3459 // Note that we don't handle copysign(x,cst) because this can always be folded 3460 // to an fneg or fabs. 3461 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3462 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3463 VT.isInteger() && !VT.isVector()) { 3464 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3465 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, 3466 MVT::getIntegerVT(OrigXWidth), 3467 N0.getOperand(1)); 3468 AddToWorkList(X.Val); 3469 3470 // If X has a different width than the result/lhs, sext it or truncate it. 3471 unsigned VTWidth = VT.getSizeInBits(); 3472 if (OrigXWidth < VTWidth) { 3473 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3474 AddToWorkList(X.Val); 3475 } else if (OrigXWidth > VTWidth) { 3476 // To get the sign bit in the right place, we have to shift it right 3477 // before truncating. 3478 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3479 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3480 AddToWorkList(X.Val); 3481 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3482 AddToWorkList(X.Val); 3483 } 3484 3485 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3486 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3487 AddToWorkList(X.Val); 3488 3489 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3490 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3491 AddToWorkList(Cst.Val); 3492 3493 return DAG.getNode(ISD::OR, VT, X, Cst); 3494 } 3495 3496 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3497 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3498 SDOperand CombineLD = CombineConsecutiveLoads(N0.Val, VT); 3499 if (CombineLD.Val) 3500 return CombineLD; 3501 } 3502 3503 return SDOperand(); 3504} 3505 3506SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3507 MVT VT = N->getValueType(0); 3508 return CombineConsecutiveLoads(N, VT); 3509} 3510 3511/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3512/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3513/// destination element value type. 3514SDOperand DAGCombiner:: 3515ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3516 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3517 3518 // If this is already the right type, we're done. 3519 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3520 3521 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3522 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3523 3524 // If this is a conversion of N elements of one type to N elements of another 3525 // type, convert each element. This handles FP<->INT cases. 3526 if (SrcBitSize == DstBitSize) { 3527 SmallVector<SDOperand, 8> Ops; 3528 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3529 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3530 AddToWorkList(Ops.back().Val); 3531 } 3532 MVT VT = MVT::getVectorVT(DstEltVT, 3533 BV->getValueType(0).getVectorNumElements()); 3534 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3535 } 3536 3537 // Otherwise, we're growing or shrinking the elements. To avoid having to 3538 // handle annoying details of growing/shrinking FP values, we convert them to 3539 // int first. 3540 if (SrcEltVT.isFloatingPoint()) { 3541 // Convert the input float vector to a int vector where the elements are the 3542 // same sizes. 3543 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3544 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3545 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3546 SrcEltVT = IntVT; 3547 } 3548 3549 // Now we know the input is an integer vector. If the output is a FP type, 3550 // convert to integer first, then to FP of the right size. 3551 if (DstEltVT.isFloatingPoint()) { 3552 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3553 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3554 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3555 3556 // Next, convert to FP elements of the same size. 3557 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3558 } 3559 3560 // Okay, we know the src/dst types are both integers of differing types. 3561 // Handling growing first. 3562 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3563 if (SrcBitSize < DstBitSize) { 3564 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3565 3566 SmallVector<SDOperand, 8> Ops; 3567 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3568 i += NumInputsPerOutput) { 3569 bool isLE = TLI.isLittleEndian(); 3570 APInt NewBits = APInt(DstBitSize, 0); 3571 bool EltIsUndef = true; 3572 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3573 // Shift the previously computed bits over. 3574 NewBits <<= SrcBitSize; 3575 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3576 if (Op.getOpcode() == ISD::UNDEF) continue; 3577 EltIsUndef = false; 3578 3579 NewBits |= 3580 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3581 } 3582 3583 if (EltIsUndef) 3584 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3585 else 3586 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3587 } 3588 3589 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3590 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3591 } 3592 3593 // Finally, this must be the case where we are shrinking elements: each input 3594 // turns into multiple outputs. 3595 bool isS2V = ISD::isScalarToVector(BV); 3596 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3597 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3598 SmallVector<SDOperand, 8> Ops; 3599 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3600 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3601 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3602 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3603 continue; 3604 } 3605 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3606 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3607 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3608 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3609 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3610 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3611 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3612 OpVal = OpVal.lshr(DstBitSize); 3613 } 3614 3615 // For big endian targets, swap the order of the pieces of each element. 3616 if (TLI.isBigEndian()) 3617 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3618 } 3619 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3620} 3621 3622 3623 3624SDOperand DAGCombiner::visitFADD(SDNode *N) { 3625 SDOperand N0 = N->getOperand(0); 3626 SDOperand N1 = N->getOperand(1); 3627 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3628 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3629 MVT VT = N->getValueType(0); 3630 3631 // fold vector ops 3632 if (VT.isVector()) { 3633 SDOperand FoldedVOp = SimplifyVBinOp(N); 3634 if (FoldedVOp.Val) return FoldedVOp; 3635 } 3636 3637 // fold (fadd c1, c2) -> c1+c2 3638 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3639 return DAG.getNode(ISD::FADD, VT, N0, N1); 3640 // canonicalize constant to RHS 3641 if (N0CFP && !N1CFP) 3642 return DAG.getNode(ISD::FADD, VT, N1, N0); 3643 // fold (A + (-B)) -> A-B 3644 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3645 return DAG.getNode(ISD::FSUB, VT, N0, 3646 GetNegatedExpression(N1, DAG, AfterLegalize)); 3647 // fold ((-A) + B) -> B-A 3648 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3649 return DAG.getNode(ISD::FSUB, VT, N1, 3650 GetNegatedExpression(N0, DAG, AfterLegalize)); 3651 3652 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3653 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3654 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3655 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3656 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3657 3658 return SDOperand(); 3659} 3660 3661SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3662 SDOperand N0 = N->getOperand(0); 3663 SDOperand N1 = N->getOperand(1); 3664 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3665 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3666 MVT VT = N->getValueType(0); 3667 3668 // fold vector ops 3669 if (VT.isVector()) { 3670 SDOperand FoldedVOp = SimplifyVBinOp(N); 3671 if (FoldedVOp.Val) return FoldedVOp; 3672 } 3673 3674 // fold (fsub c1, c2) -> c1-c2 3675 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3676 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3677 // fold (0-B) -> -B 3678 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3679 if (isNegatibleForFree(N1, AfterLegalize)) 3680 return GetNegatedExpression(N1, DAG, AfterLegalize); 3681 return DAG.getNode(ISD::FNEG, VT, N1); 3682 } 3683 // fold (A-(-B)) -> A+B 3684 if (isNegatibleForFree(N1, AfterLegalize)) 3685 return DAG.getNode(ISD::FADD, VT, N0, 3686 GetNegatedExpression(N1, DAG, AfterLegalize)); 3687 3688 return SDOperand(); 3689} 3690 3691SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3692 SDOperand N0 = N->getOperand(0); 3693 SDOperand N1 = N->getOperand(1); 3694 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3695 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3696 MVT VT = N->getValueType(0); 3697 3698 // fold vector ops 3699 if (VT.isVector()) { 3700 SDOperand FoldedVOp = SimplifyVBinOp(N); 3701 if (FoldedVOp.Val) return FoldedVOp; 3702 } 3703 3704 // fold (fmul c1, c2) -> c1*c2 3705 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3706 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3707 // canonicalize constant to RHS 3708 if (N0CFP && !N1CFP) 3709 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3710 // fold (fmul X, 2.0) -> (fadd X, X) 3711 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3712 return DAG.getNode(ISD::FADD, VT, N0, N0); 3713 // fold (fmul X, -1.0) -> (fneg X) 3714 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3715 return DAG.getNode(ISD::FNEG, VT, N0); 3716 3717 // -X * -Y -> X*Y 3718 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3719 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3720 // Both can be negated for free, check to see if at least one is cheaper 3721 // negated. 3722 if (LHSNeg == 2 || RHSNeg == 2) 3723 return DAG.getNode(ISD::FMUL, VT, 3724 GetNegatedExpression(N0, DAG, AfterLegalize), 3725 GetNegatedExpression(N1, DAG, AfterLegalize)); 3726 } 3727 } 3728 3729 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3730 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3731 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3732 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3733 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3734 3735 return SDOperand(); 3736} 3737 3738SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3739 SDOperand N0 = N->getOperand(0); 3740 SDOperand N1 = N->getOperand(1); 3741 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3742 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3743 MVT VT = N->getValueType(0); 3744 3745 // fold vector ops 3746 if (VT.isVector()) { 3747 SDOperand FoldedVOp = SimplifyVBinOp(N); 3748 if (FoldedVOp.Val) return FoldedVOp; 3749 } 3750 3751 // fold (fdiv c1, c2) -> c1/c2 3752 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3753 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3754 3755 3756 // -X / -Y -> X*Y 3757 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3758 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3759 // Both can be negated for free, check to see if at least one is cheaper 3760 // negated. 3761 if (LHSNeg == 2 || RHSNeg == 2) 3762 return DAG.getNode(ISD::FDIV, VT, 3763 GetNegatedExpression(N0, DAG, AfterLegalize), 3764 GetNegatedExpression(N1, DAG, AfterLegalize)); 3765 } 3766 } 3767 3768 return SDOperand(); 3769} 3770 3771SDOperand DAGCombiner::visitFREM(SDNode *N) { 3772 SDOperand N0 = N->getOperand(0); 3773 SDOperand N1 = N->getOperand(1); 3774 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3775 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3776 MVT VT = N->getValueType(0); 3777 3778 // fold (frem c1, c2) -> fmod(c1,c2) 3779 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3780 return DAG.getNode(ISD::FREM, VT, N0, N1); 3781 3782 return SDOperand(); 3783} 3784 3785SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3786 SDOperand N0 = N->getOperand(0); 3787 SDOperand N1 = N->getOperand(1); 3788 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3789 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3790 MVT VT = N->getValueType(0); 3791 3792 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3793 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3794 3795 if (N1CFP) { 3796 const APFloat& V = N1CFP->getValueAPF(); 3797 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3798 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3799 if (!V.isNegative()) 3800 return DAG.getNode(ISD::FABS, VT, N0); 3801 else 3802 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3803 } 3804 3805 // copysign(fabs(x), y) -> copysign(x, y) 3806 // copysign(fneg(x), y) -> copysign(x, y) 3807 // copysign(copysign(x,z), y) -> copysign(x, y) 3808 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3809 N0.getOpcode() == ISD::FCOPYSIGN) 3810 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3811 3812 // copysign(x, abs(y)) -> abs(x) 3813 if (N1.getOpcode() == ISD::FABS) 3814 return DAG.getNode(ISD::FABS, VT, N0); 3815 3816 // copysign(x, copysign(y,z)) -> copysign(x, z) 3817 if (N1.getOpcode() == ISD::FCOPYSIGN) 3818 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3819 3820 // copysign(x, fp_extend(y)) -> copysign(x, y) 3821 // copysign(x, fp_round(y)) -> copysign(x, y) 3822 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3823 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3824 3825 return SDOperand(); 3826} 3827 3828 3829 3830SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3831 SDOperand N0 = N->getOperand(0); 3832 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3833 MVT VT = N->getValueType(0); 3834 MVT OpVT = N0.getValueType(); 3835 3836 // fold (sint_to_fp c1) -> c1fp 3837 if (N0C && OpVT != MVT::ppcf128) 3838 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3839 3840 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3841 // but UINT_TO_FP is legal on this target, try to convert. 3842 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3843 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3844 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3845 if (DAG.SignBitIsZero(N0)) 3846 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3847 } 3848 3849 3850 return SDOperand(); 3851} 3852 3853SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3854 SDOperand N0 = N->getOperand(0); 3855 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3856 MVT VT = N->getValueType(0); 3857 MVT OpVT = N0.getValueType(); 3858 3859 // fold (uint_to_fp c1) -> c1fp 3860 if (N0C && OpVT != MVT::ppcf128) 3861 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3862 3863 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3864 // but SINT_TO_FP is legal on this target, try to convert. 3865 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3866 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3867 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3868 if (DAG.SignBitIsZero(N0)) 3869 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3870 } 3871 3872 return SDOperand(); 3873} 3874 3875SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3876 SDOperand N0 = N->getOperand(0); 3877 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3878 MVT VT = N->getValueType(0); 3879 3880 // fold (fp_to_sint c1fp) -> c1 3881 if (N0CFP) 3882 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3883 return SDOperand(); 3884} 3885 3886SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3887 SDOperand N0 = N->getOperand(0); 3888 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3889 MVT VT = N->getValueType(0); 3890 3891 // fold (fp_to_uint c1fp) -> c1 3892 if (N0CFP && VT != MVT::ppcf128) 3893 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3894 return SDOperand(); 3895} 3896 3897SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3898 SDOperand N0 = N->getOperand(0); 3899 SDOperand N1 = N->getOperand(1); 3900 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3901 MVT VT = N->getValueType(0); 3902 3903 // fold (fp_round c1fp) -> c1fp 3904 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3905 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3906 3907 // fold (fp_round (fp_extend x)) -> x 3908 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3909 return N0.getOperand(0); 3910 3911 // fold (fp_round (fp_round x)) -> (fp_round x) 3912 if (N0.getOpcode() == ISD::FP_ROUND) { 3913 // This is a value preserving truncation if both round's are. 3914 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3915 N0.Val->getConstantOperandVal(1) == 1; 3916 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3917 DAG.getIntPtrConstant(IsTrunc)); 3918 } 3919 3920 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3921 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3922 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3923 AddToWorkList(Tmp.Val); 3924 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3925 } 3926 3927 return SDOperand(); 3928} 3929 3930SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3931 SDOperand N0 = N->getOperand(0); 3932 MVT VT = N->getValueType(0); 3933 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3934 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3935 3936 // fold (fp_round_inreg c1fp) -> c1fp 3937 if (N0CFP) { 3938 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3939 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3940 } 3941 return SDOperand(); 3942} 3943 3944SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3945 SDOperand N0 = N->getOperand(0); 3946 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3947 MVT VT = N->getValueType(0); 3948 3949 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3950 if (N->hasOneUse() && 3951 N->use_begin().getUse().getSDOperand().getOpcode() == ISD::FP_ROUND) 3952 return SDOperand(); 3953 3954 // fold (fp_extend c1fp) -> c1fp 3955 if (N0CFP && VT != MVT::ppcf128) 3956 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3957 3958 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3959 // value of X. 3960 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3961 SDOperand In = N0.getOperand(0); 3962 if (In.getValueType() == VT) return In; 3963 if (VT.bitsLT(In.getValueType())) 3964 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3965 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3966 } 3967 3968 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3969 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3970 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3971 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3972 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3973 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3974 LN0->getBasePtr(), LN0->getSrcValue(), 3975 LN0->getSrcValueOffset(), 3976 N0.getValueType(), 3977 LN0->isVolatile(), 3978 LN0->getAlignment()); 3979 CombineTo(N, ExtLoad); 3980 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3981 DAG.getIntPtrConstant(1)), 3982 ExtLoad.getValue(1)); 3983 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3984 } 3985 3986 return SDOperand(); 3987} 3988 3989SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3990 SDOperand N0 = N->getOperand(0); 3991 3992 if (isNegatibleForFree(N0, AfterLegalize)) 3993 return GetNegatedExpression(N0, DAG, AfterLegalize); 3994 3995 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3996 // constant pool values. 3997 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3998 N0.getOperand(0).getValueType().isInteger() && 3999 !N0.getOperand(0).getValueType().isVector()) { 4000 SDOperand Int = N0.getOperand(0); 4001 MVT IntVT = Int.getValueType(); 4002 if (IntVT.isInteger() && !IntVT.isVector()) { 4003 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4004 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4005 AddToWorkList(Int.Val); 4006 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4007 } 4008 } 4009 4010 return SDOperand(); 4011} 4012 4013SDOperand DAGCombiner::visitFABS(SDNode *N) { 4014 SDOperand N0 = N->getOperand(0); 4015 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4016 MVT VT = N->getValueType(0); 4017 4018 // fold (fabs c1) -> fabs(c1) 4019 if (N0CFP && VT != MVT::ppcf128) 4020 return DAG.getNode(ISD::FABS, VT, N0); 4021 // fold (fabs (fabs x)) -> (fabs x) 4022 if (N0.getOpcode() == ISD::FABS) 4023 return N->getOperand(0); 4024 // fold (fabs (fneg x)) -> (fabs x) 4025 // fold (fabs (fcopysign x, y)) -> (fabs x) 4026 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4027 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4028 4029 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4030 // constant pool values. 4031 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 4032 N0.getOperand(0).getValueType().isInteger() && 4033 !N0.getOperand(0).getValueType().isVector()) { 4034 SDOperand Int = N0.getOperand(0); 4035 MVT IntVT = Int.getValueType(); 4036 if (IntVT.isInteger() && !IntVT.isVector()) { 4037 Int = DAG.getNode(ISD::AND, IntVT, Int, 4038 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4039 AddToWorkList(Int.Val); 4040 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4041 } 4042 } 4043 4044 return SDOperand(); 4045} 4046 4047SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 4048 SDOperand Chain = N->getOperand(0); 4049 SDOperand N1 = N->getOperand(1); 4050 SDOperand N2 = N->getOperand(2); 4051 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4052 4053 // never taken branch, fold to chain 4054 if (N1C && N1C->isNullValue()) 4055 return Chain; 4056 // unconditional branch 4057 if (N1C && N1C->getAPIntValue() == 1) 4058 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4059 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4060 // on the target. 4061 if (N1.getOpcode() == ISD::SETCC && 4062 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4063 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4064 N1.getOperand(0), N1.getOperand(1), N2); 4065 } 4066 return SDOperand(); 4067} 4068 4069// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4070// 4071SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 4072 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4073 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4074 4075 // Use SimplifySetCC to simplify SETCC's. 4076 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4077 if (Simp.Val) AddToWorkList(Simp.Val); 4078 4079 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 4080 4081 // fold br_cc true, dest -> br dest (unconditional branch) 4082 if (SCCC && !SCCC->isNullValue()) 4083 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4084 N->getOperand(4)); 4085 // fold br_cc false, dest -> unconditional fall through 4086 if (SCCC && SCCC->isNullValue()) 4087 return N->getOperand(0); 4088 4089 // fold to a simpler setcc 4090 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4091 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4092 Simp.getOperand(2), Simp.getOperand(0), 4093 Simp.getOperand(1), N->getOperand(4)); 4094 return SDOperand(); 4095} 4096 4097 4098/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4099/// pre-indexed load / store when the base pointer is an add or subtract 4100/// and it has other uses besides the load / store. After the 4101/// transformation, the new indexed load / store has effectively folded 4102/// the add / subtract in and all of its other uses are redirected to the 4103/// new load / store. 4104bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4105 if (!AfterLegalize) 4106 return false; 4107 4108 bool isLoad = true; 4109 SDOperand Ptr; 4110 MVT VT; 4111 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4112 if (LD->isIndexed()) 4113 return false; 4114 VT = LD->getMemoryVT(); 4115 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4116 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4117 return false; 4118 Ptr = LD->getBasePtr(); 4119 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4120 if (ST->isIndexed()) 4121 return false; 4122 VT = ST->getMemoryVT(); 4123 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4124 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4125 return false; 4126 Ptr = ST->getBasePtr(); 4127 isLoad = false; 4128 } else 4129 return false; 4130 4131 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4132 // out. There is no reason to make this a preinc/predec. 4133 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4134 Ptr.Val->hasOneUse()) 4135 return false; 4136 4137 // Ask the target to do addressing mode selection. 4138 SDOperand BasePtr; 4139 SDOperand Offset; 4140 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4141 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4142 return false; 4143 // Don't create a indexed load / store with zero offset. 4144 if (isa<ConstantSDNode>(Offset) && 4145 cast<ConstantSDNode>(Offset)->isNullValue()) 4146 return false; 4147 4148 // Try turning it into a pre-indexed load / store except when: 4149 // 1) The new base ptr is a frame index. 4150 // 2) If N is a store and the new base ptr is either the same as or is a 4151 // predecessor of the value being stored. 4152 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4153 // that would create a cycle. 4154 // 4) All uses are load / store ops that use it as old base ptr. 4155 4156 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4157 // (plus the implicit offset) to a register to preinc anyway. 4158 if (isa<FrameIndexSDNode>(BasePtr)) 4159 return false; 4160 4161 // Check #2. 4162 if (!isLoad) { 4163 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 4164 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4165 return false; 4166 } 4167 4168 // Now check for #3 and #4. 4169 bool RealUse = false; 4170 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4171 E = Ptr.Val->use_end(); I != E; ++I) { 4172 SDNode *Use = *I; 4173 if (Use == N) 4174 continue; 4175 if (Use->isPredecessorOf(N)) 4176 return false; 4177 4178 if (!((Use->getOpcode() == ISD::LOAD && 4179 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4180 (Use->getOpcode() == ISD::STORE && 4181 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4182 RealUse = true; 4183 } 4184 if (!RealUse) 4185 return false; 4186 4187 SDOperand Result; 4188 if (isLoad) 4189 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4190 else 4191 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4192 ++PreIndexedNodes; 4193 ++NodesCombined; 4194 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4195 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4196 DOUT << '\n'; 4197 WorkListRemover DeadNodes(*this); 4198 if (isLoad) { 4199 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4200 &DeadNodes); 4201 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4202 &DeadNodes); 4203 } else { 4204 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4205 &DeadNodes); 4206 } 4207 4208 // Finally, since the node is now dead, remove it from the graph. 4209 DAG.DeleteNode(N); 4210 4211 // Replace the uses of Ptr with uses of the updated base value. 4212 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4213 &DeadNodes); 4214 removeFromWorkList(Ptr.Val); 4215 DAG.DeleteNode(Ptr.Val); 4216 4217 return true; 4218} 4219 4220/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4221/// add / sub of the base pointer node into a post-indexed load / store. 4222/// The transformation folded the add / subtract into the new indexed 4223/// load / store effectively and all of its uses are redirected to the 4224/// new load / store. 4225bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4226 if (!AfterLegalize) 4227 return false; 4228 4229 bool isLoad = true; 4230 SDOperand Ptr; 4231 MVT VT; 4232 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4233 if (LD->isIndexed()) 4234 return false; 4235 VT = LD->getMemoryVT(); 4236 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4237 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4238 return false; 4239 Ptr = LD->getBasePtr(); 4240 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4241 if (ST->isIndexed()) 4242 return false; 4243 VT = ST->getMemoryVT(); 4244 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4245 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4246 return false; 4247 Ptr = ST->getBasePtr(); 4248 isLoad = false; 4249 } else 4250 return false; 4251 4252 if (Ptr.Val->hasOneUse()) 4253 return false; 4254 4255 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4256 E = Ptr.Val->use_end(); I != E; ++I) { 4257 SDNode *Op = *I; 4258 if (Op == N || 4259 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4260 continue; 4261 4262 SDOperand BasePtr; 4263 SDOperand Offset; 4264 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4265 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4266 if (Ptr == Offset) 4267 std::swap(BasePtr, Offset); 4268 if (Ptr != BasePtr) 4269 continue; 4270 // Don't create a indexed load / store with zero offset. 4271 if (isa<ConstantSDNode>(Offset) && 4272 cast<ConstantSDNode>(Offset)->isNullValue()) 4273 continue; 4274 4275 // Try turning it into a post-indexed load / store except when 4276 // 1) All uses are load / store ops that use it as base ptr. 4277 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4278 // nor a successor of N. Otherwise, if Op is folded that would 4279 // create a cycle. 4280 4281 // Check for #1. 4282 bool TryNext = false; 4283 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4284 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4285 SDNode *Use = *II; 4286 if (Use == Ptr.Val) 4287 continue; 4288 4289 // If all the uses are load / store addresses, then don't do the 4290 // transformation. 4291 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4292 bool RealUse = false; 4293 for (SDNode::use_iterator III = Use->use_begin(), 4294 EEE = Use->use_end(); III != EEE; ++III) { 4295 SDNode *UseUse = *III; 4296 if (!((UseUse->getOpcode() == ISD::LOAD && 4297 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4298 (UseUse->getOpcode() == ISD::STORE && 4299 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4300 RealUse = true; 4301 } 4302 4303 if (!RealUse) { 4304 TryNext = true; 4305 break; 4306 } 4307 } 4308 } 4309 if (TryNext) 4310 continue; 4311 4312 // Check for #2 4313 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4314 SDOperand Result = isLoad 4315 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4316 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4317 ++PostIndexedNodes; 4318 ++NodesCombined; 4319 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4320 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4321 DOUT << '\n'; 4322 WorkListRemover DeadNodes(*this); 4323 if (isLoad) { 4324 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4325 &DeadNodes); 4326 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4327 &DeadNodes); 4328 } else { 4329 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4330 &DeadNodes); 4331 } 4332 4333 // Finally, since the node is now dead, remove it from the graph. 4334 DAG.DeleteNode(N); 4335 4336 // Replace the uses of Use with uses of the updated base value. 4337 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4338 Result.getValue(isLoad ? 1 : 0), 4339 &DeadNodes); 4340 removeFromWorkList(Op); 4341 DAG.DeleteNode(Op); 4342 return true; 4343 } 4344 } 4345 } 4346 return false; 4347} 4348 4349/// InferAlignment - If we can infer some alignment information from this 4350/// pointer, return it. 4351static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4352 // If this is a direct reference to a stack slot, use information about the 4353 // stack slot's alignment. 4354 int FrameIdx = 1 << 31; 4355 int64_t FrameOffset = 0; 4356 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4357 FrameIdx = FI->getIndex(); 4358 } else if (Ptr.getOpcode() == ISD::ADD && 4359 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4360 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4361 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4362 FrameOffset = Ptr.getConstantOperandVal(1); 4363 } 4364 4365 if (FrameIdx != (1 << 31)) { 4366 // FIXME: Handle FI+CST. 4367 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4368 if (MFI.isFixedObjectIndex(FrameIdx)) { 4369 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4370 4371 // The alignment of the frame index can be determined from its offset from 4372 // the incoming frame position. If the frame object is at offset 32 and 4373 // the stack is guaranteed to be 16-byte aligned, then we know that the 4374 // object is 16-byte aligned. 4375 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4376 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4377 4378 // Finally, the frame object itself may have a known alignment. Factor 4379 // the alignment + offset into a new alignment. For example, if we know 4380 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4381 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4382 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4383 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4384 FrameOffset); 4385 return std::max(Align, FIInfoAlign); 4386 } 4387 } 4388 4389 return 0; 4390} 4391 4392SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4393 LoadSDNode *LD = cast<LoadSDNode>(N); 4394 SDOperand Chain = LD->getChain(); 4395 SDOperand Ptr = LD->getBasePtr(); 4396 4397 // Try to infer better alignment information than the load already has. 4398 if (LD->isUnindexed()) { 4399 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4400 if (Align > LD->getAlignment()) 4401 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4402 Chain, Ptr, LD->getSrcValue(), 4403 LD->getSrcValueOffset(), LD->getMemoryVT(), 4404 LD->isVolatile(), Align); 4405 } 4406 } 4407 4408 4409 // If load is not volatile and there are no uses of the loaded value (and 4410 // the updated indexed value in case of indexed loads), change uses of the 4411 // chain value into uses of the chain input (i.e. delete the dead load). 4412 if (!LD->isVolatile()) { 4413 if (N->getValueType(1) == MVT::Other) { 4414 // Unindexed loads. 4415 if (N->hasNUsesOfValue(0, 0)) { 4416 // It's not safe to use the two value CombineTo variant here. e.g. 4417 // v1, chain2 = load chain1, loc 4418 // v2, chain3 = load chain2, loc 4419 // v3 = add v2, c 4420 // Now we replace use of chain2 with chain1. This makes the second load 4421 // isomorphic to the one we are deleting, and thus makes this load live. 4422 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4423 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4424 DOUT << "\n"; 4425 WorkListRemover DeadNodes(*this); 4426 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4427 if (N->use_empty()) { 4428 removeFromWorkList(N); 4429 DAG.DeleteNode(N); 4430 } 4431 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4432 } 4433 } else { 4434 // Indexed loads. 4435 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4436 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4437 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4438 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4439 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4440 DOUT << " and 2 other values\n"; 4441 WorkListRemover DeadNodes(*this); 4442 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4443 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4444 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4445 &DeadNodes); 4446 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4447 removeFromWorkList(N); 4448 DAG.DeleteNode(N); 4449 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4450 } 4451 } 4452 } 4453 4454 // If this load is directly stored, replace the load value with the stored 4455 // value. 4456 // TODO: Handle store large -> read small portion. 4457 // TODO: Handle TRUNCSTORE/LOADEXT 4458 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4459 !LD->isVolatile()) { 4460 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4461 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4462 if (PrevST->getBasePtr() == Ptr && 4463 PrevST->getValue().getValueType() == N->getValueType(0)) 4464 return CombineTo(N, Chain.getOperand(1), Chain); 4465 } 4466 } 4467 4468 if (CombinerAA) { 4469 // Walk up chain skipping non-aliasing memory nodes. 4470 SDOperand BetterChain = FindBetterChain(N, Chain); 4471 4472 // If there is a better chain. 4473 if (Chain != BetterChain) { 4474 SDOperand ReplLoad; 4475 4476 // Replace the chain to void dependency. 4477 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4478 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4479 LD->getSrcValue(), LD->getSrcValueOffset(), 4480 LD->isVolatile(), LD->getAlignment()); 4481 } else { 4482 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4483 LD->getValueType(0), 4484 BetterChain, Ptr, LD->getSrcValue(), 4485 LD->getSrcValueOffset(), 4486 LD->getMemoryVT(), 4487 LD->isVolatile(), 4488 LD->getAlignment()); 4489 } 4490 4491 // Create token factor to keep old chain connected. 4492 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4493 Chain, ReplLoad.getValue(1)); 4494 4495 // Replace uses with load result and token factor. Don't add users 4496 // to work list. 4497 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4498 } 4499 } 4500 4501 // Try transforming N to an indexed load. 4502 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4503 return SDOperand(N, 0); 4504 4505 return SDOperand(); 4506} 4507 4508 4509SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4510 StoreSDNode *ST = cast<StoreSDNode>(N); 4511 SDOperand Chain = ST->getChain(); 4512 SDOperand Value = ST->getValue(); 4513 SDOperand Ptr = ST->getBasePtr(); 4514 4515 // Try to infer better alignment information than the store already has. 4516 if (ST->isUnindexed()) { 4517 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4518 if (Align > ST->getAlignment()) 4519 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4520 ST->getSrcValueOffset(), ST->getMemoryVT(), 4521 ST->isVolatile(), Align); 4522 } 4523 } 4524 4525 // If this is a store of a bit convert, store the input value if the 4526 // resultant store does not need a higher alignment than the original. 4527 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4528 ST->isUnindexed()) { 4529 unsigned Align = ST->getAlignment(); 4530 MVT SVT = Value.getOperand(0).getValueType(); 4531 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4532 getABITypeAlignment(SVT.getTypeForMVT()); 4533 if (Align <= OrigAlign && 4534 ((!AfterLegalize && !ST->isVolatile()) || 4535 TLI.isOperationLegal(ISD::STORE, SVT))) 4536 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4537 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4538 } 4539 4540 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4541 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4542 // NOTE: If the original store is volatile, this transform must not increase 4543 // the number of stores. For example, on x86-32 an f64 can be stored in one 4544 // processor operation but an i64 (which is not legal) requires two. So the 4545 // transform should not be done in this case. 4546 if (Value.getOpcode() != ISD::TargetConstantFP) { 4547 SDOperand Tmp; 4548 switch (CFP->getValueType(0).getSimpleVT()) { 4549 default: assert(0 && "Unknown FP type"); 4550 case MVT::f80: // We don't do this for these yet. 4551 case MVT::f128: 4552 case MVT::ppcf128: 4553 break; 4554 case MVT::f32: 4555 if ((!AfterLegalize && !ST->isVolatile()) || 4556 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4557 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4558 convertToAPInt().getZExtValue(), MVT::i32); 4559 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4560 ST->getSrcValueOffset(), ST->isVolatile(), 4561 ST->getAlignment()); 4562 } 4563 break; 4564 case MVT::f64: 4565 if ((!AfterLegalize && !ST->isVolatile()) || 4566 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4567 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4568 getZExtValue(), MVT::i64); 4569 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4570 ST->getSrcValueOffset(), ST->isVolatile(), 4571 ST->getAlignment()); 4572 } else if (!ST->isVolatile() && 4573 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4574 // Many FP stores are not made apparent until after legalize, e.g. for 4575 // argument passing. Since this is so common, custom legalize the 4576 // 64-bit integer store into two 32-bit stores. 4577 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4578 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4579 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4580 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4581 4582 int SVOffset = ST->getSrcValueOffset(); 4583 unsigned Alignment = ST->getAlignment(); 4584 bool isVolatile = ST->isVolatile(); 4585 4586 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4587 ST->getSrcValueOffset(), 4588 isVolatile, ST->getAlignment()); 4589 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4590 DAG.getConstant(4, Ptr.getValueType())); 4591 SVOffset += 4; 4592 Alignment = MinAlign(Alignment, 4U); 4593 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4594 SVOffset, isVolatile, Alignment); 4595 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4596 } 4597 break; 4598 } 4599 } 4600 } 4601 4602 if (CombinerAA) { 4603 // Walk up chain skipping non-aliasing memory nodes. 4604 SDOperand BetterChain = FindBetterChain(N, Chain); 4605 4606 // If there is a better chain. 4607 if (Chain != BetterChain) { 4608 // Replace the chain to avoid dependency. 4609 SDOperand ReplStore; 4610 if (ST->isTruncatingStore()) { 4611 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4612 ST->getSrcValue(),ST->getSrcValueOffset(), 4613 ST->getMemoryVT(), 4614 ST->isVolatile(), ST->getAlignment()); 4615 } else { 4616 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4617 ST->getSrcValue(), ST->getSrcValueOffset(), 4618 ST->isVolatile(), ST->getAlignment()); 4619 } 4620 4621 // Create token to keep both nodes around. 4622 SDOperand Token = 4623 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4624 4625 // Don't add users to work list. 4626 return CombineTo(N, Token, false); 4627 } 4628 } 4629 4630 // Try transforming N to an indexed store. 4631 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4632 return SDOperand(N, 0); 4633 4634 // FIXME: is there such a thing as a truncating indexed store? 4635 if (ST->isTruncatingStore() && ST->isUnindexed() && 4636 Value.getValueType().isInteger()) { 4637 // See if we can simplify the input to this truncstore with knowledge that 4638 // only the low bits are being used. For example: 4639 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4640 SDOperand Shorter = 4641 GetDemandedBits(Value, 4642 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4643 ST->getMemoryVT().getSizeInBits())); 4644 AddToWorkList(Value.Val); 4645 if (Shorter.Val) 4646 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4647 ST->getSrcValueOffset(), ST->getMemoryVT(), 4648 ST->isVolatile(), ST->getAlignment()); 4649 4650 // Otherwise, see if we can simplify the operation with 4651 // SimplifyDemandedBits, which only works if the value has a single use. 4652 if (SimplifyDemandedBits(Value, 4653 APInt::getLowBitsSet( 4654 Value.getValueSizeInBits(), 4655 ST->getMemoryVT().getSizeInBits()))) 4656 return SDOperand(N, 0); 4657 } 4658 4659 // If this is a load followed by a store to the same location, then the store 4660 // is dead/noop. 4661 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4662 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4663 ST->isUnindexed() && !ST->isVolatile() && 4664 // There can't be any side effects between the load and store, such as 4665 // a call or store. 4666 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4667 // The store is dead, remove it. 4668 return Chain; 4669 } 4670 } 4671 4672 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4673 // truncating store. We can do this even if this is already a truncstore. 4674 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4675 && Value.Val->hasOneUse() && ST->isUnindexed() && 4676 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4677 ST->getMemoryVT())) { 4678 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4679 ST->getSrcValueOffset(), ST->getMemoryVT(), 4680 ST->isVolatile(), ST->getAlignment()); 4681 } 4682 4683 return SDOperand(); 4684} 4685 4686SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4687 SDOperand InVec = N->getOperand(0); 4688 SDOperand InVal = N->getOperand(1); 4689 SDOperand EltNo = N->getOperand(2); 4690 4691 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4692 // vector with the inserted element. 4693 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4694 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4695 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4696 if (Elt < Ops.size()) 4697 Ops[Elt] = InVal; 4698 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4699 &Ops[0], Ops.size()); 4700 } 4701 4702 return SDOperand(); 4703} 4704 4705SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4706 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4707 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4708 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4709 4710 // Perform only after legalization to ensure build_vector / vector_shuffle 4711 // optimizations have already been done. 4712 if (!AfterLegalize) return SDOperand(); 4713 4714 SDOperand InVec = N->getOperand(0); 4715 SDOperand EltNo = N->getOperand(1); 4716 4717 if (isa<ConstantSDNode>(EltNo)) { 4718 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4719 bool NewLoad = false; 4720 MVT VT = InVec.getValueType(); 4721 MVT EVT = VT.getVectorElementType(); 4722 MVT LVT = EVT; 4723 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4724 MVT BCVT = InVec.getOperand(0).getValueType(); 4725 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4726 return SDOperand(); 4727 InVec = InVec.getOperand(0); 4728 EVT = BCVT.getVectorElementType(); 4729 NewLoad = true; 4730 } 4731 4732 LoadSDNode *LN0 = NULL; 4733 if (ISD::isNormalLoad(InVec.Val)) 4734 LN0 = cast<LoadSDNode>(InVec); 4735 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4736 InVec.getOperand(0).getValueType() == EVT && 4737 ISD::isNormalLoad(InVec.getOperand(0).Val)) { 4738 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4739 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4740 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4741 // => 4742 // (load $addr+1*size) 4743 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4744 getOperand(Elt))->getValue(); 4745 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4746 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4747 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4748 InVec = InVec.getOperand(0); 4749 if (ISD::isNormalLoad(InVec.Val)) { 4750 LN0 = cast<LoadSDNode>(InVec); 4751 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4752 } 4753 } 4754 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4755 return SDOperand(); 4756 4757 unsigned Align = LN0->getAlignment(); 4758 if (NewLoad) { 4759 // Check the resultant load doesn't need a higher alignment than the 4760 // original load. 4761 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4762 getABITypeAlignment(LVT.getTypeForMVT()); 4763 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4764 return SDOperand(); 4765 Align = NewAlign; 4766 } 4767 4768 SDOperand NewPtr = LN0->getBasePtr(); 4769 if (Elt) { 4770 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4771 MVT PtrType = NewPtr.getValueType(); 4772 if (TLI.isBigEndian()) 4773 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4774 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4775 DAG.getConstant(PtrOff, PtrType)); 4776 } 4777 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4778 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4779 LN0->isVolatile(), Align); 4780 } 4781 return SDOperand(); 4782} 4783 4784 4785SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4786 unsigned NumInScalars = N->getNumOperands(); 4787 MVT VT = N->getValueType(0); 4788 unsigned NumElts = VT.getVectorNumElements(); 4789 MVT EltType = VT.getVectorElementType(); 4790 4791 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4792 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4793 // at most two distinct vectors, turn this into a shuffle node. 4794 SDOperand VecIn1, VecIn2; 4795 for (unsigned i = 0; i != NumInScalars; ++i) { 4796 // Ignore undef inputs. 4797 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4798 4799 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4800 // constant index, bail out. 4801 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4802 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4803 VecIn1 = VecIn2 = SDOperand(0, 0); 4804 break; 4805 } 4806 4807 // If the input vector type disagrees with the result of the build_vector, 4808 // we can't make a shuffle. 4809 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4810 if (ExtractedFromVec.getValueType() != VT) { 4811 VecIn1 = VecIn2 = SDOperand(0, 0); 4812 break; 4813 } 4814 4815 // Otherwise, remember this. We allow up to two distinct input vectors. 4816 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4817 continue; 4818 4819 if (VecIn1.Val == 0) { 4820 VecIn1 = ExtractedFromVec; 4821 } else if (VecIn2.Val == 0) { 4822 VecIn2 = ExtractedFromVec; 4823 } else { 4824 // Too many inputs. 4825 VecIn1 = VecIn2 = SDOperand(0, 0); 4826 break; 4827 } 4828 } 4829 4830 // If everything is good, we can make a shuffle operation. 4831 if (VecIn1.Val) { 4832 SmallVector<SDOperand, 8> BuildVecIndices; 4833 for (unsigned i = 0; i != NumInScalars; ++i) { 4834 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4835 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4836 continue; 4837 } 4838 4839 SDOperand Extract = N->getOperand(i); 4840 4841 // If extracting from the first vector, just use the index directly. 4842 if (Extract.getOperand(0) == VecIn1) { 4843 BuildVecIndices.push_back(Extract.getOperand(1)); 4844 continue; 4845 } 4846 4847 // Otherwise, use InIdx + VecSize 4848 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4849 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4850 } 4851 4852 // Add count and size info. 4853 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4854 4855 // Return the new VECTOR_SHUFFLE node. 4856 SDOperand Ops[5]; 4857 Ops[0] = VecIn1; 4858 if (VecIn2.Val) { 4859 Ops[1] = VecIn2; 4860 } else { 4861 // Use an undef build_vector as input for the second operand. 4862 std::vector<SDOperand> UnOps(NumInScalars, 4863 DAG.getNode(ISD::UNDEF, 4864 EltType)); 4865 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4866 &UnOps[0], UnOps.size()); 4867 AddToWorkList(Ops[1].Val); 4868 } 4869 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4870 &BuildVecIndices[0], BuildVecIndices.size()); 4871 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4872 } 4873 4874 return SDOperand(); 4875} 4876 4877SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4878 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4879 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4880 // inputs come from at most two distinct vectors, turn this into a shuffle 4881 // node. 4882 4883 // If we only have one input vector, we don't need to do any concatenation. 4884 if (N->getNumOperands() == 1) { 4885 return N->getOperand(0); 4886 } 4887 4888 return SDOperand(); 4889} 4890 4891SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4892 SDOperand ShufMask = N->getOperand(2); 4893 unsigned NumElts = ShufMask.getNumOperands(); 4894 4895 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4896 bool isIdentity = true; 4897 for (unsigned i = 0; i != NumElts; ++i) { 4898 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4899 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4900 isIdentity = false; 4901 break; 4902 } 4903 } 4904 if (isIdentity) return N->getOperand(0); 4905 4906 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4907 isIdentity = true; 4908 for (unsigned i = 0; i != NumElts; ++i) { 4909 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4910 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4911 isIdentity = false; 4912 break; 4913 } 4914 } 4915 if (isIdentity) return N->getOperand(1); 4916 4917 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4918 // needed at all. 4919 bool isUnary = true; 4920 bool isSplat = true; 4921 int VecNum = -1; 4922 unsigned BaseIdx = 0; 4923 for (unsigned i = 0; i != NumElts; ++i) 4924 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4925 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4926 int V = (Idx < NumElts) ? 0 : 1; 4927 if (VecNum == -1) { 4928 VecNum = V; 4929 BaseIdx = Idx; 4930 } else { 4931 if (BaseIdx != Idx) 4932 isSplat = false; 4933 if (VecNum != V) { 4934 isUnary = false; 4935 break; 4936 } 4937 } 4938 } 4939 4940 SDOperand N0 = N->getOperand(0); 4941 SDOperand N1 = N->getOperand(1); 4942 // Normalize unary shuffle so the RHS is undef. 4943 if (isUnary && VecNum == 1) 4944 std::swap(N0, N1); 4945 4946 // If it is a splat, check if the argument vector is a build_vector with 4947 // all scalar elements the same. 4948 if (isSplat) { 4949 SDNode *V = N0.Val; 4950 4951 // If this is a bit convert that changes the element type of the vector but 4952 // not the number of vector elements, look through it. Be careful not to 4953 // look though conversions that change things like v4f32 to v2f64. 4954 if (V->getOpcode() == ISD::BIT_CONVERT) { 4955 SDOperand ConvInput = V->getOperand(0); 4956 if (ConvInput.getValueType().isVector() && 4957 ConvInput.getValueType().getVectorNumElements() == NumElts) 4958 V = ConvInput.Val; 4959 } 4960 4961 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4962 unsigned NumElems = V->getNumOperands(); 4963 if (NumElems > BaseIdx) { 4964 SDOperand Base; 4965 bool AllSame = true; 4966 for (unsigned i = 0; i != NumElems; ++i) { 4967 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4968 Base = V->getOperand(i); 4969 break; 4970 } 4971 } 4972 // Splat of <u, u, u, u>, return <u, u, u, u> 4973 if (!Base.Val) 4974 return N0; 4975 for (unsigned i = 0; i != NumElems; ++i) { 4976 if (V->getOperand(i) != Base) { 4977 AllSame = false; 4978 break; 4979 } 4980 } 4981 // Splat of <x, x, x, x>, return <x, x, x, x> 4982 if (AllSame) 4983 return N0; 4984 } 4985 } 4986 } 4987 4988 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4989 // into an undef. 4990 if (isUnary || N0 == N1) { 4991 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4992 // first operand. 4993 SmallVector<SDOperand, 8> MappedOps; 4994 for (unsigned i = 0; i != NumElts; ++i) { 4995 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4996 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4997 MappedOps.push_back(ShufMask.getOperand(i)); 4998 } else { 4999 unsigned NewIdx = 5000 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 5001 MappedOps.push_back(DAG.getConstant(NewIdx, 5002 ShufMask.getOperand(i).getValueType())); 5003 } 5004 } 5005 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5006 &MappedOps[0], MappedOps.size()); 5007 AddToWorkList(ShufMask.Val); 5008 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5009 N0, 5010 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5011 ShufMask); 5012 } 5013 5014 return SDOperand(); 5015} 5016 5017/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5018/// an AND to a vector_shuffle with the destination vector and a zero vector. 5019/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5020/// vector_shuffle V, Zero, <0, 4, 2, 4> 5021SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5022 SDOperand LHS = N->getOperand(0); 5023 SDOperand RHS = N->getOperand(1); 5024 if (N->getOpcode() == ISD::AND) { 5025 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5026 RHS = RHS.getOperand(0); 5027 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5028 std::vector<SDOperand> IdxOps; 5029 unsigned NumOps = RHS.getNumOperands(); 5030 unsigned NumElts = NumOps; 5031 MVT EVT = RHS.getValueType().getVectorElementType(); 5032 for (unsigned i = 0; i != NumElts; ++i) { 5033 SDOperand Elt = RHS.getOperand(i); 5034 if (!isa<ConstantSDNode>(Elt)) 5035 return SDOperand(); 5036 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5037 IdxOps.push_back(DAG.getConstant(i, EVT)); 5038 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5039 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5040 else 5041 return SDOperand(); 5042 } 5043 5044 // Let's see if the target supports this vector_shuffle. 5045 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5046 return SDOperand(); 5047 5048 // Return the new VECTOR_SHUFFLE node. 5049 MVT VT = MVT::getVectorVT(EVT, NumElts); 5050 std::vector<SDOperand> Ops; 5051 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5052 Ops.push_back(LHS); 5053 AddToWorkList(LHS.Val); 5054 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5055 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5056 &ZeroOps[0], ZeroOps.size())); 5057 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5058 &IdxOps[0], IdxOps.size())); 5059 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5060 &Ops[0], Ops.size()); 5061 if (VT != N->getValueType(0)) 5062 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5063 return Result; 5064 } 5065 } 5066 return SDOperand(); 5067} 5068 5069/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5070SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 5071 // After legalize, the target may be depending on adds and other 5072 // binary ops to provide legal ways to construct constants or other 5073 // things. Simplifying them may result in a loss of legality. 5074 if (AfterLegalize) return SDOperand(); 5075 5076 MVT VT = N->getValueType(0); 5077 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5078 5079 MVT EltType = VT.getVectorElementType(); 5080 SDOperand LHS = N->getOperand(0); 5081 SDOperand RHS = N->getOperand(1); 5082 SDOperand Shuffle = XformToShuffleWithZero(N); 5083 if (Shuffle.Val) return Shuffle; 5084 5085 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5086 // this operation. 5087 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5088 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5089 SmallVector<SDOperand, 8> Ops; 5090 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5091 SDOperand LHSOp = LHS.getOperand(i); 5092 SDOperand RHSOp = RHS.getOperand(i); 5093 // If these two elements can't be folded, bail out. 5094 if ((LHSOp.getOpcode() != ISD::UNDEF && 5095 LHSOp.getOpcode() != ISD::Constant && 5096 LHSOp.getOpcode() != ISD::ConstantFP) || 5097 (RHSOp.getOpcode() != ISD::UNDEF && 5098 RHSOp.getOpcode() != ISD::Constant && 5099 RHSOp.getOpcode() != ISD::ConstantFP)) 5100 break; 5101 // Can't fold divide by zero. 5102 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5103 N->getOpcode() == ISD::FDIV) { 5104 if ((RHSOp.getOpcode() == ISD::Constant && 5105 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 5106 (RHSOp.getOpcode() == ISD::ConstantFP && 5107 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 5108 break; 5109 } 5110 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5111 AddToWorkList(Ops.back().Val); 5112 assert((Ops.back().getOpcode() == ISD::UNDEF || 5113 Ops.back().getOpcode() == ISD::Constant || 5114 Ops.back().getOpcode() == ISD::ConstantFP) && 5115 "Scalar binop didn't fold!"); 5116 } 5117 5118 if (Ops.size() == LHS.getNumOperands()) { 5119 MVT VT = LHS.getValueType(); 5120 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5121 } 5122 } 5123 5124 return SDOperand(); 5125} 5126 5127SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 5128 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5129 5130 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5131 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5132 // If we got a simplified select_cc node back from SimplifySelectCC, then 5133 // break it down into a new SETCC node, and a new SELECT node, and then return 5134 // the SELECT node, since we were called with a SELECT node. 5135 if (SCC.Val) { 5136 // Check to see if we got a select_cc back (to turn into setcc/select). 5137 // Otherwise, just return whatever node we got back, like fabs. 5138 if (SCC.getOpcode() == ISD::SELECT_CC) { 5139 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5140 SCC.getOperand(0), SCC.getOperand(1), 5141 SCC.getOperand(4)); 5142 AddToWorkList(SETCC.Val); 5143 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5144 SCC.getOperand(3), SETCC); 5145 } 5146 return SCC; 5147 } 5148 return SDOperand(); 5149} 5150 5151/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5152/// are the two values being selected between, see if we can simplify the 5153/// select. Callers of this should assume that TheSelect is deleted if this 5154/// returns true. As such, they should return the appropriate thing (e.g. the 5155/// node) back to the top-level of the DAG combiner loop to avoid it being 5156/// looked at. 5157/// 5158bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 5159 SDOperand RHS) { 5160 5161 // If this is a select from two identical things, try to pull the operation 5162 // through the select. 5163 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5164 // If this is a load and the token chain is identical, replace the select 5165 // of two loads with a load through a select of the address to load from. 5166 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5167 // constants have been dropped into the constant pool. 5168 if (LHS.getOpcode() == ISD::LOAD && 5169 // Do not let this transformation reduce the number of volatile loads. 5170 !cast<LoadSDNode>(LHS)->isVolatile() && 5171 !cast<LoadSDNode>(RHS)->isVolatile() && 5172 // Token chains must be identical. 5173 LHS.getOperand(0) == RHS.getOperand(0)) { 5174 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5175 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5176 5177 // If this is an EXTLOAD, the VT's must match. 5178 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5179 // FIXME: this conflates two src values, discarding one. This is not 5180 // the right thing to do, but nothing uses srcvalues now. When they do, 5181 // turn SrcValue into a list of locations. 5182 SDOperand Addr; 5183 if (TheSelect->getOpcode() == ISD::SELECT) { 5184 // Check that the condition doesn't reach either load. If so, folding 5185 // this will induce a cycle into the DAG. 5186 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5187 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5188 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5189 TheSelect->getOperand(0), LLD->getBasePtr(), 5190 RLD->getBasePtr()); 5191 } 5192 } else { 5193 // Check that the condition doesn't reach either load. If so, folding 5194 // this will induce a cycle into the DAG. 5195 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5196 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5197 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5198 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5199 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5200 TheSelect->getOperand(0), 5201 TheSelect->getOperand(1), 5202 LLD->getBasePtr(), RLD->getBasePtr(), 5203 TheSelect->getOperand(4)); 5204 } 5205 } 5206 5207 if (Addr.Val) { 5208 SDOperand Load; 5209 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5210 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5211 Addr,LLD->getSrcValue(), 5212 LLD->getSrcValueOffset(), 5213 LLD->isVolatile(), 5214 LLD->getAlignment()); 5215 else { 5216 Load = DAG.getExtLoad(LLD->getExtensionType(), 5217 TheSelect->getValueType(0), 5218 LLD->getChain(), Addr, LLD->getSrcValue(), 5219 LLD->getSrcValueOffset(), 5220 LLD->getMemoryVT(), 5221 LLD->isVolatile(), 5222 LLD->getAlignment()); 5223 } 5224 // Users of the select now use the result of the load. 5225 CombineTo(TheSelect, Load); 5226 5227 // Users of the old loads now use the new load's chain. We know the 5228 // old-load value is dead now. 5229 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5230 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5231 return true; 5232 } 5233 } 5234 } 5235 } 5236 5237 return false; 5238} 5239 5240SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5241 SDOperand N2, SDOperand N3, 5242 ISD::CondCode CC, bool NotExtCompare) { 5243 5244 MVT VT = N2.getValueType(); 5245 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5246 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5247 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5248 5249 // Determine if the condition we're dealing with is constant 5250 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5251 if (SCC.Val) AddToWorkList(SCC.Val); 5252 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5253 5254 // fold select_cc true, x, y -> x 5255 if (SCCC && !SCCC->isNullValue()) 5256 return N2; 5257 // fold select_cc false, x, y -> y 5258 if (SCCC && SCCC->isNullValue()) 5259 return N3; 5260 5261 // Check to see if we can simplify the select into an fabs node 5262 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5263 // Allow either -0.0 or 0.0 5264 if (CFP->getValueAPF().isZero()) { 5265 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5266 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5267 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5268 N2 == N3.getOperand(0)) 5269 return DAG.getNode(ISD::FABS, VT, N0); 5270 5271 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5272 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5273 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5274 N2.getOperand(0) == N3) 5275 return DAG.getNode(ISD::FABS, VT, N3); 5276 } 5277 } 5278 5279 // Check to see if we can perform the "gzip trick", transforming 5280 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5281 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5282 N0.getValueType().isInteger() && 5283 N2.getValueType().isInteger() && 5284 (N1C->isNullValue() || // (a < 0) ? b : 0 5285 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5286 MVT XType = N0.getValueType(); 5287 MVT AType = N2.getValueType(); 5288 if (XType.bitsGE(AType)) { 5289 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5290 // single-bit constant. 5291 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5292 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5293 ShCtV = XType.getSizeInBits()-ShCtV-1; 5294 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5295 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5296 AddToWorkList(Shift.Val); 5297 if (XType.bitsGT(AType)) { 5298 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5299 AddToWorkList(Shift.Val); 5300 } 5301 return DAG.getNode(ISD::AND, AType, Shift, N2); 5302 } 5303 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5304 DAG.getConstant(XType.getSizeInBits()-1, 5305 TLI.getShiftAmountTy())); 5306 AddToWorkList(Shift.Val); 5307 if (XType.bitsGT(AType)) { 5308 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5309 AddToWorkList(Shift.Val); 5310 } 5311 return DAG.getNode(ISD::AND, AType, Shift, N2); 5312 } 5313 } 5314 5315 // fold select C, 16, 0 -> shl C, 4 5316 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5317 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5318 5319 // If the caller doesn't want us to simplify this into a zext of a compare, 5320 // don't do it. 5321 if (NotExtCompare && N2C->getAPIntValue() == 1) 5322 return SDOperand(); 5323 5324 // Get a SetCC of the condition 5325 // FIXME: Should probably make sure that setcc is legal if we ever have a 5326 // target where it isn't. 5327 SDOperand Temp, SCC; 5328 // cast from setcc result type to select result type 5329 if (AfterLegalize) { 5330 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5331 if (N2.getValueType().bitsLT(SCC.getValueType())) 5332 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5333 else 5334 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5335 } else { 5336 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5337 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5338 } 5339 AddToWorkList(SCC.Val); 5340 AddToWorkList(Temp.Val); 5341 5342 if (N2C->getAPIntValue() == 1) 5343 return Temp; 5344 // shl setcc result by log2 n2c 5345 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5346 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5347 TLI.getShiftAmountTy())); 5348 } 5349 5350 // Check to see if this is the equivalent of setcc 5351 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5352 // otherwise, go ahead with the folds. 5353 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5354 MVT XType = N0.getValueType(); 5355 if (!AfterLegalize || 5356 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5357 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5358 if (Res.getValueType() != VT) 5359 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5360 return Res; 5361 } 5362 5363 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5364 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5365 (!AfterLegalize || 5366 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5367 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5368 return DAG.getNode(ISD::SRL, XType, Ctlz, 5369 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5370 TLI.getShiftAmountTy())); 5371 } 5372 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5373 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5374 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5375 N0); 5376 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5377 DAG.getConstant(~0ULL, XType)); 5378 return DAG.getNode(ISD::SRL, XType, 5379 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5380 DAG.getConstant(XType.getSizeInBits()-1, 5381 TLI.getShiftAmountTy())); 5382 } 5383 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5384 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5385 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5386 DAG.getConstant(XType.getSizeInBits()-1, 5387 TLI.getShiftAmountTy())); 5388 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5389 } 5390 } 5391 5392 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5393 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5394 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5395 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5396 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5397 MVT XType = N0.getValueType(); 5398 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5399 DAG.getConstant(XType.getSizeInBits()-1, 5400 TLI.getShiftAmountTy())); 5401 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5402 AddToWorkList(Shift.Val); 5403 AddToWorkList(Add.Val); 5404 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5405 } 5406 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5407 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5408 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5409 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5410 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5411 MVT XType = N0.getValueType(); 5412 if (SubC->isNullValue() && XType.isInteger()) { 5413 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5414 DAG.getConstant(XType.getSizeInBits()-1, 5415 TLI.getShiftAmountTy())); 5416 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5417 AddToWorkList(Shift.Val); 5418 AddToWorkList(Add.Val); 5419 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5420 } 5421 } 5422 } 5423 5424 return SDOperand(); 5425} 5426 5427/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5428SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0, 5429 SDOperand N1, ISD::CondCode Cond, 5430 bool foldBooleans) { 5431 TargetLowering::DAGCombinerInfo 5432 DagCombineInfo(DAG, !AfterLegalize, false, this); 5433 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5434} 5435 5436/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5437/// return a DAG expression to select that will generate the same value by 5438/// multiplying by a magic number. See: 5439/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5440SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5441 std::vector<SDNode*> Built; 5442 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5443 5444 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5445 ii != ee; ++ii) 5446 AddToWorkList(*ii); 5447 return S; 5448} 5449 5450/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5451/// return a DAG expression to select that will generate the same value by 5452/// multiplying by a magic number. See: 5453/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5454SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5455 std::vector<SDNode*> Built; 5456 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5457 5458 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5459 ii != ee; ++ii) 5460 AddToWorkList(*ii); 5461 return S; 5462} 5463 5464/// FindBaseOffset - Return true if base is known not to alias with anything 5465/// but itself. Provides base object and offset as results. 5466static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5467 // Assume it is a primitive operation. 5468 Base = Ptr; Offset = 0; 5469 5470 // If it's an adding a simple constant then integrate the offset. 5471 if (Base.getOpcode() == ISD::ADD) { 5472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5473 Base = Base.getOperand(0); 5474 Offset += C->getValue(); 5475 } 5476 } 5477 5478 // If it's any of the following then it can't alias with anything but itself. 5479 return isa<FrameIndexSDNode>(Base) || 5480 isa<ConstantPoolSDNode>(Base) || 5481 isa<GlobalAddressSDNode>(Base); 5482} 5483 5484/// isAlias - Return true if there is any possibility that the two addresses 5485/// overlap. 5486bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5487 const Value *SrcValue1, int SrcValueOffset1, 5488 SDOperand Ptr2, int64_t Size2, 5489 const Value *SrcValue2, int SrcValueOffset2) 5490{ 5491 // If they are the same then they must be aliases. 5492 if (Ptr1 == Ptr2) return true; 5493 5494 // Gather base node and offset information. 5495 SDOperand Base1, Base2; 5496 int64_t Offset1, Offset2; 5497 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5498 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5499 5500 // If they have a same base address then... 5501 if (Base1 == Base2) { 5502 // Check to see if the addresses overlap. 5503 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5504 } 5505 5506 // If we know both bases then they can't alias. 5507 if (KnownBase1 && KnownBase2) return false; 5508 5509 if (CombinerGlobalAA) { 5510 // Use alias analysis information. 5511 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5512 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5513 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5514 AliasAnalysis::AliasResult AAResult = 5515 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5516 if (AAResult == AliasAnalysis::NoAlias) 5517 return false; 5518 } 5519 5520 // Otherwise we have to assume they alias. 5521 return true; 5522} 5523 5524/// FindAliasInfo - Extracts the relevant alias information from the memory 5525/// node. Returns true if the operand was a load. 5526bool DAGCombiner::FindAliasInfo(SDNode *N, 5527 SDOperand &Ptr, int64_t &Size, 5528 const Value *&SrcValue, int &SrcValueOffset) { 5529 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5530 Ptr = LD->getBasePtr(); 5531 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5532 SrcValue = LD->getSrcValue(); 5533 SrcValueOffset = LD->getSrcValueOffset(); 5534 return true; 5535 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5536 Ptr = ST->getBasePtr(); 5537 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5538 SrcValue = ST->getSrcValue(); 5539 SrcValueOffset = ST->getSrcValueOffset(); 5540 } else { 5541 assert(0 && "FindAliasInfo expected a memory operand"); 5542 } 5543 5544 return false; 5545} 5546 5547/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5548/// looking for aliasing nodes and adding them to the Aliases vector. 5549void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5550 SmallVector<SDOperand, 8> &Aliases) { 5551 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5552 std::set<SDNode *> Visited; // Visited node set. 5553 5554 // Get alias information for node. 5555 SDOperand Ptr; 5556 int64_t Size; 5557 const Value *SrcValue; 5558 int SrcValueOffset; 5559 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5560 5561 // Starting off. 5562 Chains.push_back(OriginalChain); 5563 5564 // Look at each chain and determine if it is an alias. If so, add it to the 5565 // aliases list. If not, then continue up the chain looking for the next 5566 // candidate. 5567 while (!Chains.empty()) { 5568 SDOperand Chain = Chains.back(); 5569 Chains.pop_back(); 5570 5571 // Don't bother if we've been before. 5572 if (Visited.find(Chain.Val) != Visited.end()) continue; 5573 Visited.insert(Chain.Val); 5574 5575 switch (Chain.getOpcode()) { 5576 case ISD::EntryToken: 5577 // Entry token is ideal chain operand, but handled in FindBetterChain. 5578 break; 5579 5580 case ISD::LOAD: 5581 case ISD::STORE: { 5582 // Get alias information for Chain. 5583 SDOperand OpPtr; 5584 int64_t OpSize; 5585 const Value *OpSrcValue; 5586 int OpSrcValueOffset; 5587 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5588 OpSrcValue, OpSrcValueOffset); 5589 5590 // If chain is alias then stop here. 5591 if (!(IsLoad && IsOpLoad) && 5592 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5593 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5594 Aliases.push_back(Chain); 5595 } else { 5596 // Look further up the chain. 5597 Chains.push_back(Chain.getOperand(0)); 5598 // Clean up old chain. 5599 AddToWorkList(Chain.Val); 5600 } 5601 break; 5602 } 5603 5604 case ISD::TokenFactor: 5605 // We have to check each of the operands of the token factor, so we queue 5606 // then up. Adding the operands to the queue (stack) in reverse order 5607 // maintains the original order and increases the likelihood that getNode 5608 // will find a matching token factor (CSE.) 5609 for (unsigned n = Chain.getNumOperands(); n;) 5610 Chains.push_back(Chain.getOperand(--n)); 5611 // Eliminate the token factor if we can. 5612 AddToWorkList(Chain.Val); 5613 break; 5614 5615 default: 5616 // For all other instructions we will just have to take what we can get. 5617 Aliases.push_back(Chain); 5618 break; 5619 } 5620 } 5621} 5622 5623/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5624/// for a better chain (aliasing node.) 5625SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5626 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5627 5628 // Accumulate all the aliases to this node. 5629 GatherAllAliases(N, OldChain, Aliases); 5630 5631 if (Aliases.size() == 0) { 5632 // If no operands then chain to entry token. 5633 return DAG.getEntryNode(); 5634 } else if (Aliases.size() == 1) { 5635 // If a single operand then chain to it. We don't need to revisit it. 5636 return Aliases[0]; 5637 } 5638 5639 // Construct a custom tailored token factor. 5640 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5641 &Aliases[0], Aliases.size()); 5642 5643 // Make sure the old chain gets cleaned up. 5644 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5645 5646 return NewChain; 5647} 5648 5649// SelectionDAG::Combine - This is the entry point for the file. 5650// 5651void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5652 /// run - This is the main entry point to this class. 5653 /// 5654 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5655} 5656