DAGCombiner.cpp revision 99a6cb92d173c142073416c81efe6d3daeb80b49
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.Val == 0 - No change was made 129 // SDValue.Val == N - N was replaced, is dead, and is already handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 194 SDValue XformToShuffleWithZero(SDNode *N); 195 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 196 197 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 198 199 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 200 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 201 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 202 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 203 SDValue N3, ISD::CondCode CC, 204 bool NotExtCompare = false); 205 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 206 ISD::CondCode Cond, bool foldBooleans = true); 207 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 208 unsigned HiOp); 209 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 210 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 211 SDValue BuildSDIV(SDNode *N); 212 SDValue BuildUDIV(SDNode *N); 213 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 214 SDValue ReduceLoadWidth(SDNode *N); 215 216 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 217 218 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 219 /// looking for aliasing nodes and adding them to the Aliases vector. 220 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 221 SmallVector<SDValue, 8> &Aliases); 222 223 /// isAlias - Return true if there is any possibility that the two addresses 224 /// overlap. 225 bool isAlias(SDValue Ptr1, int64_t Size1, 226 const Value *SrcValue1, int SrcValueOffset1, 227 SDValue Ptr2, int64_t Size2, 228 const Value *SrcValue2, int SrcValueOffset2); 229 230 /// FindAliasInfo - Extracts the relevant alias information from the memory 231 /// node. Returns true if the operand was a load. 232 bool FindAliasInfo(SDNode *N, 233 SDValue &Ptr, int64_t &Size, 234 const Value *&SrcValue, int &SrcValueOffset); 235 236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 237 /// looking for a better chain (aliasing node.) 238 SDValue FindBetterChain(SDNode *N, SDValue Chain); 239 240public: 241 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 242 : DAG(D), 243 TLI(D.getTargetLoweringInfo()), 244 AfterLegalize(false), 245 Fast(fast), 246 AA(A) {} 247 248 /// Run - runs the dag combiner on all nodes in the work list 249 void Run(bool RunningAfterLegalize); 250 }; 251} 252 253 254namespace { 255/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 256/// nodes from the worklist. 257class VISIBILITY_HIDDEN WorkListRemover : 258 public SelectionDAG::DAGUpdateListener { 259 DAGCombiner &DC; 260public: 261 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 262 263 virtual void NodeDeleted(SDNode *N, SDNode *E) { 264 DC.removeFromWorkList(N); 265 } 266 267 virtual void NodeUpdated(SDNode *N) { 268 // Ignore updates. 269 } 270}; 271} 272 273//===----------------------------------------------------------------------===// 274// TargetLowering::DAGCombinerInfo implementation 275//===----------------------------------------------------------------------===// 276 277void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 278 ((DAGCombiner*)DC)->AddToWorkList(N); 279} 280 281SDValue TargetLowering::DAGCombinerInfo:: 282CombineTo(SDNode *N, const std::vector<SDValue> &To) { 283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 284} 285 286SDValue TargetLowering::DAGCombinerInfo:: 287CombineTo(SDNode *N, SDValue Res) { 288 return ((DAGCombiner*)DC)->CombineTo(N, Res); 289} 290 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 295} 296 297 298//===----------------------------------------------------------------------===// 299// Helper Functions 300//===----------------------------------------------------------------------===// 301 302/// isNegatibleForFree - Return 1 if we can compute the negated form of the 303/// specified expression for the same cost as the expression itself, or 2 if we 304/// can compute the negated form more cheaply than the expression itself. 305static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 306 unsigned Depth = 0) { 307 // No compile time optimizations on this type. 308 if (Op.getValueType() == MVT::ppcf128) 309 return 0; 310 311 // fneg is removable even if it has multiple uses. 312 if (Op.getOpcode() == ISD::FNEG) return 2; 313 314 // Don't allow anything with multiple uses. 315 if (!Op.hasOneUse()) return 0; 316 317 // Don't recurse exponentially. 318 if (Depth > 6) return 0; 319 320 switch (Op.getOpcode()) { 321 default: return false; 322 case ISD::ConstantFP: 323 // Don't invert constant FP values after legalize. The negated constant 324 // isn't necessarily legal. 325 return AfterLegalize ? 0 : 1; 326 case ISD::FADD: 327 // FIXME: determine better conditions for this xform. 328 if (!UnsafeFPMath) return 0; 329 330 // -(A+B) -> -A - B 331 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 332 return V; 333 // -(A+B) -> -B - A 334 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 335 case ISD::FSUB: 336 // We can't turn -(A-B) into B-A when we honor signed zeros. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A-B) -> B-A 340 return 1; 341 342 case ISD::FMUL: 343 case ISD::FDIV: 344 if (HonorSignDependentRoundingFPMath()) return 0; 345 346 // -(X*Y) -> (-X * Y) or (X*-Y) 347 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 348 return V; 349 350 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 351 352 case ISD::FP_EXTEND: 353 case ISD::FP_ROUND: 354 case ISD::FSIN: 355 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 356 } 357} 358 359/// GetNegatedExpression - If isNegatibleForFree returns true, this function 360/// returns the newly negated expression. 361static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 362 bool AfterLegalize, unsigned Depth = 0) { 363 // fneg is removable even if it has multiple uses. 364 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 365 366 // Don't allow anything with multiple uses. 367 assert(Op.hasOneUse() && "Unknown reuse!"); 368 369 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 370 switch (Op.getOpcode()) { 371 default: assert(0 && "Unknown code"); 372 case ISD::ConstantFP: { 373 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 374 V.changeSign(); 375 return DAG.getConstantFP(V, Op.getValueType()); 376 } 377 case ISD::FADD: 378 // FIXME: determine better conditions for this xform. 379 assert(UnsafeFPMath); 380 381 // -(A+B) -> -A - B 382 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 383 return DAG.getNode(ISD::FSUB, Op.getValueType(), 384 GetNegatedExpression(Op.getOperand(0), DAG, 385 AfterLegalize, Depth+1), 386 Op.getOperand(1)); 387 // -(A+B) -> -B - A 388 return DAG.getNode(ISD::FSUB, Op.getValueType(), 389 GetNegatedExpression(Op.getOperand(1), DAG, 390 AfterLegalize, Depth+1), 391 Op.getOperand(0)); 392 case ISD::FSUB: 393 // We can't turn -(A-B) into B-A when we honor signed zeros. 394 assert(UnsafeFPMath); 395 396 // -(0-B) -> B 397 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 398 if (N0CFP->getValueAPF().isZero()) 399 return Op.getOperand(1); 400 401 // -(A-B) -> B-A 402 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 403 Op.getOperand(0)); 404 405 case ISD::FMUL: 406 case ISD::FDIV: 407 assert(!HonorSignDependentRoundingFPMath()); 408 409 // -(X*Y) -> -X * Y 410 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 411 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 AfterLegalize, Depth+1), 414 Op.getOperand(1)); 415 416 // -(X*Y) -> X * -Y 417 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 418 Op.getOperand(0), 419 GetNegatedExpression(Op.getOperand(1), DAG, 420 AfterLegalize, Depth+1)); 421 422 case ISD::FP_EXTEND: 423 case ISD::FSIN: 424 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 AfterLegalize, Depth+1)); 427 case ISD::FP_ROUND: 428 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 AfterLegalize, Depth+1), 431 Op.getOperand(1)); 432 } 433} 434 435 436// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 437// that selects between the values 1 and 0, making it equivalent to a setcc. 438// Also, set the incoming LHS, RHS, and CC references to the appropriate 439// nodes based on the type of node we are checking. This simplifies life a 440// bit for the callers. 441static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 442 SDValue &CC) { 443 if (N.getOpcode() == ISD::SETCC) { 444 LHS = N.getOperand(0); 445 RHS = N.getOperand(1); 446 CC = N.getOperand(2); 447 return true; 448 } 449 if (N.getOpcode() == ISD::SELECT_CC && 450 N.getOperand(2).getOpcode() == ISD::Constant && 451 N.getOperand(3).getOpcode() == ISD::Constant && 452 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(4); 457 return true; 458 } 459 return false; 460} 461 462// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 463// one use. If this is true, it allows the users to invert the operation for 464// free when it is profitable to do so. 465static bool isOneUseSetCC(SDValue N) { 466 SDValue N0, N1, N2; 467 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 468 return true; 469 return false; 470} 471 472SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 473 MVT VT = N0.getValueType(); 474 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 475 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 476 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 477 if (isa<ConstantSDNode>(N1)) { 478 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 479 AddToWorkList(OpNode.Val); 480 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 481 } else if (N0.hasOneUse()) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 483 AddToWorkList(OpNode.Val); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 485 } 486 } 487 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 488 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 489 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 490 if (isa<ConstantSDNode>(N0)) { 491 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 492 AddToWorkList(OpNode.Val); 493 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 494 } else if (N1.hasOneUse()) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 496 AddToWorkList(OpNode.Val); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 498 } 499 } 500 return SDValue(); 501} 502 503SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 504 bool AddTo) { 505 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 506 ++NodesCombined; 507 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 508 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 509 DOUT << " and " << NumTo-1 << " other values\n"; 510 WorkListRemover DeadNodes(*this); 511 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 512 513 if (AddTo) { 514 // Push the new nodes and any users onto the worklist 515 for (unsigned i = 0, e = NumTo; i != e; ++i) { 516 AddToWorkList(To[i].Val); 517 AddUsersToWorkList(To[i].Val); 518 } 519 } 520 521 // Nodes can be reintroduced into the worklist. Make sure we do not 522 // process a node that has been replaced. 523 removeFromWorkList(N); 524 525 // Finally, since the node is now dead, remove it from the graph. 526 DAG.DeleteNode(N); 527 return SDValue(N, 0); 528} 529 530/// SimplifyDemandedBits - Check the specified integer node value to see if 531/// it can be simplified or if things it uses can be simplified by bit 532/// propagation. If so, return true. 533bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 534 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 535 APInt KnownZero, KnownOne; 536 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 537 return false; 538 539 // Revisit the node. 540 AddToWorkList(Op.Val); 541 542 // Replace the old value with the new one. 543 ++NodesCombined; 544 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 545 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 546 DOUT << '\n'; 547 548 // Replace all uses. If any nodes become isomorphic to other nodes and 549 // are deleted, make sure to remove them from our worklist. 550 WorkListRemover DeadNodes(*this); 551 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 552 553 // Push the new node and any (possibly new) users onto the worklist. 554 AddToWorkList(TLO.New.Val); 555 AddUsersToWorkList(TLO.New.Val); 556 557 // Finally, if the node is now dead, remove it from the graph. The node 558 // may not be dead if the replacement process recursively simplified to 559 // something else needing this node. 560 if (TLO.Old.Val->use_empty()) { 561 removeFromWorkList(TLO.Old.Val); 562 563 // If the operands of this node are only used by the node, they will now 564 // be dead. Make sure to visit them first to delete dead nodes early. 565 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 566 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 567 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 568 569 DAG.DeleteNode(TLO.Old.Val); 570 } 571 return true; 572} 573 574//===----------------------------------------------------------------------===// 575// Main DAG Combiner implementation 576//===----------------------------------------------------------------------===// 577 578void DAGCombiner::Run(bool RunningAfterLegalize) { 579 // set the instance variable, so that the various visit routines may use it. 580 AfterLegalize = RunningAfterLegalize; 581 582 // Add all the dag nodes to the worklist. 583 WorkList.reserve(DAG.allnodes_size()); 584 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 585 E = DAG.allnodes_end(); I != E; ++I) 586 WorkList.push_back(I); 587 588 // Create a dummy node (which is not added to allnodes), that adds a reference 589 // to the root node, preventing it from being deleted, and tracking any 590 // changes of the root. 591 HandleSDNode Dummy(DAG.getRoot()); 592 593 // The root of the dag may dangle to deleted nodes until the dag combiner is 594 // done. Set it to null to avoid confusion. 595 DAG.setRoot(SDValue()); 596 597 // while the worklist isn't empty, inspect the node on the end of it and 598 // try and combine it. 599 while (!WorkList.empty()) { 600 SDNode *N = WorkList.back(); 601 WorkList.pop_back(); 602 603 // If N has no uses, it is dead. Make sure to revisit all N's operands once 604 // N is deleted from the DAG, since they too may now be dead or may have a 605 // reduced number of uses, allowing other xforms. 606 if (N->use_empty() && N != &Dummy) { 607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 608 AddToWorkList(N->getOperand(i).Val); 609 610 DAG.DeleteNode(N); 611 continue; 612 } 613 614 SDValue RV = combine(N); 615 616 if (RV.Val == 0) 617 continue; 618 619 ++NodesCombined; 620 621 // If we get back the same node we passed in, rather than a new node or 622 // zero, we know that the node must have defined multiple values and 623 // CombineTo was used. Since CombineTo takes care of the worklist 624 // mechanics for us, we have no work to do in this case. 625 if (RV.Val == N) 626 continue; 627 628 assert(N->getOpcode() != ISD::DELETED_NODE && 629 RV.Val->getOpcode() != ISD::DELETED_NODE && 630 "Node was deleted but visit returned new node!"); 631 632 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 633 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 634 DOUT << '\n'; 635 WorkListRemover DeadNodes(*this); 636 if (N->getNumValues() == RV.Val->getNumValues()) 637 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 638 else { 639 assert(N->getValueType(0) == RV.getValueType() && 640 N->getNumValues() == 1 && "Type mismatch"); 641 SDValue OpV = RV; 642 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 643 } 644 645 // Push the new node and any users onto the worklist 646 AddToWorkList(RV.Val); 647 AddUsersToWorkList(RV.Val); 648 649 // Add any uses of the old node to the worklist in case this node is the 650 // last one that uses them. They may become dead after this node is 651 // deleted. 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).Val); 654 655 // Nodes can be reintroduced into the worklist. Make sure we do not 656 // process a node that has been replaced. 657 removeFromWorkList(N); 658 659 // Finally, since the node is now dead, remove it from the graph. 660 DAG.DeleteNode(N); 661 } 662 663 // If the root changed (e.g. it was a dead load, update the root). 664 DAG.setRoot(Dummy.getValue()); 665} 666 667SDValue DAGCombiner::visit(SDNode *N) { 668 switch(N->getOpcode()) { 669 default: break; 670 case ISD::TokenFactor: return visitTokenFactor(N); 671 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 672 case ISD::ADD: return visitADD(N); 673 case ISD::SUB: return visitSUB(N); 674 case ISD::ADDC: return visitADDC(N); 675 case ISD::ADDE: return visitADDE(N); 676 case ISD::MUL: return visitMUL(N); 677 case ISD::SDIV: return visitSDIV(N); 678 case ISD::UDIV: return visitUDIV(N); 679 case ISD::SREM: return visitSREM(N); 680 case ISD::UREM: return visitUREM(N); 681 case ISD::MULHU: return visitMULHU(N); 682 case ISD::MULHS: return visitMULHS(N); 683 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 684 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 685 case ISD::SDIVREM: return visitSDIVREM(N); 686 case ISD::UDIVREM: return visitUDIVREM(N); 687 case ISD::AND: return visitAND(N); 688 case ISD::OR: return visitOR(N); 689 case ISD::XOR: return visitXOR(N); 690 case ISD::SHL: return visitSHL(N); 691 case ISD::SRA: return visitSRA(N); 692 case ISD::SRL: return visitSRL(N); 693 case ISD::CTLZ: return visitCTLZ(N); 694 case ISD::CTTZ: return visitCTTZ(N); 695 case ISD::CTPOP: return visitCTPOP(N); 696 case ISD::SELECT: return visitSELECT(N); 697 case ISD::SELECT_CC: return visitSELECT_CC(N); 698 case ISD::SETCC: return visitSETCC(N); 699 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 700 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 701 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 702 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 703 case ISD::TRUNCATE: return visitTRUNCATE(N); 704 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 705 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 706 case ISD::FADD: return visitFADD(N); 707 case ISD::FSUB: return visitFSUB(N); 708 case ISD::FMUL: return visitFMUL(N); 709 case ISD::FDIV: return visitFDIV(N); 710 case ISD::FREM: return visitFREM(N); 711 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 712 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 713 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 714 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 715 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 716 case ISD::FP_ROUND: return visitFP_ROUND(N); 717 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 718 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 719 case ISD::FNEG: return visitFNEG(N); 720 case ISD::FABS: return visitFABS(N); 721 case ISD::BRCOND: return visitBRCOND(N); 722 case ISD::BR_CC: return visitBR_CC(N); 723 case ISD::LOAD: return visitLOAD(N); 724 case ISD::STORE: return visitSTORE(N); 725 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 726 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 727 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 728 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 729 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 730 } 731 return SDValue(); 732} 733 734SDValue DAGCombiner::combine(SDNode *N) { 735 736 SDValue RV = visit(N); 737 738 // If nothing happened, try a target-specific DAG combine. 739 if (RV.Val == 0) { 740 assert(N->getOpcode() != ISD::DELETED_NODE && 741 "Node was deleted but visit returned NULL!"); 742 743 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 744 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 745 746 // Expose the DAG combiner to the target combiner impls. 747 TargetLowering::DAGCombinerInfo 748 DagCombineInfo(DAG, !AfterLegalize, false, this); 749 750 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 751 } 752 } 753 754 // If N is a commutative binary node, try commuting it to enable more 755 // sdisel CSE. 756 if (RV.Val == 0 && 757 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 758 N->getNumValues() == 1) { 759 SDValue N0 = N->getOperand(0); 760 SDValue N1 = N->getOperand(1); 761 // Constant operands are canonicalized to RHS. 762 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 763 SDValue Ops[] = { N1, N0 }; 764 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 765 Ops, 2); 766 if (CSENode) 767 return SDValue(CSENode, 0); 768 } 769 } 770 771 return RV; 772} 773 774/// getInputChainForNode - Given a node, return its input chain if it has one, 775/// otherwise return a null sd operand. 776static SDValue getInputChainForNode(SDNode *N) { 777 if (unsigned NumOps = N->getNumOperands()) { 778 if (N->getOperand(0).getValueType() == MVT::Other) 779 return N->getOperand(0); 780 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 781 return N->getOperand(NumOps-1); 782 for (unsigned i = 1; i < NumOps-1; ++i) 783 if (N->getOperand(i).getValueType() == MVT::Other) 784 return N->getOperand(i); 785 } 786 return SDValue(0, 0); 787} 788 789SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 790 // If N has two operands, where one has an input chain equal to the other, 791 // the 'other' chain is redundant. 792 if (N->getNumOperands() == 2) { 793 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 794 return N->getOperand(0); 795 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 796 return N->getOperand(1); 797 } 798 799 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 800 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 801 SmallPtrSet<SDNode*, 16> SeenOps; 802 bool Changed = false; // If we should replace this token factor. 803 804 // Start out with this token factor. 805 TFs.push_back(N); 806 807 // Iterate through token factors. The TFs grows when new token factors are 808 // encountered. 809 for (unsigned i = 0; i < TFs.size(); ++i) { 810 SDNode *TF = TFs[i]; 811 812 // Check each of the operands. 813 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 814 SDValue Op = TF->getOperand(i); 815 816 switch (Op.getOpcode()) { 817 case ISD::EntryToken: 818 // Entry tokens don't need to be added to the list. They are 819 // rededundant. 820 Changed = true; 821 break; 822 823 case ISD::TokenFactor: 824 if ((CombinerAA || Op.hasOneUse()) && 825 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 826 // Queue up for processing. 827 TFs.push_back(Op.Val); 828 // Clean up in case the token factor is removed. 829 AddToWorkList(Op.Val); 830 Changed = true; 831 break; 832 } 833 // Fall thru 834 835 default: 836 // Only add if it isn't already in the list. 837 if (SeenOps.insert(Op.Val)) 838 Ops.push_back(Op); 839 else 840 Changed = true; 841 break; 842 } 843 } 844 } 845 846 SDValue Result; 847 848 // If we've change things around then replace token factor. 849 if (Changed) { 850 if (Ops.empty()) { 851 // The entry token is the only possible outcome. 852 Result = DAG.getEntryNode(); 853 } else { 854 // New and improved token factor. 855 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 856 } 857 858 // Don't add users to work list. 859 return CombineTo(N, Result, false); 860 } 861 862 return Result; 863} 864 865/// MERGE_VALUES can always be eliminated. 866SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 867 WorkListRemover DeadNodes(*this); 868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 869 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 870 &DeadNodes); 871 removeFromWorkList(N); 872 DAG.DeleteNode(N); 873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 874} 875 876 877static 878SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 879 MVT VT = N0.getValueType(); 880 SDValue N00 = N0.getOperand(0); 881 SDValue N01 = N0.getOperand(1); 882 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 883 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 884 isa<ConstantSDNode>(N00.getOperand(1))) { 885 N0 = DAG.getNode(ISD::ADD, VT, 886 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 887 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 888 return DAG.getNode(ISD::ADD, VT, N0, N1); 889 } 890 return SDValue(); 891} 892 893static 894SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 895 SelectionDAG &DAG) { 896 MVT VT = N->getValueType(0); 897 unsigned Opc = N->getOpcode(); 898 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 899 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 900 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 901 ISD::CondCode CC = ISD::SETCC_INVALID; 902 if (isSlctCC) 903 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 904 else { 905 SDValue CCOp = Slct.getOperand(0); 906 if (CCOp.getOpcode() == ISD::SETCC) 907 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 908 } 909 910 bool DoXform = false; 911 bool InvCC = false; 912 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 913 "Bad input!"); 914 if (LHS.getOpcode() == ISD::Constant && 915 cast<ConstantSDNode>(LHS)->isNullValue()) 916 DoXform = true; 917 else if (CC != ISD::SETCC_INVALID && 918 RHS.getOpcode() == ISD::Constant && 919 cast<ConstantSDNode>(RHS)->isNullValue()) { 920 std::swap(LHS, RHS); 921 SDValue Op0 = Slct.getOperand(0); 922 bool isInt = (isSlctCC ? Op0.getValueType() : 923 Op0.getOperand(0).getValueType()).isInteger(); 924 CC = ISD::getSetCCInverse(CC, isInt); 925 DoXform = true; 926 InvCC = true; 927 } 928 929 if (DoXform) { 930 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 931 if (isSlctCC) 932 return DAG.getSelectCC(OtherOp, Result, 933 Slct.getOperand(0), Slct.getOperand(1), CC); 934 SDValue CCOp = Slct.getOperand(0); 935 if (InvCC) 936 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 937 CCOp.getOperand(1), CC); 938 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 939 } 940 return SDValue(); 941} 942 943SDValue DAGCombiner::visitADD(SDNode *N) { 944 SDValue N0 = N->getOperand(0); 945 SDValue N1 = N->getOperand(1); 946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 948 MVT VT = N0.getValueType(); 949 950 // fold vector ops 951 if (VT.isVector()) { 952 SDValue FoldedVOp = SimplifyVBinOp(N); 953 if (FoldedVOp.Val) return FoldedVOp; 954 } 955 956 // fold (add x, undef) -> undef 957 if (N0.getOpcode() == ISD::UNDEF) 958 return N0; 959 if (N1.getOpcode() == ISD::UNDEF) 960 return N1; 961 // fold (add c1, c2) -> c1+c2 962 if (N0C && N1C) 963 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 964 // canonicalize constant to RHS 965 if (N0C && !N1C) 966 return DAG.getNode(ISD::ADD, VT, N1, N0); 967 // fold (add x, 0) -> x 968 if (N1C && N1C->isNullValue()) 969 return N0; 970 // fold ((c1-A)+c2) -> (c1+c2)-A 971 if (N1C && N0.getOpcode() == ISD::SUB) 972 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 973 return DAG.getNode(ISD::SUB, VT, 974 DAG.getConstant(N1C->getAPIntValue()+ 975 N0C->getAPIntValue(), VT), 976 N0.getOperand(1)); 977 // reassociate add 978 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 979 if (RADD.Val != 0) 980 return RADD; 981 // fold ((0-A) + B) -> B-A 982 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 983 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 984 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 985 // fold (A + (0-B)) -> A-B 986 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 987 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 988 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 989 // fold (A+(B-A)) -> B 990 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 991 return N1.getOperand(0); 992 993 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 994 return SDValue(N, 0); 995 996 // fold (a+b) -> (a|b) iff a and b share no bits. 997 if (VT.isInteger() && !VT.isVector()) { 998 APInt LHSZero, LHSOne; 999 APInt RHSZero, RHSOne; 1000 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1001 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1002 if (LHSZero.getBoolValue()) { 1003 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1004 1005 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1006 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1007 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1008 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1009 return DAG.getNode(ISD::OR, VT, N0, N1); 1010 } 1011 } 1012 1013 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1014 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 1015 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1016 if (Result.Val) return Result; 1017 } 1018 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 1019 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1020 if (Result.Val) return Result; 1021 } 1022 1023 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1024 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1025 SDValue Result = combineSelectAndUse(N, N0, N1, DAG); 1026 if (Result.Val) return Result; 1027 } 1028 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1029 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1030 if (Result.Val) return Result; 1031 } 1032 1033 return SDValue(); 1034} 1035 1036SDValue DAGCombiner::visitADDC(SDNode *N) { 1037 SDValue N0 = N->getOperand(0); 1038 SDValue N1 = N->getOperand(1); 1039 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1040 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1041 MVT VT = N0.getValueType(); 1042 1043 // If the flag result is dead, turn this into an ADD. 1044 if (N->hasNUsesOfValue(0, 1)) 1045 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1046 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1047 1048 // canonicalize constant to RHS. 1049 if (N0C && !N1C) 1050 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1051 1052 // fold (addc x, 0) -> x + no carry out 1053 if (N1C && N1C->isNullValue()) 1054 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1055 1056 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1057 APInt LHSZero, LHSOne; 1058 APInt RHSZero, RHSOne; 1059 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1060 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1061 if (LHSZero.getBoolValue()) { 1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1063 1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1068 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1069 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1070 } 1071 1072 return SDValue(); 1073} 1074 1075SDValue DAGCombiner::visitADDE(SDNode *N) { 1076 SDValue N0 = N->getOperand(0); 1077 SDValue N1 = N->getOperand(1); 1078 SDValue CarryIn = N->getOperand(2); 1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1081 //MVT VT = N0.getValueType(); 1082 1083 // canonicalize constant to RHS 1084 if (N0C && !N1C) 1085 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1086 1087 // fold (adde x, y, false) -> (addc x, y) 1088 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1089 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1090 1091 return SDValue(); 1092} 1093 1094 1095 1096SDValue DAGCombiner::visitSUB(SDNode *N) { 1097 SDValue N0 = N->getOperand(0); 1098 SDValue N1 = N->getOperand(1); 1099 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1101 MVT VT = N0.getValueType(); 1102 1103 // fold vector ops 1104 if (VT.isVector()) { 1105 SDValue FoldedVOp = SimplifyVBinOp(N); 1106 if (FoldedVOp.Val) return FoldedVOp; 1107 } 1108 1109 // fold (sub x, x) -> 0 1110 if (N0 == N1) 1111 return DAG.getConstant(0, N->getValueType(0)); 1112 // fold (sub c1, c2) -> c1-c2 1113 if (N0C && N1C) 1114 return DAG.getNode(ISD::SUB, VT, N0, N1); 1115 // fold (sub x, c) -> (add x, -c) 1116 if (N1C) 1117 return DAG.getNode(ISD::ADD, VT, N0, 1118 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1119 // fold (A+B)-A -> B 1120 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1121 return N0.getOperand(1); 1122 // fold (A+B)-B -> A 1123 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1124 return N0.getOperand(0); 1125 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1126 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1127 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1128 if (Result.Val) return Result; 1129 } 1130 // If either operand of a sub is undef, the result is undef 1131 if (N0.getOpcode() == ISD::UNDEF) 1132 return N0; 1133 if (N1.getOpcode() == ISD::UNDEF) 1134 return N1; 1135 1136 return SDValue(); 1137} 1138 1139SDValue DAGCombiner::visitMUL(SDNode *N) { 1140 SDValue N0 = N->getOperand(0); 1141 SDValue N1 = N->getOperand(1); 1142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1144 MVT VT = N0.getValueType(); 1145 1146 // fold vector ops 1147 if (VT.isVector()) { 1148 SDValue FoldedVOp = SimplifyVBinOp(N); 1149 if (FoldedVOp.Val) return FoldedVOp; 1150 } 1151 1152 // fold (mul x, undef) -> 0 1153 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1154 return DAG.getConstant(0, VT); 1155 // fold (mul c1, c2) -> c1*c2 1156 if (N0C && N1C) 1157 return DAG.getNode(ISD::MUL, VT, N0, N1); 1158 // canonicalize constant to RHS 1159 if (N0C && !N1C) 1160 return DAG.getNode(ISD::MUL, VT, N1, N0); 1161 // fold (mul x, 0) -> 0 1162 if (N1C && N1C->isNullValue()) 1163 return N1; 1164 // fold (mul x, -1) -> 0-x 1165 if (N1C && N1C->isAllOnesValue()) 1166 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1167 // fold (mul x, (1 << c)) -> x << c 1168 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1169 return DAG.getNode(ISD::SHL, VT, N0, 1170 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1171 TLI.getShiftAmountTy())); 1172 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1173 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1174 // FIXME: If the input is something that is easily negated (e.g. a 1175 // single-use add), we should put the negate there. 1176 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1177 DAG.getNode(ISD::SHL, VT, N0, 1178 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1179 TLI.getShiftAmountTy()))); 1180 } 1181 1182 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1183 if (N1C && N0.getOpcode() == ISD::SHL && 1184 isa<ConstantSDNode>(N0.getOperand(1))) { 1185 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1186 AddToWorkList(C3.Val); 1187 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1188 } 1189 1190 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1191 // use. 1192 { 1193 SDValue Sh(0,0), Y(0,0); 1194 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1195 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1196 N0.Val->hasOneUse()) { 1197 Sh = N0; Y = N1; 1198 } else if (N1.getOpcode() == ISD::SHL && 1199 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1200 Sh = N1; Y = N0; 1201 } 1202 if (Sh.Val) { 1203 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1204 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1205 } 1206 } 1207 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1208 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1209 isa<ConstantSDNode>(N0.getOperand(1))) { 1210 return DAG.getNode(ISD::ADD, VT, 1211 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1212 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1213 } 1214 1215 // reassociate mul 1216 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1217 if (RMUL.Val != 0) 1218 return RMUL; 1219 1220 return SDValue(); 1221} 1222 1223SDValue DAGCombiner::visitSDIV(SDNode *N) { 1224 SDValue N0 = N->getOperand(0); 1225 SDValue N1 = N->getOperand(1); 1226 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1227 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1228 MVT VT = N->getValueType(0); 1229 1230 // fold vector ops 1231 if (VT.isVector()) { 1232 SDValue FoldedVOp = SimplifyVBinOp(N); 1233 if (FoldedVOp.Val) return FoldedVOp; 1234 } 1235 1236 // fold (sdiv c1, c2) -> c1/c2 1237 if (N0C && N1C && !N1C->isNullValue()) 1238 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1239 // fold (sdiv X, 1) -> X 1240 if (N1C && N1C->getSignExtended() == 1LL) 1241 return N0; 1242 // fold (sdiv X, -1) -> 0-X 1243 if (N1C && N1C->isAllOnesValue()) 1244 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1245 // If we know the sign bits of both operands are zero, strength reduce to a 1246 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1247 if (!VT.isVector()) { 1248 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1249 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1250 } 1251 // fold (sdiv X, pow2) -> simple ops after legalize 1252 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1253 (isPowerOf2_64(N1C->getSignExtended()) || 1254 isPowerOf2_64(-N1C->getSignExtended()))) { 1255 // If dividing by powers of two is cheap, then don't perform the following 1256 // fold. 1257 if (TLI.isPow2DivCheap()) 1258 return SDValue(); 1259 int64_t pow2 = N1C->getSignExtended(); 1260 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1261 unsigned lg2 = Log2_64(abs2); 1262 // Splat the sign bit into the register 1263 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1264 DAG.getConstant(VT.getSizeInBits()-1, 1265 TLI.getShiftAmountTy())); 1266 AddToWorkList(SGN.Val); 1267 // Add (N0 < 0) ? abs2 - 1 : 0; 1268 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1269 DAG.getConstant(VT.getSizeInBits()-lg2, 1270 TLI.getShiftAmountTy())); 1271 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1272 AddToWorkList(SRL.Val); 1273 AddToWorkList(ADD.Val); // Divide by pow2 1274 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1275 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1276 // If we're dividing by a positive value, we're done. Otherwise, we must 1277 // negate the result. 1278 if (pow2 > 0) 1279 return SRA; 1280 AddToWorkList(SRA.Val); 1281 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1282 } 1283 // if integer divide is expensive and we satisfy the requirements, emit an 1284 // alternate sequence. 1285 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1286 !TLI.isIntDivCheap()) { 1287 SDValue Op = BuildSDIV(N); 1288 if (Op.Val) return Op; 1289 } 1290 1291 // undef / X -> 0 1292 if (N0.getOpcode() == ISD::UNDEF) 1293 return DAG.getConstant(0, VT); 1294 // X / undef -> undef 1295 if (N1.getOpcode() == ISD::UNDEF) 1296 return N1; 1297 1298 return SDValue(); 1299} 1300 1301SDValue DAGCombiner::visitUDIV(SDNode *N) { 1302 SDValue N0 = N->getOperand(0); 1303 SDValue N1 = N->getOperand(1); 1304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1306 MVT VT = N->getValueType(0); 1307 1308 // fold vector ops 1309 if (VT.isVector()) { 1310 SDValue FoldedVOp = SimplifyVBinOp(N); 1311 if (FoldedVOp.Val) return FoldedVOp; 1312 } 1313 1314 // fold (udiv c1, c2) -> c1/c2 1315 if (N0C && N1C && !N1C->isNullValue()) 1316 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1317 // fold (udiv x, (1 << c)) -> x >>u c 1318 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1319 return DAG.getNode(ISD::SRL, VT, N0, 1320 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1321 TLI.getShiftAmountTy())); 1322 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1323 if (N1.getOpcode() == ISD::SHL) { 1324 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1325 if (SHC->getAPIntValue().isPowerOf2()) { 1326 MVT ADDVT = N1.getOperand(1).getValueType(); 1327 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1328 DAG.getConstant(SHC->getAPIntValue() 1329 .logBase2(), 1330 ADDVT)); 1331 AddToWorkList(Add.Val); 1332 return DAG.getNode(ISD::SRL, VT, N0, Add); 1333 } 1334 } 1335 } 1336 // fold (udiv x, c) -> alternate 1337 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1338 SDValue Op = BuildUDIV(N); 1339 if (Op.Val) return Op; 1340 } 1341 1342 // undef / X -> 0 1343 if (N0.getOpcode() == ISD::UNDEF) 1344 return DAG.getConstant(0, VT); 1345 // X / undef -> undef 1346 if (N1.getOpcode() == ISD::UNDEF) 1347 return N1; 1348 1349 return SDValue(); 1350} 1351 1352SDValue DAGCombiner::visitSREM(SDNode *N) { 1353 SDValue N0 = N->getOperand(0); 1354 SDValue N1 = N->getOperand(1); 1355 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1357 MVT VT = N->getValueType(0); 1358 1359 // fold (srem c1, c2) -> c1%c2 1360 if (N0C && N1C && !N1C->isNullValue()) 1361 return DAG.getNode(ISD::SREM, VT, N0, N1); 1362 // If we know the sign bits of both operands are zero, strength reduce to a 1363 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1364 if (!VT.isVector()) { 1365 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1366 return DAG.getNode(ISD::UREM, VT, N0, N1); 1367 } 1368 1369 // If X/C can be simplified by the division-by-constant logic, lower 1370 // X%C to the equivalent of X-X/C*C. 1371 if (N1C && !N1C->isNullValue()) { 1372 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1373 AddToWorkList(Div.Val); 1374 SDValue OptimizedDiv = combine(Div.Val); 1375 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1376 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1377 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1378 AddToWorkList(Mul.Val); 1379 return Sub; 1380 } 1381 } 1382 1383 // undef % X -> 0 1384 if (N0.getOpcode() == ISD::UNDEF) 1385 return DAG.getConstant(0, VT); 1386 // X % undef -> undef 1387 if (N1.getOpcode() == ISD::UNDEF) 1388 return N1; 1389 1390 return SDValue(); 1391} 1392 1393SDValue DAGCombiner::visitUREM(SDNode *N) { 1394 SDValue N0 = N->getOperand(0); 1395 SDValue N1 = N->getOperand(1); 1396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1398 MVT VT = N->getValueType(0); 1399 1400 // fold (urem c1, c2) -> c1%c2 1401 if (N0C && N1C && !N1C->isNullValue()) 1402 return DAG.getNode(ISD::UREM, VT, N0, N1); 1403 // fold (urem x, pow2) -> (and x, pow2-1) 1404 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1405 return DAG.getNode(ISD::AND, VT, N0, 1406 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1407 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1408 if (N1.getOpcode() == ISD::SHL) { 1409 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1410 if (SHC->getAPIntValue().isPowerOf2()) { 1411 SDValue Add = 1412 DAG.getNode(ISD::ADD, VT, N1, 1413 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1414 VT)); 1415 AddToWorkList(Add.Val); 1416 return DAG.getNode(ISD::AND, VT, N0, Add); 1417 } 1418 } 1419 } 1420 1421 // If X/C can be simplified by the division-by-constant logic, lower 1422 // X%C to the equivalent of X-X/C*C. 1423 if (N1C && !N1C->isNullValue()) { 1424 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1425 SDValue OptimizedDiv = combine(Div.Val); 1426 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1427 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1428 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1429 AddToWorkList(Mul.Val); 1430 return Sub; 1431 } 1432 } 1433 1434 // undef % X -> 0 1435 if (N0.getOpcode() == ISD::UNDEF) 1436 return DAG.getConstant(0, VT); 1437 // X % undef -> undef 1438 if (N1.getOpcode() == ISD::UNDEF) 1439 return N1; 1440 1441 return SDValue(); 1442} 1443 1444SDValue DAGCombiner::visitMULHS(SDNode *N) { 1445 SDValue N0 = N->getOperand(0); 1446 SDValue N1 = N->getOperand(1); 1447 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1448 MVT VT = N->getValueType(0); 1449 1450 // fold (mulhs x, 0) -> 0 1451 if (N1C && N1C->isNullValue()) 1452 return N1; 1453 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1454 if (N1C && N1C->getAPIntValue() == 1) 1455 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1456 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1457 TLI.getShiftAmountTy())); 1458 // fold (mulhs x, undef) -> 0 1459 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1460 return DAG.getConstant(0, VT); 1461 1462 return SDValue(); 1463} 1464 1465SDValue DAGCombiner::visitMULHU(SDNode *N) { 1466 SDValue N0 = N->getOperand(0); 1467 SDValue N1 = N->getOperand(1); 1468 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1469 MVT VT = N->getValueType(0); 1470 1471 // fold (mulhu x, 0) -> 0 1472 if (N1C && N1C->isNullValue()) 1473 return N1; 1474 // fold (mulhu x, 1) -> 0 1475 if (N1C && N1C->getAPIntValue() == 1) 1476 return DAG.getConstant(0, N0.getValueType()); 1477 // fold (mulhu x, undef) -> 0 1478 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1479 return DAG.getConstant(0, VT); 1480 1481 return SDValue(); 1482} 1483 1484/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1485/// compute two values. LoOp and HiOp give the opcodes for the two computations 1486/// that are being performed. Return true if a simplification was made. 1487/// 1488SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1489 unsigned HiOp) { 1490 // If the high half is not needed, just compute the low half. 1491 bool HiExists = N->hasAnyUseOfValue(1); 1492 if (!HiExists && 1493 (!AfterLegalize || 1494 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1495 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1496 N->getNumOperands()); 1497 return CombineTo(N, Res, Res); 1498 } 1499 1500 // If the low half is not needed, just compute the high half. 1501 bool LoExists = N->hasAnyUseOfValue(0); 1502 if (!LoExists && 1503 (!AfterLegalize || 1504 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1505 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1506 N->getNumOperands()); 1507 return CombineTo(N, Res, Res); 1508 } 1509 1510 // If both halves are used, return as it is. 1511 if (LoExists && HiExists) 1512 return SDValue(); 1513 1514 // If the two computed results can be simplified separately, separate them. 1515 if (LoExists) { 1516 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1517 N->op_begin(), N->getNumOperands()); 1518 AddToWorkList(Lo.Val); 1519 SDValue LoOpt = combine(Lo.Val); 1520 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1521 (!AfterLegalize || 1522 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1523 return CombineTo(N, LoOpt, LoOpt); 1524 } 1525 1526 if (HiExists) { 1527 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1528 N->op_begin(), N->getNumOperands()); 1529 AddToWorkList(Hi.Val); 1530 SDValue HiOpt = combine(Hi.Val); 1531 if (HiOpt.Val && HiOpt != Hi && 1532 (!AfterLegalize || 1533 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1534 return CombineTo(N, HiOpt, HiOpt); 1535 } 1536 return SDValue(); 1537} 1538 1539SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1540 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1541 if (Res.Val) return Res; 1542 1543 return SDValue(); 1544} 1545 1546SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1547 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1548 if (Res.Val) return Res; 1549 1550 return SDValue(); 1551} 1552 1553SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1554 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1555 if (Res.Val) return Res; 1556 1557 return SDValue(); 1558} 1559 1560SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1561 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1562 if (Res.Val) return Res; 1563 1564 return SDValue(); 1565} 1566 1567/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1568/// two operands of the same opcode, try to simplify it. 1569SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1570 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1571 MVT VT = N0.getValueType(); 1572 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1573 1574 // For each of OP in AND/OR/XOR: 1575 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1576 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1577 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1578 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1579 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1580 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1581 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1582 SDValue ORNode = DAG.getNode(N->getOpcode(), 1583 N0.getOperand(0).getValueType(), 1584 N0.getOperand(0), N1.getOperand(0)); 1585 AddToWorkList(ORNode.Val); 1586 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1587 } 1588 1589 // For each of OP in SHL/SRL/SRA/AND... 1590 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1591 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1592 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1593 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1594 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1595 N0.getOperand(1) == N1.getOperand(1)) { 1596 SDValue ORNode = DAG.getNode(N->getOpcode(), 1597 N0.getOperand(0).getValueType(), 1598 N0.getOperand(0), N1.getOperand(0)); 1599 AddToWorkList(ORNode.Val); 1600 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1601 } 1602 1603 return SDValue(); 1604} 1605 1606SDValue DAGCombiner::visitAND(SDNode *N) { 1607 SDValue N0 = N->getOperand(0); 1608 SDValue N1 = N->getOperand(1); 1609 SDValue LL, LR, RL, RR, CC0, CC1; 1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1612 MVT VT = N1.getValueType(); 1613 unsigned BitWidth = VT.getSizeInBits(); 1614 1615 // fold vector ops 1616 if (VT.isVector()) { 1617 SDValue FoldedVOp = SimplifyVBinOp(N); 1618 if (FoldedVOp.Val) return FoldedVOp; 1619 } 1620 1621 // fold (and x, undef) -> 0 1622 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1623 return DAG.getConstant(0, VT); 1624 // fold (and c1, c2) -> c1&c2 1625 if (N0C && N1C) 1626 return DAG.getNode(ISD::AND, VT, N0, N1); 1627 // canonicalize constant to RHS 1628 if (N0C && !N1C) 1629 return DAG.getNode(ISD::AND, VT, N1, N0); 1630 // fold (and x, -1) -> x 1631 if (N1C && N1C->isAllOnesValue()) 1632 return N0; 1633 // if (and x, c) is known to be zero, return 0 1634 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1635 APInt::getAllOnesValue(BitWidth))) 1636 return DAG.getConstant(0, VT); 1637 // reassociate and 1638 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1639 if (RAND.Val != 0) 1640 return RAND; 1641 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1642 if (N1C && N0.getOpcode() == ISD::OR) 1643 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1644 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1645 return N1; 1646 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1647 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1648 SDValue N0Op0 = N0.getOperand(0); 1649 APInt Mask = ~N1C->getAPIntValue(); 1650 Mask.trunc(N0Op0.getValueSizeInBits()); 1651 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1652 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1653 N0Op0); 1654 1655 // Replace uses of the AND with uses of the Zero extend node. 1656 CombineTo(N, Zext); 1657 1658 // We actually want to replace all uses of the any_extend with the 1659 // zero_extend, to avoid duplicating things. This will later cause this 1660 // AND to be folded. 1661 CombineTo(N0.Val, Zext); 1662 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1663 } 1664 } 1665 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1666 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1667 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1668 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1669 1670 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1671 LL.getValueType().isInteger()) { 1672 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1673 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1674 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1675 AddToWorkList(ORNode.Val); 1676 return DAG.getSetCC(VT, ORNode, LR, Op1); 1677 } 1678 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1679 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1680 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1681 AddToWorkList(ANDNode.Val); 1682 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1683 } 1684 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1685 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1686 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1687 AddToWorkList(ORNode.Val); 1688 return DAG.getSetCC(VT, ORNode, LR, Op1); 1689 } 1690 } 1691 // canonicalize equivalent to ll == rl 1692 if (LL == RR && LR == RL) { 1693 Op1 = ISD::getSetCCSwappedOperands(Op1); 1694 std::swap(RL, RR); 1695 } 1696 if (LL == RL && LR == RR) { 1697 bool isInteger = LL.getValueType().isInteger(); 1698 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1699 if (Result != ISD::SETCC_INVALID) 1700 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1701 } 1702 } 1703 1704 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1705 if (N0.getOpcode() == N1.getOpcode()) { 1706 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1707 if (Tmp.Val) return Tmp; 1708 } 1709 1710 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1711 // fold (and (sra)) -> (and (srl)) when possible. 1712 if (!VT.isVector() && 1713 SimplifyDemandedBits(SDValue(N, 0))) 1714 return SDValue(N, 0); 1715 // fold (zext_inreg (extload x)) -> (zextload x) 1716 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1717 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1718 MVT EVT = LN0->getMemoryVT(); 1719 // If we zero all the possible extended bits, then we can turn this into 1720 // a zextload if we are running before legalize or the operation is legal. 1721 unsigned BitWidth = N1.getValueSizeInBits(); 1722 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1723 BitWidth - EVT.getSizeInBits())) && 1724 ((!AfterLegalize && !LN0->isVolatile()) || 1725 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1726 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1727 LN0->getBasePtr(), LN0->getSrcValue(), 1728 LN0->getSrcValueOffset(), EVT, 1729 LN0->isVolatile(), 1730 LN0->getAlignment()); 1731 AddToWorkList(N); 1732 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1733 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1734 } 1735 } 1736 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1737 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1738 N0.hasOneUse()) { 1739 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1740 MVT EVT = LN0->getMemoryVT(); 1741 // If we zero all the possible extended bits, then we can turn this into 1742 // a zextload if we are running before legalize or the operation is legal. 1743 unsigned BitWidth = N1.getValueSizeInBits(); 1744 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1745 BitWidth - EVT.getSizeInBits())) && 1746 ((!AfterLegalize && !LN0->isVolatile()) || 1747 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1748 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1749 LN0->getBasePtr(), LN0->getSrcValue(), 1750 LN0->getSrcValueOffset(), EVT, 1751 LN0->isVolatile(), 1752 LN0->getAlignment()); 1753 AddToWorkList(N); 1754 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1755 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1756 } 1757 } 1758 1759 // fold (and (load x), 255) -> (zextload x, i8) 1760 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1761 if (N1C && N0.getOpcode() == ISD::LOAD) { 1762 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1763 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1764 LN0->isUnindexed() && N0.hasOneUse() && 1765 // Do not change the width of a volatile load. 1766 !LN0->isVolatile()) { 1767 MVT EVT = MVT::Other; 1768 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1769 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1770 EVT = MVT::getIntegerVT(ActiveBits); 1771 1772 MVT LoadedVT = LN0->getMemoryVT(); 1773 // Do not generate loads of non-round integer types since these can 1774 // be expensive (and would be wrong if the type is not byte sized). 1775 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1776 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1777 MVT PtrType = N0.getOperand(1).getValueType(); 1778 // For big endian targets, we need to add an offset to the pointer to 1779 // load the correct bytes. For little endian systems, we merely need to 1780 // read fewer bytes from the same pointer. 1781 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1782 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1783 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1784 unsigned Alignment = LN0->getAlignment(); 1785 SDValue NewPtr = LN0->getBasePtr(); 1786 if (TLI.isBigEndian()) { 1787 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1788 DAG.getConstant(PtrOff, PtrType)); 1789 Alignment = MinAlign(Alignment, PtrOff); 1790 } 1791 AddToWorkList(NewPtr.Val); 1792 SDValue Load = 1793 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1794 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1795 LN0->isVolatile(), Alignment); 1796 AddToWorkList(N); 1797 CombineTo(N0.Val, Load, Load.getValue(1)); 1798 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1799 } 1800 } 1801 } 1802 1803 return SDValue(); 1804} 1805 1806SDValue DAGCombiner::visitOR(SDNode *N) { 1807 SDValue N0 = N->getOperand(0); 1808 SDValue N1 = N->getOperand(1); 1809 SDValue LL, LR, RL, RR, CC0, CC1; 1810 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1812 MVT VT = N1.getValueType(); 1813 1814 // fold vector ops 1815 if (VT.isVector()) { 1816 SDValue FoldedVOp = SimplifyVBinOp(N); 1817 if (FoldedVOp.Val) return FoldedVOp; 1818 } 1819 1820 // fold (or x, undef) -> -1 1821 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1822 return DAG.getConstant(~0ULL, VT); 1823 // fold (or c1, c2) -> c1|c2 1824 if (N0C && N1C) 1825 return DAG.getNode(ISD::OR, VT, N0, N1); 1826 // canonicalize constant to RHS 1827 if (N0C && !N1C) 1828 return DAG.getNode(ISD::OR, VT, N1, N0); 1829 // fold (or x, 0) -> x 1830 if (N1C && N1C->isNullValue()) 1831 return N0; 1832 // fold (or x, -1) -> -1 1833 if (N1C && N1C->isAllOnesValue()) 1834 return N1; 1835 // fold (or x, c) -> c iff (x & ~c) == 0 1836 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1837 return N1; 1838 // reassociate or 1839 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1840 if (ROR.Val != 0) 1841 return ROR; 1842 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1843 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1844 isa<ConstantSDNode>(N0.getOperand(1))) { 1845 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1846 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1847 N1), 1848 DAG.getConstant(N1C->getAPIntValue() | 1849 C1->getAPIntValue(), VT)); 1850 } 1851 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1852 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1853 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1854 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1855 1856 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1857 LL.getValueType().isInteger()) { 1858 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1859 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1860 if (cast<ConstantSDNode>(LR)->isNullValue() && 1861 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1862 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1863 AddToWorkList(ORNode.Val); 1864 return DAG.getSetCC(VT, ORNode, LR, Op1); 1865 } 1866 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1867 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1868 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1869 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1870 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1871 AddToWorkList(ANDNode.Val); 1872 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1873 } 1874 } 1875 // canonicalize equivalent to ll == rl 1876 if (LL == RR && LR == RL) { 1877 Op1 = ISD::getSetCCSwappedOperands(Op1); 1878 std::swap(RL, RR); 1879 } 1880 if (LL == RL && LR == RR) { 1881 bool isInteger = LL.getValueType().isInteger(); 1882 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1883 if (Result != ISD::SETCC_INVALID) 1884 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1885 } 1886 } 1887 1888 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1889 if (N0.getOpcode() == N1.getOpcode()) { 1890 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1891 if (Tmp.Val) return Tmp; 1892 } 1893 1894 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1895 if (N0.getOpcode() == ISD::AND && 1896 N1.getOpcode() == ISD::AND && 1897 N0.getOperand(1).getOpcode() == ISD::Constant && 1898 N1.getOperand(1).getOpcode() == ISD::Constant && 1899 // Don't increase # computations. 1900 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1901 // We can only do this xform if we know that bits from X that are set in C2 1902 // but not in C1 are already zero. Likewise for Y. 1903 const APInt &LHSMask = 1904 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1905 const APInt &RHSMask = 1906 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1907 1908 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1909 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1910 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1911 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1912 } 1913 } 1914 1915 1916 // See if this is some rotate idiom. 1917 if (SDNode *Rot = MatchRotate(N0, N1)) 1918 return SDValue(Rot, 0); 1919 1920 return SDValue(); 1921} 1922 1923 1924/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1925static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1926 if (Op.getOpcode() == ISD::AND) { 1927 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1928 Mask = Op.getOperand(1); 1929 Op = Op.getOperand(0); 1930 } else { 1931 return false; 1932 } 1933 } 1934 1935 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1936 Shift = Op; 1937 return true; 1938 } 1939 return false; 1940} 1941 1942 1943// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1944// idioms for rotate, and if the target supports rotation instructions, generate 1945// a rot[lr]. 1946SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1947 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1948 MVT VT = LHS.getValueType(); 1949 if (!TLI.isTypeLegal(VT)) return 0; 1950 1951 // The target must have at least one rotate flavor. 1952 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1953 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1954 if (!HasROTL && !HasROTR) return 0; 1955 1956 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1957 SDValue LHSShift; // The shift. 1958 SDValue LHSMask; // AND value if any. 1959 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1960 return 0; // Not part of a rotate. 1961 1962 SDValue RHSShift; // The shift. 1963 SDValue RHSMask; // AND value if any. 1964 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1965 return 0; // Not part of a rotate. 1966 1967 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1968 return 0; // Not shifting the same value. 1969 1970 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1971 return 0; // Shifts must disagree. 1972 1973 // Canonicalize shl to left side in a shl/srl pair. 1974 if (RHSShift.getOpcode() == ISD::SHL) { 1975 std::swap(LHS, RHS); 1976 std::swap(LHSShift, RHSShift); 1977 std::swap(LHSMask , RHSMask ); 1978 } 1979 1980 unsigned OpSizeInBits = VT.getSizeInBits(); 1981 SDValue LHSShiftArg = LHSShift.getOperand(0); 1982 SDValue LHSShiftAmt = LHSShift.getOperand(1); 1983 SDValue RHSShiftAmt = RHSShift.getOperand(1); 1984 1985 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1986 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1987 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1988 RHSShiftAmt.getOpcode() == ISD::Constant) { 1989 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1990 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1991 if ((LShVal + RShVal) != OpSizeInBits) 1992 return 0; 1993 1994 SDValue Rot; 1995 if (HasROTL) 1996 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1997 else 1998 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1999 2000 // If there is an AND of either shifted operand, apply it to the result. 2001 if (LHSMask.Val || RHSMask.Val) { 2002 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2003 2004 if (LHSMask.Val) { 2005 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2006 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2007 } 2008 if (RHSMask.Val) { 2009 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2010 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2011 } 2012 2013 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2014 } 2015 2016 return Rot.Val; 2017 } 2018 2019 // If there is a mask here, and we have a variable shift, we can't be sure 2020 // that we're masking out the right stuff. 2021 if (LHSMask.Val || RHSMask.Val) 2022 return 0; 2023 2024 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2025 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2026 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2027 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2028 if (ConstantSDNode *SUBC = 2029 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2030 if (SUBC->getAPIntValue() == OpSizeInBits) { 2031 if (HasROTL) 2032 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2033 else 2034 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2035 } 2036 } 2037 } 2038 2039 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2040 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2041 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2042 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2043 if (ConstantSDNode *SUBC = 2044 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2045 if (SUBC->getAPIntValue() == OpSizeInBits) { 2046 if (HasROTL) 2047 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2048 else 2049 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2050 } 2051 } 2052 } 2053 2054 // Look for sign/zext/any-extended cases: 2055 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2056 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2057 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2058 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2059 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2060 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2061 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2062 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2063 if (RExtOp0.getOpcode() == ISD::SUB && 2064 RExtOp0.getOperand(1) == LExtOp0) { 2065 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2066 // (rotr x, y) 2067 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2068 // (rotl x, (sub 32, y)) 2069 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2070 if (SUBC->getAPIntValue() == OpSizeInBits) { 2071 if (HasROTL) 2072 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2073 else 2074 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2075 } 2076 } 2077 } else if (LExtOp0.getOpcode() == ISD::SUB && 2078 RExtOp0 == LExtOp0.getOperand(1)) { 2079 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2080 // (rotl x, y) 2081 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2082 // (rotr x, (sub 32, y)) 2083 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2084 if (SUBC->getAPIntValue() == OpSizeInBits) { 2085 if (HasROTL) 2086 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2087 else 2088 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2089 } 2090 } 2091 } 2092 } 2093 2094 return 0; 2095} 2096 2097 2098SDValue DAGCombiner::visitXOR(SDNode *N) { 2099 SDValue N0 = N->getOperand(0); 2100 SDValue N1 = N->getOperand(1); 2101 SDValue LHS, RHS, CC; 2102 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2103 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2104 MVT VT = N0.getValueType(); 2105 2106 // fold vector ops 2107 if (VT.isVector()) { 2108 SDValue FoldedVOp = SimplifyVBinOp(N); 2109 if (FoldedVOp.Val) return FoldedVOp; 2110 } 2111 2112 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2113 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2114 return DAG.getConstant(0, VT); 2115 // fold (xor x, undef) -> undef 2116 if (N0.getOpcode() == ISD::UNDEF) 2117 return N0; 2118 if (N1.getOpcode() == ISD::UNDEF) 2119 return N1; 2120 // fold (xor c1, c2) -> c1^c2 2121 if (N0C && N1C) 2122 return DAG.getNode(ISD::XOR, VT, N0, N1); 2123 // canonicalize constant to RHS 2124 if (N0C && !N1C) 2125 return DAG.getNode(ISD::XOR, VT, N1, N0); 2126 // fold (xor x, 0) -> x 2127 if (N1C && N1C->isNullValue()) 2128 return N0; 2129 // reassociate xor 2130 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2131 if (RXOR.Val != 0) 2132 return RXOR; 2133 // fold !(x cc y) -> (x !cc y) 2134 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2135 bool isInt = LHS.getValueType().isInteger(); 2136 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2137 isInt); 2138 if (N0.getOpcode() == ISD::SETCC) 2139 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2140 if (N0.getOpcode() == ISD::SELECT_CC) 2141 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2142 assert(0 && "Unhandled SetCC Equivalent!"); 2143 abort(); 2144 } 2145 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2146 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2147 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2148 SDValue V = N0.getOperand(0); 2149 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2150 DAG.getConstant(1, V.getValueType())); 2151 AddToWorkList(V.Val); 2152 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2153 } 2154 2155 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2156 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2157 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2158 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2159 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2160 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2161 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2162 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2163 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2164 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2165 } 2166 } 2167 // fold !(x or y) -> (!x and !y) iff x or y are constants 2168 if (N1C && N1C->isAllOnesValue() && 2169 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2170 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2171 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2172 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2173 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2174 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2175 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2176 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2177 } 2178 } 2179 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2180 if (N1C && N0.getOpcode() == ISD::XOR) { 2181 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2182 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2183 if (N00C) 2184 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2185 DAG.getConstant(N1C->getAPIntValue()^ 2186 N00C->getAPIntValue(), VT)); 2187 if (N01C) 2188 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2189 DAG.getConstant(N1C->getAPIntValue()^ 2190 N01C->getAPIntValue(), VT)); 2191 } 2192 // fold (xor x, x) -> 0 2193 if (N0 == N1) { 2194 if (!VT.isVector()) { 2195 return DAG.getConstant(0, VT); 2196 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2197 // Produce a vector of zeros. 2198 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2199 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2200 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2201 } 2202 } 2203 2204 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2205 if (N0.getOpcode() == N1.getOpcode()) { 2206 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2207 if (Tmp.Val) return Tmp; 2208 } 2209 2210 // Simplify the expression using non-local knowledge. 2211 if (!VT.isVector() && 2212 SimplifyDemandedBits(SDValue(N, 0))) 2213 return SDValue(N, 0); 2214 2215 return SDValue(); 2216} 2217 2218/// visitShiftByConstant - Handle transforms common to the three shifts, when 2219/// the shift amount is a constant. 2220SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2221 SDNode *LHS = N->getOperand(0).Val; 2222 if (!LHS->hasOneUse()) return SDValue(); 2223 2224 // We want to pull some binops through shifts, so that we have (and (shift)) 2225 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2226 // thing happens with address calculations, so it's important to canonicalize 2227 // it. 2228 bool HighBitSet = false; // Can we transform this if the high bit is set? 2229 2230 switch (LHS->getOpcode()) { 2231 default: return SDValue(); 2232 case ISD::OR: 2233 case ISD::XOR: 2234 HighBitSet = false; // We can only transform sra if the high bit is clear. 2235 break; 2236 case ISD::AND: 2237 HighBitSet = true; // We can only transform sra if the high bit is set. 2238 break; 2239 case ISD::ADD: 2240 if (N->getOpcode() != ISD::SHL) 2241 return SDValue(); // only shl(add) not sr[al](add). 2242 HighBitSet = false; // We can only transform sra if the high bit is clear. 2243 break; 2244 } 2245 2246 // We require the RHS of the binop to be a constant as well. 2247 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2248 if (!BinOpCst) return SDValue(); 2249 2250 2251 // FIXME: disable this for unless the input to the binop is a shift by a 2252 // constant. If it is not a shift, it pessimizes some common cases like: 2253 // 2254 //void foo(int *X, int i) { X[i & 1235] = 1; } 2255 //int bar(int *X, int i) { return X[i & 255]; } 2256 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2257 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2258 BinOpLHSVal->getOpcode() != ISD::SRA && 2259 BinOpLHSVal->getOpcode() != ISD::SRL) || 2260 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2261 return SDValue(); 2262 2263 MVT VT = N->getValueType(0); 2264 2265 // If this is a signed shift right, and the high bit is modified 2266 // by the logical operation, do not perform the transformation. 2267 // The highBitSet boolean indicates the value of the high bit of 2268 // the constant which would cause it to be modified for this 2269 // operation. 2270 if (N->getOpcode() == ISD::SRA) { 2271 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2272 if (BinOpRHSSignSet != HighBitSet) 2273 return SDValue(); 2274 } 2275 2276 // Fold the constants, shifting the binop RHS by the shift amount. 2277 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2278 LHS->getOperand(1), N->getOperand(1)); 2279 2280 // Create the new shift. 2281 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2282 N->getOperand(1)); 2283 2284 // Create the new binop. 2285 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2286} 2287 2288 2289SDValue DAGCombiner::visitSHL(SDNode *N) { 2290 SDValue N0 = N->getOperand(0); 2291 SDValue N1 = N->getOperand(1); 2292 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2293 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2294 MVT VT = N0.getValueType(); 2295 unsigned OpSizeInBits = VT.getSizeInBits(); 2296 2297 // fold (shl c1, c2) -> c1<<c2 2298 if (N0C && N1C) 2299 return DAG.getNode(ISD::SHL, VT, N0, N1); 2300 // fold (shl 0, x) -> 0 2301 if (N0C && N0C->isNullValue()) 2302 return N0; 2303 // fold (shl x, c >= size(x)) -> undef 2304 if (N1C && N1C->getValue() >= OpSizeInBits) 2305 return DAG.getNode(ISD::UNDEF, VT); 2306 // fold (shl x, 0) -> x 2307 if (N1C && N1C->isNullValue()) 2308 return N0; 2309 // if (shl x, c) is known to be zero, return 0 2310 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2311 APInt::getAllOnesValue(VT.getSizeInBits()))) 2312 return DAG.getConstant(0, VT); 2313 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2314 return SDValue(N, 0); 2315 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2316 if (N1C && N0.getOpcode() == ISD::SHL && 2317 N0.getOperand(1).getOpcode() == ISD::Constant) { 2318 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2319 uint64_t c2 = N1C->getValue(); 2320 if (c1 + c2 > OpSizeInBits) 2321 return DAG.getConstant(0, VT); 2322 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2323 DAG.getConstant(c1 + c2, N1.getValueType())); 2324 } 2325 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2326 // (srl (and x, -1 << c1), c1-c2) 2327 if (N1C && N0.getOpcode() == ISD::SRL && 2328 N0.getOperand(1).getOpcode() == ISD::Constant) { 2329 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2330 uint64_t c2 = N1C->getValue(); 2331 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2332 DAG.getConstant(~0ULL << c1, VT)); 2333 if (c2 > c1) 2334 return DAG.getNode(ISD::SHL, VT, Mask, 2335 DAG.getConstant(c2-c1, N1.getValueType())); 2336 else 2337 return DAG.getNode(ISD::SRL, VT, Mask, 2338 DAG.getConstant(c1-c2, N1.getValueType())); 2339 } 2340 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2341 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2342 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2343 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2344 2345 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue(); 2346} 2347 2348SDValue DAGCombiner::visitSRA(SDNode *N) { 2349 SDValue N0 = N->getOperand(0); 2350 SDValue N1 = N->getOperand(1); 2351 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2353 MVT VT = N0.getValueType(); 2354 2355 // fold (sra c1, c2) -> c1>>c2 2356 if (N0C && N1C) 2357 return DAG.getNode(ISD::SRA, VT, N0, N1); 2358 // fold (sra 0, x) -> 0 2359 if (N0C && N0C->isNullValue()) 2360 return N0; 2361 // fold (sra -1, x) -> -1 2362 if (N0C && N0C->isAllOnesValue()) 2363 return N0; 2364 // fold (sra x, c >= size(x)) -> undef 2365 if (N1C && N1C->getValue() >= VT.getSizeInBits()) 2366 return DAG.getNode(ISD::UNDEF, VT); 2367 // fold (sra x, 0) -> x 2368 if (N1C && N1C->isNullValue()) 2369 return N0; 2370 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2371 // sext_inreg. 2372 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2373 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue(); 2374 MVT EVT = MVT::getIntegerVT(LowBits); 2375 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2376 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2377 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2378 DAG.getValueType(EVT)); 2379 } 2380 2381 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2382 if (N1C && N0.getOpcode() == ISD::SRA) { 2383 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2384 unsigned Sum = N1C->getValue() + C1->getValue(); 2385 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2386 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2387 DAG.getConstant(Sum, N1C->getValueType(0))); 2388 } 2389 } 2390 2391 // fold sra (shl X, m), result_size - n 2392 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2393 // result_size - n != m. 2394 // If truncate is free for the target sext(shl) is likely to result in better 2395 // code. 2396 if (N0.getOpcode() == ISD::SHL) { 2397 // Get the two constanst of the shifts, CN0 = m, CN = n. 2398 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2399 if (N01C && N1C) { 2400 // Determine what the truncate's result bitsize and type would be. 2401 unsigned VTValSize = VT.getSizeInBits(); 2402 MVT TruncVT = 2403 MVT::getIntegerVT(VTValSize - N1C->getValue()); 2404 // Determine the residual right-shift amount. 2405 unsigned ShiftAmt = N1C->getValue() - N01C->getValue(); 2406 2407 // If the shift is not a no-op (in which case this should be just a sign 2408 // extend already), the truncated to type is legal, sign_extend is legal 2409 // on that type, and the the truncate to that type is both legal and free, 2410 // perform the transform. 2411 if (ShiftAmt && 2412 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2413 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2414 TLI.isTruncateFree(VT, TruncVT)) { 2415 2416 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2417 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2418 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2419 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2420 } 2421 } 2422 } 2423 2424 // Simplify, based on bits shifted out of the LHS. 2425 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2426 return SDValue(N, 0); 2427 2428 2429 // If the sign bit is known to be zero, switch this to a SRL. 2430 if (DAG.SignBitIsZero(N0)) 2431 return DAG.getNode(ISD::SRL, VT, N0, N1); 2432 2433 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue(); 2434} 2435 2436SDValue DAGCombiner::visitSRL(SDNode *N) { 2437 SDValue N0 = N->getOperand(0); 2438 SDValue N1 = N->getOperand(1); 2439 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2440 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2441 MVT VT = N0.getValueType(); 2442 unsigned OpSizeInBits = VT.getSizeInBits(); 2443 2444 // fold (srl c1, c2) -> c1 >>u c2 2445 if (N0C && N1C) 2446 return DAG.getNode(ISD::SRL, VT, N0, N1); 2447 // fold (srl 0, x) -> 0 2448 if (N0C && N0C->isNullValue()) 2449 return N0; 2450 // fold (srl x, c >= size(x)) -> undef 2451 if (N1C && N1C->getValue() >= OpSizeInBits) 2452 return DAG.getNode(ISD::UNDEF, VT); 2453 // fold (srl x, 0) -> x 2454 if (N1C && N1C->isNullValue()) 2455 return N0; 2456 // if (srl x, c) is known to be zero, return 0 2457 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2458 APInt::getAllOnesValue(OpSizeInBits))) 2459 return DAG.getConstant(0, VT); 2460 2461 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2462 if (N1C && N0.getOpcode() == ISD::SRL && 2463 N0.getOperand(1).getOpcode() == ISD::Constant) { 2464 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2465 uint64_t c2 = N1C->getValue(); 2466 if (c1 + c2 > OpSizeInBits) 2467 return DAG.getConstant(0, VT); 2468 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2469 DAG.getConstant(c1 + c2, N1.getValueType())); 2470 } 2471 2472 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2473 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2474 // Shifting in all undef bits? 2475 MVT SmallVT = N0.getOperand(0).getValueType(); 2476 if (N1C->getValue() >= SmallVT.getSizeInBits()) 2477 return DAG.getNode(ISD::UNDEF, VT); 2478 2479 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2480 AddToWorkList(SmallShift.Val); 2481 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2482 } 2483 2484 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2485 // bit, which is unmodified by sra. 2486 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) { 2487 if (N0.getOpcode() == ISD::SRA) 2488 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2489 } 2490 2491 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2492 if (N1C && N0.getOpcode() == ISD::CTLZ && 2493 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2494 APInt KnownZero, KnownOne; 2495 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2496 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2497 2498 // If any of the input bits are KnownOne, then the input couldn't be all 2499 // zeros, thus the result of the srl will always be zero. 2500 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2501 2502 // If all of the bits input the to ctlz node are known to be zero, then 2503 // the result of the ctlz is "32" and the result of the shift is one. 2504 APInt UnknownBits = ~KnownZero & Mask; 2505 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2506 2507 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2508 if ((UnknownBits & (UnknownBits-1)) == 0) { 2509 // Okay, we know that only that the single bit specified by UnknownBits 2510 // could be set on input to the CTLZ node. If this bit is set, the SRL 2511 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2512 // to an SRL,XOR pair, which is likely to simplify more. 2513 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2514 SDValue Op = N0.getOperand(0); 2515 if (ShAmt) { 2516 Op = DAG.getNode(ISD::SRL, VT, Op, 2517 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2518 AddToWorkList(Op.Val); 2519 } 2520 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2521 } 2522 } 2523 2524 // fold operands of srl based on knowledge that the low bits are not 2525 // demanded. 2526 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2527 return SDValue(N, 0); 2528 2529 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDValue(); 2530} 2531 2532SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2533 SDValue N0 = N->getOperand(0); 2534 MVT VT = N->getValueType(0); 2535 2536 // fold (ctlz c1) -> c2 2537 if (isa<ConstantSDNode>(N0)) 2538 return DAG.getNode(ISD::CTLZ, VT, N0); 2539 return SDValue(); 2540} 2541 2542SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2543 SDValue N0 = N->getOperand(0); 2544 MVT VT = N->getValueType(0); 2545 2546 // fold (cttz c1) -> c2 2547 if (isa<ConstantSDNode>(N0)) 2548 return DAG.getNode(ISD::CTTZ, VT, N0); 2549 return SDValue(); 2550} 2551 2552SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2553 SDValue N0 = N->getOperand(0); 2554 MVT VT = N->getValueType(0); 2555 2556 // fold (ctpop c1) -> c2 2557 if (isa<ConstantSDNode>(N0)) 2558 return DAG.getNode(ISD::CTPOP, VT, N0); 2559 return SDValue(); 2560} 2561 2562SDValue DAGCombiner::visitSELECT(SDNode *N) { 2563 SDValue N0 = N->getOperand(0); 2564 SDValue N1 = N->getOperand(1); 2565 SDValue N2 = N->getOperand(2); 2566 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2568 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2569 MVT VT = N->getValueType(0); 2570 MVT VT0 = N0.getValueType(); 2571 2572 // fold select C, X, X -> X 2573 if (N1 == N2) 2574 return N1; 2575 // fold select true, X, Y -> X 2576 if (N0C && !N0C->isNullValue()) 2577 return N1; 2578 // fold select false, X, Y -> Y 2579 if (N0C && N0C->isNullValue()) 2580 return N2; 2581 // fold select C, 1, X -> C | X 2582 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2583 return DAG.getNode(ISD::OR, VT, N0, N2); 2584 // fold select C, 0, 1 -> ~C 2585 if (VT.isInteger() && VT0.isInteger() && 2586 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2587 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2588 if (VT == VT0) 2589 return XORNode; 2590 AddToWorkList(XORNode.Val); 2591 if (VT.bitsGT(VT0)) 2592 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2593 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2594 } 2595 // fold select C, 0, X -> ~C & X 2596 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2597 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2598 AddToWorkList(XORNode.Val); 2599 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2600 } 2601 // fold select C, X, 1 -> ~C | X 2602 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2603 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2604 AddToWorkList(XORNode.Val); 2605 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2606 } 2607 // fold select C, X, 0 -> C & X 2608 // FIXME: this should check for C type == X type, not i1? 2609 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2610 return DAG.getNode(ISD::AND, VT, N0, N1); 2611 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2612 if (VT == MVT::i1 && N0 == N1) 2613 return DAG.getNode(ISD::OR, VT, N0, N2); 2614 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2615 if (VT == MVT::i1 && N0 == N2) 2616 return DAG.getNode(ISD::AND, VT, N0, N1); 2617 2618 // If we can fold this based on the true/false value, do so. 2619 if (SimplifySelectOps(N, N1, N2)) 2620 return SDValue(N, 0); // Don't revisit N. 2621 2622 // fold selects based on a setcc into other things, such as min/max/abs 2623 if (N0.getOpcode() == ISD::SETCC) { 2624 // FIXME: 2625 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2626 // having to say they don't support SELECT_CC on every type the DAG knows 2627 // about, since there is no way to mark an opcode illegal at all value types 2628 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2629 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2630 N1, N2, N0.getOperand(2)); 2631 else 2632 return SimplifySelect(N0, N1, N2); 2633 } 2634 return SDValue(); 2635} 2636 2637SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2638 SDValue N0 = N->getOperand(0); 2639 SDValue N1 = N->getOperand(1); 2640 SDValue N2 = N->getOperand(2); 2641 SDValue N3 = N->getOperand(3); 2642 SDValue N4 = N->getOperand(4); 2643 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2644 2645 // fold select_cc lhs, rhs, x, x, cc -> x 2646 if (N2 == N3) 2647 return N2; 2648 2649 // Determine if the condition we're dealing with is constant 2650 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2651 if (SCC.Val) AddToWorkList(SCC.Val); 2652 2653 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2654 if (!SCCC->isNullValue()) 2655 return N2; // cond always true -> true val 2656 else 2657 return N3; // cond always false -> false val 2658 } 2659 2660 // Fold to a simpler select_cc 2661 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2662 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2663 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2664 SCC.getOperand(2)); 2665 2666 // If we can fold this based on the true/false value, do so. 2667 if (SimplifySelectOps(N, N2, N3)) 2668 return SDValue(N, 0); // Don't revisit N. 2669 2670 // fold select_cc into other things, such as min/max/abs 2671 return SimplifySelectCC(N0, N1, N2, N3, CC); 2672} 2673 2674SDValue DAGCombiner::visitSETCC(SDNode *N) { 2675 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2676 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2677} 2678 2679// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2680// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2681// transformation. Returns true if extension are possible and the above 2682// mentioned transformation is profitable. 2683static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2684 unsigned ExtOpc, 2685 SmallVector<SDNode*, 4> &ExtendNodes, 2686 TargetLowering &TLI) { 2687 bool HasCopyToRegUses = false; 2688 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2689 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2690 UI != UE; ++UI) { 2691 SDNode *User = *UI; 2692 if (User == N) 2693 continue; 2694 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2695 if (User->getOpcode() == ISD::SETCC) { 2696 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2697 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2698 // Sign bits will be lost after a zext. 2699 return false; 2700 bool Add = false; 2701 for (unsigned i = 0; i != 2; ++i) { 2702 SDValue UseOp = User->getOperand(i); 2703 if (UseOp == N0) 2704 continue; 2705 if (!isa<ConstantSDNode>(UseOp)) 2706 return false; 2707 Add = true; 2708 } 2709 if (Add) 2710 ExtendNodes.push_back(User); 2711 } else { 2712 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2713 SDValue UseOp = User->getOperand(i); 2714 if (UseOp == N0) { 2715 // If truncate from extended type to original load type is free 2716 // on this target, then it's ok to extend a CopyToReg. 2717 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2718 HasCopyToRegUses = true; 2719 else 2720 return false; 2721 } 2722 } 2723 } 2724 } 2725 2726 if (HasCopyToRegUses) { 2727 bool BothLiveOut = false; 2728 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2729 UI != UE; ++UI) { 2730 SDNode *User = *UI; 2731 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2732 SDValue UseOp = User->getOperand(i); 2733 if (UseOp.Val == N && UseOp.getResNo() == 0) { 2734 BothLiveOut = true; 2735 break; 2736 } 2737 } 2738 } 2739 if (BothLiveOut) 2740 // Both unextended and extended values are live out. There had better be 2741 // good a reason for the transformation. 2742 return ExtendNodes.size(); 2743 } 2744 return true; 2745} 2746 2747SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2748 SDValue N0 = N->getOperand(0); 2749 MVT VT = N->getValueType(0); 2750 2751 // fold (sext c1) -> c1 2752 if (isa<ConstantSDNode>(N0)) 2753 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2754 2755 // fold (sext (sext x)) -> (sext x) 2756 // fold (sext (aext x)) -> (sext x) 2757 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2758 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2759 2760 if (N0.getOpcode() == ISD::TRUNCATE) { 2761 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2762 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2763 SDValue NarrowLoad = ReduceLoadWidth(N0.Val); 2764 if (NarrowLoad.Val) { 2765 if (NarrowLoad.Val != N0.Val) 2766 CombineTo(N0.Val, NarrowLoad); 2767 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2768 } 2769 2770 // See if the value being truncated is already sign extended. If so, just 2771 // eliminate the trunc/sext pair. 2772 SDValue Op = N0.getOperand(0); 2773 unsigned OpBits = Op.getValueType().getSizeInBits(); 2774 unsigned MidBits = N0.getValueType().getSizeInBits(); 2775 unsigned DestBits = VT.getSizeInBits(); 2776 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2777 2778 if (OpBits == DestBits) { 2779 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2780 // bits, it is already ready. 2781 if (NumSignBits > DestBits-MidBits) 2782 return Op; 2783 } else if (OpBits < DestBits) { 2784 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2785 // bits, just sext from i32. 2786 if (NumSignBits > OpBits-MidBits) 2787 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2788 } else { 2789 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2790 // bits, just truncate to i32. 2791 if (NumSignBits > OpBits-MidBits) 2792 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2793 } 2794 2795 // fold (sext (truncate x)) -> (sextinreg x). 2796 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2797 N0.getValueType())) { 2798 if (Op.getValueType().bitsLT(VT)) 2799 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2800 else if (Op.getValueType().bitsGT(VT)) 2801 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2802 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2803 DAG.getValueType(N0.getValueType())); 2804 } 2805 } 2806 2807 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2808 if (ISD::isNON_EXTLoad(N0.Val) && 2809 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2810 TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2811 bool DoXform = true; 2812 SmallVector<SDNode*, 4> SetCCs; 2813 if (!N0.hasOneUse()) 2814 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2815 if (DoXform) { 2816 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2817 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2818 LN0->getBasePtr(), LN0->getSrcValue(), 2819 LN0->getSrcValueOffset(), 2820 N0.getValueType(), 2821 LN0->isVolatile(), 2822 LN0->getAlignment()); 2823 CombineTo(N, ExtLoad); 2824 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2825 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2826 // Extend SetCC uses if necessary. 2827 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2828 SDNode *SetCC = SetCCs[i]; 2829 SmallVector<SDValue, 4> Ops; 2830 for (unsigned j = 0; j != 2; ++j) { 2831 SDValue SOp = SetCC->getOperand(j); 2832 if (SOp == Trunc) 2833 Ops.push_back(ExtLoad); 2834 else 2835 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2836 } 2837 Ops.push_back(SetCC->getOperand(2)); 2838 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2839 &Ops[0], Ops.size())); 2840 } 2841 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2842 } 2843 } 2844 2845 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2846 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2847 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2848 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2849 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2850 MVT EVT = LN0->getMemoryVT(); 2851 if ((!AfterLegalize && !LN0->isVolatile()) || 2852 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2853 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2854 LN0->getBasePtr(), LN0->getSrcValue(), 2855 LN0->getSrcValueOffset(), EVT, 2856 LN0->isVolatile(), 2857 LN0->getAlignment()); 2858 CombineTo(N, ExtLoad); 2859 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2860 ExtLoad.getValue(1)); 2861 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2862 } 2863 } 2864 2865 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2866 if (N0.getOpcode() == ISD::SETCC) { 2867 SDValue SCC = 2868 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2869 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2870 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2871 if (SCC.Val) return SCC; 2872 } 2873 2874 // fold (sext x) -> (zext x) if the sign bit is known zero. 2875 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2876 DAG.SignBitIsZero(N0)) 2877 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2878 2879 return SDValue(); 2880} 2881 2882SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2883 SDValue N0 = N->getOperand(0); 2884 MVT VT = N->getValueType(0); 2885 2886 // fold (zext c1) -> c1 2887 if (isa<ConstantSDNode>(N0)) 2888 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2889 // fold (zext (zext x)) -> (zext x) 2890 // fold (zext (aext x)) -> (zext x) 2891 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2892 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2893 2894 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2895 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2896 if (N0.getOpcode() == ISD::TRUNCATE) { 2897 SDValue NarrowLoad = ReduceLoadWidth(N0.Val); 2898 if (NarrowLoad.Val) { 2899 if (NarrowLoad.Val != N0.Val) 2900 CombineTo(N0.Val, NarrowLoad); 2901 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2902 } 2903 } 2904 2905 // fold (zext (truncate x)) -> (and x, mask) 2906 if (N0.getOpcode() == ISD::TRUNCATE && 2907 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2908 SDValue Op = N0.getOperand(0); 2909 if (Op.getValueType().bitsLT(VT)) { 2910 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2911 } else if (Op.getValueType().bitsGT(VT)) { 2912 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2913 } 2914 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2915 } 2916 2917 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2918 if (N0.getOpcode() == ISD::AND && 2919 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2920 N0.getOperand(1).getOpcode() == ISD::Constant) { 2921 SDValue X = N0.getOperand(0).getOperand(0); 2922 if (X.getValueType().bitsLT(VT)) { 2923 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2924 } else if (X.getValueType().bitsGT(VT)) { 2925 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2926 } 2927 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2928 Mask.zext(VT.getSizeInBits()); 2929 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2930 } 2931 2932 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2933 if (ISD::isNON_EXTLoad(N0.Val) && 2934 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2935 TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2936 bool DoXform = true; 2937 SmallVector<SDNode*, 4> SetCCs; 2938 if (!N0.hasOneUse()) 2939 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2940 if (DoXform) { 2941 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2942 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2943 LN0->getBasePtr(), LN0->getSrcValue(), 2944 LN0->getSrcValueOffset(), 2945 N0.getValueType(), 2946 LN0->isVolatile(), 2947 LN0->getAlignment()); 2948 CombineTo(N, ExtLoad); 2949 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2950 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2951 // Extend SetCC uses if necessary. 2952 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2953 SDNode *SetCC = SetCCs[i]; 2954 SmallVector<SDValue, 4> Ops; 2955 for (unsigned j = 0; j != 2; ++j) { 2956 SDValue SOp = SetCC->getOperand(j); 2957 if (SOp == Trunc) 2958 Ops.push_back(ExtLoad); 2959 else 2960 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2961 } 2962 Ops.push_back(SetCC->getOperand(2)); 2963 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2964 &Ops[0], Ops.size())); 2965 } 2966 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2967 } 2968 } 2969 2970 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2971 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2972 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2973 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2974 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2975 MVT EVT = LN0->getMemoryVT(); 2976 if ((!AfterLegalize && !LN0->isVolatile()) || 2977 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) { 2978 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2979 LN0->getBasePtr(), LN0->getSrcValue(), 2980 LN0->getSrcValueOffset(), EVT, 2981 LN0->isVolatile(), 2982 LN0->getAlignment()); 2983 CombineTo(N, ExtLoad); 2984 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2985 ExtLoad.getValue(1)); 2986 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2987 } 2988 } 2989 2990 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2991 if (N0.getOpcode() == ISD::SETCC) { 2992 SDValue SCC = 2993 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2994 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2995 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2996 if (SCC.Val) return SCC; 2997 } 2998 2999 return SDValue(); 3000} 3001 3002SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3003 SDValue N0 = N->getOperand(0); 3004 MVT VT = N->getValueType(0); 3005 3006 // fold (aext c1) -> c1 3007 if (isa<ConstantSDNode>(N0)) 3008 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3009 // fold (aext (aext x)) -> (aext x) 3010 // fold (aext (zext x)) -> (zext x) 3011 // fold (aext (sext x)) -> (sext x) 3012 if (N0.getOpcode() == ISD::ANY_EXTEND || 3013 N0.getOpcode() == ISD::ZERO_EXTEND || 3014 N0.getOpcode() == ISD::SIGN_EXTEND) 3015 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3016 3017 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3018 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3019 if (N0.getOpcode() == ISD::TRUNCATE) { 3020 SDValue NarrowLoad = ReduceLoadWidth(N0.Val); 3021 if (NarrowLoad.Val) { 3022 if (NarrowLoad.Val != N0.Val) 3023 CombineTo(N0.Val, NarrowLoad); 3024 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3025 } 3026 } 3027 3028 // fold (aext (truncate x)) 3029 if (N0.getOpcode() == ISD::TRUNCATE) { 3030 SDValue TruncOp = N0.getOperand(0); 3031 if (TruncOp.getValueType() == VT) 3032 return TruncOp; // x iff x size == zext size. 3033 if (TruncOp.getValueType().bitsGT(VT)) 3034 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3035 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3036 } 3037 3038 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3039 if (N0.getOpcode() == ISD::AND && 3040 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3041 N0.getOperand(1).getOpcode() == ISD::Constant) { 3042 SDValue X = N0.getOperand(0).getOperand(0); 3043 if (X.getValueType().bitsLT(VT)) { 3044 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3045 } else if (X.getValueType().bitsGT(VT)) { 3046 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3047 } 3048 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3049 Mask.zext(VT.getSizeInBits()); 3050 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3051 } 3052 3053 // fold (aext (load x)) -> (aext (truncate (extload x))) 3054 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3055 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3056 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3057 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3058 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3059 LN0->getBasePtr(), LN0->getSrcValue(), 3060 LN0->getSrcValueOffset(), 3061 N0.getValueType(), 3062 LN0->isVolatile(), 3063 LN0->getAlignment()); 3064 CombineTo(N, ExtLoad); 3065 // Redirect any chain users to the new load. 3066 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), SDValue(ExtLoad.Val, 1)); 3067 // If any node needs the original loaded value, recompute it. 3068 if (!LN0->use_empty()) 3069 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3070 ExtLoad.getValue(1)); 3071 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3072 } 3073 3074 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3075 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3076 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3077 if (N0.getOpcode() == ISD::LOAD && 3078 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3079 N0.hasOneUse()) { 3080 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3081 MVT EVT = LN0->getMemoryVT(); 3082 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3083 LN0->getChain(), LN0->getBasePtr(), 3084 LN0->getSrcValue(), 3085 LN0->getSrcValueOffset(), EVT, 3086 LN0->isVolatile(), 3087 LN0->getAlignment()); 3088 CombineTo(N, ExtLoad); 3089 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3090 ExtLoad.getValue(1)); 3091 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3092 } 3093 3094 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3095 if (N0.getOpcode() == ISD::SETCC) { 3096 SDValue SCC = 3097 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3098 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3099 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3100 if (SCC.Val) 3101 return SCC; 3102 } 3103 3104 return SDValue(); 3105} 3106 3107/// GetDemandedBits - See if the specified operand can be simplified with the 3108/// knowledge that only the bits specified by Mask are used. If so, return the 3109/// simpler operand, otherwise return a null SDValue. 3110SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3111 switch (V.getOpcode()) { 3112 default: break; 3113 case ISD::OR: 3114 case ISD::XOR: 3115 // If the LHS or RHS don't contribute bits to the or, drop them. 3116 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3117 return V.getOperand(1); 3118 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3119 return V.getOperand(0); 3120 break; 3121 case ISD::SRL: 3122 // Only look at single-use SRLs. 3123 if (!V.Val->hasOneUse()) 3124 break; 3125 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3126 // See if we can recursively simplify the LHS. 3127 unsigned Amt = RHSC->getValue(); 3128 APInt NewMask = Mask << Amt; 3129 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3130 if (SimplifyLHS.Val) { 3131 return DAG.getNode(ISD::SRL, V.getValueType(), 3132 SimplifyLHS, V.getOperand(1)); 3133 } 3134 } 3135 } 3136 return SDValue(); 3137} 3138 3139/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3140/// bits and then truncated to a narrower type and where N is a multiple 3141/// of number of bits of the narrower type, transform it to a narrower load 3142/// from address + N / num of bits of new type. If the result is to be 3143/// extended, also fold the extension to form a extending load. 3144SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3145 unsigned Opc = N->getOpcode(); 3146 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3147 SDValue N0 = N->getOperand(0); 3148 MVT VT = N->getValueType(0); 3149 MVT EVT = N->getValueType(0); 3150 3151 // This transformation isn't valid for vector loads. 3152 if (VT.isVector()) 3153 return SDValue(); 3154 3155 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3156 // extended to VT. 3157 if (Opc == ISD::SIGN_EXTEND_INREG) { 3158 ExtType = ISD::SEXTLOAD; 3159 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3160 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3161 return SDValue(); 3162 } 3163 3164 unsigned EVTBits = EVT.getSizeInBits(); 3165 unsigned ShAmt = 0; 3166 bool CombineSRL = false; 3167 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3168 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3169 ShAmt = N01->getValue(); 3170 // Is the shift amount a multiple of size of VT? 3171 if ((ShAmt & (EVTBits-1)) == 0) { 3172 N0 = N0.getOperand(0); 3173 if (N0.getValueType().getSizeInBits() <= EVTBits) 3174 return SDValue(); 3175 CombineSRL = true; 3176 } 3177 } 3178 } 3179 3180 // Do not generate loads of non-round integer types since these can 3181 // be expensive (and would be wrong if the type is not byte sized). 3182 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3183 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3184 // Do not change the width of a volatile load. 3185 !cast<LoadSDNode>(N0)->isVolatile()) { 3186 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3187 MVT PtrType = N0.getOperand(1).getValueType(); 3188 // For big endian targets, we need to adjust the offset to the pointer to 3189 // load the correct bytes. 3190 if (TLI.isBigEndian()) { 3191 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3192 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3193 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3194 } 3195 uint64_t PtrOff = ShAmt / 8; 3196 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3197 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3198 DAG.getConstant(PtrOff, PtrType)); 3199 AddToWorkList(NewPtr.Val); 3200 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3201 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3202 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3203 LN0->isVolatile(), NewAlign) 3204 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3205 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3206 EVT, LN0->isVolatile(), NewAlign); 3207 AddToWorkList(N); 3208 if (CombineSRL) { 3209 WorkListRemover DeadNodes(*this); 3210 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3211 &DeadNodes); 3212 CombineTo(N->getOperand(0).Val, Load); 3213 } else 3214 CombineTo(N0.Val, Load, Load.getValue(1)); 3215 if (ShAmt) { 3216 if (Opc == ISD::SIGN_EXTEND_INREG) 3217 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3218 else 3219 return DAG.getNode(Opc, VT, Load); 3220 } 3221 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3222 } 3223 3224 return SDValue(); 3225} 3226 3227 3228SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3229 SDValue N0 = N->getOperand(0); 3230 SDValue N1 = N->getOperand(1); 3231 MVT VT = N->getValueType(0); 3232 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3233 unsigned VTBits = VT.getSizeInBits(); 3234 unsigned EVTBits = EVT.getSizeInBits(); 3235 3236 // fold (sext_in_reg c1) -> c1 3237 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3238 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3239 3240 // If the input is already sign extended, just drop the extension. 3241 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3242 return N0; 3243 3244 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3245 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3246 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3247 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3248 } 3249 3250 // fold (sext_in_reg (sext x)) -> (sext x) 3251 // fold (sext_in_reg (aext x)) -> (sext x) 3252 // if x is small enough. 3253 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3254 SDValue N00 = N0.getOperand(0); 3255 if (N00.getValueType().getSizeInBits() < EVTBits) 3256 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3257 } 3258 3259 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3260 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3261 return DAG.getZeroExtendInReg(N0, EVT); 3262 3263 // fold operands of sext_in_reg based on knowledge that the top bits are not 3264 // demanded. 3265 if (SimplifyDemandedBits(SDValue(N, 0))) 3266 return SDValue(N, 0); 3267 3268 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3269 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3270 SDValue NarrowLoad = ReduceLoadWidth(N); 3271 if (NarrowLoad.Val) 3272 return NarrowLoad; 3273 3274 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3275 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3276 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3277 if (N0.getOpcode() == ISD::SRL) { 3278 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3279 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) { 3280 // We can turn this into an SRA iff the input to the SRL is already sign 3281 // extended enough. 3282 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3283 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits) 3284 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3285 } 3286 } 3287 3288 // fold (sext_inreg (extload x)) -> (sextload x) 3289 if (ISD::isEXTLoad(N0.Val) && 3290 ISD::isUNINDEXEDLoad(N0.Val) && 3291 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3292 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3293 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3294 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3295 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3296 LN0->getBasePtr(), LN0->getSrcValue(), 3297 LN0->getSrcValueOffset(), EVT, 3298 LN0->isVolatile(), 3299 LN0->getAlignment()); 3300 CombineTo(N, ExtLoad); 3301 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3302 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3303 } 3304 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3305 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3306 N0.hasOneUse() && 3307 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3308 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3309 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3310 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3311 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3312 LN0->getBasePtr(), LN0->getSrcValue(), 3313 LN0->getSrcValueOffset(), EVT, 3314 LN0->isVolatile(), 3315 LN0->getAlignment()); 3316 CombineTo(N, ExtLoad); 3317 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3318 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3319 } 3320 return SDValue(); 3321} 3322 3323SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3324 SDValue N0 = N->getOperand(0); 3325 MVT VT = N->getValueType(0); 3326 3327 // noop truncate 3328 if (N0.getValueType() == N->getValueType(0)) 3329 return N0; 3330 // fold (truncate c1) -> c1 3331 if (isa<ConstantSDNode>(N0)) 3332 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3333 // fold (truncate (truncate x)) -> (truncate x) 3334 if (N0.getOpcode() == ISD::TRUNCATE) 3335 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3336 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3337 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3338 N0.getOpcode() == ISD::ANY_EXTEND) { 3339 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3340 // if the source is smaller than the dest, we still need an extend 3341 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3342 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3343 // if the source is larger than the dest, than we just need the truncate 3344 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3345 else 3346 // if the source and dest are the same type, we can drop both the extend 3347 // and the truncate 3348 return N0.getOperand(0); 3349 } 3350 3351 // See if we can simplify the input to this truncate through knowledge that 3352 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3353 // -> trunc y 3354 SDValue Shorter = 3355 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3356 VT.getSizeInBits())); 3357 if (Shorter.Val) 3358 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3359 3360 // fold (truncate (load x)) -> (smaller load x) 3361 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3362 return ReduceLoadWidth(N); 3363} 3364 3365static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3366 SDValue Elt = N->getOperand(i); 3367 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3368 return Elt.Val; 3369 return Elt.getOperand(Elt.getResNo()).Val; 3370} 3371 3372/// CombineConsecutiveLoads - build_pair (load, load) -> load 3373/// if load locations are consecutive. 3374SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3375 assert(N->getOpcode() == ISD::BUILD_PAIR); 3376 3377 SDNode *LD1 = getBuildPairElt(N, 0); 3378 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3379 return SDValue(); 3380 MVT LD1VT = LD1->getValueType(0); 3381 SDNode *LD2 = getBuildPairElt(N, 1); 3382 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3383 if (ISD::isNON_EXTLoad(LD2) && 3384 LD2->hasOneUse() && 3385 // If both are volatile this would reduce the number of volatile loads. 3386 // If one is volatile it might be ok, but play conservative and bail out. 3387 !cast<LoadSDNode>(LD1)->isVolatile() && 3388 !cast<LoadSDNode>(LD2)->isVolatile() && 3389 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3390 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3391 unsigned Align = LD->getAlignment(); 3392 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 3393 getABITypeAlignment(VT.getTypeForMVT()); 3394 if (NewAlign <= Align && 3395 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3396 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3397 LD->getSrcValue(), LD->getSrcValueOffset(), 3398 false, Align); 3399 } 3400 return SDValue(); 3401} 3402 3403SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3404 SDValue N0 = N->getOperand(0); 3405 MVT VT = N->getValueType(0); 3406 3407 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3408 // Only do this before legalize, since afterward the target may be depending 3409 // on the bitconvert. 3410 // First check to see if this is all constant. 3411 if (!AfterLegalize && 3412 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3413 VT.isVector()) { 3414 bool isSimple = true; 3415 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3416 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3417 N0.getOperand(i).getOpcode() != ISD::Constant && 3418 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3419 isSimple = false; 3420 break; 3421 } 3422 3423 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3424 assert(!DestEltVT.isVector() && 3425 "Element type of vector ValueType must not be vector!"); 3426 if (isSimple) { 3427 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3428 } 3429 } 3430 3431 // If the input is a constant, let getNode() fold it. 3432 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3433 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3434 if (Res.Val != N) return Res; 3435 } 3436 3437 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3438 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3439 3440 // fold (conv (load x)) -> (load (conv*)x) 3441 // If the resultant load doesn't need a higher alignment than the original! 3442 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3443 // Do not change the width of a volatile load. 3444 !cast<LoadSDNode>(N0)->isVolatile() && 3445 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3446 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3447 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3448 getABITypeAlignment(VT.getTypeForMVT()); 3449 unsigned OrigAlign = LN0->getAlignment(); 3450 if (Align <= OrigAlign) { 3451 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3452 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3453 LN0->isVolatile(), OrigAlign); 3454 AddToWorkList(N); 3455 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3456 Load.getValue(1)); 3457 return Load; 3458 } 3459 } 3460 3461 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3462 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3463 // This often reduces constant pool loads. 3464 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3465 N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3466 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3467 AddToWorkList(NewConv.Val); 3468 3469 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3470 if (N0.getOpcode() == ISD::FNEG) 3471 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3472 assert(N0.getOpcode() == ISD::FABS); 3473 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3474 } 3475 3476 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3477 // Note that we don't handle copysign(x,cst) because this can always be folded 3478 // to an fneg or fabs. 3479 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3480 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3481 VT.isInteger() && !VT.isVector()) { 3482 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3483 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3484 MVT::getIntegerVT(OrigXWidth), 3485 N0.getOperand(1)); 3486 AddToWorkList(X.Val); 3487 3488 // If X has a different width than the result/lhs, sext it or truncate it. 3489 unsigned VTWidth = VT.getSizeInBits(); 3490 if (OrigXWidth < VTWidth) { 3491 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3492 AddToWorkList(X.Val); 3493 } else if (OrigXWidth > VTWidth) { 3494 // To get the sign bit in the right place, we have to shift it right 3495 // before truncating. 3496 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3497 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3498 AddToWorkList(X.Val); 3499 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3500 AddToWorkList(X.Val); 3501 } 3502 3503 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3504 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3505 AddToWorkList(X.Val); 3506 3507 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3508 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3509 AddToWorkList(Cst.Val); 3510 3511 return DAG.getNode(ISD::OR, VT, X, Cst); 3512 } 3513 3514 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3515 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3516 SDValue CombineLD = CombineConsecutiveLoads(N0.Val, VT); 3517 if (CombineLD.Val) 3518 return CombineLD; 3519 } 3520 3521 return SDValue(); 3522} 3523 3524SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3525 MVT VT = N->getValueType(0); 3526 return CombineConsecutiveLoads(N, VT); 3527} 3528 3529/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3530/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3531/// destination element value type. 3532SDValue DAGCombiner:: 3533ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3534 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3535 3536 // If this is already the right type, we're done. 3537 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3538 3539 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3540 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3541 3542 // If this is a conversion of N elements of one type to N elements of another 3543 // type, convert each element. This handles FP<->INT cases. 3544 if (SrcBitSize == DstBitSize) { 3545 SmallVector<SDValue, 8> Ops; 3546 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3547 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3548 AddToWorkList(Ops.back().Val); 3549 } 3550 MVT VT = MVT::getVectorVT(DstEltVT, 3551 BV->getValueType(0).getVectorNumElements()); 3552 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3553 } 3554 3555 // Otherwise, we're growing or shrinking the elements. To avoid having to 3556 // handle annoying details of growing/shrinking FP values, we convert them to 3557 // int first. 3558 if (SrcEltVT.isFloatingPoint()) { 3559 // Convert the input float vector to a int vector where the elements are the 3560 // same sizes. 3561 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3562 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3563 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3564 SrcEltVT = IntVT; 3565 } 3566 3567 // Now we know the input is an integer vector. If the output is a FP type, 3568 // convert to integer first, then to FP of the right size. 3569 if (DstEltVT.isFloatingPoint()) { 3570 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3571 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3572 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3573 3574 // Next, convert to FP elements of the same size. 3575 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3576 } 3577 3578 // Okay, we know the src/dst types are both integers of differing types. 3579 // Handling growing first. 3580 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3581 if (SrcBitSize < DstBitSize) { 3582 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3583 3584 SmallVector<SDValue, 8> Ops; 3585 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3586 i += NumInputsPerOutput) { 3587 bool isLE = TLI.isLittleEndian(); 3588 APInt NewBits = APInt(DstBitSize, 0); 3589 bool EltIsUndef = true; 3590 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3591 // Shift the previously computed bits over. 3592 NewBits <<= SrcBitSize; 3593 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3594 if (Op.getOpcode() == ISD::UNDEF) continue; 3595 EltIsUndef = false; 3596 3597 NewBits |= 3598 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3599 } 3600 3601 if (EltIsUndef) 3602 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3603 else 3604 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3605 } 3606 3607 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3608 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3609 } 3610 3611 // Finally, this must be the case where we are shrinking elements: each input 3612 // turns into multiple outputs. 3613 bool isS2V = ISD::isScalarToVector(BV); 3614 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3615 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3616 SmallVector<SDValue, 8> Ops; 3617 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3618 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3619 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3620 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3621 continue; 3622 } 3623 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3624 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3625 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3626 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3627 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3628 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3629 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3630 OpVal = OpVal.lshr(DstBitSize); 3631 } 3632 3633 // For big endian targets, swap the order of the pieces of each element. 3634 if (TLI.isBigEndian()) 3635 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3636 } 3637 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3638} 3639 3640 3641 3642SDValue DAGCombiner::visitFADD(SDNode *N) { 3643 SDValue N0 = N->getOperand(0); 3644 SDValue N1 = N->getOperand(1); 3645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3646 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3647 MVT VT = N->getValueType(0); 3648 3649 // fold vector ops 3650 if (VT.isVector()) { 3651 SDValue FoldedVOp = SimplifyVBinOp(N); 3652 if (FoldedVOp.Val) return FoldedVOp; 3653 } 3654 3655 // fold (fadd c1, c2) -> c1+c2 3656 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3657 return DAG.getNode(ISD::FADD, VT, N0, N1); 3658 // canonicalize constant to RHS 3659 if (N0CFP && !N1CFP) 3660 return DAG.getNode(ISD::FADD, VT, N1, N0); 3661 // fold (A + (-B)) -> A-B 3662 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3663 return DAG.getNode(ISD::FSUB, VT, N0, 3664 GetNegatedExpression(N1, DAG, AfterLegalize)); 3665 // fold ((-A) + B) -> B-A 3666 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3667 return DAG.getNode(ISD::FSUB, VT, N1, 3668 GetNegatedExpression(N0, DAG, AfterLegalize)); 3669 3670 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3671 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3672 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3673 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3674 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3675 3676 return SDValue(); 3677} 3678 3679SDValue DAGCombiner::visitFSUB(SDNode *N) { 3680 SDValue N0 = N->getOperand(0); 3681 SDValue N1 = N->getOperand(1); 3682 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3683 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3684 MVT VT = N->getValueType(0); 3685 3686 // fold vector ops 3687 if (VT.isVector()) { 3688 SDValue FoldedVOp = SimplifyVBinOp(N); 3689 if (FoldedVOp.Val) return FoldedVOp; 3690 } 3691 3692 // fold (fsub c1, c2) -> c1-c2 3693 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3694 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3695 // fold (0-B) -> -B 3696 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3697 if (isNegatibleForFree(N1, AfterLegalize)) 3698 return GetNegatedExpression(N1, DAG, AfterLegalize); 3699 return DAG.getNode(ISD::FNEG, VT, N1); 3700 } 3701 // fold (A-(-B)) -> A+B 3702 if (isNegatibleForFree(N1, AfterLegalize)) 3703 return DAG.getNode(ISD::FADD, VT, N0, 3704 GetNegatedExpression(N1, DAG, AfterLegalize)); 3705 3706 return SDValue(); 3707} 3708 3709SDValue DAGCombiner::visitFMUL(SDNode *N) { 3710 SDValue N0 = N->getOperand(0); 3711 SDValue N1 = N->getOperand(1); 3712 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3713 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3714 MVT VT = N->getValueType(0); 3715 3716 // fold vector ops 3717 if (VT.isVector()) { 3718 SDValue FoldedVOp = SimplifyVBinOp(N); 3719 if (FoldedVOp.Val) return FoldedVOp; 3720 } 3721 3722 // fold (fmul c1, c2) -> c1*c2 3723 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3724 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3725 // canonicalize constant to RHS 3726 if (N0CFP && !N1CFP) 3727 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3728 // fold (fmul X, 2.0) -> (fadd X, X) 3729 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3730 return DAG.getNode(ISD::FADD, VT, N0, N0); 3731 // fold (fmul X, -1.0) -> (fneg X) 3732 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3733 return DAG.getNode(ISD::FNEG, VT, N0); 3734 3735 // -X * -Y -> X*Y 3736 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3737 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3738 // Both can be negated for free, check to see if at least one is cheaper 3739 // negated. 3740 if (LHSNeg == 2 || RHSNeg == 2) 3741 return DAG.getNode(ISD::FMUL, VT, 3742 GetNegatedExpression(N0, DAG, AfterLegalize), 3743 GetNegatedExpression(N1, DAG, AfterLegalize)); 3744 } 3745 } 3746 3747 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3748 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3749 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3750 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3751 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3752 3753 return SDValue(); 3754} 3755 3756SDValue DAGCombiner::visitFDIV(SDNode *N) { 3757 SDValue N0 = N->getOperand(0); 3758 SDValue N1 = N->getOperand(1); 3759 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3760 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3761 MVT VT = N->getValueType(0); 3762 3763 // fold vector ops 3764 if (VT.isVector()) { 3765 SDValue FoldedVOp = SimplifyVBinOp(N); 3766 if (FoldedVOp.Val) return FoldedVOp; 3767 } 3768 3769 // fold (fdiv c1, c2) -> c1/c2 3770 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3771 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3772 3773 3774 // -X / -Y -> X*Y 3775 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3776 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3777 // Both can be negated for free, check to see if at least one is cheaper 3778 // negated. 3779 if (LHSNeg == 2 || RHSNeg == 2) 3780 return DAG.getNode(ISD::FDIV, VT, 3781 GetNegatedExpression(N0, DAG, AfterLegalize), 3782 GetNegatedExpression(N1, DAG, AfterLegalize)); 3783 } 3784 } 3785 3786 return SDValue(); 3787} 3788 3789SDValue DAGCombiner::visitFREM(SDNode *N) { 3790 SDValue N0 = N->getOperand(0); 3791 SDValue N1 = N->getOperand(1); 3792 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3793 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3794 MVT VT = N->getValueType(0); 3795 3796 // fold (frem c1, c2) -> fmod(c1,c2) 3797 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3798 return DAG.getNode(ISD::FREM, VT, N0, N1); 3799 3800 return SDValue(); 3801} 3802 3803SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3804 SDValue N0 = N->getOperand(0); 3805 SDValue N1 = N->getOperand(1); 3806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3807 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3808 MVT VT = N->getValueType(0); 3809 3810 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3811 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3812 3813 if (N1CFP) { 3814 const APFloat& V = N1CFP->getValueAPF(); 3815 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3816 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3817 if (!V.isNegative()) 3818 return DAG.getNode(ISD::FABS, VT, N0); 3819 else 3820 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3821 } 3822 3823 // copysign(fabs(x), y) -> copysign(x, y) 3824 // copysign(fneg(x), y) -> copysign(x, y) 3825 // copysign(copysign(x,z), y) -> copysign(x, y) 3826 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3827 N0.getOpcode() == ISD::FCOPYSIGN) 3828 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3829 3830 // copysign(x, abs(y)) -> abs(x) 3831 if (N1.getOpcode() == ISD::FABS) 3832 return DAG.getNode(ISD::FABS, VT, N0); 3833 3834 // copysign(x, copysign(y,z)) -> copysign(x, z) 3835 if (N1.getOpcode() == ISD::FCOPYSIGN) 3836 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3837 3838 // copysign(x, fp_extend(y)) -> copysign(x, y) 3839 // copysign(x, fp_round(y)) -> copysign(x, y) 3840 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3841 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3842 3843 return SDValue(); 3844} 3845 3846 3847 3848SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3849 SDValue N0 = N->getOperand(0); 3850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3851 MVT VT = N->getValueType(0); 3852 MVT OpVT = N0.getValueType(); 3853 3854 // fold (sint_to_fp c1) -> c1fp 3855 if (N0C && OpVT != MVT::ppcf128) 3856 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3857 3858 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3859 // but UINT_TO_FP is legal on this target, try to convert. 3860 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3861 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3862 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3863 if (DAG.SignBitIsZero(N0)) 3864 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3865 } 3866 3867 3868 return SDValue(); 3869} 3870 3871SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3872 SDValue N0 = N->getOperand(0); 3873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3874 MVT VT = N->getValueType(0); 3875 MVT OpVT = N0.getValueType(); 3876 3877 // fold (uint_to_fp c1) -> c1fp 3878 if (N0C && OpVT != MVT::ppcf128) 3879 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3880 3881 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3882 // but SINT_TO_FP is legal on this target, try to convert. 3883 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3884 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3885 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3886 if (DAG.SignBitIsZero(N0)) 3887 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3888 } 3889 3890 return SDValue(); 3891} 3892 3893SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3894 SDValue N0 = N->getOperand(0); 3895 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3896 MVT VT = N->getValueType(0); 3897 3898 // fold (fp_to_sint c1fp) -> c1 3899 if (N0CFP) 3900 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3901 return SDValue(); 3902} 3903 3904SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3905 SDValue N0 = N->getOperand(0); 3906 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3907 MVT VT = N->getValueType(0); 3908 3909 // fold (fp_to_uint c1fp) -> c1 3910 if (N0CFP && VT != MVT::ppcf128) 3911 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3912 return SDValue(); 3913} 3914 3915SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 3916 SDValue N0 = N->getOperand(0); 3917 SDValue N1 = N->getOperand(1); 3918 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3919 MVT VT = N->getValueType(0); 3920 3921 // fold (fp_round c1fp) -> c1fp 3922 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3923 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3924 3925 // fold (fp_round (fp_extend x)) -> x 3926 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3927 return N0.getOperand(0); 3928 3929 // fold (fp_round (fp_round x)) -> (fp_round x) 3930 if (N0.getOpcode() == ISD::FP_ROUND) { 3931 // This is a value preserving truncation if both round's are. 3932 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3933 N0.Val->getConstantOperandVal(1) == 1; 3934 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3935 DAG.getIntPtrConstant(IsTrunc)); 3936 } 3937 3938 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3939 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3940 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3941 AddToWorkList(Tmp.Val); 3942 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3943 } 3944 3945 return SDValue(); 3946} 3947 3948SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3949 SDValue N0 = N->getOperand(0); 3950 MVT VT = N->getValueType(0); 3951 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3952 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3953 3954 // fold (fp_round_inreg c1fp) -> c1fp 3955 if (N0CFP) { 3956 SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3957 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3958 } 3959 return SDValue(); 3960} 3961 3962SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 3963 SDValue N0 = N->getOperand(0); 3964 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3965 MVT VT = N->getValueType(0); 3966 3967 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3968 if (N->hasOneUse() && 3969 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 3970 return SDValue(); 3971 3972 // fold (fp_extend c1fp) -> c1fp 3973 if (N0CFP && VT != MVT::ppcf128) 3974 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3975 3976 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3977 // value of X. 3978 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3979 SDValue In = N0.getOperand(0); 3980 if (In.getValueType() == VT) return In; 3981 if (VT.bitsLT(In.getValueType())) 3982 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3983 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3984 } 3985 3986 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3987 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3988 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3989 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3990 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3991 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3992 LN0->getBasePtr(), LN0->getSrcValue(), 3993 LN0->getSrcValueOffset(), 3994 N0.getValueType(), 3995 LN0->isVolatile(), 3996 LN0->getAlignment()); 3997 CombineTo(N, ExtLoad); 3998 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3999 DAG.getIntPtrConstant(1)), 4000 ExtLoad.getValue(1)); 4001 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4002 } 4003 4004 return SDValue(); 4005} 4006 4007SDValue DAGCombiner::visitFNEG(SDNode *N) { 4008 SDValue N0 = N->getOperand(0); 4009 4010 if (isNegatibleForFree(N0, AfterLegalize)) 4011 return GetNegatedExpression(N0, DAG, AfterLegalize); 4012 4013 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4014 // constant pool values. 4015 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 4016 N0.getOperand(0).getValueType().isInteger() && 4017 !N0.getOperand(0).getValueType().isVector()) { 4018 SDValue Int = N0.getOperand(0); 4019 MVT IntVT = Int.getValueType(); 4020 if (IntVT.isInteger() && !IntVT.isVector()) { 4021 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4022 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4023 AddToWorkList(Int.Val); 4024 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4025 } 4026 } 4027 4028 return SDValue(); 4029} 4030 4031SDValue DAGCombiner::visitFABS(SDNode *N) { 4032 SDValue N0 = N->getOperand(0); 4033 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4034 MVT VT = N->getValueType(0); 4035 4036 // fold (fabs c1) -> fabs(c1) 4037 if (N0CFP && VT != MVT::ppcf128) 4038 return DAG.getNode(ISD::FABS, VT, N0); 4039 // fold (fabs (fabs x)) -> (fabs x) 4040 if (N0.getOpcode() == ISD::FABS) 4041 return N->getOperand(0); 4042 // fold (fabs (fneg x)) -> (fabs x) 4043 // fold (fabs (fcopysign x, y)) -> (fabs x) 4044 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4045 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4046 4047 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4048 // constant pool values. 4049 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 4050 N0.getOperand(0).getValueType().isInteger() && 4051 !N0.getOperand(0).getValueType().isVector()) { 4052 SDValue Int = N0.getOperand(0); 4053 MVT IntVT = Int.getValueType(); 4054 if (IntVT.isInteger() && !IntVT.isVector()) { 4055 Int = DAG.getNode(ISD::AND, IntVT, Int, 4056 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4057 AddToWorkList(Int.Val); 4058 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4059 } 4060 } 4061 4062 return SDValue(); 4063} 4064 4065SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4066 SDValue Chain = N->getOperand(0); 4067 SDValue N1 = N->getOperand(1); 4068 SDValue N2 = N->getOperand(2); 4069 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4070 4071 // never taken branch, fold to chain 4072 if (N1C && N1C->isNullValue()) 4073 return Chain; 4074 // unconditional branch 4075 if (N1C && N1C->getAPIntValue() == 1) 4076 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4077 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4078 // on the target. 4079 if (N1.getOpcode() == ISD::SETCC && 4080 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4081 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4082 N1.getOperand(0), N1.getOperand(1), N2); 4083 } 4084 return SDValue(); 4085} 4086 4087// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4088// 4089SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4090 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4091 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4092 4093 // Use SimplifySetCC to simplify SETCC's. 4094 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4095 if (Simp.Val) AddToWorkList(Simp.Val); 4096 4097 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 4098 4099 // fold br_cc true, dest -> br dest (unconditional branch) 4100 if (SCCC && !SCCC->isNullValue()) 4101 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4102 N->getOperand(4)); 4103 // fold br_cc false, dest -> unconditional fall through 4104 if (SCCC && SCCC->isNullValue()) 4105 return N->getOperand(0); 4106 4107 // fold to a simpler setcc 4108 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 4109 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4110 Simp.getOperand(2), Simp.getOperand(0), 4111 Simp.getOperand(1), N->getOperand(4)); 4112 return SDValue(); 4113} 4114 4115 4116/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4117/// pre-indexed load / store when the base pointer is an add or subtract 4118/// and it has other uses besides the load / store. After the 4119/// transformation, the new indexed load / store has effectively folded 4120/// the add / subtract in and all of its other uses are redirected to the 4121/// new load / store. 4122bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4123 if (!AfterLegalize) 4124 return false; 4125 4126 bool isLoad = true; 4127 SDValue Ptr; 4128 MVT VT; 4129 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4130 if (LD->isIndexed()) 4131 return false; 4132 VT = LD->getMemoryVT(); 4133 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4134 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4135 return false; 4136 Ptr = LD->getBasePtr(); 4137 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4138 if (ST->isIndexed()) 4139 return false; 4140 VT = ST->getMemoryVT(); 4141 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4142 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4143 return false; 4144 Ptr = ST->getBasePtr(); 4145 isLoad = false; 4146 } else 4147 return false; 4148 4149 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4150 // out. There is no reason to make this a preinc/predec. 4151 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4152 Ptr.Val->hasOneUse()) 4153 return false; 4154 4155 // Ask the target to do addressing mode selection. 4156 SDValue BasePtr; 4157 SDValue Offset; 4158 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4159 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4160 return false; 4161 // Don't create a indexed load / store with zero offset. 4162 if (isa<ConstantSDNode>(Offset) && 4163 cast<ConstantSDNode>(Offset)->isNullValue()) 4164 return false; 4165 4166 // Try turning it into a pre-indexed load / store except when: 4167 // 1) The new base ptr is a frame index. 4168 // 2) If N is a store and the new base ptr is either the same as or is a 4169 // predecessor of the value being stored. 4170 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4171 // that would create a cycle. 4172 // 4) All uses are load / store ops that use it as old base ptr. 4173 4174 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4175 // (plus the implicit offset) to a register to preinc anyway. 4176 if (isa<FrameIndexSDNode>(BasePtr)) 4177 return false; 4178 4179 // Check #2. 4180 if (!isLoad) { 4181 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4182 if (Val == BasePtr || BasePtr.Val->isPredecessorOf(Val.Val)) 4183 return false; 4184 } 4185 4186 // Now check for #3 and #4. 4187 bool RealUse = false; 4188 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4189 E = Ptr.Val->use_end(); I != E; ++I) { 4190 SDNode *Use = *I; 4191 if (Use == N) 4192 continue; 4193 if (Use->isPredecessorOf(N)) 4194 return false; 4195 4196 if (!((Use->getOpcode() == ISD::LOAD && 4197 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4198 (Use->getOpcode() == ISD::STORE && 4199 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4200 RealUse = true; 4201 } 4202 if (!RealUse) 4203 return false; 4204 4205 SDValue Result; 4206 if (isLoad) 4207 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4208 else 4209 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4210 ++PreIndexedNodes; 4211 ++NodesCombined; 4212 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4213 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4214 DOUT << '\n'; 4215 WorkListRemover DeadNodes(*this); 4216 if (isLoad) { 4217 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4218 &DeadNodes); 4219 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4220 &DeadNodes); 4221 } else { 4222 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4223 &DeadNodes); 4224 } 4225 4226 // Finally, since the node is now dead, remove it from the graph. 4227 DAG.DeleteNode(N); 4228 4229 // Replace the uses of Ptr with uses of the updated base value. 4230 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4231 &DeadNodes); 4232 removeFromWorkList(Ptr.Val); 4233 DAG.DeleteNode(Ptr.Val); 4234 4235 return true; 4236} 4237 4238/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4239/// add / sub of the base pointer node into a post-indexed load / store. 4240/// The transformation folded the add / subtract into the new indexed 4241/// load / store effectively and all of its uses are redirected to the 4242/// new load / store. 4243bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4244 if (!AfterLegalize) 4245 return false; 4246 4247 bool isLoad = true; 4248 SDValue Ptr; 4249 MVT VT; 4250 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4251 if (LD->isIndexed()) 4252 return false; 4253 VT = LD->getMemoryVT(); 4254 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4255 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4256 return false; 4257 Ptr = LD->getBasePtr(); 4258 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4259 if (ST->isIndexed()) 4260 return false; 4261 VT = ST->getMemoryVT(); 4262 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4263 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4264 return false; 4265 Ptr = ST->getBasePtr(); 4266 isLoad = false; 4267 } else 4268 return false; 4269 4270 if (Ptr.Val->hasOneUse()) 4271 return false; 4272 4273 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4274 E = Ptr.Val->use_end(); I != E; ++I) { 4275 SDNode *Op = *I; 4276 if (Op == N || 4277 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4278 continue; 4279 4280 SDValue BasePtr; 4281 SDValue Offset; 4282 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4283 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4284 if (Ptr == Offset) 4285 std::swap(BasePtr, Offset); 4286 if (Ptr != BasePtr) 4287 continue; 4288 // Don't create a indexed load / store with zero offset. 4289 if (isa<ConstantSDNode>(Offset) && 4290 cast<ConstantSDNode>(Offset)->isNullValue()) 4291 continue; 4292 4293 // Try turning it into a post-indexed load / store except when 4294 // 1) All uses are load / store ops that use it as base ptr. 4295 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4296 // nor a successor of N. Otherwise, if Op is folded that would 4297 // create a cycle. 4298 4299 // Check for #1. 4300 bool TryNext = false; 4301 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4302 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4303 SDNode *Use = *II; 4304 if (Use == Ptr.Val) 4305 continue; 4306 4307 // If all the uses are load / store addresses, then don't do the 4308 // transformation. 4309 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4310 bool RealUse = false; 4311 for (SDNode::use_iterator III = Use->use_begin(), 4312 EEE = Use->use_end(); III != EEE; ++III) { 4313 SDNode *UseUse = *III; 4314 if (!((UseUse->getOpcode() == ISD::LOAD && 4315 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4316 (UseUse->getOpcode() == ISD::STORE && 4317 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))) 4318 RealUse = true; 4319 } 4320 4321 if (!RealUse) { 4322 TryNext = true; 4323 break; 4324 } 4325 } 4326 } 4327 if (TryNext) 4328 continue; 4329 4330 // Check for #2 4331 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4332 SDValue Result = isLoad 4333 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4334 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4335 ++PostIndexedNodes; 4336 ++NodesCombined; 4337 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4338 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4339 DOUT << '\n'; 4340 WorkListRemover DeadNodes(*this); 4341 if (isLoad) { 4342 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4343 &DeadNodes); 4344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4345 &DeadNodes); 4346 } else { 4347 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4348 &DeadNodes); 4349 } 4350 4351 // Finally, since the node is now dead, remove it from the graph. 4352 DAG.DeleteNode(N); 4353 4354 // Replace the uses of Use with uses of the updated base value. 4355 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4356 Result.getValue(isLoad ? 1 : 0), 4357 &DeadNodes); 4358 removeFromWorkList(Op); 4359 DAG.DeleteNode(Op); 4360 return true; 4361 } 4362 } 4363 } 4364 return false; 4365} 4366 4367/// InferAlignment - If we can infer some alignment information from this 4368/// pointer, return it. 4369static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4370 // If this is a direct reference to a stack slot, use information about the 4371 // stack slot's alignment. 4372 int FrameIdx = 1 << 31; 4373 int64_t FrameOffset = 0; 4374 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4375 FrameIdx = FI->getIndex(); 4376 } else if (Ptr.getOpcode() == ISD::ADD && 4377 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4378 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4379 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4380 FrameOffset = Ptr.getConstantOperandVal(1); 4381 } 4382 4383 if (FrameIdx != (1 << 31)) { 4384 // FIXME: Handle FI+CST. 4385 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4386 if (MFI.isFixedObjectIndex(FrameIdx)) { 4387 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4388 4389 // The alignment of the frame index can be determined from its offset from 4390 // the incoming frame position. If the frame object is at offset 32 and 4391 // the stack is guaranteed to be 16-byte aligned, then we know that the 4392 // object is 16-byte aligned. 4393 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4394 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4395 4396 // Finally, the frame object itself may have a known alignment. Factor 4397 // the alignment + offset into a new alignment. For example, if we know 4398 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4399 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4400 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4401 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4402 FrameOffset); 4403 return std::max(Align, FIInfoAlign); 4404 } 4405 } 4406 4407 return 0; 4408} 4409 4410SDValue DAGCombiner::visitLOAD(SDNode *N) { 4411 LoadSDNode *LD = cast<LoadSDNode>(N); 4412 SDValue Chain = LD->getChain(); 4413 SDValue Ptr = LD->getBasePtr(); 4414 4415 // Try to infer better alignment information than the load already has. 4416 if (!Fast && LD->isUnindexed()) { 4417 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4418 if (Align > LD->getAlignment()) 4419 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4420 Chain, Ptr, LD->getSrcValue(), 4421 LD->getSrcValueOffset(), LD->getMemoryVT(), 4422 LD->isVolatile(), Align); 4423 } 4424 } 4425 4426 4427 // If load is not volatile and there are no uses of the loaded value (and 4428 // the updated indexed value in case of indexed loads), change uses of the 4429 // chain value into uses of the chain input (i.e. delete the dead load). 4430 if (!LD->isVolatile()) { 4431 if (N->getValueType(1) == MVT::Other) { 4432 // Unindexed loads. 4433 if (N->hasNUsesOfValue(0, 0)) { 4434 // It's not safe to use the two value CombineTo variant here. e.g. 4435 // v1, chain2 = load chain1, loc 4436 // v2, chain3 = load chain2, loc 4437 // v3 = add v2, c 4438 // Now we replace use of chain2 with chain1. This makes the second load 4439 // isomorphic to the one we are deleting, and thus makes this load live. 4440 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4441 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4442 DOUT << "\n"; 4443 WorkListRemover DeadNodes(*this); 4444 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4445 if (N->use_empty()) { 4446 removeFromWorkList(N); 4447 DAG.DeleteNode(N); 4448 } 4449 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4450 } 4451 } else { 4452 // Indexed loads. 4453 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4454 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4455 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4456 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4457 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4458 DOUT << " and 2 other values\n"; 4459 WorkListRemover DeadNodes(*this); 4460 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4461 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4462 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4463 &DeadNodes); 4464 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4465 removeFromWorkList(N); 4466 DAG.DeleteNode(N); 4467 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4468 } 4469 } 4470 } 4471 4472 // If this load is directly stored, replace the load value with the stored 4473 // value. 4474 // TODO: Handle store large -> read small portion. 4475 // TODO: Handle TRUNCSTORE/LOADEXT 4476 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4477 !LD->isVolatile()) { 4478 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4479 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4480 if (PrevST->getBasePtr() == Ptr && 4481 PrevST->getValue().getValueType() == N->getValueType(0)) 4482 return CombineTo(N, Chain.getOperand(1), Chain); 4483 } 4484 } 4485 4486 if (CombinerAA) { 4487 // Walk up chain skipping non-aliasing memory nodes. 4488 SDValue BetterChain = FindBetterChain(N, Chain); 4489 4490 // If there is a better chain. 4491 if (Chain != BetterChain) { 4492 SDValue ReplLoad; 4493 4494 // Replace the chain to void dependency. 4495 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4496 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4497 LD->getSrcValue(), LD->getSrcValueOffset(), 4498 LD->isVolatile(), LD->getAlignment()); 4499 } else { 4500 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4501 LD->getValueType(0), 4502 BetterChain, Ptr, LD->getSrcValue(), 4503 LD->getSrcValueOffset(), 4504 LD->getMemoryVT(), 4505 LD->isVolatile(), 4506 LD->getAlignment()); 4507 } 4508 4509 // Create token factor to keep old chain connected. 4510 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4511 Chain, ReplLoad.getValue(1)); 4512 4513 // Replace uses with load result and token factor. Don't add users 4514 // to work list. 4515 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4516 } 4517 } 4518 4519 // Try transforming N to an indexed load. 4520 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4521 return SDValue(N, 0); 4522 4523 return SDValue(); 4524} 4525 4526 4527SDValue DAGCombiner::visitSTORE(SDNode *N) { 4528 StoreSDNode *ST = cast<StoreSDNode>(N); 4529 SDValue Chain = ST->getChain(); 4530 SDValue Value = ST->getValue(); 4531 SDValue Ptr = ST->getBasePtr(); 4532 4533 // Try to infer better alignment information than the store already has. 4534 if (!Fast && ST->isUnindexed()) { 4535 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4536 if (Align > ST->getAlignment()) 4537 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4538 ST->getSrcValueOffset(), ST->getMemoryVT(), 4539 ST->isVolatile(), Align); 4540 } 4541 } 4542 4543 // If this is a store of a bit convert, store the input value if the 4544 // resultant store does not need a higher alignment than the original. 4545 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4546 ST->isUnindexed()) { 4547 unsigned Align = ST->getAlignment(); 4548 MVT SVT = Value.getOperand(0).getValueType(); 4549 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4550 getABITypeAlignment(SVT.getTypeForMVT()); 4551 if (Align <= OrigAlign && 4552 ((!AfterLegalize && !ST->isVolatile()) || 4553 TLI.isOperationLegal(ISD::STORE, SVT))) 4554 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4555 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4556 } 4557 4558 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4559 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4560 // NOTE: If the original store is volatile, this transform must not increase 4561 // the number of stores. For example, on x86-32 an f64 can be stored in one 4562 // processor operation but an i64 (which is not legal) requires two. So the 4563 // transform should not be done in this case. 4564 if (Value.getOpcode() != ISD::TargetConstantFP) { 4565 SDValue Tmp; 4566 switch (CFP->getValueType(0).getSimpleVT()) { 4567 default: assert(0 && "Unknown FP type"); 4568 case MVT::f80: // We don't do this for these yet. 4569 case MVT::f128: 4570 case MVT::ppcf128: 4571 break; 4572 case MVT::f32: 4573 if ((!AfterLegalize && !ST->isVolatile()) || 4574 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4575 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4576 convertToAPInt().getZExtValue(), MVT::i32); 4577 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4578 ST->getSrcValueOffset(), ST->isVolatile(), 4579 ST->getAlignment()); 4580 } 4581 break; 4582 case MVT::f64: 4583 if ((!AfterLegalize && !ST->isVolatile()) || 4584 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4585 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4586 getZExtValue(), MVT::i64); 4587 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4588 ST->getSrcValueOffset(), ST->isVolatile(), 4589 ST->getAlignment()); 4590 } else if (!ST->isVolatile() && 4591 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4592 // Many FP stores are not made apparent until after legalize, e.g. for 4593 // argument passing. Since this is so common, custom legalize the 4594 // 64-bit integer store into two 32-bit stores. 4595 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4596 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4597 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4598 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4599 4600 int SVOffset = ST->getSrcValueOffset(); 4601 unsigned Alignment = ST->getAlignment(); 4602 bool isVolatile = ST->isVolatile(); 4603 4604 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4605 ST->getSrcValueOffset(), 4606 isVolatile, ST->getAlignment()); 4607 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4608 DAG.getConstant(4, Ptr.getValueType())); 4609 SVOffset += 4; 4610 Alignment = MinAlign(Alignment, 4U); 4611 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4612 SVOffset, isVolatile, Alignment); 4613 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4614 } 4615 break; 4616 } 4617 } 4618 } 4619 4620 if (CombinerAA) { 4621 // Walk up chain skipping non-aliasing memory nodes. 4622 SDValue BetterChain = FindBetterChain(N, Chain); 4623 4624 // If there is a better chain. 4625 if (Chain != BetterChain) { 4626 // Replace the chain to avoid dependency. 4627 SDValue ReplStore; 4628 if (ST->isTruncatingStore()) { 4629 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4630 ST->getSrcValue(),ST->getSrcValueOffset(), 4631 ST->getMemoryVT(), 4632 ST->isVolatile(), ST->getAlignment()); 4633 } else { 4634 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4635 ST->getSrcValue(), ST->getSrcValueOffset(), 4636 ST->isVolatile(), ST->getAlignment()); 4637 } 4638 4639 // Create token to keep both nodes around. 4640 SDValue Token = 4641 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4642 4643 // Don't add users to work list. 4644 return CombineTo(N, Token, false); 4645 } 4646 } 4647 4648 // Try transforming N to an indexed store. 4649 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4650 return SDValue(N, 0); 4651 4652 // FIXME: is there such a thing as a truncating indexed store? 4653 if (ST->isTruncatingStore() && ST->isUnindexed() && 4654 Value.getValueType().isInteger()) { 4655 // See if we can simplify the input to this truncstore with knowledge that 4656 // only the low bits are being used. For example: 4657 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4658 SDValue Shorter = 4659 GetDemandedBits(Value, 4660 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4661 ST->getMemoryVT().getSizeInBits())); 4662 AddToWorkList(Value.Val); 4663 if (Shorter.Val) 4664 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4665 ST->getSrcValueOffset(), ST->getMemoryVT(), 4666 ST->isVolatile(), ST->getAlignment()); 4667 4668 // Otherwise, see if we can simplify the operation with 4669 // SimplifyDemandedBits, which only works if the value has a single use. 4670 if (SimplifyDemandedBits(Value, 4671 APInt::getLowBitsSet( 4672 Value.getValueSizeInBits(), 4673 ST->getMemoryVT().getSizeInBits()))) 4674 return SDValue(N, 0); 4675 } 4676 4677 // If this is a load followed by a store to the same location, then the store 4678 // is dead/noop. 4679 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4680 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4681 ST->isUnindexed() && !ST->isVolatile() && 4682 // There can't be any side effects between the load and store, such as 4683 // a call or store. 4684 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4685 // The store is dead, remove it. 4686 return Chain; 4687 } 4688 } 4689 4690 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4691 // truncating store. We can do this even if this is already a truncstore. 4692 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4693 && Value.Val->hasOneUse() && ST->isUnindexed() && 4694 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4695 ST->getMemoryVT())) { 4696 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4697 ST->getSrcValueOffset(), ST->getMemoryVT(), 4698 ST->isVolatile(), ST->getAlignment()); 4699 } 4700 4701 return SDValue(); 4702} 4703 4704SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4705 SDValue InVec = N->getOperand(0); 4706 SDValue InVal = N->getOperand(1); 4707 SDValue EltNo = N->getOperand(2); 4708 4709 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4710 // vector with the inserted element. 4711 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4712 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4713 SmallVector<SDValue, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4714 if (Elt < Ops.size()) 4715 Ops[Elt] = InVal; 4716 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4717 &Ops[0], Ops.size()); 4718 } 4719 4720 return SDValue(); 4721} 4722 4723SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4724 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4725 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4726 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4727 4728 // Perform only after legalization to ensure build_vector / vector_shuffle 4729 // optimizations have already been done. 4730 if (!AfterLegalize) return SDValue(); 4731 4732 SDValue InVec = N->getOperand(0); 4733 SDValue EltNo = N->getOperand(1); 4734 4735 if (isa<ConstantSDNode>(EltNo)) { 4736 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4737 bool NewLoad = false; 4738 MVT VT = InVec.getValueType(); 4739 MVT EVT = VT.getVectorElementType(); 4740 MVT LVT = EVT; 4741 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4742 MVT BCVT = InVec.getOperand(0).getValueType(); 4743 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4744 return SDValue(); 4745 InVec = InVec.getOperand(0); 4746 EVT = BCVT.getVectorElementType(); 4747 NewLoad = true; 4748 } 4749 4750 LoadSDNode *LN0 = NULL; 4751 if (ISD::isNormalLoad(InVec.Val)) 4752 LN0 = cast<LoadSDNode>(InVec); 4753 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4754 InVec.getOperand(0).getValueType() == EVT && 4755 ISD::isNormalLoad(InVec.getOperand(0).Val)) { 4756 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4757 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4758 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4759 // => 4760 // (load $addr+1*size) 4761 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4762 getOperand(Elt))->getValue(); 4763 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4764 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4765 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4766 InVec = InVec.getOperand(0); 4767 if (ISD::isNormalLoad(InVec.Val)) { 4768 LN0 = cast<LoadSDNode>(InVec); 4769 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4770 } 4771 } 4772 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4773 return SDValue(); 4774 4775 unsigned Align = LN0->getAlignment(); 4776 if (NewLoad) { 4777 // Check the resultant load doesn't need a higher alignment than the 4778 // original load. 4779 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4780 getABITypeAlignment(LVT.getTypeForMVT()); 4781 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4782 return SDValue(); 4783 Align = NewAlign; 4784 } 4785 4786 SDValue NewPtr = LN0->getBasePtr(); 4787 if (Elt) { 4788 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4789 MVT PtrType = NewPtr.getValueType(); 4790 if (TLI.isBigEndian()) 4791 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4792 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4793 DAG.getConstant(PtrOff, PtrType)); 4794 } 4795 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4796 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4797 LN0->isVolatile(), Align); 4798 } 4799 return SDValue(); 4800} 4801 4802 4803SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4804 unsigned NumInScalars = N->getNumOperands(); 4805 MVT VT = N->getValueType(0); 4806 unsigned NumElts = VT.getVectorNumElements(); 4807 MVT EltType = VT.getVectorElementType(); 4808 4809 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4810 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4811 // at most two distinct vectors, turn this into a shuffle node. 4812 SDValue VecIn1, VecIn2; 4813 for (unsigned i = 0; i != NumInScalars; ++i) { 4814 // Ignore undef inputs. 4815 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4816 4817 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4818 // constant index, bail out. 4819 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4820 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4821 VecIn1 = VecIn2 = SDValue(0, 0); 4822 break; 4823 } 4824 4825 // If the input vector type disagrees with the result of the build_vector, 4826 // we can't make a shuffle. 4827 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4828 if (ExtractedFromVec.getValueType() != VT) { 4829 VecIn1 = VecIn2 = SDValue(0, 0); 4830 break; 4831 } 4832 4833 // Otherwise, remember this. We allow up to two distinct input vectors. 4834 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4835 continue; 4836 4837 if (VecIn1.Val == 0) { 4838 VecIn1 = ExtractedFromVec; 4839 } else if (VecIn2.Val == 0) { 4840 VecIn2 = ExtractedFromVec; 4841 } else { 4842 // Too many inputs. 4843 VecIn1 = VecIn2 = SDValue(0, 0); 4844 break; 4845 } 4846 } 4847 4848 // If everything is good, we can make a shuffle operation. 4849 if (VecIn1.Val) { 4850 SmallVector<SDValue, 8> BuildVecIndices; 4851 for (unsigned i = 0; i != NumInScalars; ++i) { 4852 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4853 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4854 continue; 4855 } 4856 4857 SDValue Extract = N->getOperand(i); 4858 4859 // If extracting from the first vector, just use the index directly. 4860 if (Extract.getOperand(0) == VecIn1) { 4861 BuildVecIndices.push_back(Extract.getOperand(1)); 4862 continue; 4863 } 4864 4865 // Otherwise, use InIdx + VecSize 4866 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4867 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4868 } 4869 4870 // Add count and size info. 4871 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4872 4873 // Return the new VECTOR_SHUFFLE node. 4874 SDValue Ops[5]; 4875 Ops[0] = VecIn1; 4876 if (VecIn2.Val) { 4877 Ops[1] = VecIn2; 4878 } else { 4879 // Use an undef build_vector as input for the second operand. 4880 std::vector<SDValue> UnOps(NumInScalars, 4881 DAG.getNode(ISD::UNDEF, 4882 EltType)); 4883 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4884 &UnOps[0], UnOps.size()); 4885 AddToWorkList(Ops[1].Val); 4886 } 4887 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4888 &BuildVecIndices[0], BuildVecIndices.size()); 4889 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4890 } 4891 4892 return SDValue(); 4893} 4894 4895SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4896 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4897 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4898 // inputs come from at most two distinct vectors, turn this into a shuffle 4899 // node. 4900 4901 // If we only have one input vector, we don't need to do any concatenation. 4902 if (N->getNumOperands() == 1) { 4903 return N->getOperand(0); 4904 } 4905 4906 return SDValue(); 4907} 4908 4909SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4910 SDValue ShufMask = N->getOperand(2); 4911 unsigned NumElts = ShufMask.getNumOperands(); 4912 4913 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4914 bool isIdentity = true; 4915 for (unsigned i = 0; i != NumElts; ++i) { 4916 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4917 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4918 isIdentity = false; 4919 break; 4920 } 4921 } 4922 if (isIdentity) return N->getOperand(0); 4923 4924 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4925 isIdentity = true; 4926 for (unsigned i = 0; i != NumElts; ++i) { 4927 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4928 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4929 isIdentity = false; 4930 break; 4931 } 4932 } 4933 if (isIdentity) return N->getOperand(1); 4934 4935 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4936 // needed at all. 4937 bool isUnary = true; 4938 bool isSplat = true; 4939 int VecNum = -1; 4940 unsigned BaseIdx = 0; 4941 for (unsigned i = 0; i != NumElts; ++i) 4942 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4943 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4944 int V = (Idx < NumElts) ? 0 : 1; 4945 if (VecNum == -1) { 4946 VecNum = V; 4947 BaseIdx = Idx; 4948 } else { 4949 if (BaseIdx != Idx) 4950 isSplat = false; 4951 if (VecNum != V) { 4952 isUnary = false; 4953 break; 4954 } 4955 } 4956 } 4957 4958 SDValue N0 = N->getOperand(0); 4959 SDValue N1 = N->getOperand(1); 4960 // Normalize unary shuffle so the RHS is undef. 4961 if (isUnary && VecNum == 1) 4962 std::swap(N0, N1); 4963 4964 // If it is a splat, check if the argument vector is a build_vector with 4965 // all scalar elements the same. 4966 if (isSplat) { 4967 SDNode *V = N0.Val; 4968 4969 // If this is a bit convert that changes the element type of the vector but 4970 // not the number of vector elements, look through it. Be careful not to 4971 // look though conversions that change things like v4f32 to v2f64. 4972 if (V->getOpcode() == ISD::BIT_CONVERT) { 4973 SDValue ConvInput = V->getOperand(0); 4974 if (ConvInput.getValueType().isVector() && 4975 ConvInput.getValueType().getVectorNumElements() == NumElts) 4976 V = ConvInput.Val; 4977 } 4978 4979 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4980 unsigned NumElems = V->getNumOperands(); 4981 if (NumElems > BaseIdx) { 4982 SDValue Base; 4983 bool AllSame = true; 4984 for (unsigned i = 0; i != NumElems; ++i) { 4985 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4986 Base = V->getOperand(i); 4987 break; 4988 } 4989 } 4990 // Splat of <u, u, u, u>, return <u, u, u, u> 4991 if (!Base.Val) 4992 return N0; 4993 for (unsigned i = 0; i != NumElems; ++i) { 4994 if (V->getOperand(i) != Base) { 4995 AllSame = false; 4996 break; 4997 } 4998 } 4999 // Splat of <x, x, x, x>, return <x, x, x, x> 5000 if (AllSame) 5001 return N0; 5002 } 5003 } 5004 } 5005 5006 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5007 // into an undef. 5008 if (isUnary || N0 == N1) { 5009 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5010 // first operand. 5011 SmallVector<SDValue, 8> MappedOps; 5012 for (unsigned i = 0; i != NumElts; ++i) { 5013 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5014 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 5015 MappedOps.push_back(ShufMask.getOperand(i)); 5016 } else { 5017 unsigned NewIdx = 5018 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 5019 MappedOps.push_back(DAG.getConstant(NewIdx, 5020 ShufMask.getOperand(i).getValueType())); 5021 } 5022 } 5023 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5024 &MappedOps[0], MappedOps.size()); 5025 AddToWorkList(ShufMask.Val); 5026 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5027 N0, 5028 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5029 ShufMask); 5030 } 5031 5032 return SDValue(); 5033} 5034 5035/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5036/// an AND to a vector_shuffle with the destination vector and a zero vector. 5037/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5038/// vector_shuffle V, Zero, <0, 4, 2, 4> 5039SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5040 SDValue LHS = N->getOperand(0); 5041 SDValue RHS = N->getOperand(1); 5042 if (N->getOpcode() == ISD::AND) { 5043 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5044 RHS = RHS.getOperand(0); 5045 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5046 std::vector<SDValue> IdxOps; 5047 unsigned NumOps = RHS.getNumOperands(); 5048 unsigned NumElts = NumOps; 5049 MVT EVT = RHS.getValueType().getVectorElementType(); 5050 for (unsigned i = 0; i != NumElts; ++i) { 5051 SDValue Elt = RHS.getOperand(i); 5052 if (!isa<ConstantSDNode>(Elt)) 5053 return SDValue(); 5054 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5055 IdxOps.push_back(DAG.getConstant(i, EVT)); 5056 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5057 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5058 else 5059 return SDValue(); 5060 } 5061 5062 // Let's see if the target supports this vector_shuffle. 5063 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5064 return SDValue(); 5065 5066 // Return the new VECTOR_SHUFFLE node. 5067 MVT VT = MVT::getVectorVT(EVT, NumElts); 5068 std::vector<SDValue> Ops; 5069 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5070 Ops.push_back(LHS); 5071 AddToWorkList(LHS.Val); 5072 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5073 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5074 &ZeroOps[0], ZeroOps.size())); 5075 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5076 &IdxOps[0], IdxOps.size())); 5077 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5078 &Ops[0], Ops.size()); 5079 if (VT != N->getValueType(0)) 5080 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5081 return Result; 5082 } 5083 } 5084 return SDValue(); 5085} 5086 5087/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5088SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5089 // After legalize, the target may be depending on adds and other 5090 // binary ops to provide legal ways to construct constants or other 5091 // things. Simplifying them may result in a loss of legality. 5092 if (AfterLegalize) return SDValue(); 5093 5094 MVT VT = N->getValueType(0); 5095 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5096 5097 MVT EltType = VT.getVectorElementType(); 5098 SDValue LHS = N->getOperand(0); 5099 SDValue RHS = N->getOperand(1); 5100 SDValue Shuffle = XformToShuffleWithZero(N); 5101 if (Shuffle.Val) return Shuffle; 5102 5103 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5104 // this operation. 5105 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5106 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5107 SmallVector<SDValue, 8> Ops; 5108 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5109 SDValue LHSOp = LHS.getOperand(i); 5110 SDValue RHSOp = RHS.getOperand(i); 5111 // If these two elements can't be folded, bail out. 5112 if ((LHSOp.getOpcode() != ISD::UNDEF && 5113 LHSOp.getOpcode() != ISD::Constant && 5114 LHSOp.getOpcode() != ISD::ConstantFP) || 5115 (RHSOp.getOpcode() != ISD::UNDEF && 5116 RHSOp.getOpcode() != ISD::Constant && 5117 RHSOp.getOpcode() != ISD::ConstantFP)) 5118 break; 5119 // Can't fold divide by zero. 5120 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5121 N->getOpcode() == ISD::FDIV) { 5122 if ((RHSOp.getOpcode() == ISD::Constant && 5123 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 5124 (RHSOp.getOpcode() == ISD::ConstantFP && 5125 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 5126 break; 5127 } 5128 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5129 AddToWorkList(Ops.back().Val); 5130 assert((Ops.back().getOpcode() == ISD::UNDEF || 5131 Ops.back().getOpcode() == ISD::Constant || 5132 Ops.back().getOpcode() == ISD::ConstantFP) && 5133 "Scalar binop didn't fold!"); 5134 } 5135 5136 if (Ops.size() == LHS.getNumOperands()) { 5137 MVT VT = LHS.getValueType(); 5138 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5139 } 5140 } 5141 5142 return SDValue(); 5143} 5144 5145SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5146 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5147 5148 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5149 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5150 // If we got a simplified select_cc node back from SimplifySelectCC, then 5151 // break it down into a new SETCC node, and a new SELECT node, and then return 5152 // the SELECT node, since we were called with a SELECT node. 5153 if (SCC.Val) { 5154 // Check to see if we got a select_cc back (to turn into setcc/select). 5155 // Otherwise, just return whatever node we got back, like fabs. 5156 if (SCC.getOpcode() == ISD::SELECT_CC) { 5157 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5158 SCC.getOperand(0), SCC.getOperand(1), 5159 SCC.getOperand(4)); 5160 AddToWorkList(SETCC.Val); 5161 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5162 SCC.getOperand(3), SETCC); 5163 } 5164 return SCC; 5165 } 5166 return SDValue(); 5167} 5168 5169/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5170/// are the two values being selected between, see if we can simplify the 5171/// select. Callers of this should assume that TheSelect is deleted if this 5172/// returns true. As such, they should return the appropriate thing (e.g. the 5173/// node) back to the top-level of the DAG combiner loop to avoid it being 5174/// looked at. 5175/// 5176bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5177 SDValue RHS) { 5178 5179 // If this is a select from two identical things, try to pull the operation 5180 // through the select. 5181 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5182 // If this is a load and the token chain is identical, replace the select 5183 // of two loads with a load through a select of the address to load from. 5184 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5185 // constants have been dropped into the constant pool. 5186 if (LHS.getOpcode() == ISD::LOAD && 5187 // Do not let this transformation reduce the number of volatile loads. 5188 !cast<LoadSDNode>(LHS)->isVolatile() && 5189 !cast<LoadSDNode>(RHS)->isVolatile() && 5190 // Token chains must be identical. 5191 LHS.getOperand(0) == RHS.getOperand(0)) { 5192 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5193 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5194 5195 // If this is an EXTLOAD, the VT's must match. 5196 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5197 // FIXME: this conflates two src values, discarding one. This is not 5198 // the right thing to do, but nothing uses srcvalues now. When they do, 5199 // turn SrcValue into a list of locations. 5200 SDValue Addr; 5201 if (TheSelect->getOpcode() == ISD::SELECT) { 5202 // Check that the condition doesn't reach either load. If so, folding 5203 // this will induce a cycle into the DAG. 5204 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5205 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val)) { 5206 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5207 TheSelect->getOperand(0), LLD->getBasePtr(), 5208 RLD->getBasePtr()); 5209 } 5210 } else { 5211 // Check that the condition doesn't reach either load. If so, folding 5212 // this will induce a cycle into the DAG. 5213 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5214 !RLD->isPredecessorOf(TheSelect->getOperand(0).Val) && 5215 !LLD->isPredecessorOf(TheSelect->getOperand(1).Val) && 5216 !RLD->isPredecessorOf(TheSelect->getOperand(1).Val)) { 5217 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5218 TheSelect->getOperand(0), 5219 TheSelect->getOperand(1), 5220 LLD->getBasePtr(), RLD->getBasePtr(), 5221 TheSelect->getOperand(4)); 5222 } 5223 } 5224 5225 if (Addr.Val) { 5226 SDValue Load; 5227 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5228 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5229 Addr,LLD->getSrcValue(), 5230 LLD->getSrcValueOffset(), 5231 LLD->isVolatile(), 5232 LLD->getAlignment()); 5233 else { 5234 Load = DAG.getExtLoad(LLD->getExtensionType(), 5235 TheSelect->getValueType(0), 5236 LLD->getChain(), Addr, LLD->getSrcValue(), 5237 LLD->getSrcValueOffset(), 5238 LLD->getMemoryVT(), 5239 LLD->isVolatile(), 5240 LLD->getAlignment()); 5241 } 5242 // Users of the select now use the result of the load. 5243 CombineTo(TheSelect, Load); 5244 5245 // Users of the old loads now use the new load's chain. We know the 5246 // old-load value is dead now. 5247 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5248 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5249 return true; 5250 } 5251 } 5252 } 5253 } 5254 5255 return false; 5256} 5257 5258SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5259 SDValue N2, SDValue N3, 5260 ISD::CondCode CC, bool NotExtCompare) { 5261 5262 MVT VT = N2.getValueType(); 5263 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5264 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5265 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5266 5267 // Determine if the condition we're dealing with is constant 5268 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5269 if (SCC.Val) AddToWorkList(SCC.Val); 5270 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5271 5272 // fold select_cc true, x, y -> x 5273 if (SCCC && !SCCC->isNullValue()) 5274 return N2; 5275 // fold select_cc false, x, y -> y 5276 if (SCCC && SCCC->isNullValue()) 5277 return N3; 5278 5279 // Check to see if we can simplify the select into an fabs node 5280 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5281 // Allow either -0.0 or 0.0 5282 if (CFP->getValueAPF().isZero()) { 5283 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5284 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5285 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5286 N2 == N3.getOperand(0)) 5287 return DAG.getNode(ISD::FABS, VT, N0); 5288 5289 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5290 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5291 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5292 N2.getOperand(0) == N3) 5293 return DAG.getNode(ISD::FABS, VT, N3); 5294 } 5295 } 5296 5297 // Check to see if we can perform the "gzip trick", transforming 5298 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5299 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5300 N0.getValueType().isInteger() && 5301 N2.getValueType().isInteger() && 5302 (N1C->isNullValue() || // (a < 0) ? b : 0 5303 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5304 MVT XType = N0.getValueType(); 5305 MVT AType = N2.getValueType(); 5306 if (XType.bitsGE(AType)) { 5307 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5308 // single-bit constant. 5309 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5310 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5311 ShCtV = XType.getSizeInBits()-ShCtV-1; 5312 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5313 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5314 AddToWorkList(Shift.Val); 5315 if (XType.bitsGT(AType)) { 5316 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5317 AddToWorkList(Shift.Val); 5318 } 5319 return DAG.getNode(ISD::AND, AType, Shift, N2); 5320 } 5321 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5322 DAG.getConstant(XType.getSizeInBits()-1, 5323 TLI.getShiftAmountTy())); 5324 AddToWorkList(Shift.Val); 5325 if (XType.bitsGT(AType)) { 5326 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5327 AddToWorkList(Shift.Val); 5328 } 5329 return DAG.getNode(ISD::AND, AType, Shift, N2); 5330 } 5331 } 5332 5333 // fold select C, 16, 0 -> shl C, 4 5334 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5335 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5336 5337 // If the caller doesn't want us to simplify this into a zext of a compare, 5338 // don't do it. 5339 if (NotExtCompare && N2C->getAPIntValue() == 1) 5340 return SDValue(); 5341 5342 // Get a SetCC of the condition 5343 // FIXME: Should probably make sure that setcc is legal if we ever have a 5344 // target where it isn't. 5345 SDValue Temp, SCC; 5346 // cast from setcc result type to select result type 5347 if (AfterLegalize) { 5348 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5349 if (N2.getValueType().bitsLT(SCC.getValueType())) 5350 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5351 else 5352 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5353 } else { 5354 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5355 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5356 } 5357 AddToWorkList(SCC.Val); 5358 AddToWorkList(Temp.Val); 5359 5360 if (N2C->getAPIntValue() == 1) 5361 return Temp; 5362 // shl setcc result by log2 n2c 5363 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5364 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5365 TLI.getShiftAmountTy())); 5366 } 5367 5368 // Check to see if this is the equivalent of setcc 5369 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5370 // otherwise, go ahead with the folds. 5371 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5372 MVT XType = N0.getValueType(); 5373 if (!AfterLegalize || 5374 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5375 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5376 if (Res.getValueType() != VT) 5377 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5378 return Res; 5379 } 5380 5381 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5382 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5383 (!AfterLegalize || 5384 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5385 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5386 return DAG.getNode(ISD::SRL, XType, Ctlz, 5387 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5388 TLI.getShiftAmountTy())); 5389 } 5390 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5391 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5392 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5393 N0); 5394 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5395 DAG.getConstant(~0ULL, XType)); 5396 return DAG.getNode(ISD::SRL, XType, 5397 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5398 DAG.getConstant(XType.getSizeInBits()-1, 5399 TLI.getShiftAmountTy())); 5400 } 5401 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5402 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5403 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5404 DAG.getConstant(XType.getSizeInBits()-1, 5405 TLI.getShiftAmountTy())); 5406 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5407 } 5408 } 5409 5410 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5411 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5412 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5413 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5414 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5415 MVT XType = N0.getValueType(); 5416 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5417 DAG.getConstant(XType.getSizeInBits()-1, 5418 TLI.getShiftAmountTy())); 5419 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5420 AddToWorkList(Shift.Val); 5421 AddToWorkList(Add.Val); 5422 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5423 } 5424 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5425 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5426 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5427 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5428 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5429 MVT XType = N0.getValueType(); 5430 if (SubC->isNullValue() && XType.isInteger()) { 5431 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5432 DAG.getConstant(XType.getSizeInBits()-1, 5433 TLI.getShiftAmountTy())); 5434 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5435 AddToWorkList(Shift.Val); 5436 AddToWorkList(Add.Val); 5437 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5438 } 5439 } 5440 } 5441 5442 return SDValue(); 5443} 5444 5445/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5446SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5447 SDValue N1, ISD::CondCode Cond, 5448 bool foldBooleans) { 5449 TargetLowering::DAGCombinerInfo 5450 DagCombineInfo(DAG, !AfterLegalize, false, this); 5451 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5452} 5453 5454/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5455/// return a DAG expression to select that will generate the same value by 5456/// multiplying by a magic number. See: 5457/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5458SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5459 std::vector<SDNode*> Built; 5460 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5461 5462 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5463 ii != ee; ++ii) 5464 AddToWorkList(*ii); 5465 return S; 5466} 5467 5468/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5469/// return a DAG expression to select that will generate the same value by 5470/// multiplying by a magic number. See: 5471/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5472SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5473 std::vector<SDNode*> Built; 5474 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5475 5476 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5477 ii != ee; ++ii) 5478 AddToWorkList(*ii); 5479 return S; 5480} 5481 5482/// FindBaseOffset - Return true if base is known not to alias with anything 5483/// but itself. Provides base object and offset as results. 5484static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5485 // Assume it is a primitive operation. 5486 Base = Ptr; Offset = 0; 5487 5488 // If it's an adding a simple constant then integrate the offset. 5489 if (Base.getOpcode() == ISD::ADD) { 5490 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5491 Base = Base.getOperand(0); 5492 Offset += C->getValue(); 5493 } 5494 } 5495 5496 // If it's any of the following then it can't alias with anything but itself. 5497 return isa<FrameIndexSDNode>(Base) || 5498 isa<ConstantPoolSDNode>(Base) || 5499 isa<GlobalAddressSDNode>(Base); 5500} 5501 5502/// isAlias - Return true if there is any possibility that the two addresses 5503/// overlap. 5504bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5505 const Value *SrcValue1, int SrcValueOffset1, 5506 SDValue Ptr2, int64_t Size2, 5507 const Value *SrcValue2, int SrcValueOffset2) 5508{ 5509 // If they are the same then they must be aliases. 5510 if (Ptr1 == Ptr2) return true; 5511 5512 // Gather base node and offset information. 5513 SDValue Base1, Base2; 5514 int64_t Offset1, Offset2; 5515 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5516 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5517 5518 // If they have a same base address then... 5519 if (Base1 == Base2) { 5520 // Check to see if the addresses overlap. 5521 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5522 } 5523 5524 // If we know both bases then they can't alias. 5525 if (KnownBase1 && KnownBase2) return false; 5526 5527 if (CombinerGlobalAA) { 5528 // Use alias analysis information. 5529 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5530 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5531 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5532 AliasAnalysis::AliasResult AAResult = 5533 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5534 if (AAResult == AliasAnalysis::NoAlias) 5535 return false; 5536 } 5537 5538 // Otherwise we have to assume they alias. 5539 return true; 5540} 5541 5542/// FindAliasInfo - Extracts the relevant alias information from the memory 5543/// node. Returns true if the operand was a load. 5544bool DAGCombiner::FindAliasInfo(SDNode *N, 5545 SDValue &Ptr, int64_t &Size, 5546 const Value *&SrcValue, int &SrcValueOffset) { 5547 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5548 Ptr = LD->getBasePtr(); 5549 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5550 SrcValue = LD->getSrcValue(); 5551 SrcValueOffset = LD->getSrcValueOffset(); 5552 return true; 5553 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5554 Ptr = ST->getBasePtr(); 5555 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5556 SrcValue = ST->getSrcValue(); 5557 SrcValueOffset = ST->getSrcValueOffset(); 5558 } else { 5559 assert(0 && "FindAliasInfo expected a memory operand"); 5560 } 5561 5562 return false; 5563} 5564 5565/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5566/// looking for aliasing nodes and adding them to the Aliases vector. 5567void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5568 SmallVector<SDValue, 8> &Aliases) { 5569 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5570 std::set<SDNode *> Visited; // Visited node set. 5571 5572 // Get alias information for node. 5573 SDValue Ptr; 5574 int64_t Size; 5575 const Value *SrcValue; 5576 int SrcValueOffset; 5577 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5578 5579 // Starting off. 5580 Chains.push_back(OriginalChain); 5581 5582 // Look at each chain and determine if it is an alias. If so, add it to the 5583 // aliases list. If not, then continue up the chain looking for the next 5584 // candidate. 5585 while (!Chains.empty()) { 5586 SDValue Chain = Chains.back(); 5587 Chains.pop_back(); 5588 5589 // Don't bother if we've been before. 5590 if (Visited.find(Chain.Val) != Visited.end()) continue; 5591 Visited.insert(Chain.Val); 5592 5593 switch (Chain.getOpcode()) { 5594 case ISD::EntryToken: 5595 // Entry token is ideal chain operand, but handled in FindBetterChain. 5596 break; 5597 5598 case ISD::LOAD: 5599 case ISD::STORE: { 5600 // Get alias information for Chain. 5601 SDValue OpPtr; 5602 int64_t OpSize; 5603 const Value *OpSrcValue; 5604 int OpSrcValueOffset; 5605 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5606 OpSrcValue, OpSrcValueOffset); 5607 5608 // If chain is alias then stop here. 5609 if (!(IsLoad && IsOpLoad) && 5610 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5611 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5612 Aliases.push_back(Chain); 5613 } else { 5614 // Look further up the chain. 5615 Chains.push_back(Chain.getOperand(0)); 5616 // Clean up old chain. 5617 AddToWorkList(Chain.Val); 5618 } 5619 break; 5620 } 5621 5622 case ISD::TokenFactor: 5623 // We have to check each of the operands of the token factor, so we queue 5624 // then up. Adding the operands to the queue (stack) in reverse order 5625 // maintains the original order and increases the likelihood that getNode 5626 // will find a matching token factor (CSE.) 5627 for (unsigned n = Chain.getNumOperands(); n;) 5628 Chains.push_back(Chain.getOperand(--n)); 5629 // Eliminate the token factor if we can. 5630 AddToWorkList(Chain.Val); 5631 break; 5632 5633 default: 5634 // For all other instructions we will just have to take what we can get. 5635 Aliases.push_back(Chain); 5636 break; 5637 } 5638 } 5639} 5640 5641/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5642/// for a better chain (aliasing node.) 5643SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5644 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5645 5646 // Accumulate all the aliases to this node. 5647 GatherAllAliases(N, OldChain, Aliases); 5648 5649 if (Aliases.size() == 0) { 5650 // If no operands then chain to entry token. 5651 return DAG.getEntryNode(); 5652 } else if (Aliases.size() == 1) { 5653 // If a single operand then chain to it. We don't need to revisit it. 5654 return Aliases[0]; 5655 } 5656 5657 // Construct a custom tailored token factor. 5658 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5659 &Aliases[0], Aliases.size()); 5660 5661 // Make sure the old chain gets cleaned up. 5662 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5663 5664 return NewChain; 5665} 5666 5667// SelectionDAG::Combine - This is the entry point for the file. 5668// 5669void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5670 bool Fast) { 5671 /// run - This is the main entry point to this class. 5672 /// 5673 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5674} 5675