DAGCombiner.cpp revision 9a526495e0c06c4014d7500788cad1929fd244d3
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBIT_CONVERT(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 239 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 240 241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 242 /// looking for aliasing nodes and adding them to the Aliases vector. 243 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 244 SmallVector<SDValue, 8> &Aliases); 245 246 /// isAlias - Return true if there is any possibility that the two addresses 247 /// overlap. 248 bool isAlias(SDValue Ptr1, int64_t Size1, 249 const Value *SrcValue1, int SrcValueOffset1, 250 unsigned SrcValueAlign1, 251 SDValue Ptr2, int64_t Size2, 252 const Value *SrcValue2, int SrcValueOffset2, 253 unsigned SrcValueAlign2) const; 254 255 /// FindAliasInfo - Extracts the relevant alias information from the memory 256 /// node. Returns true if the operand was a load. 257 bool FindAliasInfo(SDNode *N, 258 SDValue &Ptr, int64_t &Size, 259 const Value *&SrcValue, int &SrcValueOffset, 260 unsigned &SrcValueAlignment) const; 261 262 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 263 /// looking for a better chain (aliasing node.) 264 SDValue FindBetterChain(SDNode *N, SDValue Chain); 265 266 public: 267 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 268 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 269 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 270 271 /// Run - runs the dag combiner on all nodes in the work list 272 void Run(CombineLevel AtLevel); 273 274 SelectionDAG &getDAG() const { return DAG; } 275 276 /// getShiftAmountTy - Returns a type large enough to hold any valid 277 /// shift amount - before type legalization these can be huge. 278 EVT getShiftAmountTy() { 279 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 280 } 281 282 /// isTypeLegal - This method returns true if we are running before type 283 /// legalization or if the specified VT is legal. 284 bool isTypeLegal(const EVT &VT) { 285 if (!LegalTypes) return true; 286 return TLI.isTypeLegal(VT); 287 } 288 }; 289} 290 291 292namespace { 293/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 294/// nodes from the worklist. 295class WorkListRemover : public SelectionDAG::DAGUpdateListener { 296 DAGCombiner &DC; 297public: 298 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 299 300 virtual void NodeDeleted(SDNode *N, SDNode *E) { 301 DC.removeFromWorkList(N); 302 } 303 304 virtual void NodeUpdated(SDNode *N) { 305 // Ignore updates. 306 } 307}; 308} 309 310//===----------------------------------------------------------------------===// 311// TargetLowering::DAGCombinerInfo implementation 312//===----------------------------------------------------------------------===// 313 314void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 315 ((DAGCombiner*)DC)->AddToWorkList(N); 316} 317 318SDValue TargetLowering::DAGCombinerInfo:: 319CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 320 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 321} 322 323SDValue TargetLowering::DAGCombinerInfo:: 324CombineTo(SDNode *N, SDValue Res, bool AddTo) { 325 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 326} 327 328 329SDValue TargetLowering::DAGCombinerInfo:: 330CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 331 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 332} 333 334void TargetLowering::DAGCombinerInfo:: 335CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 336 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 337} 338 339//===----------------------------------------------------------------------===// 340// Helper Functions 341//===----------------------------------------------------------------------===// 342 343/// isNegatibleForFree - Return 1 if we can compute the negated form of the 344/// specified expression for the same cost as the expression itself, or 2 if we 345/// can compute the negated form more cheaply than the expression itself. 346static char isNegatibleForFree(SDValue Op, bool LegalOperations, 347 unsigned Depth = 0) { 348 // No compile time optimizations on this type. 349 if (Op.getValueType() == MVT::ppcf128) 350 return 0; 351 352 // fneg is removable even if it has multiple uses. 353 if (Op.getOpcode() == ISD::FNEG) return 2; 354 355 // Don't allow anything with multiple uses. 356 if (!Op.hasOneUse()) return 0; 357 358 // Don't recurse exponentially. 359 if (Depth > 6) return 0; 360 361 switch (Op.getOpcode()) { 362 default: return false; 363 case ISD::ConstantFP: 364 // Don't invert constant FP values after legalize. The negated constant 365 // isn't necessarily legal. 366 return LegalOperations ? 0 : 1; 367 case ISD::FADD: 368 // FIXME: determine better conditions for this xform. 369 if (!UnsafeFPMath) return 0; 370 371 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 372 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 373 return V; 374 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 375 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 376 case ISD::FSUB: 377 // We can't turn -(A-B) into B-A when we honor signed zeros. 378 if (!UnsafeFPMath) return 0; 379 380 // fold (fneg (fsub A, B)) -> (fsub B, A) 381 return 1; 382 383 case ISD::FMUL: 384 case ISD::FDIV: 385 if (HonorSignDependentRoundingFPMath()) return 0; 386 387 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 388 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 389 return V; 390 391 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 392 393 case ISD::FP_EXTEND: 394 case ISD::FP_ROUND: 395 case ISD::FSIN: 396 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 397 } 398} 399 400/// GetNegatedExpression - If isNegatibleForFree returns true, this function 401/// returns the newly negated expression. 402static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 403 bool LegalOperations, unsigned Depth = 0) { 404 // fneg is removable even if it has multiple uses. 405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 406 407 // Don't allow anything with multiple uses. 408 assert(Op.hasOneUse() && "Unknown reuse!"); 409 410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 411 switch (Op.getOpcode()) { 412 default: llvm_unreachable("Unknown code"); 413 case ISD::ConstantFP: { 414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 415 V.changeSign(); 416 return DAG.getConstantFP(V, Op.getValueType()); 417 } 418 case ISD::FADD: 419 // FIXME: determine better conditions for this xform. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 423 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 424 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 LegalOperations, Depth+1), 427 Op.getOperand(1)); 428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 429 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 430 GetNegatedExpression(Op.getOperand(1), DAG, 431 LegalOperations, Depth+1), 432 Op.getOperand(0)); 433 case ISD::FSUB: 434 // We can't turn -(A-B) into B-A when we honor signed zeros. 435 assert(UnsafeFPMath); 436 437 // fold (fneg (fsub 0, B)) -> B 438 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 439 if (N0CFP->getValueAPF().isZero()) 440 return Op.getOperand(1); 441 442 // fold (fneg (fsub A, B)) -> (fsub B, A) 443 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(1), Op.getOperand(0)); 445 446 case ISD::FMUL: 447 case ISD::FDIV: 448 assert(!HonorSignDependentRoundingFPMath()); 449 450 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 451 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 457 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 458 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 459 Op.getOperand(0), 460 GetNegatedExpression(Op.getOperand(1), DAG, 461 LegalOperations, Depth+1)); 462 463 case ISD::FP_EXTEND: 464 case ISD::FSIN: 465 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 466 GetNegatedExpression(Op.getOperand(0), DAG, 467 LegalOperations, Depth+1)); 468 case ISD::FP_ROUND: 469 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 470 GetNegatedExpression(Op.getOperand(0), DAG, 471 LegalOperations, Depth+1), 472 Op.getOperand(1)); 473 } 474} 475 476 477// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 478// that selects between the values 1 and 0, making it equivalent to a setcc. 479// Also, set the incoming LHS, RHS, and CC references to the appropriate 480// nodes based on the type of node we are checking. This simplifies life a 481// bit for the callers. 482static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 483 SDValue &CC) { 484 if (N.getOpcode() == ISD::SETCC) { 485 LHS = N.getOperand(0); 486 RHS = N.getOperand(1); 487 CC = N.getOperand(2); 488 return true; 489 } 490 if (N.getOpcode() == ISD::SELECT_CC && 491 N.getOperand(2).getOpcode() == ISD::Constant && 492 N.getOperand(3).getOpcode() == ISD::Constant && 493 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 494 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 495 LHS = N.getOperand(0); 496 RHS = N.getOperand(1); 497 CC = N.getOperand(4); 498 return true; 499 } 500 return false; 501} 502 503// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 504// one use. If this is true, it allows the users to invert the operation for 505// free when it is profitable to do so. 506static bool isOneUseSetCC(SDValue N) { 507 SDValue N0, N1, N2; 508 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 509 return true; 510 return false; 511} 512 513SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 514 SDValue N0, SDValue N1) { 515 EVT VT = N0.getValueType(); 516 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 517 if (isa<ConstantSDNode>(N1)) { 518 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 519 SDValue OpNode = 520 DAG.FoldConstantArithmetic(Opc, VT, 521 cast<ConstantSDNode>(N0.getOperand(1)), 522 cast<ConstantSDNode>(N1)); 523 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 524 } else if (N0.hasOneUse()) { 525 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 527 N0.getOperand(0), N1); 528 AddToWorkList(OpNode.getNode()); 529 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 530 } 531 } 532 533 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 534 if (isa<ConstantSDNode>(N0)) { 535 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 536 SDValue OpNode = 537 DAG.FoldConstantArithmetic(Opc, VT, 538 cast<ConstantSDNode>(N1.getOperand(1)), 539 cast<ConstantSDNode>(N0)); 540 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 541 } else if (N1.hasOneUse()) { 542 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 543 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 544 N1.getOperand(0), N0); 545 AddToWorkList(OpNode.getNode()); 546 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 547 } 548 } 549 550 return SDValue(); 551} 552 553SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 554 bool AddTo) { 555 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 556 ++NodesCombined; 557 DEBUG(dbgs() << "\nReplacing.1 "; 558 N->dump(&DAG); 559 dbgs() << "\nWith: "; 560 To[0].getNode()->dump(&DAG); 561 dbgs() << " and " << NumTo-1 << " other values\n"; 562 for (unsigned i = 0, e = NumTo; i != e; ++i) 563 assert((!To[i].getNode() || 564 N->getValueType(i) == To[i].getValueType()) && 565 "Cannot combine value to value of different type!")); 566 WorkListRemover DeadNodes(*this); 567 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 568 569 if (AddTo) { 570 // Push the new nodes and any users onto the worklist 571 for (unsigned i = 0, e = NumTo; i != e; ++i) { 572 if (To[i].getNode()) { 573 AddToWorkList(To[i].getNode()); 574 AddUsersToWorkList(To[i].getNode()); 575 } 576 } 577 } 578 579 // Finally, if the node is now dead, remove it from the graph. The node 580 // may not be dead if the replacement process recursively simplified to 581 // something else needing this node. 582 if (N->use_empty()) { 583 // Nodes can be reintroduced into the worklist. Make sure we do not 584 // process a node that has been replaced. 585 removeFromWorkList(N); 586 587 // Finally, since the node is now dead, remove it from the graph. 588 DAG.DeleteNode(N); 589 } 590 return SDValue(N, 0); 591} 592 593void DAGCombiner:: 594CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 595 // Replace all uses. If any nodes become isomorphic to other nodes and 596 // are deleted, make sure to remove them from our worklist. 597 WorkListRemover DeadNodes(*this); 598 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 599 600 // Push the new node and any (possibly new) users onto the worklist. 601 AddToWorkList(TLO.New.getNode()); 602 AddUsersToWorkList(TLO.New.getNode()); 603 604 // Finally, if the node is now dead, remove it from the graph. The node 605 // may not be dead if the replacement process recursively simplified to 606 // something else needing this node. 607 if (TLO.Old.getNode()->use_empty()) { 608 removeFromWorkList(TLO.Old.getNode()); 609 610 // If the operands of this node are only used by the node, they will now 611 // be dead. Make sure to visit them first to delete dead nodes early. 612 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 613 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 614 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 615 616 DAG.DeleteNode(TLO.Old.getNode()); 617 } 618} 619 620/// SimplifyDemandedBits - Check the specified integer node value to see if 621/// it can be simplified or if things it uses can be simplified by bit 622/// propagation. If so, return true. 623bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 624 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 625 APInt KnownZero, KnownOne; 626 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 627 return false; 628 629 // Revisit the node. 630 AddToWorkList(Op.getNode()); 631 632 // Replace the old value with the new one. 633 ++NodesCombined; 634 DEBUG(dbgs() << "\nReplacing.2 "; 635 TLO.Old.getNode()->dump(&DAG); 636 dbgs() << "\nWith: "; 637 TLO.New.getNode()->dump(&DAG); 638 dbgs() << '\n'); 639 640 CommitTargetLoweringOpt(TLO); 641 return true; 642} 643 644void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 645 DebugLoc dl = Load->getDebugLoc(); 646 EVT VT = Load->getValueType(0); 647 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 648 649 DEBUG(dbgs() << "\nReplacing.9 "; 650 Load->dump(&DAG); 651 dbgs() << "\nWith: "; 652 Trunc.getNode()->dump(&DAG); 653 dbgs() << '\n'); 654 WorkListRemover DeadNodes(*this); 655 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 656 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 657 &DeadNodes); 658 removeFromWorkList(Load); 659 DAG.DeleteNode(Load); 660 AddToWorkList(Trunc.getNode()); 661} 662 663SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 664 Replace = false; 665 DebugLoc dl = Op.getDebugLoc(); 666 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 667 EVT MemVT = LD->getMemoryVT(); 668 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 669 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 670 : LD->getExtensionType(); 671 Replace = true; 672 return DAG.getExtLoad(ExtType, dl, PVT, 673 LD->getChain(), LD->getBasePtr(), 674 LD->getSrcValue(), LD->getSrcValueOffset(), 675 MemVT, LD->isVolatile(), 676 LD->isNonTemporal(), LD->getAlignment()); 677 } 678 679 unsigned Opc = Op.getOpcode(); 680 switch (Opc) { 681 default: break; 682 case ISD::AssertSext: 683 return DAG.getNode(ISD::AssertSext, dl, PVT, 684 SExtPromoteOperand(Op.getOperand(0), PVT), 685 Op.getOperand(1)); 686 case ISD::AssertZext: 687 return DAG.getNode(ISD::AssertZext, dl, PVT, 688 ZExtPromoteOperand(Op.getOperand(0), PVT), 689 Op.getOperand(1)); 690 case ISD::Constant: { 691 unsigned ExtOpc = 692 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 693 return DAG.getNode(ExtOpc, dl, PVT, Op); 694 } 695 } 696 697 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 698 return SDValue(); 699 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 700} 701 702SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 703 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 704 return SDValue(); 705 EVT OldVT = Op.getValueType(); 706 DebugLoc dl = Op.getDebugLoc(); 707 bool Replace = false; 708 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 709 if (NewOp.getNode() == 0) 710 return SDValue(); 711 AddToWorkList(NewOp.getNode()); 712 713 if (Replace) 714 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 715 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 716 DAG.getValueType(OldVT)); 717} 718 719SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 720 EVT OldVT = Op.getValueType(); 721 DebugLoc dl = Op.getDebugLoc(); 722 bool Replace = false; 723 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 724 if (NewOp.getNode() == 0) 725 return SDValue(); 726 AddToWorkList(NewOp.getNode()); 727 728 if (Replace) 729 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 730 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 731} 732 733/// PromoteIntBinOp - Promote the specified integer binary operation if the 734/// target indicates it is beneficial. e.g. On x86, it's usually better to 735/// promote i16 operations to i32 since i16 instructions are longer. 736SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 737 if (!LegalOperations) 738 return SDValue(); 739 740 EVT VT = Op.getValueType(); 741 if (VT.isVector() || !VT.isInteger()) 742 return SDValue(); 743 744 // If operation type is 'undesirable', e.g. i16 on x86, consider 745 // promoting it. 746 unsigned Opc = Op.getOpcode(); 747 if (TLI.isTypeDesirableForOp(Opc, VT)) 748 return SDValue(); 749 750 EVT PVT = VT; 751 // Consult target whether it is a good idea to promote this operation and 752 // what's the right type to promote it to. 753 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 754 assert(PVT != VT && "Don't know what type to promote to!"); 755 756 bool Replace0 = false; 757 SDValue N0 = Op.getOperand(0); 758 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 759 if (NN0.getNode() == 0) 760 return SDValue(); 761 762 bool Replace1 = false; 763 SDValue N1 = Op.getOperand(1); 764 SDValue NN1; 765 if (N0 == N1) 766 NN1 = NN0; 767 else { 768 NN1 = PromoteOperand(N1, PVT, Replace1); 769 if (NN1.getNode() == 0) 770 return SDValue(); 771 } 772 773 AddToWorkList(NN0.getNode()); 774 if (NN1.getNode()) 775 AddToWorkList(NN1.getNode()); 776 777 if (Replace0) 778 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 779 if (Replace1) 780 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 781 782 DEBUG(dbgs() << "\nPromoting "; 783 Op.getNode()->dump(&DAG)); 784 DebugLoc dl = Op.getDebugLoc(); 785 return DAG.getNode(ISD::TRUNCATE, dl, VT, 786 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 787 } 788 return SDValue(); 789} 790 791/// PromoteIntShiftOp - Promote the specified integer shift operation if the 792/// target indicates it is beneficial. e.g. On x86, it's usually better to 793/// promote i16 operations to i32 since i16 instructions are longer. 794SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 795 if (!LegalOperations) 796 return SDValue(); 797 798 EVT VT = Op.getValueType(); 799 if (VT.isVector() || !VT.isInteger()) 800 return SDValue(); 801 802 // If operation type is 'undesirable', e.g. i16 on x86, consider 803 // promoting it. 804 unsigned Opc = Op.getOpcode(); 805 if (TLI.isTypeDesirableForOp(Opc, VT)) 806 return SDValue(); 807 808 EVT PVT = VT; 809 // Consult target whether it is a good idea to promote this operation and 810 // what's the right type to promote it to. 811 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 812 assert(PVT != VT && "Don't know what type to promote to!"); 813 814 bool Replace = false; 815 SDValue N0 = Op.getOperand(0); 816 if (Opc == ISD::SRA) 817 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 818 else if (Opc == ISD::SRL) 819 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 820 else 821 N0 = PromoteOperand(N0, PVT, Replace); 822 if (N0.getNode() == 0) 823 return SDValue(); 824 825 AddToWorkList(N0.getNode()); 826 if (Replace) 827 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 828 829 DEBUG(dbgs() << "\nPromoting "; 830 Op.getNode()->dump(&DAG)); 831 DebugLoc dl = Op.getDebugLoc(); 832 return DAG.getNode(ISD::TRUNCATE, dl, VT, 833 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 834 } 835 return SDValue(); 836} 837 838SDValue DAGCombiner::PromoteExtend(SDValue Op) { 839 if (!LegalOperations) 840 return SDValue(); 841 842 EVT VT = Op.getValueType(); 843 if (VT.isVector() || !VT.isInteger()) 844 return SDValue(); 845 846 // If operation type is 'undesirable', e.g. i16 on x86, consider 847 // promoting it. 848 unsigned Opc = Op.getOpcode(); 849 if (TLI.isTypeDesirableForOp(Opc, VT)) 850 return SDValue(); 851 852 EVT PVT = VT; 853 // Consult target whether it is a good idea to promote this operation and 854 // what's the right type to promote it to. 855 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 856 assert(PVT != VT && "Don't know what type to promote to!"); 857 // fold (aext (aext x)) -> (aext x) 858 // fold (aext (zext x)) -> (zext x) 859 // fold (aext (sext x)) -> (sext x) 860 DEBUG(dbgs() << "\nPromoting "; 861 Op.getNode()->dump(&DAG)); 862 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 863 } 864 return SDValue(); 865} 866 867bool DAGCombiner::PromoteLoad(SDValue Op) { 868 if (!LegalOperations) 869 return false; 870 871 EVT VT = Op.getValueType(); 872 if (VT.isVector() || !VT.isInteger()) 873 return false; 874 875 // If operation type is 'undesirable', e.g. i16 on x86, consider 876 // promoting it. 877 unsigned Opc = Op.getOpcode(); 878 if (TLI.isTypeDesirableForOp(Opc, VT)) 879 return false; 880 881 EVT PVT = VT; 882 // Consult target whether it is a good idea to promote this operation and 883 // what's the right type to promote it to. 884 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 885 assert(PVT != VT && "Don't know what type to promote to!"); 886 887 DebugLoc dl = Op.getDebugLoc(); 888 SDNode *N = Op.getNode(); 889 LoadSDNode *LD = cast<LoadSDNode>(N); 890 EVT MemVT = LD->getMemoryVT(); 891 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 892 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD) 893 : LD->getExtensionType(); 894 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 895 LD->getChain(), LD->getBasePtr(), 896 LD->getSrcValue(), LD->getSrcValueOffset(), 897 MemVT, LD->isVolatile(), 898 LD->isNonTemporal(), LD->getAlignment()); 899 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 900 901 DEBUG(dbgs() << "\nPromoting "; 902 N->dump(&DAG); 903 dbgs() << "\nTo: "; 904 Result.getNode()->dump(&DAG); 905 dbgs() << '\n'); 906 WorkListRemover DeadNodes(*this); 907 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 908 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 909 removeFromWorkList(N); 910 DAG.DeleteNode(N); 911 AddToWorkList(Result.getNode()); 912 return true; 913 } 914 return false; 915} 916 917 918//===----------------------------------------------------------------------===// 919// Main DAG Combiner implementation 920//===----------------------------------------------------------------------===// 921 922void DAGCombiner::Run(CombineLevel AtLevel) { 923 // set the instance variables, so that the various visit routines may use it. 924 Level = AtLevel; 925 LegalOperations = Level >= NoIllegalOperations; 926 LegalTypes = Level >= NoIllegalTypes; 927 928 // Add all the dag nodes to the worklist. 929 WorkList.reserve(DAG.allnodes_size()); 930 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 931 E = DAG.allnodes_end(); I != E; ++I) 932 WorkList.push_back(I); 933 934 // Create a dummy node (which is not added to allnodes), that adds a reference 935 // to the root node, preventing it from being deleted, and tracking any 936 // changes of the root. 937 HandleSDNode Dummy(DAG.getRoot()); 938 939 // The root of the dag may dangle to deleted nodes until the dag combiner is 940 // done. Set it to null to avoid confusion. 941 DAG.setRoot(SDValue()); 942 943 // while the worklist isn't empty, inspect the node on the end of it and 944 // try and combine it. 945 while (!WorkList.empty()) { 946 SDNode *N = WorkList.back(); 947 WorkList.pop_back(); 948 949 // If N has no uses, it is dead. Make sure to revisit all N's operands once 950 // N is deleted from the DAG, since they too may now be dead or may have a 951 // reduced number of uses, allowing other xforms. 952 if (N->use_empty() && N != &Dummy) { 953 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 954 AddToWorkList(N->getOperand(i).getNode()); 955 956 DAG.DeleteNode(N); 957 continue; 958 } 959 960 SDValue RV = combine(N); 961 962 if (RV.getNode() == 0) 963 continue; 964 965 ++NodesCombined; 966 967 // If we get back the same node we passed in, rather than a new node or 968 // zero, we know that the node must have defined multiple values and 969 // CombineTo was used. Since CombineTo takes care of the worklist 970 // mechanics for us, we have no work to do in this case. 971 if (RV.getNode() == N) 972 continue; 973 974 assert(N->getOpcode() != ISD::DELETED_NODE && 975 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 976 "Node was deleted but visit returned new node!"); 977 978 DEBUG(dbgs() << "\nReplacing.3 "; 979 N->dump(&DAG); 980 dbgs() << "\nWith: "; 981 RV.getNode()->dump(&DAG); 982 dbgs() << '\n'); 983 WorkListRemover DeadNodes(*this); 984 if (N->getNumValues() == RV.getNode()->getNumValues()) 985 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 986 else { 987 assert(N->getValueType(0) == RV.getValueType() && 988 N->getNumValues() == 1 && "Type mismatch"); 989 SDValue OpV = RV; 990 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 991 } 992 993 // Push the new node and any users onto the worklist 994 AddToWorkList(RV.getNode()); 995 AddUsersToWorkList(RV.getNode()); 996 997 // Add any uses of the old node to the worklist in case this node is the 998 // last one that uses them. They may become dead after this node is 999 // deleted. 1000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1001 AddToWorkList(N->getOperand(i).getNode()); 1002 1003 // Finally, if the node is now dead, remove it from the graph. The node 1004 // may not be dead if the replacement process recursively simplified to 1005 // something else needing this node. 1006 if (N->use_empty()) { 1007 // Nodes can be reintroduced into the worklist. Make sure we do not 1008 // process a node that has been replaced. 1009 removeFromWorkList(N); 1010 1011 // Finally, since the node is now dead, remove it from the graph. 1012 DAG.DeleteNode(N); 1013 } 1014 } 1015 1016 // If the root changed (e.g. it was a dead load, update the root). 1017 DAG.setRoot(Dummy.getValue()); 1018} 1019 1020SDValue DAGCombiner::visit(SDNode *N) { 1021 switch (N->getOpcode()) { 1022 default: break; 1023 case ISD::TokenFactor: return visitTokenFactor(N); 1024 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1025 case ISD::ADD: return visitADD(N); 1026 case ISD::SUB: return visitSUB(N); 1027 case ISD::ADDC: return visitADDC(N); 1028 case ISD::ADDE: return visitADDE(N); 1029 case ISD::MUL: return visitMUL(N); 1030 case ISD::SDIV: return visitSDIV(N); 1031 case ISD::UDIV: return visitUDIV(N); 1032 case ISD::SREM: return visitSREM(N); 1033 case ISD::UREM: return visitUREM(N); 1034 case ISD::MULHU: return visitMULHU(N); 1035 case ISD::MULHS: return visitMULHS(N); 1036 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1037 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1038 case ISD::SDIVREM: return visitSDIVREM(N); 1039 case ISD::UDIVREM: return visitUDIVREM(N); 1040 case ISD::AND: return visitAND(N); 1041 case ISD::OR: return visitOR(N); 1042 case ISD::XOR: return visitXOR(N); 1043 case ISD::SHL: return visitSHL(N); 1044 case ISD::SRA: return visitSRA(N); 1045 case ISD::SRL: return visitSRL(N); 1046 case ISD::CTLZ: return visitCTLZ(N); 1047 case ISD::CTTZ: return visitCTTZ(N); 1048 case ISD::CTPOP: return visitCTPOP(N); 1049 case ISD::SELECT: return visitSELECT(N); 1050 case ISD::SELECT_CC: return visitSELECT_CC(N); 1051 case ISD::SETCC: return visitSETCC(N); 1052 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1053 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1054 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1055 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1056 case ISD::TRUNCATE: return visitTRUNCATE(N); 1057 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 1058 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1059 case ISD::FADD: return visitFADD(N); 1060 case ISD::FSUB: return visitFSUB(N); 1061 case ISD::FMUL: return visitFMUL(N); 1062 case ISD::FDIV: return visitFDIV(N); 1063 case ISD::FREM: return visitFREM(N); 1064 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1065 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1066 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1067 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1068 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1069 case ISD::FP_ROUND: return visitFP_ROUND(N); 1070 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1071 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1072 case ISD::FNEG: return visitFNEG(N); 1073 case ISD::FABS: return visitFABS(N); 1074 case ISD::BRCOND: return visitBRCOND(N); 1075 case ISD::BR_CC: return visitBR_CC(N); 1076 case ISD::LOAD: return visitLOAD(N); 1077 case ISD::STORE: return visitSTORE(N); 1078 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1079 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1080 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1081 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1082 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1083 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1084 } 1085 return SDValue(); 1086} 1087 1088SDValue DAGCombiner::combine(SDNode *N) { 1089 SDValue RV = visit(N); 1090 1091 // If nothing happened, try a target-specific DAG combine. 1092 if (RV.getNode() == 0) { 1093 assert(N->getOpcode() != ISD::DELETED_NODE && 1094 "Node was deleted but visit returned NULL!"); 1095 1096 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1097 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1098 1099 // Expose the DAG combiner to the target combiner impls. 1100 TargetLowering::DAGCombinerInfo 1101 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1102 1103 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1104 } 1105 } 1106 1107 // If nothing happened still, try promoting the operation. 1108 if (RV.getNode() == 0) { 1109 switch (N->getOpcode()) { 1110 default: break; 1111 case ISD::ADD: 1112 case ISD::SUB: 1113 case ISD::MUL: 1114 case ISD::AND: 1115 case ISD::OR: 1116 case ISD::XOR: 1117 RV = PromoteIntBinOp(SDValue(N, 0)); 1118 break; 1119 case ISD::SHL: 1120 case ISD::SRA: 1121 case ISD::SRL: 1122 RV = PromoteIntShiftOp(SDValue(N, 0)); 1123 break; 1124 case ISD::SIGN_EXTEND: 1125 case ISD::ZERO_EXTEND: 1126 case ISD::ANY_EXTEND: 1127 RV = PromoteExtend(SDValue(N, 0)); 1128 break; 1129 case ISD::LOAD: 1130 if (PromoteLoad(SDValue(N, 0))) 1131 RV = SDValue(N, 0); 1132 break; 1133 } 1134 } 1135 1136 // If N is a commutative binary node, try commuting it to enable more 1137 // sdisel CSE. 1138 if (RV.getNode() == 0 && 1139 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1140 N->getNumValues() == 1) { 1141 SDValue N0 = N->getOperand(0); 1142 SDValue N1 = N->getOperand(1); 1143 1144 // Constant operands are canonicalized to RHS. 1145 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1146 SDValue Ops[] = { N1, N0 }; 1147 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1148 Ops, 2); 1149 if (CSENode) 1150 return SDValue(CSENode, 0); 1151 } 1152 } 1153 1154 return RV; 1155} 1156 1157/// getInputChainForNode - Given a node, return its input chain if it has one, 1158/// otherwise return a null sd operand. 1159static SDValue getInputChainForNode(SDNode *N) { 1160 if (unsigned NumOps = N->getNumOperands()) { 1161 if (N->getOperand(0).getValueType() == MVT::Other) 1162 return N->getOperand(0); 1163 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1164 return N->getOperand(NumOps-1); 1165 for (unsigned i = 1; i < NumOps-1; ++i) 1166 if (N->getOperand(i).getValueType() == MVT::Other) 1167 return N->getOperand(i); 1168 } 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1173 // If N has two operands, where one has an input chain equal to the other, 1174 // the 'other' chain is redundant. 1175 if (N->getNumOperands() == 2) { 1176 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1177 return N->getOperand(0); 1178 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1179 return N->getOperand(1); 1180 } 1181 1182 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1183 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1184 SmallPtrSet<SDNode*, 16> SeenOps; 1185 bool Changed = false; // If we should replace this token factor. 1186 1187 // Start out with this token factor. 1188 TFs.push_back(N); 1189 1190 // Iterate through token factors. The TFs grows when new token factors are 1191 // encountered. 1192 for (unsigned i = 0; i < TFs.size(); ++i) { 1193 SDNode *TF = TFs[i]; 1194 1195 // Check each of the operands. 1196 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1197 SDValue Op = TF->getOperand(i); 1198 1199 switch (Op.getOpcode()) { 1200 case ISD::EntryToken: 1201 // Entry tokens don't need to be added to the list. They are 1202 // rededundant. 1203 Changed = true; 1204 break; 1205 1206 case ISD::TokenFactor: 1207 if (Op.hasOneUse() && 1208 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1209 // Queue up for processing. 1210 TFs.push_back(Op.getNode()); 1211 // Clean up in case the token factor is removed. 1212 AddToWorkList(Op.getNode()); 1213 Changed = true; 1214 break; 1215 } 1216 // Fall thru 1217 1218 default: 1219 // Only add if it isn't already in the list. 1220 if (SeenOps.insert(Op.getNode())) 1221 Ops.push_back(Op); 1222 else 1223 Changed = true; 1224 break; 1225 } 1226 } 1227 } 1228 1229 SDValue Result; 1230 1231 // If we've change things around then replace token factor. 1232 if (Changed) { 1233 if (Ops.empty()) { 1234 // The entry token is the only possible outcome. 1235 Result = DAG.getEntryNode(); 1236 } else { 1237 // New and improved token factor. 1238 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1239 MVT::Other, &Ops[0], Ops.size()); 1240 } 1241 1242 // Don't add users to work list. 1243 return CombineTo(N, Result, false); 1244 } 1245 1246 return Result; 1247} 1248 1249/// MERGE_VALUES can always be eliminated. 1250SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1251 WorkListRemover DeadNodes(*this); 1252 // Replacing results may cause a different MERGE_VALUES to suddenly 1253 // be CSE'd with N, and carry its uses with it. Iterate until no 1254 // uses remain, to ensure that the node can be safely deleted. 1255 do { 1256 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1257 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1258 &DeadNodes); 1259 } while (!N->use_empty()); 1260 removeFromWorkList(N); 1261 DAG.DeleteNode(N); 1262 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1263} 1264 1265static 1266SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1267 SelectionDAG &DAG) { 1268 EVT VT = N0.getValueType(); 1269 SDValue N00 = N0.getOperand(0); 1270 SDValue N01 = N0.getOperand(1); 1271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1272 1273 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1274 isa<ConstantSDNode>(N00.getOperand(1))) { 1275 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1276 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1277 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1278 N00.getOperand(0), N01), 1279 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1280 N00.getOperand(1), N01)); 1281 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1282 } 1283 1284 return SDValue(); 1285} 1286 1287SDValue DAGCombiner::visitADD(SDNode *N) { 1288 SDValue N0 = N->getOperand(0); 1289 SDValue N1 = N->getOperand(1); 1290 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1291 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1292 EVT VT = N0.getValueType(); 1293 1294 // fold vector ops 1295 if (VT.isVector()) { 1296 SDValue FoldedVOp = SimplifyVBinOp(N); 1297 if (FoldedVOp.getNode()) return FoldedVOp; 1298 } 1299 1300 // fold (add x, undef) -> undef 1301 if (N0.getOpcode() == ISD::UNDEF) 1302 return N0; 1303 if (N1.getOpcode() == ISD::UNDEF) 1304 return N1; 1305 // fold (add c1, c2) -> c1+c2 1306 if (N0C && N1C) 1307 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1308 // canonicalize constant to RHS 1309 if (N0C && !N1C) 1310 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1311 // fold (add x, 0) -> x 1312 if (N1C && N1C->isNullValue()) 1313 return N0; 1314 // fold (add Sym, c) -> Sym+c 1315 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1316 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1317 GA->getOpcode() == ISD::GlobalAddress) 1318 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1319 GA->getOffset() + 1320 (uint64_t)N1C->getSExtValue()); 1321 // fold ((c1-A)+c2) -> (c1+c2)-A 1322 if (N1C && N0.getOpcode() == ISD::SUB) 1323 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1325 DAG.getConstant(N1C->getAPIntValue()+ 1326 N0C->getAPIntValue(), VT), 1327 N0.getOperand(1)); 1328 // reassociate add 1329 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1330 if (RADD.getNode() != 0) 1331 return RADD; 1332 // fold ((0-A) + B) -> B-A 1333 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1334 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1335 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1336 // fold (A + (0-B)) -> A-B 1337 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1338 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1339 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1340 // fold (A+(B-A)) -> B 1341 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1342 return N1.getOperand(0); 1343 // fold ((B-A)+A) -> B 1344 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1345 return N0.getOperand(0); 1346 // fold (A+(B-(A+C))) to (B-C) 1347 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1348 N0 == N1.getOperand(1).getOperand(0)) 1349 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1350 N1.getOperand(1).getOperand(1)); 1351 // fold (A+(B-(C+A))) to (B-C) 1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1353 N0 == N1.getOperand(1).getOperand(1)) 1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1355 N1.getOperand(1).getOperand(0)); 1356 // fold (A+((B-A)+or-C)) to (B+or-C) 1357 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1358 N1.getOperand(0).getOpcode() == ISD::SUB && 1359 N0 == N1.getOperand(0).getOperand(1)) 1360 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1361 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1362 1363 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1364 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1365 SDValue N00 = N0.getOperand(0); 1366 SDValue N01 = N0.getOperand(1); 1367 SDValue N10 = N1.getOperand(0); 1368 SDValue N11 = N1.getOperand(1); 1369 1370 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1372 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1373 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1374 } 1375 1376 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1377 return SDValue(N, 0); 1378 1379 // fold (a+b) -> (a|b) iff a and b share no bits. 1380 if (VT.isInteger() && !VT.isVector()) { 1381 APInt LHSZero, LHSOne; 1382 APInt RHSZero, RHSOne; 1383 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1384 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1385 1386 if (LHSZero.getBoolValue()) { 1387 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1388 1389 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1390 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1391 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1392 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1393 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1394 } 1395 } 1396 1397 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1398 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1399 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1400 if (Result.getNode()) return Result; 1401 } 1402 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1403 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1404 if (Result.getNode()) return Result; 1405 } 1406 1407 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1408 if (N1.getOpcode() == ISD::SHL && 1409 N1.getOperand(0).getOpcode() == ISD::SUB) 1410 if (ConstantSDNode *C = 1411 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1412 if (C->getAPIntValue() == 0) 1413 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1414 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1415 N1.getOperand(0).getOperand(1), 1416 N1.getOperand(1))); 1417 if (N0.getOpcode() == ISD::SHL && 1418 N0.getOperand(0).getOpcode() == ISD::SUB) 1419 if (ConstantSDNode *C = 1420 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1421 if (C->getAPIntValue() == 0) 1422 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1423 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1424 N0.getOperand(0).getOperand(1), 1425 N0.getOperand(1))); 1426 1427 return SDValue(); 1428} 1429 1430SDValue DAGCombiner::visitADDC(SDNode *N) { 1431 SDValue N0 = N->getOperand(0); 1432 SDValue N1 = N->getOperand(1); 1433 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1434 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1435 EVT VT = N0.getValueType(); 1436 1437 // If the flag result is dead, turn this into an ADD. 1438 if (N->hasNUsesOfValue(0, 1)) 1439 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1440 DAG.getNode(ISD::CARRY_FALSE, 1441 N->getDebugLoc(), MVT::Flag)); 1442 1443 // canonicalize constant to RHS. 1444 if (N0C && !N1C) 1445 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1446 1447 // fold (addc x, 0) -> x + no carry out 1448 if (N1C && N1C->isNullValue()) 1449 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1450 N->getDebugLoc(), MVT::Flag)); 1451 1452 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1453 APInt LHSZero, LHSOne; 1454 APInt RHSZero, RHSOne; 1455 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1456 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1457 1458 if (LHSZero.getBoolValue()) { 1459 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1460 1461 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1462 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1463 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1464 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1465 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1466 DAG.getNode(ISD::CARRY_FALSE, 1467 N->getDebugLoc(), MVT::Flag)); 1468 } 1469 1470 return SDValue(); 1471} 1472 1473SDValue DAGCombiner::visitADDE(SDNode *N) { 1474 SDValue N0 = N->getOperand(0); 1475 SDValue N1 = N->getOperand(1); 1476 SDValue CarryIn = N->getOperand(2); 1477 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1478 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1479 1480 // canonicalize constant to RHS 1481 if (N0C && !N1C) 1482 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1483 N1, N0, CarryIn); 1484 1485 // fold (adde x, y, false) -> (addc x, y) 1486 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1487 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1488 1489 return SDValue(); 1490} 1491 1492SDValue DAGCombiner::visitSUB(SDNode *N) { 1493 SDValue N0 = N->getOperand(0); 1494 SDValue N1 = N->getOperand(1); 1495 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1496 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1497 EVT VT = N0.getValueType(); 1498 1499 // fold vector ops 1500 if (VT.isVector()) { 1501 SDValue FoldedVOp = SimplifyVBinOp(N); 1502 if (FoldedVOp.getNode()) return FoldedVOp; 1503 } 1504 1505 // fold (sub x, x) -> 0 1506 if (N0 == N1) 1507 return DAG.getConstant(0, N->getValueType(0)); 1508 // fold (sub c1, c2) -> c1-c2 1509 if (N0C && N1C) 1510 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1511 // fold (sub x, c) -> (add x, -c) 1512 if (N1C) 1513 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1514 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1515 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1516 if (N0C && N0C->isAllOnesValue()) 1517 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1518 // fold (A+B)-A -> B 1519 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1520 return N0.getOperand(1); 1521 // fold (A+B)-B -> A 1522 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1523 return N0.getOperand(0); 1524 // fold ((A+(B+or-C))-B) -> A+or-C 1525 if (N0.getOpcode() == ISD::ADD && 1526 (N0.getOperand(1).getOpcode() == ISD::SUB || 1527 N0.getOperand(1).getOpcode() == ISD::ADD) && 1528 N0.getOperand(1).getOperand(0) == N1) 1529 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1530 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1531 // fold ((A+(C+B))-B) -> A+C 1532 if (N0.getOpcode() == ISD::ADD && 1533 N0.getOperand(1).getOpcode() == ISD::ADD && 1534 N0.getOperand(1).getOperand(1) == N1) 1535 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1536 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1537 // fold ((A-(B-C))-C) -> A-B 1538 if (N0.getOpcode() == ISD::SUB && 1539 N0.getOperand(1).getOpcode() == ISD::SUB && 1540 N0.getOperand(1).getOperand(1) == N1) 1541 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1542 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1543 1544 // If either operand of a sub is undef, the result is undef 1545 if (N0.getOpcode() == ISD::UNDEF) 1546 return N0; 1547 if (N1.getOpcode() == ISD::UNDEF) 1548 return N1; 1549 1550 // If the relocation model supports it, consider symbol offsets. 1551 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1552 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1553 // fold (sub Sym, c) -> Sym-c 1554 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1555 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1556 GA->getOffset() - 1557 (uint64_t)N1C->getSExtValue()); 1558 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1559 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1560 if (GA->getGlobal() == GB->getGlobal()) 1561 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1562 VT); 1563 } 1564 1565 return SDValue(); 1566} 1567 1568SDValue DAGCombiner::visitMUL(SDNode *N) { 1569 SDValue N0 = N->getOperand(0); 1570 SDValue N1 = N->getOperand(1); 1571 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1572 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1573 EVT VT = N0.getValueType(); 1574 1575 // fold vector ops 1576 if (VT.isVector()) { 1577 SDValue FoldedVOp = SimplifyVBinOp(N); 1578 if (FoldedVOp.getNode()) return FoldedVOp; 1579 } 1580 1581 // fold (mul x, undef) -> 0 1582 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1583 return DAG.getConstant(0, VT); 1584 // fold (mul c1, c2) -> c1*c2 1585 if (N0C && N1C) 1586 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1587 // canonicalize constant to RHS 1588 if (N0C && !N1C) 1589 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1590 // fold (mul x, 0) -> 0 1591 if (N1C && N1C->isNullValue()) 1592 return N1; 1593 // fold (mul x, -1) -> 0-x 1594 if (N1C && N1C->isAllOnesValue()) 1595 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1596 DAG.getConstant(0, VT), N0); 1597 // fold (mul x, (1 << c)) -> x << c 1598 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1599 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1600 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1601 getShiftAmountTy())); 1602 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1603 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1604 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1605 // FIXME: If the input is something that is easily negated (e.g. a 1606 // single-use add), we should put the negate there. 1607 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1608 DAG.getConstant(0, VT), 1609 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1610 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1611 } 1612 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1613 if (N1C && N0.getOpcode() == ISD::SHL && 1614 isa<ConstantSDNode>(N0.getOperand(1))) { 1615 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1616 N1, N0.getOperand(1)); 1617 AddToWorkList(C3.getNode()); 1618 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1619 N0.getOperand(0), C3); 1620 } 1621 1622 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1623 // use. 1624 { 1625 SDValue Sh(0,0), Y(0,0); 1626 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1627 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1628 N0.getNode()->hasOneUse()) { 1629 Sh = N0; Y = N1; 1630 } else if (N1.getOpcode() == ISD::SHL && 1631 isa<ConstantSDNode>(N1.getOperand(1)) && 1632 N1.getNode()->hasOneUse()) { 1633 Sh = N1; Y = N0; 1634 } 1635 1636 if (Sh.getNode()) { 1637 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1638 Sh.getOperand(0), Y); 1639 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1640 Mul, Sh.getOperand(1)); 1641 } 1642 } 1643 1644 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1645 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1646 isa<ConstantSDNode>(N0.getOperand(1))) 1647 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1648 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1649 N0.getOperand(0), N1), 1650 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1651 N0.getOperand(1), N1)); 1652 1653 // reassociate mul 1654 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1655 if (RMUL.getNode() != 0) 1656 return RMUL; 1657 1658 return SDValue(); 1659} 1660 1661SDValue DAGCombiner::visitSDIV(SDNode *N) { 1662 SDValue N0 = N->getOperand(0); 1663 SDValue N1 = N->getOperand(1); 1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1666 EVT VT = N->getValueType(0); 1667 1668 // fold vector ops 1669 if (VT.isVector()) { 1670 SDValue FoldedVOp = SimplifyVBinOp(N); 1671 if (FoldedVOp.getNode()) return FoldedVOp; 1672 } 1673 1674 // fold (sdiv c1, c2) -> c1/c2 1675 if (N0C && N1C && !N1C->isNullValue()) 1676 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1677 // fold (sdiv X, 1) -> X 1678 if (N1C && N1C->getSExtValue() == 1LL) 1679 return N0; 1680 // fold (sdiv X, -1) -> 0-X 1681 if (N1C && N1C->isAllOnesValue()) 1682 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1683 DAG.getConstant(0, VT), N0); 1684 // If we know the sign bits of both operands are zero, strength reduce to a 1685 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1686 if (!VT.isVector()) { 1687 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1688 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1689 N0, N1); 1690 } 1691 // fold (sdiv X, pow2) -> simple ops after legalize 1692 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1693 (isPowerOf2_64(N1C->getSExtValue()) || 1694 isPowerOf2_64(-N1C->getSExtValue()))) { 1695 // If dividing by powers of two is cheap, then don't perform the following 1696 // fold. 1697 if (TLI.isPow2DivCheap()) 1698 return SDValue(); 1699 1700 int64_t pow2 = N1C->getSExtValue(); 1701 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1702 unsigned lg2 = Log2_64(abs2); 1703 1704 // Splat the sign bit into the register 1705 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1706 DAG.getConstant(VT.getSizeInBits()-1, 1707 getShiftAmountTy())); 1708 AddToWorkList(SGN.getNode()); 1709 1710 // Add (N0 < 0) ? abs2 - 1 : 0; 1711 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1712 DAG.getConstant(VT.getSizeInBits() - lg2, 1713 getShiftAmountTy())); 1714 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1715 AddToWorkList(SRL.getNode()); 1716 AddToWorkList(ADD.getNode()); // Divide by pow2 1717 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1718 DAG.getConstant(lg2, getShiftAmountTy())); 1719 1720 // If we're dividing by a positive value, we're done. Otherwise, we must 1721 // negate the result. 1722 if (pow2 > 0) 1723 return SRA; 1724 1725 AddToWorkList(SRA.getNode()); 1726 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1727 DAG.getConstant(0, VT), SRA); 1728 } 1729 1730 // if integer divide is expensive and we satisfy the requirements, emit an 1731 // alternate sequence. 1732 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1733 !TLI.isIntDivCheap()) { 1734 SDValue Op = BuildSDIV(N); 1735 if (Op.getNode()) return Op; 1736 } 1737 1738 // undef / X -> 0 1739 if (N0.getOpcode() == ISD::UNDEF) 1740 return DAG.getConstant(0, VT); 1741 // X / undef -> undef 1742 if (N1.getOpcode() == ISD::UNDEF) 1743 return N1; 1744 1745 return SDValue(); 1746} 1747 1748SDValue DAGCombiner::visitUDIV(SDNode *N) { 1749 SDValue N0 = N->getOperand(0); 1750 SDValue N1 = N->getOperand(1); 1751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1752 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1753 EVT VT = N->getValueType(0); 1754 1755 // fold vector ops 1756 if (VT.isVector()) { 1757 SDValue FoldedVOp = SimplifyVBinOp(N); 1758 if (FoldedVOp.getNode()) return FoldedVOp; 1759 } 1760 1761 // fold (udiv c1, c2) -> c1/c2 1762 if (N0C && N1C && !N1C->isNullValue()) 1763 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1764 // fold (udiv x, (1 << c)) -> x >>u c 1765 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1766 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1767 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1768 getShiftAmountTy())); 1769 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1770 if (N1.getOpcode() == ISD::SHL) { 1771 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1772 if (SHC->getAPIntValue().isPowerOf2()) { 1773 EVT ADDVT = N1.getOperand(1).getValueType(); 1774 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1775 N1.getOperand(1), 1776 DAG.getConstant(SHC->getAPIntValue() 1777 .logBase2(), 1778 ADDVT)); 1779 AddToWorkList(Add.getNode()); 1780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1781 } 1782 } 1783 } 1784 // fold (udiv x, c) -> alternate 1785 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1786 SDValue Op = BuildUDIV(N); 1787 if (Op.getNode()) return Op; 1788 } 1789 1790 // undef / X -> 0 1791 if (N0.getOpcode() == ISD::UNDEF) 1792 return DAG.getConstant(0, VT); 1793 // X / undef -> undef 1794 if (N1.getOpcode() == ISD::UNDEF) 1795 return N1; 1796 1797 return SDValue(); 1798} 1799 1800SDValue DAGCombiner::visitSREM(SDNode *N) { 1801 SDValue N0 = N->getOperand(0); 1802 SDValue N1 = N->getOperand(1); 1803 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1804 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1805 EVT VT = N->getValueType(0); 1806 1807 // fold (srem c1, c2) -> c1%c2 1808 if (N0C && N1C && !N1C->isNullValue()) 1809 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1810 // If we know the sign bits of both operands are zero, strength reduce to a 1811 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1812 if (!VT.isVector()) { 1813 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1814 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1815 } 1816 1817 // If X/C can be simplified by the division-by-constant logic, lower 1818 // X%C to the equivalent of X-X/C*C. 1819 if (N1C && !N1C->isNullValue()) { 1820 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1821 AddToWorkList(Div.getNode()); 1822 SDValue OptimizedDiv = combine(Div.getNode()); 1823 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1824 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1825 OptimizedDiv, N1); 1826 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1827 AddToWorkList(Mul.getNode()); 1828 return Sub; 1829 } 1830 } 1831 1832 // undef % X -> 0 1833 if (N0.getOpcode() == ISD::UNDEF) 1834 return DAG.getConstant(0, VT); 1835 // X % undef -> undef 1836 if (N1.getOpcode() == ISD::UNDEF) 1837 return N1; 1838 1839 return SDValue(); 1840} 1841 1842SDValue DAGCombiner::visitUREM(SDNode *N) { 1843 SDValue N0 = N->getOperand(0); 1844 SDValue N1 = N->getOperand(1); 1845 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1847 EVT VT = N->getValueType(0); 1848 1849 // fold (urem c1, c2) -> c1%c2 1850 if (N0C && N1C && !N1C->isNullValue()) 1851 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1852 // fold (urem x, pow2) -> (and x, pow2-1) 1853 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1854 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1855 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1856 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1857 if (N1.getOpcode() == ISD::SHL) { 1858 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1859 if (SHC->getAPIntValue().isPowerOf2()) { 1860 SDValue Add = 1861 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1862 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1863 VT)); 1864 AddToWorkList(Add.getNode()); 1865 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1866 } 1867 } 1868 } 1869 1870 // If X/C can be simplified by the division-by-constant logic, lower 1871 // X%C to the equivalent of X-X/C*C. 1872 if (N1C && !N1C->isNullValue()) { 1873 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1874 AddToWorkList(Div.getNode()); 1875 SDValue OptimizedDiv = combine(Div.getNode()); 1876 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1877 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1878 OptimizedDiv, N1); 1879 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1880 AddToWorkList(Mul.getNode()); 1881 return Sub; 1882 } 1883 } 1884 1885 // undef % X -> 0 1886 if (N0.getOpcode() == ISD::UNDEF) 1887 return DAG.getConstant(0, VT); 1888 // X % undef -> undef 1889 if (N1.getOpcode() == ISD::UNDEF) 1890 return N1; 1891 1892 return SDValue(); 1893} 1894 1895SDValue DAGCombiner::visitMULHS(SDNode *N) { 1896 SDValue N0 = N->getOperand(0); 1897 SDValue N1 = N->getOperand(1); 1898 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1899 EVT VT = N->getValueType(0); 1900 1901 // fold (mulhs x, 0) -> 0 1902 if (N1C && N1C->isNullValue()) 1903 return N1; 1904 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1905 if (N1C && N1C->getAPIntValue() == 1) 1906 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1907 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1908 getShiftAmountTy())); 1909 // fold (mulhs x, undef) -> 0 1910 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1911 return DAG.getConstant(0, VT); 1912 1913 return SDValue(); 1914} 1915 1916SDValue DAGCombiner::visitMULHU(SDNode *N) { 1917 SDValue N0 = N->getOperand(0); 1918 SDValue N1 = N->getOperand(1); 1919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1920 EVT VT = N->getValueType(0); 1921 1922 // fold (mulhu x, 0) -> 0 1923 if (N1C && N1C->isNullValue()) 1924 return N1; 1925 // fold (mulhu x, 1) -> 0 1926 if (N1C && N1C->getAPIntValue() == 1) 1927 return DAG.getConstant(0, N0.getValueType()); 1928 // fold (mulhu x, undef) -> 0 1929 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1930 return DAG.getConstant(0, VT); 1931 1932 return SDValue(); 1933} 1934 1935/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1936/// compute two values. LoOp and HiOp give the opcodes for the two computations 1937/// that are being performed. Return true if a simplification was made. 1938/// 1939SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1940 unsigned HiOp) { 1941 // If the high half is not needed, just compute the low half. 1942 bool HiExists = N->hasAnyUseOfValue(1); 1943 if (!HiExists && 1944 (!LegalOperations || 1945 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1946 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1947 N->op_begin(), N->getNumOperands()); 1948 return CombineTo(N, Res, Res); 1949 } 1950 1951 // If the low half is not needed, just compute the high half. 1952 bool LoExists = N->hasAnyUseOfValue(0); 1953 if (!LoExists && 1954 (!LegalOperations || 1955 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1956 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1957 N->op_begin(), N->getNumOperands()); 1958 return CombineTo(N, Res, Res); 1959 } 1960 1961 // If both halves are used, return as it is. 1962 if (LoExists && HiExists) 1963 return SDValue(); 1964 1965 // If the two computed results can be simplified separately, separate them. 1966 if (LoExists) { 1967 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1968 N->op_begin(), N->getNumOperands()); 1969 AddToWorkList(Lo.getNode()); 1970 SDValue LoOpt = combine(Lo.getNode()); 1971 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1972 (!LegalOperations || 1973 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1974 return CombineTo(N, LoOpt, LoOpt); 1975 } 1976 1977 if (HiExists) { 1978 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1979 N->op_begin(), N->getNumOperands()); 1980 AddToWorkList(Hi.getNode()); 1981 SDValue HiOpt = combine(Hi.getNode()); 1982 if (HiOpt.getNode() && HiOpt != Hi && 1983 (!LegalOperations || 1984 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1985 return CombineTo(N, HiOpt, HiOpt); 1986 } 1987 1988 return SDValue(); 1989} 1990 1991SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1992 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1993 if (Res.getNode()) return Res; 1994 1995 return SDValue(); 1996} 1997 1998SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1999 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2000 if (Res.getNode()) return Res; 2001 2002 return SDValue(); 2003} 2004 2005SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2006 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2007 if (Res.getNode()) return Res; 2008 2009 return SDValue(); 2010} 2011 2012SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2013 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2014 if (Res.getNode()) return Res; 2015 2016 return SDValue(); 2017} 2018 2019/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2020/// two operands of the same opcode, try to simplify it. 2021SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2022 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2023 EVT VT = N0.getValueType(); 2024 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2025 2026 // Bail early if none of these transforms apply. 2027 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2028 2029 // For each of OP in AND/OR/XOR: 2030 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2031 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2032 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2033 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2034 // 2035 // do not sink logical op inside of a vector extend, since it may combine 2036 // into a vsetcc. 2037 EVT Op0VT = N0.getOperand(0).getValueType(); 2038 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2039 N0.getOpcode() == ISD::SIGN_EXTEND || 2040 // Avoid infinite looping with PromoteIntBinOp. 2041 (N0.getOpcode() == ISD::ANY_EXTEND && 2042 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2043 (N0.getOpcode() == ISD::TRUNCATE && 2044 (!TLI.isZExtFree(VT, Op0VT) || 2045 !TLI.isTruncateFree(Op0VT, VT)) && 2046 TLI.isTypeLegal(Op0VT))) && 2047 !VT.isVector() && 2048 Op0VT == N1.getOperand(0).getValueType() && 2049 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2050 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2051 N0.getOperand(0).getValueType(), 2052 N0.getOperand(0), N1.getOperand(0)); 2053 AddToWorkList(ORNode.getNode()); 2054 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2055 } 2056 2057 // For each of OP in SHL/SRL/SRA/AND... 2058 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2059 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2060 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2061 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2062 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2063 N0.getOperand(1) == N1.getOperand(1)) { 2064 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2065 N0.getOperand(0).getValueType(), 2066 N0.getOperand(0), N1.getOperand(0)); 2067 AddToWorkList(ORNode.getNode()); 2068 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2069 ORNode, N0.getOperand(1)); 2070 } 2071 2072 return SDValue(); 2073} 2074 2075SDValue DAGCombiner::visitAND(SDNode *N) { 2076 SDValue N0 = N->getOperand(0); 2077 SDValue N1 = N->getOperand(1); 2078 SDValue LL, LR, RL, RR, CC0, CC1; 2079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2081 EVT VT = N1.getValueType(); 2082 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2083 2084 // fold vector ops 2085 if (VT.isVector()) { 2086 SDValue FoldedVOp = SimplifyVBinOp(N); 2087 if (FoldedVOp.getNode()) return FoldedVOp; 2088 } 2089 2090 // fold (and x, undef) -> 0 2091 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2092 return DAG.getConstant(0, VT); 2093 // fold (and c1, c2) -> c1&c2 2094 if (N0C && N1C) 2095 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2096 // canonicalize constant to RHS 2097 if (N0C && !N1C) 2098 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2099 // fold (and x, -1) -> x 2100 if (N1C && N1C->isAllOnesValue()) 2101 return N0; 2102 // if (and x, c) is known to be zero, return 0 2103 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2104 APInt::getAllOnesValue(BitWidth))) 2105 return DAG.getConstant(0, VT); 2106 // reassociate and 2107 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2108 if (RAND.getNode() != 0) 2109 return RAND; 2110 // fold (and (or x, C), D) -> D if (C & D) == D 2111 if (N1C && N0.getOpcode() == ISD::OR) 2112 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2113 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2114 return N1; 2115 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2116 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2117 SDValue N0Op0 = N0.getOperand(0); 2118 APInt Mask = ~N1C->getAPIntValue(); 2119 Mask.trunc(N0Op0.getValueSizeInBits()); 2120 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2121 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2122 N0.getValueType(), N0Op0); 2123 2124 // Replace uses of the AND with uses of the Zero extend node. 2125 CombineTo(N, Zext); 2126 2127 // We actually want to replace all uses of the any_extend with the 2128 // zero_extend, to avoid duplicating things. This will later cause this 2129 // AND to be folded. 2130 CombineTo(N0.getNode(), Zext); 2131 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2132 } 2133 } 2134 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2135 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2136 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2137 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2138 2139 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2140 LL.getValueType().isInteger()) { 2141 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2142 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2143 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2144 LR.getValueType(), LL, RL); 2145 AddToWorkList(ORNode.getNode()); 2146 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2147 } 2148 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2149 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2150 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2151 LR.getValueType(), LL, RL); 2152 AddToWorkList(ANDNode.getNode()); 2153 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2154 } 2155 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2156 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2157 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2158 LR.getValueType(), LL, RL); 2159 AddToWorkList(ORNode.getNode()); 2160 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2161 } 2162 } 2163 // canonicalize equivalent to ll == rl 2164 if (LL == RR && LR == RL) { 2165 Op1 = ISD::getSetCCSwappedOperands(Op1); 2166 std::swap(RL, RR); 2167 } 2168 if (LL == RL && LR == RR) { 2169 bool isInteger = LL.getValueType().isInteger(); 2170 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2171 if (Result != ISD::SETCC_INVALID && 2172 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2173 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2174 LL, LR, Result); 2175 } 2176 } 2177 2178 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2179 if (N0.getOpcode() == N1.getOpcode()) { 2180 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2181 if (Tmp.getNode()) return Tmp; 2182 } 2183 2184 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2185 // fold (and (sra)) -> (and (srl)) when possible. 2186 if (!VT.isVector() && 2187 SimplifyDemandedBits(SDValue(N, 0))) 2188 return SDValue(N, 0); 2189 2190 // fold (zext_inreg (extload x)) -> (zextload x) 2191 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2192 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2193 EVT MemVT = LN0->getMemoryVT(); 2194 // If we zero all the possible extended bits, then we can turn this into 2195 // a zextload if we are running before legalize or the operation is legal. 2196 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2197 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2198 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2199 ((!LegalOperations && !LN0->isVolatile()) || 2200 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2201 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2202 LN0->getChain(), LN0->getBasePtr(), 2203 LN0->getSrcValue(), 2204 LN0->getSrcValueOffset(), MemVT, 2205 LN0->isVolatile(), LN0->isNonTemporal(), 2206 LN0->getAlignment()); 2207 AddToWorkList(N); 2208 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2209 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2210 } 2211 } 2212 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2213 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2214 N0.hasOneUse()) { 2215 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2216 EVT MemVT = LN0->getMemoryVT(); 2217 // If we zero all the possible extended bits, then we can turn this into 2218 // a zextload if we are running before legalize or the operation is legal. 2219 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2220 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2221 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2222 ((!LegalOperations && !LN0->isVolatile()) || 2223 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2224 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2225 LN0->getChain(), 2226 LN0->getBasePtr(), LN0->getSrcValue(), 2227 LN0->getSrcValueOffset(), MemVT, 2228 LN0->isVolatile(), LN0->isNonTemporal(), 2229 LN0->getAlignment()); 2230 AddToWorkList(N); 2231 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2232 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2233 } 2234 } 2235 2236 // fold (and (load x), 255) -> (zextload x, i8) 2237 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2238 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2239 if (N1C && (N0.getOpcode() == ISD::LOAD || 2240 (N0.getOpcode() == ISD::ANY_EXTEND && 2241 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2242 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2243 LoadSDNode *LN0 = HasAnyExt 2244 ? cast<LoadSDNode>(N0.getOperand(0)) 2245 : cast<LoadSDNode>(N0); 2246 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2247 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2248 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2249 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2250 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2251 EVT LoadedVT = LN0->getMemoryVT(); 2252 2253 if (ExtVT == LoadedVT && 2254 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2255 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2256 2257 SDValue NewLoad = 2258 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2259 LN0->getChain(), LN0->getBasePtr(), 2260 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2261 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2262 LN0->getAlignment()); 2263 AddToWorkList(N); 2264 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2265 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2266 } 2267 2268 // Do not change the width of a volatile load. 2269 // Do not generate loads of non-round integer types since these can 2270 // be expensive (and would be wrong if the type is not byte sized). 2271 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2272 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2273 EVT PtrType = LN0->getOperand(1).getValueType(); 2274 2275 unsigned Alignment = LN0->getAlignment(); 2276 SDValue NewPtr = LN0->getBasePtr(); 2277 2278 // For big endian targets, we need to add an offset to the pointer 2279 // to load the correct bytes. For little endian systems, we merely 2280 // need to read fewer bytes from the same pointer. 2281 if (TLI.isBigEndian()) { 2282 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2283 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2284 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2285 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2286 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2287 Alignment = MinAlign(Alignment, PtrOff); 2288 } 2289 2290 AddToWorkList(NewPtr.getNode()); 2291 2292 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2293 SDValue Load = 2294 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2295 LN0->getChain(), NewPtr, 2296 LN0->getSrcValue(), LN0->getSrcValueOffset(), 2297 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2298 Alignment); 2299 AddToWorkList(N); 2300 CombineTo(LN0, Load, Load.getValue(1)); 2301 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2302 } 2303 } 2304 } 2305 } 2306 2307 return SDValue(); 2308} 2309 2310SDValue DAGCombiner::visitOR(SDNode *N) { 2311 SDValue N0 = N->getOperand(0); 2312 SDValue N1 = N->getOperand(1); 2313 SDValue LL, LR, RL, RR, CC0, CC1; 2314 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2315 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2316 EVT VT = N1.getValueType(); 2317 2318 // fold vector ops 2319 if (VT.isVector()) { 2320 SDValue FoldedVOp = SimplifyVBinOp(N); 2321 if (FoldedVOp.getNode()) return FoldedVOp; 2322 } 2323 2324 // fold (or x, undef) -> -1 2325 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2326 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2327 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2328 } 2329 // fold (or c1, c2) -> c1|c2 2330 if (N0C && N1C) 2331 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2332 // canonicalize constant to RHS 2333 if (N0C && !N1C) 2334 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2335 // fold (or x, 0) -> x 2336 if (N1C && N1C->isNullValue()) 2337 return N0; 2338 // fold (or x, -1) -> -1 2339 if (N1C && N1C->isAllOnesValue()) 2340 return N1; 2341 // fold (or x, c) -> c iff (x & ~c) == 0 2342 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2343 return N1; 2344 // reassociate or 2345 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2346 if (ROR.getNode() != 0) 2347 return ROR; 2348 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2349 // iff (c1 & c2) == 0. 2350 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2351 isa<ConstantSDNode>(N0.getOperand(1))) { 2352 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2353 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2354 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2355 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2356 N0.getOperand(0), N1), 2357 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2358 } 2359 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2360 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2361 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2362 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2363 2364 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2365 LL.getValueType().isInteger()) { 2366 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2367 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2368 if (cast<ConstantSDNode>(LR)->isNullValue() && 2369 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2370 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2371 LR.getValueType(), LL, RL); 2372 AddToWorkList(ORNode.getNode()); 2373 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2374 } 2375 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2376 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2377 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2378 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2379 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2380 LR.getValueType(), LL, RL); 2381 AddToWorkList(ANDNode.getNode()); 2382 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2383 } 2384 } 2385 // canonicalize equivalent to ll == rl 2386 if (LL == RR && LR == RL) { 2387 Op1 = ISD::getSetCCSwappedOperands(Op1); 2388 std::swap(RL, RR); 2389 } 2390 if (LL == RL && LR == RR) { 2391 bool isInteger = LL.getValueType().isInteger(); 2392 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2393 if (Result != ISD::SETCC_INVALID && 2394 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2395 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2396 LL, LR, Result); 2397 } 2398 } 2399 2400 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2401 if (N0.getOpcode() == N1.getOpcode()) { 2402 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2403 if (Tmp.getNode()) return Tmp; 2404 } 2405 2406 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2407 if (N0.getOpcode() == ISD::AND && 2408 N1.getOpcode() == ISD::AND && 2409 N0.getOperand(1).getOpcode() == ISD::Constant && 2410 N1.getOperand(1).getOpcode() == ISD::Constant && 2411 // Don't increase # computations. 2412 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2413 // We can only do this xform if we know that bits from X that are set in C2 2414 // but not in C1 are already zero. Likewise for Y. 2415 const APInt &LHSMask = 2416 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2417 const APInt &RHSMask = 2418 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2419 2420 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2421 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2422 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2423 N0.getOperand(0), N1.getOperand(0)); 2424 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2425 DAG.getConstant(LHSMask | RHSMask, VT)); 2426 } 2427 } 2428 2429 // See if this is some rotate idiom. 2430 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2431 return SDValue(Rot, 0); 2432 2433 // Simplify the operands using demanded-bits information. 2434 if (!VT.isVector() && 2435 SimplifyDemandedBits(SDValue(N, 0))) 2436 return SDValue(N, 0); 2437 2438 return SDValue(); 2439} 2440 2441/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2442static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2443 if (Op.getOpcode() == ISD::AND) { 2444 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2445 Mask = Op.getOperand(1); 2446 Op = Op.getOperand(0); 2447 } else { 2448 return false; 2449 } 2450 } 2451 2452 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2453 Shift = Op; 2454 return true; 2455 } 2456 2457 return false; 2458} 2459 2460// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2461// idioms for rotate, and if the target supports rotation instructions, generate 2462// a rot[lr]. 2463SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2464 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2465 EVT VT = LHS.getValueType(); 2466 if (!TLI.isTypeLegal(VT)) return 0; 2467 2468 // The target must have at least one rotate flavor. 2469 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2470 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2471 if (!HasROTL && !HasROTR) return 0; 2472 2473 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2474 SDValue LHSShift; // The shift. 2475 SDValue LHSMask; // AND value if any. 2476 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2477 return 0; // Not part of a rotate. 2478 2479 SDValue RHSShift; // The shift. 2480 SDValue RHSMask; // AND value if any. 2481 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2482 return 0; // Not part of a rotate. 2483 2484 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2485 return 0; // Not shifting the same value. 2486 2487 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2488 return 0; // Shifts must disagree. 2489 2490 // Canonicalize shl to left side in a shl/srl pair. 2491 if (RHSShift.getOpcode() == ISD::SHL) { 2492 std::swap(LHS, RHS); 2493 std::swap(LHSShift, RHSShift); 2494 std::swap(LHSMask , RHSMask ); 2495 } 2496 2497 unsigned OpSizeInBits = VT.getSizeInBits(); 2498 SDValue LHSShiftArg = LHSShift.getOperand(0); 2499 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2500 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2501 2502 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2503 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2504 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2505 RHSShiftAmt.getOpcode() == ISD::Constant) { 2506 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2507 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2508 if ((LShVal + RShVal) != OpSizeInBits) 2509 return 0; 2510 2511 SDValue Rot; 2512 if (HasROTL) 2513 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2514 else 2515 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2516 2517 // If there is an AND of either shifted operand, apply it to the result. 2518 if (LHSMask.getNode() || RHSMask.getNode()) { 2519 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2520 2521 if (LHSMask.getNode()) { 2522 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2523 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2524 } 2525 if (RHSMask.getNode()) { 2526 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2527 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2528 } 2529 2530 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2531 } 2532 2533 return Rot.getNode(); 2534 } 2535 2536 // If there is a mask here, and we have a variable shift, we can't be sure 2537 // that we're masking out the right stuff. 2538 if (LHSMask.getNode() || RHSMask.getNode()) 2539 return 0; 2540 2541 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2542 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2543 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2544 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2545 if (ConstantSDNode *SUBC = 2546 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2547 if (SUBC->getAPIntValue() == OpSizeInBits) { 2548 if (HasROTL) 2549 return DAG.getNode(ISD::ROTL, DL, VT, 2550 LHSShiftArg, LHSShiftAmt).getNode(); 2551 else 2552 return DAG.getNode(ISD::ROTR, DL, VT, 2553 LHSShiftArg, RHSShiftAmt).getNode(); 2554 } 2555 } 2556 } 2557 2558 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2559 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2560 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2561 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2562 if (ConstantSDNode *SUBC = 2563 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2564 if (SUBC->getAPIntValue() == OpSizeInBits) { 2565 if (HasROTR) 2566 return DAG.getNode(ISD::ROTR, DL, VT, 2567 LHSShiftArg, RHSShiftAmt).getNode(); 2568 else 2569 return DAG.getNode(ISD::ROTL, DL, VT, 2570 LHSShiftArg, LHSShiftAmt).getNode(); 2571 } 2572 } 2573 } 2574 2575 // Look for sign/zext/any-extended or truncate cases: 2576 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2577 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2578 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2579 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2580 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2581 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2582 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2583 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2584 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2585 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2586 if (RExtOp0.getOpcode() == ISD::SUB && 2587 RExtOp0.getOperand(1) == LExtOp0) { 2588 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2589 // (rotl x, y) 2590 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2591 // (rotr x, (sub 32, y)) 2592 if (ConstantSDNode *SUBC = 2593 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2594 if (SUBC->getAPIntValue() == OpSizeInBits) { 2595 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2596 LHSShiftArg, 2597 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2598 } 2599 } 2600 } else if (LExtOp0.getOpcode() == ISD::SUB && 2601 RExtOp0 == LExtOp0.getOperand(1)) { 2602 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2603 // (rotr x, y) 2604 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2605 // (rotl x, (sub 32, y)) 2606 if (ConstantSDNode *SUBC = 2607 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2608 if (SUBC->getAPIntValue() == OpSizeInBits) { 2609 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2610 LHSShiftArg, 2611 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2612 } 2613 } 2614 } 2615 } 2616 2617 return 0; 2618} 2619 2620SDValue DAGCombiner::visitXOR(SDNode *N) { 2621 SDValue N0 = N->getOperand(0); 2622 SDValue N1 = N->getOperand(1); 2623 SDValue LHS, RHS, CC; 2624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2626 EVT VT = N0.getValueType(); 2627 2628 // fold vector ops 2629 if (VT.isVector()) { 2630 SDValue FoldedVOp = SimplifyVBinOp(N); 2631 if (FoldedVOp.getNode()) return FoldedVOp; 2632 } 2633 2634 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2635 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2636 return DAG.getConstant(0, VT); 2637 // fold (xor x, undef) -> undef 2638 if (N0.getOpcode() == ISD::UNDEF) 2639 return N0; 2640 if (N1.getOpcode() == ISD::UNDEF) 2641 return N1; 2642 // fold (xor c1, c2) -> c1^c2 2643 if (N0C && N1C) 2644 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2645 // canonicalize constant to RHS 2646 if (N0C && !N1C) 2647 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2648 // fold (xor x, 0) -> x 2649 if (N1C && N1C->isNullValue()) 2650 return N0; 2651 // reassociate xor 2652 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2653 if (RXOR.getNode() != 0) 2654 return RXOR; 2655 2656 // fold !(x cc y) -> (x !cc y) 2657 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2658 bool isInt = LHS.getValueType().isInteger(); 2659 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2660 isInt); 2661 2662 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2663 switch (N0.getOpcode()) { 2664 default: 2665 llvm_unreachable("Unhandled SetCC Equivalent!"); 2666 case ISD::SETCC: 2667 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2668 case ISD::SELECT_CC: 2669 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2670 N0.getOperand(3), NotCC); 2671 } 2672 } 2673 } 2674 2675 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2676 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2677 N0.getNode()->hasOneUse() && 2678 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2679 SDValue V = N0.getOperand(0); 2680 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2681 DAG.getConstant(1, V.getValueType())); 2682 AddToWorkList(V.getNode()); 2683 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2684 } 2685 2686 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2687 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2688 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2689 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2690 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2691 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2692 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2693 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2694 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2695 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2696 } 2697 } 2698 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2699 if (N1C && N1C->isAllOnesValue() && 2700 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2701 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2702 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2703 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2704 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2705 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2706 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2707 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2708 } 2709 } 2710 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2711 if (N1C && N0.getOpcode() == ISD::XOR) { 2712 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2713 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2714 if (N00C) 2715 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2716 DAG.getConstant(N1C->getAPIntValue() ^ 2717 N00C->getAPIntValue(), VT)); 2718 if (N01C) 2719 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2720 DAG.getConstant(N1C->getAPIntValue() ^ 2721 N01C->getAPIntValue(), VT)); 2722 } 2723 // fold (xor x, x) -> 0 2724 if (N0 == N1) { 2725 if (!VT.isVector()) { 2726 return DAG.getConstant(0, VT); 2727 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2728 // Produce a vector of zeros. 2729 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2730 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2731 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2732 &Ops[0], Ops.size()); 2733 } 2734 } 2735 2736 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2737 if (N0.getOpcode() == N1.getOpcode()) { 2738 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2739 if (Tmp.getNode()) return Tmp; 2740 } 2741 2742 // Simplify the expression using non-local knowledge. 2743 if (!VT.isVector() && 2744 SimplifyDemandedBits(SDValue(N, 0))) 2745 return SDValue(N, 0); 2746 2747 return SDValue(); 2748} 2749 2750/// visitShiftByConstant - Handle transforms common to the three shifts, when 2751/// the shift amount is a constant. 2752SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2753 SDNode *LHS = N->getOperand(0).getNode(); 2754 if (!LHS->hasOneUse()) return SDValue(); 2755 2756 // We want to pull some binops through shifts, so that we have (and (shift)) 2757 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2758 // thing happens with address calculations, so it's important to canonicalize 2759 // it. 2760 bool HighBitSet = false; // Can we transform this if the high bit is set? 2761 2762 switch (LHS->getOpcode()) { 2763 default: return SDValue(); 2764 case ISD::OR: 2765 case ISD::XOR: 2766 HighBitSet = false; // We can only transform sra if the high bit is clear. 2767 break; 2768 case ISD::AND: 2769 HighBitSet = true; // We can only transform sra if the high bit is set. 2770 break; 2771 case ISD::ADD: 2772 if (N->getOpcode() != ISD::SHL) 2773 return SDValue(); // only shl(add) not sr[al](add). 2774 HighBitSet = false; // We can only transform sra if the high bit is clear. 2775 break; 2776 } 2777 2778 // We require the RHS of the binop to be a constant as well. 2779 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2780 if (!BinOpCst) return SDValue(); 2781 2782 // FIXME: disable this unless the input to the binop is a shift by a constant. 2783 // If it is not a shift, it pessimizes some common cases like: 2784 // 2785 // void foo(int *X, int i) { X[i & 1235] = 1; } 2786 // int bar(int *X, int i) { return X[i & 255]; } 2787 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2788 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2789 BinOpLHSVal->getOpcode() != ISD::SRA && 2790 BinOpLHSVal->getOpcode() != ISD::SRL) || 2791 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2792 return SDValue(); 2793 2794 EVT VT = N->getValueType(0); 2795 2796 // If this is a signed shift right, and the high bit is modified by the 2797 // logical operation, do not perform the transformation. The highBitSet 2798 // boolean indicates the value of the high bit of the constant which would 2799 // cause it to be modified for this operation. 2800 if (N->getOpcode() == ISD::SRA) { 2801 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2802 if (BinOpRHSSignSet != HighBitSet) 2803 return SDValue(); 2804 } 2805 2806 // Fold the constants, shifting the binop RHS by the shift amount. 2807 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2808 N->getValueType(0), 2809 LHS->getOperand(1), N->getOperand(1)); 2810 2811 // Create the new shift. 2812 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2813 VT, LHS->getOperand(0), N->getOperand(1)); 2814 2815 // Create the new binop. 2816 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2817} 2818 2819SDValue DAGCombiner::visitSHL(SDNode *N) { 2820 SDValue N0 = N->getOperand(0); 2821 SDValue N1 = N->getOperand(1); 2822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2824 EVT VT = N0.getValueType(); 2825 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2826 2827 // fold (shl c1, c2) -> c1<<c2 2828 if (N0C && N1C) 2829 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2830 // fold (shl 0, x) -> 0 2831 if (N0C && N0C->isNullValue()) 2832 return N0; 2833 // fold (shl x, c >= size(x)) -> undef 2834 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2835 return DAG.getUNDEF(VT); 2836 // fold (shl x, 0) -> x 2837 if (N1C && N1C->isNullValue()) 2838 return N0; 2839 // if (shl x, c) is known to be zero, return 0 2840 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2841 APInt::getAllOnesValue(OpSizeInBits))) 2842 return DAG.getConstant(0, VT); 2843 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2844 if (N1.getOpcode() == ISD::TRUNCATE && 2845 N1.getOperand(0).getOpcode() == ISD::AND && 2846 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2847 SDValue N101 = N1.getOperand(0).getOperand(1); 2848 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2849 EVT TruncVT = N1.getValueType(); 2850 SDValue N100 = N1.getOperand(0).getOperand(0); 2851 APInt TruncC = N101C->getAPIntValue(); 2852 TruncC.trunc(TruncVT.getSizeInBits()); 2853 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2854 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2855 DAG.getNode(ISD::TRUNCATE, 2856 N->getDebugLoc(), 2857 TruncVT, N100), 2858 DAG.getConstant(TruncC, TruncVT))); 2859 } 2860 } 2861 2862 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2863 return SDValue(N, 0); 2864 2865 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2866 if (N1C && N0.getOpcode() == ISD::SHL && 2867 N0.getOperand(1).getOpcode() == ISD::Constant) { 2868 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2869 uint64_t c2 = N1C->getZExtValue(); 2870 if (c1 + c2 > OpSizeInBits) 2871 return DAG.getConstant(0, VT); 2872 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2873 DAG.getConstant(c1 + c2, N1.getValueType())); 2874 } 2875 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2876 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2877 if (N1C && N0.getOpcode() == ISD::SRL && 2878 N0.getOperand(1).getOpcode() == ISD::Constant) { 2879 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2880 if (c1 < VT.getSizeInBits()) { 2881 uint64_t c2 = N1C->getZExtValue(); 2882 SDValue HiBitsMask = 2883 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2884 VT.getSizeInBits() - c1), 2885 VT); 2886 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2887 N0.getOperand(0), 2888 HiBitsMask); 2889 if (c2 > c1) 2890 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2891 DAG.getConstant(c2-c1, N1.getValueType())); 2892 else 2893 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2894 DAG.getConstant(c1-c2, N1.getValueType())); 2895 } 2896 } 2897 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2898 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2899 SDValue HiBitsMask = 2900 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2901 VT.getSizeInBits() - 2902 N1C->getZExtValue()), 2903 VT); 2904 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2905 HiBitsMask); 2906 } 2907 2908 if (N1C) { 2909 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 2910 if (NewSHL.getNode()) 2911 return NewSHL; 2912 } 2913 2914 return SDValue(); 2915} 2916 2917SDValue DAGCombiner::visitSRA(SDNode *N) { 2918 SDValue N0 = N->getOperand(0); 2919 SDValue N1 = N->getOperand(1); 2920 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2921 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2922 EVT VT = N0.getValueType(); 2923 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2924 2925 // fold (sra c1, c2) -> (sra c1, c2) 2926 if (N0C && N1C) 2927 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2928 // fold (sra 0, x) -> 0 2929 if (N0C && N0C->isNullValue()) 2930 return N0; 2931 // fold (sra -1, x) -> -1 2932 if (N0C && N0C->isAllOnesValue()) 2933 return N0; 2934 // fold (sra x, (setge c, size(x))) -> undef 2935 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2936 return DAG.getUNDEF(VT); 2937 // fold (sra x, 0) -> x 2938 if (N1C && N1C->isNullValue()) 2939 return N0; 2940 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2941 // sext_inreg. 2942 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2943 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2944 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2945 if (VT.isVector()) 2946 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2947 ExtVT, VT.getVectorNumElements()); 2948 if ((!LegalOperations || 2949 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2950 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2951 N0.getOperand(0), DAG.getValueType(ExtVT)); 2952 } 2953 2954 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2955 if (N1C && N0.getOpcode() == ISD::SRA) { 2956 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2957 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2958 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2959 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2960 DAG.getConstant(Sum, N1C->getValueType(0))); 2961 } 2962 } 2963 2964 // fold (sra (shl X, m), (sub result_size, n)) 2965 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2966 // result_size - n != m. 2967 // If truncate is free for the target sext(shl) is likely to result in better 2968 // code. 2969 if (N0.getOpcode() == ISD::SHL) { 2970 // Get the two constanst of the shifts, CN0 = m, CN = n. 2971 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2972 if (N01C && N1C) { 2973 // Determine what the truncate's result bitsize and type would be. 2974 EVT TruncVT = 2975 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2976 // Determine the residual right-shift amount. 2977 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2978 2979 // If the shift is not a no-op (in which case this should be just a sign 2980 // extend already), the truncated to type is legal, sign_extend is legal 2981 // on that type, and the truncate to that type is both legal and free, 2982 // perform the transform. 2983 if ((ShiftAmt > 0) && 2984 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2985 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2986 TLI.isTruncateFree(VT, TruncVT)) { 2987 2988 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2989 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2990 N0.getOperand(0), Amt); 2991 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2992 Shift); 2993 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2994 N->getValueType(0), Trunc); 2995 } 2996 } 2997 } 2998 2999 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3000 if (N1.getOpcode() == ISD::TRUNCATE && 3001 N1.getOperand(0).getOpcode() == ISD::AND && 3002 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3003 SDValue N101 = N1.getOperand(0).getOperand(1); 3004 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3005 EVT TruncVT = N1.getValueType(); 3006 SDValue N100 = N1.getOperand(0).getOperand(0); 3007 APInt TruncC = N101C->getAPIntValue(); 3008 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3009 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3010 DAG.getNode(ISD::AND, N->getDebugLoc(), 3011 TruncVT, 3012 DAG.getNode(ISD::TRUNCATE, 3013 N->getDebugLoc(), 3014 TruncVT, N100), 3015 DAG.getConstant(TruncC, TruncVT))); 3016 } 3017 } 3018 3019 // Simplify, based on bits shifted out of the LHS. 3020 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3021 return SDValue(N, 0); 3022 3023 3024 // If the sign bit is known to be zero, switch this to a SRL. 3025 if (DAG.SignBitIsZero(N0)) 3026 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3027 3028 if (N1C) { 3029 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3030 if (NewSRA.getNode()) 3031 return NewSRA; 3032 } 3033 3034 return SDValue(); 3035} 3036 3037SDValue DAGCombiner::visitSRL(SDNode *N) { 3038 SDValue N0 = N->getOperand(0); 3039 SDValue N1 = N->getOperand(1); 3040 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3041 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3042 EVT VT = N0.getValueType(); 3043 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3044 3045 // fold (srl c1, c2) -> c1 >>u c2 3046 if (N0C && N1C) 3047 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3048 // fold (srl 0, x) -> 0 3049 if (N0C && N0C->isNullValue()) 3050 return N0; 3051 // fold (srl x, c >= size(x)) -> undef 3052 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3053 return DAG.getUNDEF(VT); 3054 // fold (srl x, 0) -> x 3055 if (N1C && N1C->isNullValue()) 3056 return N0; 3057 // if (srl x, c) is known to be zero, return 0 3058 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3059 APInt::getAllOnesValue(OpSizeInBits))) 3060 return DAG.getConstant(0, VT); 3061 3062 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3063 if (N1C && N0.getOpcode() == ISD::SRL && 3064 N0.getOperand(1).getOpcode() == ISD::Constant) { 3065 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3066 uint64_t c2 = N1C->getZExtValue(); 3067 if (c1 + c2 > OpSizeInBits) 3068 return DAG.getConstant(0, VT); 3069 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3070 DAG.getConstant(c1 + c2, N1.getValueType())); 3071 } 3072 3073 // fold (srl (shl x, c), c) -> (and x, cst2) 3074 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3075 N0.getValueSizeInBits() <= 64) { 3076 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3078 DAG.getConstant(~0ULL >> ShAmt, VT)); 3079 } 3080 3081 3082 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3083 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3084 // Shifting in all undef bits? 3085 EVT SmallVT = N0.getOperand(0).getValueType(); 3086 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3087 return DAG.getUNDEF(VT); 3088 3089 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3090 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3091 N0.getOperand(0), N1); 3092 AddToWorkList(SmallShift.getNode()); 3093 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3094 } 3095 } 3096 3097 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3098 // bit, which is unmodified by sra. 3099 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3100 if (N0.getOpcode() == ISD::SRA) 3101 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3102 } 3103 3104 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3105 if (N1C && N0.getOpcode() == ISD::CTLZ && 3106 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3107 APInt KnownZero, KnownOne; 3108 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3109 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3110 3111 // If any of the input bits are KnownOne, then the input couldn't be all 3112 // zeros, thus the result of the srl will always be zero. 3113 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3114 3115 // If all of the bits input the to ctlz node are known to be zero, then 3116 // the result of the ctlz is "32" and the result of the shift is one. 3117 APInt UnknownBits = ~KnownZero & Mask; 3118 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3119 3120 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3121 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3122 // Okay, we know that only that the single bit specified by UnknownBits 3123 // could be set on input to the CTLZ node. If this bit is set, the SRL 3124 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3125 // to an SRL/XOR pair, which is likely to simplify more. 3126 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3127 SDValue Op = N0.getOperand(0); 3128 3129 if (ShAmt) { 3130 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3131 DAG.getConstant(ShAmt, getShiftAmountTy())); 3132 AddToWorkList(Op.getNode()); 3133 } 3134 3135 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3136 Op, DAG.getConstant(1, VT)); 3137 } 3138 } 3139 3140 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3141 if (N1.getOpcode() == ISD::TRUNCATE && 3142 N1.getOperand(0).getOpcode() == ISD::AND && 3143 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3144 SDValue N101 = N1.getOperand(0).getOperand(1); 3145 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3146 EVT TruncVT = N1.getValueType(); 3147 SDValue N100 = N1.getOperand(0).getOperand(0); 3148 APInt TruncC = N101C->getAPIntValue(); 3149 TruncC.trunc(TruncVT.getSizeInBits()); 3150 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3151 DAG.getNode(ISD::AND, N->getDebugLoc(), 3152 TruncVT, 3153 DAG.getNode(ISD::TRUNCATE, 3154 N->getDebugLoc(), 3155 TruncVT, N100), 3156 DAG.getConstant(TruncC, TruncVT))); 3157 } 3158 } 3159 3160 // fold operands of srl based on knowledge that the low bits are not 3161 // demanded. 3162 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3163 return SDValue(N, 0); 3164 3165 if (N1C) { 3166 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3167 if (NewSRL.getNode()) 3168 return NewSRL; 3169 } 3170 3171 // Attempt to convert a srl of a load into a narrower zero-extending load. 3172 SDValue NarrowLoad = ReduceLoadWidth(N); 3173 if (NarrowLoad.getNode()) 3174 return NarrowLoad; 3175 3176 // Here is a common situation. We want to optimize: 3177 // 3178 // %a = ... 3179 // %b = and i32 %a, 2 3180 // %c = srl i32 %b, 1 3181 // brcond i32 %c ... 3182 // 3183 // into 3184 // 3185 // %a = ... 3186 // %b = and %a, 2 3187 // %c = setcc eq %b, 0 3188 // brcond %c ... 3189 // 3190 // However when after the source operand of SRL is optimized into AND, the SRL 3191 // itself may not be optimized further. Look for it and add the BRCOND into 3192 // the worklist. 3193 if (N->hasOneUse()) { 3194 SDNode *Use = *N->use_begin(); 3195 if (Use->getOpcode() == ISD::BRCOND) 3196 AddToWorkList(Use); 3197 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3198 // Also look pass the truncate. 3199 Use = *Use->use_begin(); 3200 if (Use->getOpcode() == ISD::BRCOND) 3201 AddToWorkList(Use); 3202 } 3203 } 3204 3205 return SDValue(); 3206} 3207 3208SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3209 SDValue N0 = N->getOperand(0); 3210 EVT VT = N->getValueType(0); 3211 3212 // fold (ctlz c1) -> c2 3213 if (isa<ConstantSDNode>(N0)) 3214 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3215 return SDValue(); 3216} 3217 3218SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3219 SDValue N0 = N->getOperand(0); 3220 EVT VT = N->getValueType(0); 3221 3222 // fold (cttz c1) -> c2 3223 if (isa<ConstantSDNode>(N0)) 3224 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3225 return SDValue(); 3226} 3227 3228SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3229 SDValue N0 = N->getOperand(0); 3230 EVT VT = N->getValueType(0); 3231 3232 // fold (ctpop c1) -> c2 3233 if (isa<ConstantSDNode>(N0)) 3234 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3235 return SDValue(); 3236} 3237 3238SDValue DAGCombiner::visitSELECT(SDNode *N) { 3239 SDValue N0 = N->getOperand(0); 3240 SDValue N1 = N->getOperand(1); 3241 SDValue N2 = N->getOperand(2); 3242 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3243 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3244 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3245 EVT VT = N->getValueType(0); 3246 EVT VT0 = N0.getValueType(); 3247 3248 // fold (select C, X, X) -> X 3249 if (N1 == N2) 3250 return N1; 3251 // fold (select true, X, Y) -> X 3252 if (N0C && !N0C->isNullValue()) 3253 return N1; 3254 // fold (select false, X, Y) -> Y 3255 if (N0C && N0C->isNullValue()) 3256 return N2; 3257 // fold (select C, 1, X) -> (or C, X) 3258 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3259 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3260 // fold (select C, 0, 1) -> (xor C, 1) 3261 if (VT.isInteger() && 3262 (VT0 == MVT::i1 || 3263 (VT0.isInteger() && 3264 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3265 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3266 SDValue XORNode; 3267 if (VT == VT0) 3268 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3269 N0, DAG.getConstant(1, VT0)); 3270 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3271 N0, DAG.getConstant(1, VT0)); 3272 AddToWorkList(XORNode.getNode()); 3273 if (VT.bitsGT(VT0)) 3274 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3275 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3276 } 3277 // fold (select C, 0, X) -> (and (not C), X) 3278 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3279 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3280 AddToWorkList(NOTNode.getNode()); 3281 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3282 } 3283 // fold (select C, X, 1) -> (or (not C), X) 3284 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3285 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3286 AddToWorkList(NOTNode.getNode()); 3287 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3288 } 3289 // fold (select C, X, 0) -> (and C, X) 3290 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3291 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3292 // fold (select X, X, Y) -> (or X, Y) 3293 // fold (select X, 1, Y) -> (or X, Y) 3294 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3295 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3296 // fold (select X, Y, X) -> (and X, Y) 3297 // fold (select X, Y, 0) -> (and X, Y) 3298 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3299 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3300 3301 // If we can fold this based on the true/false value, do so. 3302 if (SimplifySelectOps(N, N1, N2)) 3303 return SDValue(N, 0); // Don't revisit N. 3304 3305 // fold selects based on a setcc into other things, such as min/max/abs 3306 if (N0.getOpcode() == ISD::SETCC) { 3307 // FIXME: 3308 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3309 // having to say they don't support SELECT_CC on every type the DAG knows 3310 // about, since there is no way to mark an opcode illegal at all value types 3311 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3312 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3313 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3314 N0.getOperand(0), N0.getOperand(1), 3315 N1, N2, N0.getOperand(2)); 3316 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3317 } 3318 3319 return SDValue(); 3320} 3321 3322SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3323 SDValue N0 = N->getOperand(0); 3324 SDValue N1 = N->getOperand(1); 3325 SDValue N2 = N->getOperand(2); 3326 SDValue N3 = N->getOperand(3); 3327 SDValue N4 = N->getOperand(4); 3328 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3329 3330 // fold select_cc lhs, rhs, x, x, cc -> x 3331 if (N2 == N3) 3332 return N2; 3333 3334 // Determine if the condition we're dealing with is constant 3335 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3336 N0, N1, CC, N->getDebugLoc(), false); 3337 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3338 3339 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3340 if (!SCCC->isNullValue()) 3341 return N2; // cond always true -> true val 3342 else 3343 return N3; // cond always false -> false val 3344 } 3345 3346 // Fold to a simpler select_cc 3347 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3348 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3349 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3350 SCC.getOperand(2)); 3351 3352 // If we can fold this based on the true/false value, do so. 3353 if (SimplifySelectOps(N, N2, N3)) 3354 return SDValue(N, 0); // Don't revisit N. 3355 3356 // fold select_cc into other things, such as min/max/abs 3357 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3358} 3359 3360SDValue DAGCombiner::visitSETCC(SDNode *N) { 3361 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3362 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3363 N->getDebugLoc()); 3364} 3365 3366// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3367// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3368// transformation. Returns true if extension are possible and the above 3369// mentioned transformation is profitable. 3370static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3371 unsigned ExtOpc, 3372 SmallVector<SDNode*, 4> &ExtendNodes, 3373 const TargetLowering &TLI) { 3374 bool HasCopyToRegUses = false; 3375 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3376 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3377 UE = N0.getNode()->use_end(); 3378 UI != UE; ++UI) { 3379 SDNode *User = *UI; 3380 if (User == N) 3381 continue; 3382 if (UI.getUse().getResNo() != N0.getResNo()) 3383 continue; 3384 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3385 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3386 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3387 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3388 // Sign bits will be lost after a zext. 3389 return false; 3390 bool Add = false; 3391 for (unsigned i = 0; i != 2; ++i) { 3392 SDValue UseOp = User->getOperand(i); 3393 if (UseOp == N0) 3394 continue; 3395 if (!isa<ConstantSDNode>(UseOp)) 3396 return false; 3397 Add = true; 3398 } 3399 if (Add) 3400 ExtendNodes.push_back(User); 3401 continue; 3402 } 3403 // If truncates aren't free and there are users we can't 3404 // extend, it isn't worthwhile. 3405 if (!isTruncFree) 3406 return false; 3407 // Remember if this value is live-out. 3408 if (User->getOpcode() == ISD::CopyToReg) 3409 HasCopyToRegUses = true; 3410 } 3411 3412 if (HasCopyToRegUses) { 3413 bool BothLiveOut = false; 3414 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3415 UI != UE; ++UI) { 3416 SDUse &Use = UI.getUse(); 3417 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3418 BothLiveOut = true; 3419 break; 3420 } 3421 } 3422 if (BothLiveOut) 3423 // Both unextended and extended values are live out. There had better be 3424 // good a reason for the transformation. 3425 return ExtendNodes.size(); 3426 } 3427 return true; 3428} 3429 3430SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3431 SDValue N0 = N->getOperand(0); 3432 EVT VT = N->getValueType(0); 3433 3434 // fold (sext c1) -> c1 3435 if (isa<ConstantSDNode>(N0)) 3436 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3437 3438 // fold (sext (sext x)) -> (sext x) 3439 // fold (sext (aext x)) -> (sext x) 3440 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3441 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3442 N0.getOperand(0)); 3443 3444 if (N0.getOpcode() == ISD::TRUNCATE) { 3445 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3446 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3447 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3448 if (NarrowLoad.getNode()) { 3449 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3450 if (NarrowLoad.getNode() != N0.getNode()) { 3451 CombineTo(N0.getNode(), NarrowLoad); 3452 // CombineTo deleted the truncate, if needed, but not what's under it. 3453 AddToWorkList(oye); 3454 } 3455 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3456 } 3457 3458 // See if the value being truncated is already sign extended. If so, just 3459 // eliminate the trunc/sext pair. 3460 SDValue Op = N0.getOperand(0); 3461 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3462 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3463 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3464 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3465 3466 if (OpBits == DestBits) { 3467 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3468 // bits, it is already ready. 3469 if (NumSignBits > DestBits-MidBits) 3470 return Op; 3471 } else if (OpBits < DestBits) { 3472 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3473 // bits, just sext from i32. 3474 if (NumSignBits > OpBits-MidBits) 3475 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3476 } else { 3477 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3478 // bits, just truncate to i32. 3479 if (NumSignBits > OpBits-MidBits) 3480 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3481 } 3482 3483 // fold (sext (truncate x)) -> (sextinreg x). 3484 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3485 N0.getValueType())) { 3486 if (OpBits < DestBits) 3487 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3488 else if (OpBits > DestBits) 3489 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3490 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3491 DAG.getValueType(N0.getValueType())); 3492 } 3493 } 3494 3495 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3496 if (ISD::isNON_EXTLoad(N0.getNode()) && 3497 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3498 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3499 bool DoXform = true; 3500 SmallVector<SDNode*, 4> SetCCs; 3501 if (!N0.hasOneUse()) 3502 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3503 if (DoXform) { 3504 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3505 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3506 LN0->getChain(), 3507 LN0->getBasePtr(), LN0->getSrcValue(), 3508 LN0->getSrcValueOffset(), 3509 N0.getValueType(), 3510 LN0->isVolatile(), LN0->isNonTemporal(), 3511 LN0->getAlignment()); 3512 CombineTo(N, ExtLoad); 3513 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3514 N0.getValueType(), ExtLoad); 3515 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3516 3517 // Extend SetCC uses if necessary. 3518 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3519 SDNode *SetCC = SetCCs[i]; 3520 SmallVector<SDValue, 4> Ops; 3521 3522 for (unsigned j = 0; j != 2; ++j) { 3523 SDValue SOp = SetCC->getOperand(j); 3524 if (SOp == Trunc) 3525 Ops.push_back(ExtLoad); 3526 else 3527 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3528 N->getDebugLoc(), VT, SOp)); 3529 } 3530 3531 Ops.push_back(SetCC->getOperand(2)); 3532 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3533 SetCC->getValueType(0), 3534 &Ops[0], Ops.size())); 3535 } 3536 3537 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3538 } 3539 } 3540 3541 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3542 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3543 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3544 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3545 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3546 EVT MemVT = LN0->getMemoryVT(); 3547 if ((!LegalOperations && !LN0->isVolatile()) || 3548 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3549 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3550 LN0->getChain(), 3551 LN0->getBasePtr(), LN0->getSrcValue(), 3552 LN0->getSrcValueOffset(), MemVT, 3553 LN0->isVolatile(), LN0->isNonTemporal(), 3554 LN0->getAlignment()); 3555 CombineTo(N, ExtLoad); 3556 CombineTo(N0.getNode(), 3557 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3558 N0.getValueType(), ExtLoad), 3559 ExtLoad.getValue(1)); 3560 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3561 } 3562 } 3563 3564 if (N0.getOpcode() == ISD::SETCC) { 3565 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3566 // Only do this before legalize for now. 3567 if (VT.isVector() && !LegalOperations) { 3568 EVT N0VT = N0.getOperand(0).getValueType(); 3569 // We know that the # elements of the results is the same as the 3570 // # elements of the compare (and the # elements of the compare result 3571 // for that matter). Check to see that they are the same size. If so, 3572 // we know that the element size of the sext'd result matches the 3573 // element size of the compare operands. 3574 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3575 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3576 N0.getOperand(1), 3577 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3578 // If the desired elements are smaller or larger than the source 3579 // elements we can use a matching integer vector type and then 3580 // truncate/sign extend 3581 else { 3582 EVT MatchingElementType = 3583 EVT::getIntegerVT(*DAG.getContext(), 3584 N0VT.getScalarType().getSizeInBits()); 3585 EVT MatchingVectorType = 3586 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3587 N0VT.getVectorNumElements()); 3588 SDValue VsetCC = 3589 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3590 N0.getOperand(1), 3591 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3592 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3593 } 3594 } 3595 3596 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3597 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3598 SDValue NegOne = 3599 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3600 SDValue SCC = 3601 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3602 NegOne, DAG.getConstant(0, VT), 3603 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3604 if (SCC.getNode()) return SCC; 3605 if (!LegalOperations || 3606 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3607 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3608 DAG.getSetCC(N->getDebugLoc(), 3609 TLI.getSetCCResultType(VT), 3610 N0.getOperand(0), N0.getOperand(1), 3611 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3612 NegOne, DAG.getConstant(0, VT)); 3613 } 3614 3615 // fold (sext x) -> (zext x) if the sign bit is known zero. 3616 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3617 DAG.SignBitIsZero(N0)) 3618 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3619 3620 return SDValue(); 3621} 3622 3623SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3624 SDValue N0 = N->getOperand(0); 3625 EVT VT = N->getValueType(0); 3626 3627 // fold (zext c1) -> c1 3628 if (isa<ConstantSDNode>(N0)) 3629 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3630 // fold (zext (zext x)) -> (zext x) 3631 // fold (zext (aext x)) -> (zext x) 3632 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3633 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3634 N0.getOperand(0)); 3635 3636 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3637 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3638 if (N0.getOpcode() == ISD::TRUNCATE) { 3639 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3640 if (NarrowLoad.getNode()) { 3641 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3642 if (NarrowLoad.getNode() != N0.getNode()) { 3643 CombineTo(N0.getNode(), NarrowLoad); 3644 // CombineTo deleted the truncate, if needed, but not what's under it. 3645 AddToWorkList(oye); 3646 } 3647 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3648 } 3649 } 3650 3651 // fold (zext (truncate x)) -> (and x, mask) 3652 if (N0.getOpcode() == ISD::TRUNCATE && 3653 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3654 SDValue Op = N0.getOperand(0); 3655 if (Op.getValueType().bitsLT(VT)) { 3656 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3657 } else if (Op.getValueType().bitsGT(VT)) { 3658 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3659 } 3660 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3661 N0.getValueType().getScalarType()); 3662 } 3663 3664 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3665 // if either of the casts is not free. 3666 if (N0.getOpcode() == ISD::AND && 3667 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3668 N0.getOperand(1).getOpcode() == ISD::Constant && 3669 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3670 N0.getValueType()) || 3671 !TLI.isZExtFree(N0.getValueType(), VT))) { 3672 SDValue X = N0.getOperand(0).getOperand(0); 3673 if (X.getValueType().bitsLT(VT)) { 3674 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3675 } else if (X.getValueType().bitsGT(VT)) { 3676 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3677 } 3678 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3679 Mask.zext(VT.getSizeInBits()); 3680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3681 X, DAG.getConstant(Mask, VT)); 3682 } 3683 3684 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3685 if (ISD::isNON_EXTLoad(N0.getNode()) && 3686 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3687 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3688 bool DoXform = true; 3689 SmallVector<SDNode*, 4> SetCCs; 3690 if (!N0.hasOneUse()) 3691 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3692 if (DoXform) { 3693 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3694 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3695 LN0->getChain(), 3696 LN0->getBasePtr(), LN0->getSrcValue(), 3697 LN0->getSrcValueOffset(), 3698 N0.getValueType(), 3699 LN0->isVolatile(), LN0->isNonTemporal(), 3700 LN0->getAlignment()); 3701 CombineTo(N, ExtLoad); 3702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3703 N0.getValueType(), ExtLoad); 3704 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3705 3706 // Extend SetCC uses if necessary. 3707 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3708 SDNode *SetCC = SetCCs[i]; 3709 SmallVector<SDValue, 4> Ops; 3710 3711 for (unsigned j = 0; j != 2; ++j) { 3712 SDValue SOp = SetCC->getOperand(j); 3713 if (SOp == Trunc) 3714 Ops.push_back(ExtLoad); 3715 else 3716 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3717 N->getDebugLoc(), VT, SOp)); 3718 } 3719 3720 Ops.push_back(SetCC->getOperand(2)); 3721 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3722 SetCC->getValueType(0), 3723 &Ops[0], Ops.size())); 3724 } 3725 3726 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3727 } 3728 } 3729 3730 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3731 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3732 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3733 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3734 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3735 EVT MemVT = LN0->getMemoryVT(); 3736 if ((!LegalOperations && !LN0->isVolatile()) || 3737 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3738 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3739 LN0->getChain(), 3740 LN0->getBasePtr(), LN0->getSrcValue(), 3741 LN0->getSrcValueOffset(), MemVT, 3742 LN0->isVolatile(), LN0->isNonTemporal(), 3743 LN0->getAlignment()); 3744 CombineTo(N, ExtLoad); 3745 CombineTo(N0.getNode(), 3746 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3747 ExtLoad), 3748 ExtLoad.getValue(1)); 3749 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3750 } 3751 } 3752 3753 if (N0.getOpcode() == ISD::SETCC) { 3754 if (!LegalOperations && VT.isVector()) { 3755 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3756 // Only do this before legalize for now. 3757 EVT N0VT = N0.getOperand(0).getValueType(); 3758 EVT EltVT = VT.getVectorElementType(); 3759 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3760 DAG.getConstant(1, EltVT)); 3761 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3762 // We know that the # elements of the results is the same as the 3763 // # elements of the compare (and the # elements of the compare result 3764 // for that matter). Check to see that they are the same size. If so, 3765 // we know that the element size of the sext'd result matches the 3766 // element size of the compare operands. 3767 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3768 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3769 N0.getOperand(1), 3770 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3771 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3772 &OneOps[0], OneOps.size())); 3773 } else { 3774 // If the desired elements are smaller or larger than the source 3775 // elements we can use a matching integer vector type and then 3776 // truncate/sign extend 3777 EVT MatchingElementType = 3778 EVT::getIntegerVT(*DAG.getContext(), 3779 N0VT.getScalarType().getSizeInBits()); 3780 EVT MatchingVectorType = 3781 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3782 N0VT.getVectorNumElements()); 3783 SDValue VsetCC = 3784 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3785 N0.getOperand(1), 3786 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3787 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3788 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3789 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3790 &OneOps[0], OneOps.size())); 3791 } 3792 } 3793 3794 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3795 SDValue SCC = 3796 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3797 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3798 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3799 if (SCC.getNode()) return SCC; 3800 } 3801 3802 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3803 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3804 isa<ConstantSDNode>(N0.getOperand(1)) && 3805 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3806 N0.hasOneUse()) { 3807 if (N0.getOpcode() == ISD::SHL) { 3808 // If the original shl may be shifting out bits, do not perform this 3809 // transformation. 3810 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3811 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3812 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3813 if (ShAmt > KnownZeroBits) 3814 return SDValue(); 3815 } 3816 DebugLoc dl = N->getDebugLoc(); 3817 return DAG.getNode(N0.getOpcode(), dl, VT, 3818 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3819 DAG.getNode(ISD::ZERO_EXTEND, dl, 3820 N0.getOperand(1).getValueType(), 3821 N0.getOperand(1))); 3822 } 3823 3824 return SDValue(); 3825} 3826 3827SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3828 SDValue N0 = N->getOperand(0); 3829 EVT VT = N->getValueType(0); 3830 3831 // fold (aext c1) -> c1 3832 if (isa<ConstantSDNode>(N0)) 3833 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3834 // fold (aext (aext x)) -> (aext x) 3835 // fold (aext (zext x)) -> (zext x) 3836 // fold (aext (sext x)) -> (sext x) 3837 if (N0.getOpcode() == ISD::ANY_EXTEND || 3838 N0.getOpcode() == ISD::ZERO_EXTEND || 3839 N0.getOpcode() == ISD::SIGN_EXTEND) 3840 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3841 3842 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3843 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3844 if (N0.getOpcode() == ISD::TRUNCATE) { 3845 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3846 if (NarrowLoad.getNode()) { 3847 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3848 if (NarrowLoad.getNode() != N0.getNode()) { 3849 CombineTo(N0.getNode(), NarrowLoad); 3850 // CombineTo deleted the truncate, if needed, but not what's under it. 3851 AddToWorkList(oye); 3852 } 3853 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3854 } 3855 } 3856 3857 // fold (aext (truncate x)) 3858 if (N0.getOpcode() == ISD::TRUNCATE) { 3859 SDValue TruncOp = N0.getOperand(0); 3860 if (TruncOp.getValueType() == VT) 3861 return TruncOp; // x iff x size == zext size. 3862 if (TruncOp.getValueType().bitsGT(VT)) 3863 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3864 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3865 } 3866 3867 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3868 // if the trunc is not free. 3869 if (N0.getOpcode() == ISD::AND && 3870 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3871 N0.getOperand(1).getOpcode() == ISD::Constant && 3872 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3873 N0.getValueType())) { 3874 SDValue X = N0.getOperand(0).getOperand(0); 3875 if (X.getValueType().bitsLT(VT)) { 3876 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3877 } else if (X.getValueType().bitsGT(VT)) { 3878 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3879 } 3880 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3881 Mask.zext(VT.getSizeInBits()); 3882 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3883 X, DAG.getConstant(Mask, VT)); 3884 } 3885 3886 // fold (aext (load x)) -> (aext (truncate (extload x))) 3887 if (ISD::isNON_EXTLoad(N0.getNode()) && 3888 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3889 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3890 bool DoXform = true; 3891 SmallVector<SDNode*, 4> SetCCs; 3892 if (!N0.hasOneUse()) 3893 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3894 if (DoXform) { 3895 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3896 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3897 LN0->getChain(), 3898 LN0->getBasePtr(), LN0->getSrcValue(), 3899 LN0->getSrcValueOffset(), 3900 N0.getValueType(), 3901 LN0->isVolatile(), LN0->isNonTemporal(), 3902 LN0->getAlignment()); 3903 CombineTo(N, ExtLoad); 3904 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3905 N0.getValueType(), ExtLoad); 3906 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3907 3908 // Extend SetCC uses if necessary. 3909 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3910 SDNode *SetCC = SetCCs[i]; 3911 SmallVector<SDValue, 4> Ops; 3912 3913 for (unsigned j = 0; j != 2; ++j) { 3914 SDValue SOp = SetCC->getOperand(j); 3915 if (SOp == Trunc) 3916 Ops.push_back(ExtLoad); 3917 else 3918 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3919 N->getDebugLoc(), VT, SOp)); 3920 } 3921 3922 Ops.push_back(SetCC->getOperand(2)); 3923 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3924 SetCC->getValueType(0), 3925 &Ops[0], Ops.size())); 3926 } 3927 3928 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3929 } 3930 } 3931 3932 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3933 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3934 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3935 if (N0.getOpcode() == ISD::LOAD && 3936 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3937 N0.hasOneUse()) { 3938 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3939 EVT MemVT = LN0->getMemoryVT(); 3940 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3941 VT, LN0->getChain(), LN0->getBasePtr(), 3942 LN0->getSrcValue(), 3943 LN0->getSrcValueOffset(), MemVT, 3944 LN0->isVolatile(), LN0->isNonTemporal(), 3945 LN0->getAlignment()); 3946 CombineTo(N, ExtLoad); 3947 CombineTo(N0.getNode(), 3948 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3949 N0.getValueType(), ExtLoad), 3950 ExtLoad.getValue(1)); 3951 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3952 } 3953 3954 if (N0.getOpcode() == ISD::SETCC) { 3955 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 3956 // Only do this before legalize for now. 3957 if (VT.isVector() && !LegalOperations) { 3958 EVT N0VT = N0.getOperand(0).getValueType(); 3959 // We know that the # elements of the results is the same as the 3960 // # elements of the compare (and the # elements of the compare result 3961 // for that matter). Check to see that they are the same size. If so, 3962 // we know that the element size of the sext'd result matches the 3963 // element size of the compare operands. 3964 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3965 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3966 N0.getOperand(1), 3967 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3968 // If the desired elements are smaller or larger than the source 3969 // elements we can use a matching integer vector type and then 3970 // truncate/sign extend 3971 else { 3972 EVT MatchingElementType = 3973 EVT::getIntegerVT(*DAG.getContext(), 3974 N0VT.getScalarType().getSizeInBits()); 3975 EVT MatchingVectorType = 3976 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3977 N0VT.getVectorNumElements()); 3978 SDValue VsetCC = 3979 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3980 N0.getOperand(1), 3981 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3982 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3983 } 3984 } 3985 3986 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3987 SDValue SCC = 3988 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3989 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3990 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3991 if (SCC.getNode()) 3992 return SCC; 3993 } 3994 3995 return SDValue(); 3996} 3997 3998/// GetDemandedBits - See if the specified operand can be simplified with the 3999/// knowledge that only the bits specified by Mask are used. If so, return the 4000/// simpler operand, otherwise return a null SDValue. 4001SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4002 switch (V.getOpcode()) { 4003 default: break; 4004 case ISD::OR: 4005 case ISD::XOR: 4006 // If the LHS or RHS don't contribute bits to the or, drop them. 4007 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4008 return V.getOperand(1); 4009 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4010 return V.getOperand(0); 4011 break; 4012 case ISD::SRL: 4013 // Only look at single-use SRLs. 4014 if (!V.getNode()->hasOneUse()) 4015 break; 4016 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4017 // See if we can recursively simplify the LHS. 4018 unsigned Amt = RHSC->getZExtValue(); 4019 4020 // Watch out for shift count overflow though. 4021 if (Amt >= Mask.getBitWidth()) break; 4022 APInt NewMask = Mask << Amt; 4023 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4024 if (SimplifyLHS.getNode()) 4025 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4026 SimplifyLHS, V.getOperand(1)); 4027 } 4028 } 4029 return SDValue(); 4030} 4031 4032/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4033/// bits and then truncated to a narrower type and where N is a multiple 4034/// of number of bits of the narrower type, transform it to a narrower load 4035/// from address + N / num of bits of new type. If the result is to be 4036/// extended, also fold the extension to form a extending load. 4037SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4038 unsigned Opc = N->getOpcode(); 4039 4040 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4041 SDValue N0 = N->getOperand(0); 4042 EVT VT = N->getValueType(0); 4043 EVT ExtVT = VT; 4044 4045 // This transformation isn't valid for vector loads. 4046 if (VT.isVector()) 4047 return SDValue(); 4048 4049 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4050 // extended to VT. 4051 if (Opc == ISD::SIGN_EXTEND_INREG) { 4052 ExtType = ISD::SEXTLOAD; 4053 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4054 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4055 return SDValue(); 4056 } else if (Opc == ISD::SRL) { 4057 // Annother special-case: SRL is basically zero-extending a narrower 4058 // value. 4059 ExtType = ISD::ZEXTLOAD; 4060 N0 = SDValue(N, 0); 4061 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4062 if (!N01) return SDValue(); 4063 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4064 VT.getSizeInBits() - N01->getZExtValue()); 4065 } 4066 4067 unsigned EVTBits = ExtVT.getSizeInBits(); 4068 unsigned ShAmt = 0; 4069 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4070 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4071 ShAmt = N01->getZExtValue(); 4072 // Is the shift amount a multiple of size of VT? 4073 if ((ShAmt & (EVTBits-1)) == 0) { 4074 N0 = N0.getOperand(0); 4075 // Is the load width a multiple of size of VT? 4076 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4077 return SDValue(); 4078 } 4079 } 4080 } 4081 4082 // Do not generate loads of non-round integer types since these can 4083 // be expensive (and would be wrong if the type is not byte sized). 4084 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4085 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4086 // Do not change the width of a volatile load. 4087 !cast<LoadSDNode>(N0)->isVolatile()) { 4088 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4089 EVT PtrType = N0.getOperand(1).getValueType(); 4090 4091 // For big endian targets, we need to adjust the offset to the pointer to 4092 // load the correct bytes. 4093 if (TLI.isBigEndian()) { 4094 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4095 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4096 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4097 } 4098 4099 uint64_t PtrOff = ShAmt / 8; 4100 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4101 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4102 PtrType, LN0->getBasePtr(), 4103 DAG.getConstant(PtrOff, PtrType)); 4104 AddToWorkList(NewPtr.getNode()); 4105 4106 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4107 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4108 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4109 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4110 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 4111 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 4112 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4113 NewAlign); 4114 4115 // Replace the old load's chain with the new load's chain. 4116 WorkListRemover DeadNodes(*this); 4117 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4118 &DeadNodes); 4119 4120 // Return the new loaded value. 4121 return Load; 4122 } 4123 4124 return SDValue(); 4125} 4126 4127SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4128 SDValue N0 = N->getOperand(0); 4129 SDValue N1 = N->getOperand(1); 4130 EVT VT = N->getValueType(0); 4131 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4132 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4133 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4134 4135 // fold (sext_in_reg c1) -> c1 4136 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4137 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4138 4139 // If the input is already sign extended, just drop the extension. 4140 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4141 return N0; 4142 4143 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4144 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4145 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4147 N0.getOperand(0), N1); 4148 } 4149 4150 // fold (sext_in_reg (sext x)) -> (sext x) 4151 // fold (sext_in_reg (aext x)) -> (sext x) 4152 // if x is small enough. 4153 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4154 SDValue N00 = N0.getOperand(0); 4155 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4156 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4157 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4158 } 4159 4160 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4161 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4162 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4163 4164 // fold operands of sext_in_reg based on knowledge that the top bits are not 4165 // demanded. 4166 if (SimplifyDemandedBits(SDValue(N, 0))) 4167 return SDValue(N, 0); 4168 4169 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4170 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4171 SDValue NarrowLoad = ReduceLoadWidth(N); 4172 if (NarrowLoad.getNode()) 4173 return NarrowLoad; 4174 4175 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4176 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4177 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4178 if (N0.getOpcode() == ISD::SRL) { 4179 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4180 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4181 // We can turn this into an SRA iff the input to the SRL is already sign 4182 // extended enough. 4183 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4184 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4185 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4186 N0.getOperand(0), N0.getOperand(1)); 4187 } 4188 } 4189 4190 // fold (sext_inreg (extload x)) -> (sextload x) 4191 if (ISD::isEXTLoad(N0.getNode()) && 4192 ISD::isUNINDEXEDLoad(N0.getNode()) && 4193 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4194 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4195 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4196 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4197 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4198 LN0->getChain(), 4199 LN0->getBasePtr(), LN0->getSrcValue(), 4200 LN0->getSrcValueOffset(), EVT, 4201 LN0->isVolatile(), LN0->isNonTemporal(), 4202 LN0->getAlignment()); 4203 CombineTo(N, ExtLoad); 4204 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4205 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4206 } 4207 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4208 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4209 N0.hasOneUse() && 4210 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4211 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4212 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4213 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4214 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4215 LN0->getChain(), 4216 LN0->getBasePtr(), LN0->getSrcValue(), 4217 LN0->getSrcValueOffset(), EVT, 4218 LN0->isVolatile(), LN0->isNonTemporal(), 4219 LN0->getAlignment()); 4220 CombineTo(N, ExtLoad); 4221 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4222 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4223 } 4224 return SDValue(); 4225} 4226 4227SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4228 SDValue N0 = N->getOperand(0); 4229 EVT VT = N->getValueType(0); 4230 4231 // noop truncate 4232 if (N0.getValueType() == N->getValueType(0)) 4233 return N0; 4234 // fold (truncate c1) -> c1 4235 if (isa<ConstantSDNode>(N0)) 4236 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4237 // fold (truncate (truncate x)) -> (truncate x) 4238 if (N0.getOpcode() == ISD::TRUNCATE) 4239 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4240 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4241 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4242 N0.getOpcode() == ISD::SIGN_EXTEND || 4243 N0.getOpcode() == ISD::ANY_EXTEND) { 4244 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4245 // if the source is smaller than the dest, we still need an extend 4246 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4247 N0.getOperand(0)); 4248 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4249 // if the source is larger than the dest, than we just need the truncate 4250 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4251 else 4252 // if the source and dest are the same type, we can drop both the extend 4253 // and the truncate. 4254 return N0.getOperand(0); 4255 } 4256 4257 // See if we can simplify the input to this truncate through knowledge that 4258 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4259 // -> trunc y 4260 SDValue Shorter = 4261 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4262 VT.getSizeInBits())); 4263 if (Shorter.getNode()) 4264 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4265 4266 // fold (truncate (load x)) -> (smaller load x) 4267 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4268 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4269 SDValue Reduced = ReduceLoadWidth(N); 4270 if (Reduced.getNode()) 4271 return Reduced; 4272 } 4273 4274 // Simplify the operands using demanded-bits information. 4275 if (!VT.isVector() && 4276 SimplifyDemandedBits(SDValue(N, 0))) 4277 return SDValue(N, 0); 4278 4279 return SDValue(); 4280} 4281 4282static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4283 SDValue Elt = N->getOperand(i); 4284 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4285 return Elt.getNode(); 4286 return Elt.getOperand(Elt.getResNo()).getNode(); 4287} 4288 4289/// CombineConsecutiveLoads - build_pair (load, load) -> load 4290/// if load locations are consecutive. 4291SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4292 assert(N->getOpcode() == ISD::BUILD_PAIR); 4293 4294 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4295 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4296 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 4297 return SDValue(); 4298 EVT LD1VT = LD1->getValueType(0); 4299 4300 if (ISD::isNON_EXTLoad(LD2) && 4301 LD2->hasOneUse() && 4302 // If both are volatile this would reduce the number of volatile loads. 4303 // If one is volatile it might be ok, but play conservative and bail out. 4304 !LD1->isVolatile() && 4305 !LD2->isVolatile() && 4306 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4307 unsigned Align = LD1->getAlignment(); 4308 unsigned NewAlign = TLI.getTargetData()-> 4309 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4310 4311 if (NewAlign <= Align && 4312 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4313 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4314 LD1->getBasePtr(), LD1->getSrcValue(), 4315 LD1->getSrcValueOffset(), false, false, Align); 4316 } 4317 4318 return SDValue(); 4319} 4320 4321SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 4322 SDValue N0 = N->getOperand(0); 4323 EVT VT = N->getValueType(0); 4324 4325 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4326 // Only do this before legalize, since afterward the target may be depending 4327 // on the bitconvert. 4328 // First check to see if this is all constant. 4329 if (!LegalTypes && 4330 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4331 VT.isVector()) { 4332 bool isSimple = true; 4333 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4334 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4335 N0.getOperand(i).getOpcode() != ISD::Constant && 4336 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4337 isSimple = false; 4338 break; 4339 } 4340 4341 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4342 assert(!DestEltVT.isVector() && 4343 "Element type of vector ValueType must not be vector!"); 4344 if (isSimple) 4345 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4346 } 4347 4348 // If the input is a constant, let getNode fold it. 4349 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4350 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 4351 if (Res.getNode() != N) { 4352 if (!LegalOperations || 4353 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4354 return Res; 4355 4356 // Folding it resulted in an illegal node, and it's too late to 4357 // do that. Clean up the old node and forego the transformation. 4358 // Ideally this won't happen very often, because instcombine 4359 // and the earlier dagcombine runs (where illegal nodes are 4360 // permitted) should have folded most of them already. 4361 DAG.DeleteNode(Res.getNode()); 4362 } 4363 } 4364 4365 // (conv (conv x, t1), t2) -> (conv x, t2) 4366 if (N0.getOpcode() == ISD::BIT_CONVERT) 4367 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 4368 N0.getOperand(0)); 4369 4370 // fold (conv (load x)) -> (load (conv*)x) 4371 // If the resultant load doesn't need a higher alignment than the original! 4372 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4373 // Do not change the width of a volatile load. 4374 !cast<LoadSDNode>(N0)->isVolatile() && 4375 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4376 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4377 unsigned Align = TLI.getTargetData()-> 4378 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4379 unsigned OrigAlign = LN0->getAlignment(); 4380 4381 if (Align <= OrigAlign) { 4382 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4383 LN0->getBasePtr(), 4384 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4385 LN0->isVolatile(), LN0->isNonTemporal(), 4386 OrigAlign); 4387 AddToWorkList(N); 4388 CombineTo(N0.getNode(), 4389 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4390 N0.getValueType(), Load), 4391 Load.getValue(1)); 4392 return Load; 4393 } 4394 } 4395 4396 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4397 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4398 // This often reduces constant pool loads. 4399 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4400 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4401 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 4402 N0.getOperand(0)); 4403 AddToWorkList(NewConv.getNode()); 4404 4405 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4406 if (N0.getOpcode() == ISD::FNEG) 4407 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4408 NewConv, DAG.getConstant(SignBit, VT)); 4409 assert(N0.getOpcode() == ISD::FABS); 4410 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4411 NewConv, DAG.getConstant(~SignBit, VT)); 4412 } 4413 4414 // fold (bitconvert (fcopysign cst, x)) -> 4415 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4416 // Note that we don't handle (copysign x, cst) because this can always be 4417 // folded to an fneg or fabs. 4418 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4419 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4420 VT.isInteger() && !VT.isVector()) { 4421 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4422 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4423 if (isTypeLegal(IntXVT)) { 4424 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4425 IntXVT, N0.getOperand(1)); 4426 AddToWorkList(X.getNode()); 4427 4428 // If X has a different width than the result/lhs, sext it or truncate it. 4429 unsigned VTWidth = VT.getSizeInBits(); 4430 if (OrigXWidth < VTWidth) { 4431 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4432 AddToWorkList(X.getNode()); 4433 } else if (OrigXWidth > VTWidth) { 4434 // To get the sign bit in the right place, we have to shift it right 4435 // before truncating. 4436 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4437 X.getValueType(), X, 4438 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4439 AddToWorkList(X.getNode()); 4440 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4441 AddToWorkList(X.getNode()); 4442 } 4443 4444 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4445 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4446 X, DAG.getConstant(SignBit, VT)); 4447 AddToWorkList(X.getNode()); 4448 4449 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 4450 VT, N0.getOperand(0)); 4451 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4452 Cst, DAG.getConstant(~SignBit, VT)); 4453 AddToWorkList(Cst.getNode()); 4454 4455 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4456 } 4457 } 4458 4459 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4460 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4461 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4462 if (CombineLD.getNode()) 4463 return CombineLD; 4464 } 4465 4466 return SDValue(); 4467} 4468 4469SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4470 EVT VT = N->getValueType(0); 4471 return CombineConsecutiveLoads(N, VT); 4472} 4473 4474/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4475/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4476/// destination element value type. 4477SDValue DAGCombiner:: 4478ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4479 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4480 4481 // If this is already the right type, we're done. 4482 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4483 4484 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4485 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4486 4487 // If this is a conversion of N elements of one type to N elements of another 4488 // type, convert each element. This handles FP<->INT cases. 4489 if (SrcBitSize == DstBitSize) { 4490 SmallVector<SDValue, 8> Ops; 4491 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4492 SDValue Op = BV->getOperand(i); 4493 // If the vector element type is not legal, the BUILD_VECTOR operands 4494 // are promoted and implicitly truncated. Make that explicit here. 4495 if (Op.getValueType() != SrcEltVT) 4496 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4497 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4498 DstEltVT, Op)); 4499 AddToWorkList(Ops.back().getNode()); 4500 } 4501 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4502 BV->getValueType(0).getVectorNumElements()); 4503 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4504 &Ops[0], Ops.size()); 4505 } 4506 4507 // Otherwise, we're growing or shrinking the elements. To avoid having to 4508 // handle annoying details of growing/shrinking FP values, we convert them to 4509 // int first. 4510 if (SrcEltVT.isFloatingPoint()) { 4511 // Convert the input float vector to a int vector where the elements are the 4512 // same sizes. 4513 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4514 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4515 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4516 SrcEltVT = IntVT; 4517 } 4518 4519 // Now we know the input is an integer vector. If the output is a FP type, 4520 // convert to integer first, then to FP of the right size. 4521 if (DstEltVT.isFloatingPoint()) { 4522 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4523 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4524 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4525 4526 // Next, convert to FP elements of the same size. 4527 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4528 } 4529 4530 // Okay, we know the src/dst types are both integers of differing types. 4531 // Handling growing first. 4532 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4533 if (SrcBitSize < DstBitSize) { 4534 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4535 4536 SmallVector<SDValue, 8> Ops; 4537 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4538 i += NumInputsPerOutput) { 4539 bool isLE = TLI.isLittleEndian(); 4540 APInt NewBits = APInt(DstBitSize, 0); 4541 bool EltIsUndef = true; 4542 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4543 // Shift the previously computed bits over. 4544 NewBits <<= SrcBitSize; 4545 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4546 if (Op.getOpcode() == ISD::UNDEF) continue; 4547 EltIsUndef = false; 4548 4549 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4550 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4551 } 4552 4553 if (EltIsUndef) 4554 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4555 else 4556 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4557 } 4558 4559 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4560 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4561 &Ops[0], Ops.size()); 4562 } 4563 4564 // Finally, this must be the case where we are shrinking elements: each input 4565 // turns into multiple outputs. 4566 bool isS2V = ISD::isScalarToVector(BV); 4567 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4568 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4569 NumOutputsPerInput*BV->getNumOperands()); 4570 SmallVector<SDValue, 8> Ops; 4571 4572 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4573 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4574 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4575 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4576 continue; 4577 } 4578 4579 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4580 getAPIntValue()).zextOrTrunc(SrcBitSize); 4581 4582 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4583 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4584 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4585 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4586 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4587 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4588 Ops[0]); 4589 OpVal = OpVal.lshr(DstBitSize); 4590 } 4591 4592 // For big endian targets, swap the order of the pieces of each element. 4593 if (TLI.isBigEndian()) 4594 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4595 } 4596 4597 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4598 &Ops[0], Ops.size()); 4599} 4600 4601SDValue DAGCombiner::visitFADD(SDNode *N) { 4602 SDValue N0 = N->getOperand(0); 4603 SDValue N1 = N->getOperand(1); 4604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4605 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4606 EVT VT = N->getValueType(0); 4607 4608 // fold vector ops 4609 if (VT.isVector()) { 4610 SDValue FoldedVOp = SimplifyVBinOp(N); 4611 if (FoldedVOp.getNode()) return FoldedVOp; 4612 } 4613 4614 // fold (fadd c1, c2) -> (fadd c1, c2) 4615 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4616 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4617 // canonicalize constant to RHS 4618 if (N0CFP && !N1CFP) 4619 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4620 // fold (fadd A, 0) -> A 4621 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4622 return N0; 4623 // fold (fadd A, (fneg B)) -> (fsub A, B) 4624 if (isNegatibleForFree(N1, LegalOperations) == 2) 4625 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4626 GetNegatedExpression(N1, DAG, LegalOperations)); 4627 // fold (fadd (fneg A), B) -> (fsub B, A) 4628 if (isNegatibleForFree(N0, LegalOperations) == 2) 4629 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4630 GetNegatedExpression(N0, DAG, LegalOperations)); 4631 4632 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4633 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4634 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4635 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4636 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4637 N0.getOperand(1), N1)); 4638 4639 return SDValue(); 4640} 4641 4642SDValue DAGCombiner::visitFSUB(SDNode *N) { 4643 SDValue N0 = N->getOperand(0); 4644 SDValue N1 = N->getOperand(1); 4645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4646 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4647 EVT VT = N->getValueType(0); 4648 4649 // fold vector ops 4650 if (VT.isVector()) { 4651 SDValue FoldedVOp = SimplifyVBinOp(N); 4652 if (FoldedVOp.getNode()) return FoldedVOp; 4653 } 4654 4655 // fold (fsub c1, c2) -> c1-c2 4656 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4657 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4658 // fold (fsub A, 0) -> A 4659 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4660 return N0; 4661 // fold (fsub 0, B) -> -B 4662 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4663 if (isNegatibleForFree(N1, LegalOperations)) 4664 return GetNegatedExpression(N1, DAG, LegalOperations); 4665 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4666 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4667 } 4668 // fold (fsub A, (fneg B)) -> (fadd A, B) 4669 if (isNegatibleForFree(N1, LegalOperations)) 4670 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4671 GetNegatedExpression(N1, DAG, LegalOperations)); 4672 4673 return SDValue(); 4674} 4675 4676SDValue DAGCombiner::visitFMUL(SDNode *N) { 4677 SDValue N0 = N->getOperand(0); 4678 SDValue N1 = N->getOperand(1); 4679 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4680 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4681 EVT VT = N->getValueType(0); 4682 4683 // fold vector ops 4684 if (VT.isVector()) { 4685 SDValue FoldedVOp = SimplifyVBinOp(N); 4686 if (FoldedVOp.getNode()) return FoldedVOp; 4687 } 4688 4689 // fold (fmul c1, c2) -> c1*c2 4690 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4691 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4692 // canonicalize constant to RHS 4693 if (N0CFP && !N1CFP) 4694 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4695 // fold (fmul A, 0) -> 0 4696 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4697 return N1; 4698 // fold (fmul A, 0) -> 0, vector edition. 4699 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4700 return N1; 4701 // fold (fmul X, 2.0) -> (fadd X, X) 4702 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4703 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4704 // fold (fmul X, -1.0) -> (fneg X) 4705 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4706 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4707 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4708 4709 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4710 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4711 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4712 // Both can be negated for free, check to see if at least one is cheaper 4713 // negated. 4714 if (LHSNeg == 2 || RHSNeg == 2) 4715 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4716 GetNegatedExpression(N0, DAG, LegalOperations), 4717 GetNegatedExpression(N1, DAG, LegalOperations)); 4718 } 4719 } 4720 4721 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4722 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4723 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4724 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4725 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4726 N0.getOperand(1), N1)); 4727 4728 return SDValue(); 4729} 4730 4731SDValue DAGCombiner::visitFDIV(SDNode *N) { 4732 SDValue N0 = N->getOperand(0); 4733 SDValue N1 = N->getOperand(1); 4734 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4735 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4736 EVT VT = N->getValueType(0); 4737 4738 // fold vector ops 4739 if (VT.isVector()) { 4740 SDValue FoldedVOp = SimplifyVBinOp(N); 4741 if (FoldedVOp.getNode()) return FoldedVOp; 4742 } 4743 4744 // fold (fdiv c1, c2) -> c1/c2 4745 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4746 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4747 4748 4749 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4750 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4751 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4752 // Both can be negated for free, check to see if at least one is cheaper 4753 // negated. 4754 if (LHSNeg == 2 || RHSNeg == 2) 4755 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4756 GetNegatedExpression(N0, DAG, LegalOperations), 4757 GetNegatedExpression(N1, DAG, LegalOperations)); 4758 } 4759 } 4760 4761 return SDValue(); 4762} 4763 4764SDValue DAGCombiner::visitFREM(SDNode *N) { 4765 SDValue N0 = N->getOperand(0); 4766 SDValue N1 = N->getOperand(1); 4767 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4768 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4769 EVT VT = N->getValueType(0); 4770 4771 // fold (frem c1, c2) -> fmod(c1,c2) 4772 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4773 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4774 4775 return SDValue(); 4776} 4777 4778SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4779 SDValue N0 = N->getOperand(0); 4780 SDValue N1 = N->getOperand(1); 4781 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4782 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4783 EVT VT = N->getValueType(0); 4784 4785 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4786 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4787 4788 if (N1CFP) { 4789 const APFloat& V = N1CFP->getValueAPF(); 4790 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4791 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4792 if (!V.isNegative()) { 4793 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4794 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4795 } else { 4796 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4797 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4798 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4799 } 4800 } 4801 4802 // copysign(fabs(x), y) -> copysign(x, y) 4803 // copysign(fneg(x), y) -> copysign(x, y) 4804 // copysign(copysign(x,z), y) -> copysign(x, y) 4805 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4806 N0.getOpcode() == ISD::FCOPYSIGN) 4807 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4808 N0.getOperand(0), N1); 4809 4810 // copysign(x, abs(y)) -> abs(x) 4811 if (N1.getOpcode() == ISD::FABS) 4812 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4813 4814 // copysign(x, copysign(y,z)) -> copysign(x, z) 4815 if (N1.getOpcode() == ISD::FCOPYSIGN) 4816 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4817 N0, N1.getOperand(1)); 4818 4819 // copysign(x, fp_extend(y)) -> copysign(x, y) 4820 // copysign(x, fp_round(y)) -> copysign(x, y) 4821 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4822 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4823 N0, N1.getOperand(0)); 4824 4825 return SDValue(); 4826} 4827 4828SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4829 SDValue N0 = N->getOperand(0); 4830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4831 EVT VT = N->getValueType(0); 4832 EVT OpVT = N0.getValueType(); 4833 4834 // fold (sint_to_fp c1) -> c1fp 4835 if (N0C && OpVT != MVT::ppcf128) 4836 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4837 4838 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4839 // but UINT_TO_FP is legal on this target, try to convert. 4840 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4841 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4842 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4843 if (DAG.SignBitIsZero(N0)) 4844 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4845 } 4846 4847 return SDValue(); 4848} 4849 4850SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4851 SDValue N0 = N->getOperand(0); 4852 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4853 EVT VT = N->getValueType(0); 4854 EVT OpVT = N0.getValueType(); 4855 4856 // fold (uint_to_fp c1) -> c1fp 4857 if (N0C && OpVT != MVT::ppcf128) 4858 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4859 4860 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4861 // but SINT_TO_FP is legal on this target, try to convert. 4862 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4863 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4864 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4865 if (DAG.SignBitIsZero(N0)) 4866 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4867 } 4868 4869 return SDValue(); 4870} 4871 4872SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4873 SDValue N0 = N->getOperand(0); 4874 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4875 EVT VT = N->getValueType(0); 4876 4877 // fold (fp_to_sint c1fp) -> c1 4878 if (N0CFP) 4879 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4880 4881 return SDValue(); 4882} 4883 4884SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4885 SDValue N0 = N->getOperand(0); 4886 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4887 EVT VT = N->getValueType(0); 4888 4889 // fold (fp_to_uint c1fp) -> c1 4890 if (N0CFP && VT != MVT::ppcf128) 4891 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4892 4893 return SDValue(); 4894} 4895 4896SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4897 SDValue N0 = N->getOperand(0); 4898 SDValue N1 = N->getOperand(1); 4899 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4900 EVT VT = N->getValueType(0); 4901 4902 // fold (fp_round c1fp) -> c1fp 4903 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4904 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4905 4906 // fold (fp_round (fp_extend x)) -> x 4907 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4908 return N0.getOperand(0); 4909 4910 // fold (fp_round (fp_round x)) -> (fp_round x) 4911 if (N0.getOpcode() == ISD::FP_ROUND) { 4912 // This is a value preserving truncation if both round's are. 4913 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4914 N0.getNode()->getConstantOperandVal(1) == 1; 4915 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4916 DAG.getIntPtrConstant(IsTrunc)); 4917 } 4918 4919 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4920 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4921 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4922 N0.getOperand(0), N1); 4923 AddToWorkList(Tmp.getNode()); 4924 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4925 Tmp, N0.getOperand(1)); 4926 } 4927 4928 return SDValue(); 4929} 4930 4931SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4932 SDValue N0 = N->getOperand(0); 4933 EVT VT = N->getValueType(0); 4934 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4935 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4936 4937 // fold (fp_round_inreg c1fp) -> c1fp 4938 if (N0CFP && isTypeLegal(EVT)) { 4939 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4940 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4941 } 4942 4943 return SDValue(); 4944} 4945 4946SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4947 SDValue N0 = N->getOperand(0); 4948 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4949 EVT VT = N->getValueType(0); 4950 4951 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4952 if (N->hasOneUse() && 4953 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4954 return SDValue(); 4955 4956 // fold (fp_extend c1fp) -> c1fp 4957 if (N0CFP && VT != MVT::ppcf128) 4958 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4959 4960 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4961 // value of X. 4962 if (N0.getOpcode() == ISD::FP_ROUND 4963 && N0.getNode()->getConstantOperandVal(1) == 1) { 4964 SDValue In = N0.getOperand(0); 4965 if (In.getValueType() == VT) return In; 4966 if (VT.bitsLT(In.getValueType())) 4967 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4968 In, N0.getOperand(1)); 4969 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4970 } 4971 4972 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4973 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4974 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4975 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4976 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4977 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4978 LN0->getChain(), 4979 LN0->getBasePtr(), LN0->getSrcValue(), 4980 LN0->getSrcValueOffset(), 4981 N0.getValueType(), 4982 LN0->isVolatile(), LN0->isNonTemporal(), 4983 LN0->getAlignment()); 4984 CombineTo(N, ExtLoad); 4985 CombineTo(N0.getNode(), 4986 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4987 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4988 ExtLoad.getValue(1)); 4989 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4990 } 4991 4992 return SDValue(); 4993} 4994 4995SDValue DAGCombiner::visitFNEG(SDNode *N) { 4996 SDValue N0 = N->getOperand(0); 4997 EVT VT = N->getValueType(0); 4998 4999 if (isNegatibleForFree(N0, LegalOperations)) 5000 return GetNegatedExpression(N0, DAG, LegalOperations); 5001 5002 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5003 // constant pool values. 5004 if (N0.getOpcode() == ISD::BIT_CONVERT && 5005 !VT.isVector() && 5006 N0.getNode()->hasOneUse() && 5007 N0.getOperand(0).getValueType().isInteger()) { 5008 SDValue Int = N0.getOperand(0); 5009 EVT IntVT = Int.getValueType(); 5010 if (IntVT.isInteger() && !IntVT.isVector()) { 5011 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5012 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5013 AddToWorkList(Int.getNode()); 5014 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5015 VT, Int); 5016 } 5017 } 5018 5019 return SDValue(); 5020} 5021 5022SDValue DAGCombiner::visitFABS(SDNode *N) { 5023 SDValue N0 = N->getOperand(0); 5024 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5025 EVT VT = N->getValueType(0); 5026 5027 // fold (fabs c1) -> fabs(c1) 5028 if (N0CFP && VT != MVT::ppcf128) 5029 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5030 // fold (fabs (fabs x)) -> (fabs x) 5031 if (N0.getOpcode() == ISD::FABS) 5032 return N->getOperand(0); 5033 // fold (fabs (fneg x)) -> (fabs x) 5034 // fold (fabs (fcopysign x, y)) -> (fabs x) 5035 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5036 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5037 5038 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5039 // constant pool values. 5040 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 5041 N0.getOperand(0).getValueType().isInteger() && 5042 !N0.getOperand(0).getValueType().isVector()) { 5043 SDValue Int = N0.getOperand(0); 5044 EVT IntVT = Int.getValueType(); 5045 if (IntVT.isInteger() && !IntVT.isVector()) { 5046 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5047 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5048 AddToWorkList(Int.getNode()); 5049 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 5050 N->getValueType(0), Int); 5051 } 5052 } 5053 5054 return SDValue(); 5055} 5056 5057SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5058 SDValue Chain = N->getOperand(0); 5059 SDValue N1 = N->getOperand(1); 5060 SDValue N2 = N->getOperand(2); 5061 5062 // If N is a constant we could fold this into a fallthrough or unconditional 5063 // branch. However that doesn't happen very often in normal code, because 5064 // Instcombine/SimplifyCFG should have handled the available opportunities. 5065 // If we did this folding here, it would be necessary to update the 5066 // MachineBasicBlock CFG, which is awkward. 5067 5068 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5069 // on the target. 5070 if (N1.getOpcode() == ISD::SETCC && 5071 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5072 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5073 Chain, N1.getOperand(2), 5074 N1.getOperand(0), N1.getOperand(1), N2); 5075 } 5076 5077 SDNode *Trunc = 0; 5078 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 5079 // Look past truncate. 5080 Trunc = N1.getNode(); 5081 N1 = N1.getOperand(0); 5082 } 5083 5084 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 5085 // Match this pattern so that we can generate simpler code: 5086 // 5087 // %a = ... 5088 // %b = and i32 %a, 2 5089 // %c = srl i32 %b, 1 5090 // brcond i32 %c ... 5091 // 5092 // into 5093 // 5094 // %a = ... 5095 // %b = and i32 %a, 2 5096 // %c = setcc eq %b, 0 5097 // brcond %c ... 5098 // 5099 // This applies only when the AND constant value has one bit set and the 5100 // SRL constant is equal to the log2 of the AND constant. The back-end is 5101 // smart enough to convert the result into a TEST/JMP sequence. 5102 SDValue Op0 = N1.getOperand(0); 5103 SDValue Op1 = N1.getOperand(1); 5104 5105 if (Op0.getOpcode() == ISD::AND && 5106 Op1.getOpcode() == ISD::Constant) { 5107 SDValue AndOp1 = Op0.getOperand(1); 5108 5109 if (AndOp1.getOpcode() == ISD::Constant) { 5110 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5111 5112 if (AndConst.isPowerOf2() && 5113 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5114 SDValue SetCC = 5115 DAG.getSetCC(N->getDebugLoc(), 5116 TLI.getSetCCResultType(Op0.getValueType()), 5117 Op0, DAG.getConstant(0, Op0.getValueType()), 5118 ISD::SETNE); 5119 5120 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5121 MVT::Other, Chain, SetCC, N2); 5122 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5123 // will convert it back to (X & C1) >> C2. 5124 CombineTo(N, NewBRCond, false); 5125 // Truncate is dead. 5126 if (Trunc) { 5127 removeFromWorkList(Trunc); 5128 DAG.DeleteNode(Trunc); 5129 } 5130 // Replace the uses of SRL with SETCC 5131 WorkListRemover DeadNodes(*this); 5132 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5133 removeFromWorkList(N1.getNode()); 5134 DAG.DeleteNode(N1.getNode()); 5135 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5136 } 5137 } 5138 } 5139 } 5140 5141 // Transform br(xor(x, y)) -> br(x != y) 5142 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5143 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5144 SDNode *TheXor = N1.getNode(); 5145 SDValue Op0 = TheXor->getOperand(0); 5146 SDValue Op1 = TheXor->getOperand(1); 5147 if (Op0.getOpcode() == Op1.getOpcode()) { 5148 // Avoid missing important xor optimizations. 5149 SDValue Tmp = visitXOR(TheXor); 5150 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5151 DEBUG(dbgs() << "\nReplacing.8 "; 5152 TheXor->dump(&DAG); 5153 dbgs() << "\nWith: "; 5154 Tmp.getNode()->dump(&DAG); 5155 dbgs() << '\n'); 5156 WorkListRemover DeadNodes(*this); 5157 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5158 removeFromWorkList(TheXor); 5159 DAG.DeleteNode(TheXor); 5160 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5161 MVT::Other, Chain, Tmp, N2); 5162 } 5163 } 5164 5165 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5166 bool Equal = false; 5167 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5168 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5169 Op0.getOpcode() == ISD::XOR) { 5170 TheXor = Op0.getNode(); 5171 Equal = true; 5172 } 5173 5174 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 5175 5176 EVT SetCCVT = NodeToReplace.getValueType(); 5177 if (LegalTypes) 5178 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5179 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5180 SetCCVT, 5181 Op0, Op1, 5182 Equal ? ISD::SETEQ : ISD::SETNE); 5183 // Replace the uses of XOR with SETCC 5184 WorkListRemover DeadNodes(*this); 5185 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 5186 removeFromWorkList(NodeToReplace.getNode()); 5187 DAG.DeleteNode(NodeToReplace.getNode()); 5188 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5189 MVT::Other, Chain, SetCC, N2); 5190 } 5191 } 5192 5193 return SDValue(); 5194} 5195 5196// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5197// 5198SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5199 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5200 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5201 5202 // If N is a constant we could fold this into a fallthrough or unconditional 5203 // branch. However that doesn't happen very often in normal code, because 5204 // Instcombine/SimplifyCFG should have handled the available opportunities. 5205 // If we did this folding here, it would be necessary to update the 5206 // MachineBasicBlock CFG, which is awkward. 5207 5208 // Use SimplifySetCC to simplify SETCC's. 5209 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5210 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5211 false); 5212 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5213 5214 // fold to a simpler setcc 5215 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5216 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5217 N->getOperand(0), Simp.getOperand(2), 5218 Simp.getOperand(0), Simp.getOperand(1), 5219 N->getOperand(4)); 5220 5221 return SDValue(); 5222} 5223 5224/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5225/// pre-indexed load / store when the base pointer is an add or subtract 5226/// and it has other uses besides the load / store. After the 5227/// transformation, the new indexed load / store has effectively folded 5228/// the add / subtract in and all of its other uses are redirected to the 5229/// new load / store. 5230bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5231 if (!LegalOperations) 5232 return false; 5233 5234 bool isLoad = true; 5235 SDValue Ptr; 5236 EVT VT; 5237 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5238 if (LD->isIndexed()) 5239 return false; 5240 VT = LD->getMemoryVT(); 5241 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5242 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5243 return false; 5244 Ptr = LD->getBasePtr(); 5245 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5246 if (ST->isIndexed()) 5247 return false; 5248 VT = ST->getMemoryVT(); 5249 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5250 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5251 return false; 5252 Ptr = ST->getBasePtr(); 5253 isLoad = false; 5254 } else { 5255 return false; 5256 } 5257 5258 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5259 // out. There is no reason to make this a preinc/predec. 5260 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5261 Ptr.getNode()->hasOneUse()) 5262 return false; 5263 5264 // Ask the target to do addressing mode selection. 5265 SDValue BasePtr; 5266 SDValue Offset; 5267 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5268 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5269 return false; 5270 // Don't create a indexed load / store with zero offset. 5271 if (isa<ConstantSDNode>(Offset) && 5272 cast<ConstantSDNode>(Offset)->isNullValue()) 5273 return false; 5274 5275 // Try turning it into a pre-indexed load / store except when: 5276 // 1) The new base ptr is a frame index. 5277 // 2) If N is a store and the new base ptr is either the same as or is a 5278 // predecessor of the value being stored. 5279 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5280 // that would create a cycle. 5281 // 4) All uses are load / store ops that use it as old base ptr. 5282 5283 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5284 // (plus the implicit offset) to a register to preinc anyway. 5285 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5286 return false; 5287 5288 // Check #2. 5289 if (!isLoad) { 5290 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5291 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5292 return false; 5293 } 5294 5295 // Now check for #3 and #4. 5296 bool RealUse = false; 5297 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5298 E = Ptr.getNode()->use_end(); I != E; ++I) { 5299 SDNode *Use = *I; 5300 if (Use == N) 5301 continue; 5302 if (Use->isPredecessorOf(N)) 5303 return false; 5304 5305 if (!((Use->getOpcode() == ISD::LOAD && 5306 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5307 (Use->getOpcode() == ISD::STORE && 5308 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5309 RealUse = true; 5310 } 5311 5312 if (!RealUse) 5313 return false; 5314 5315 SDValue Result; 5316 if (isLoad) 5317 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5318 BasePtr, Offset, AM); 5319 else 5320 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5321 BasePtr, Offset, AM); 5322 ++PreIndexedNodes; 5323 ++NodesCombined; 5324 DEBUG(dbgs() << "\nReplacing.4 "; 5325 N->dump(&DAG); 5326 dbgs() << "\nWith: "; 5327 Result.getNode()->dump(&DAG); 5328 dbgs() << '\n'); 5329 WorkListRemover DeadNodes(*this); 5330 if (isLoad) { 5331 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5332 &DeadNodes); 5333 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5334 &DeadNodes); 5335 } else { 5336 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5337 &DeadNodes); 5338 } 5339 5340 // Finally, since the node is now dead, remove it from the graph. 5341 DAG.DeleteNode(N); 5342 5343 // Replace the uses of Ptr with uses of the updated base value. 5344 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5345 &DeadNodes); 5346 removeFromWorkList(Ptr.getNode()); 5347 DAG.DeleteNode(Ptr.getNode()); 5348 5349 return true; 5350} 5351 5352/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5353/// add / sub of the base pointer node into a post-indexed load / store. 5354/// The transformation folded the add / subtract into the new indexed 5355/// load / store effectively and all of its uses are redirected to the 5356/// new load / store. 5357bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5358 if (!LegalOperations) 5359 return false; 5360 5361 bool isLoad = true; 5362 SDValue Ptr; 5363 EVT VT; 5364 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5365 if (LD->isIndexed()) 5366 return false; 5367 VT = LD->getMemoryVT(); 5368 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5369 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5370 return false; 5371 Ptr = LD->getBasePtr(); 5372 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5373 if (ST->isIndexed()) 5374 return false; 5375 VT = ST->getMemoryVT(); 5376 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5377 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5378 return false; 5379 Ptr = ST->getBasePtr(); 5380 isLoad = false; 5381 } else { 5382 return false; 5383 } 5384 5385 if (Ptr.getNode()->hasOneUse()) 5386 return false; 5387 5388 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5389 E = Ptr.getNode()->use_end(); I != E; ++I) { 5390 SDNode *Op = *I; 5391 if (Op == N || 5392 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5393 continue; 5394 5395 SDValue BasePtr; 5396 SDValue Offset; 5397 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5398 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5399 // Don't create a indexed load / store with zero offset. 5400 if (isa<ConstantSDNode>(Offset) && 5401 cast<ConstantSDNode>(Offset)->isNullValue()) 5402 continue; 5403 5404 // Try turning it into a post-indexed load / store except when 5405 // 1) All uses are load / store ops that use it as base ptr. 5406 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5407 // nor a successor of N. Otherwise, if Op is folded that would 5408 // create a cycle. 5409 5410 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5411 continue; 5412 5413 // Check for #1. 5414 bool TryNext = false; 5415 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5416 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5417 SDNode *Use = *II; 5418 if (Use == Ptr.getNode()) 5419 continue; 5420 5421 // If all the uses are load / store addresses, then don't do the 5422 // transformation. 5423 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5424 bool RealUse = false; 5425 for (SDNode::use_iterator III = Use->use_begin(), 5426 EEE = Use->use_end(); III != EEE; ++III) { 5427 SDNode *UseUse = *III; 5428 if (!((UseUse->getOpcode() == ISD::LOAD && 5429 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5430 (UseUse->getOpcode() == ISD::STORE && 5431 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5432 RealUse = true; 5433 } 5434 5435 if (!RealUse) { 5436 TryNext = true; 5437 break; 5438 } 5439 } 5440 } 5441 5442 if (TryNext) 5443 continue; 5444 5445 // Check for #2 5446 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5447 SDValue Result = isLoad 5448 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5449 BasePtr, Offset, AM) 5450 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5451 BasePtr, Offset, AM); 5452 ++PostIndexedNodes; 5453 ++NodesCombined; 5454 DEBUG(dbgs() << "\nReplacing.5 "; 5455 N->dump(&DAG); 5456 dbgs() << "\nWith: "; 5457 Result.getNode()->dump(&DAG); 5458 dbgs() << '\n'); 5459 WorkListRemover DeadNodes(*this); 5460 if (isLoad) { 5461 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5462 &DeadNodes); 5463 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5464 &DeadNodes); 5465 } else { 5466 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5467 &DeadNodes); 5468 } 5469 5470 // Finally, since the node is now dead, remove it from the graph. 5471 DAG.DeleteNode(N); 5472 5473 // Replace the uses of Use with uses of the updated base value. 5474 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5475 Result.getValue(isLoad ? 1 : 0), 5476 &DeadNodes); 5477 removeFromWorkList(Op); 5478 DAG.DeleteNode(Op); 5479 return true; 5480 } 5481 } 5482 } 5483 5484 return false; 5485} 5486 5487SDValue DAGCombiner::visitLOAD(SDNode *N) { 5488 LoadSDNode *LD = cast<LoadSDNode>(N); 5489 SDValue Chain = LD->getChain(); 5490 SDValue Ptr = LD->getBasePtr(); 5491 5492 // If load is not volatile and there are no uses of the loaded value (and 5493 // the updated indexed value in case of indexed loads), change uses of the 5494 // chain value into uses of the chain input (i.e. delete the dead load). 5495 if (!LD->isVolatile()) { 5496 if (N->getValueType(1) == MVT::Other) { 5497 // Unindexed loads. 5498 if (N->hasNUsesOfValue(0, 0)) { 5499 // It's not safe to use the two value CombineTo variant here. e.g. 5500 // v1, chain2 = load chain1, loc 5501 // v2, chain3 = load chain2, loc 5502 // v3 = add v2, c 5503 // Now we replace use of chain2 with chain1. This makes the second load 5504 // isomorphic to the one we are deleting, and thus makes this load live. 5505 DEBUG(dbgs() << "\nReplacing.6 "; 5506 N->dump(&DAG); 5507 dbgs() << "\nWith chain: "; 5508 Chain.getNode()->dump(&DAG); 5509 dbgs() << "\n"); 5510 WorkListRemover DeadNodes(*this); 5511 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5512 5513 if (N->use_empty()) { 5514 removeFromWorkList(N); 5515 DAG.DeleteNode(N); 5516 } 5517 5518 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5519 } 5520 } else { 5521 // Indexed loads. 5522 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5523 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5524 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5525 DEBUG(dbgs() << "\nReplacing.7 "; 5526 N->dump(&DAG); 5527 dbgs() << "\nWith: "; 5528 Undef.getNode()->dump(&DAG); 5529 dbgs() << " and 2 other values\n"); 5530 WorkListRemover DeadNodes(*this); 5531 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5532 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5533 DAG.getUNDEF(N->getValueType(1)), 5534 &DeadNodes); 5535 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5536 removeFromWorkList(N); 5537 DAG.DeleteNode(N); 5538 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5539 } 5540 } 5541 } 5542 5543 // If this load is directly stored, replace the load value with the stored 5544 // value. 5545 // TODO: Handle store large -> read small portion. 5546 // TODO: Handle TRUNCSTORE/LOADEXT 5547 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5548 !LD->isVolatile()) { 5549 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5550 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5551 if (PrevST->getBasePtr() == Ptr && 5552 PrevST->getValue().getValueType() == N->getValueType(0)) 5553 return CombineTo(N, Chain.getOperand(1), Chain); 5554 } 5555 } 5556 5557 // Try to infer better alignment information than the load already has. 5558 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5559 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5560 if (Align > LD->getAlignment()) 5561 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5562 LD->getValueType(0), 5563 Chain, Ptr, LD->getSrcValue(), 5564 LD->getSrcValueOffset(), LD->getMemoryVT(), 5565 LD->isVolatile(), LD->isNonTemporal(), Align); 5566 } 5567 } 5568 5569 if (CombinerAA) { 5570 // Walk up chain skipping non-aliasing memory nodes. 5571 SDValue BetterChain = FindBetterChain(N, Chain); 5572 5573 // If there is a better chain. 5574 if (Chain != BetterChain) { 5575 SDValue ReplLoad; 5576 5577 // Replace the chain to void dependency. 5578 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5579 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5580 BetterChain, Ptr, 5581 LD->getSrcValue(), LD->getSrcValueOffset(), 5582 LD->isVolatile(), LD->isNonTemporal(), 5583 LD->getAlignment()); 5584 } else { 5585 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5586 LD->getValueType(0), 5587 BetterChain, Ptr, LD->getSrcValue(), 5588 LD->getSrcValueOffset(), 5589 LD->getMemoryVT(), 5590 LD->isVolatile(), 5591 LD->isNonTemporal(), 5592 LD->getAlignment()); 5593 } 5594 5595 // Create token factor to keep old chain connected. 5596 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5597 MVT::Other, Chain, ReplLoad.getValue(1)); 5598 5599 // Make sure the new and old chains are cleaned up. 5600 AddToWorkList(Token.getNode()); 5601 5602 // Replace uses with load result and token factor. Don't add users 5603 // to work list. 5604 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5605 } 5606 } 5607 5608 // Try transforming N to an indexed load. 5609 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5610 return SDValue(N, 0); 5611 5612 return SDValue(); 5613} 5614 5615/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5616/// load is having specific bytes cleared out. If so, return the byte size 5617/// being masked out and the shift amount. 5618static std::pair<unsigned, unsigned> 5619CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5620 std::pair<unsigned, unsigned> Result(0, 0); 5621 5622 // Check for the structure we're looking for. 5623 if (V->getOpcode() != ISD::AND || 5624 !isa<ConstantSDNode>(V->getOperand(1)) || 5625 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5626 return Result; 5627 5628 // Check the chain and pointer. 5629 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5630 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5631 5632 // The store should be chained directly to the load or be an operand of a 5633 // tokenfactor. 5634 if (LD == Chain.getNode()) 5635 ; // ok. 5636 else if (Chain->getOpcode() != ISD::TokenFactor) 5637 return Result; // Fail. 5638 else { 5639 bool isOk = false; 5640 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5641 if (Chain->getOperand(i).getNode() == LD) { 5642 isOk = true; 5643 break; 5644 } 5645 if (!isOk) return Result; 5646 } 5647 5648 // This only handles simple types. 5649 if (V.getValueType() != MVT::i16 && 5650 V.getValueType() != MVT::i32 && 5651 V.getValueType() != MVT::i64) 5652 return Result; 5653 5654 // Check the constant mask. Invert it so that the bits being masked out are 5655 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5656 // follow the sign bit for uniformity. 5657 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5658 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5659 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5660 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5661 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5662 if (NotMaskLZ == 64) return Result; // All zero mask. 5663 5664 // See if we have a continuous run of bits. If so, we have 0*1+0* 5665 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5666 return Result; 5667 5668 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5669 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5670 NotMaskLZ -= 64-V.getValueSizeInBits(); 5671 5672 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5673 switch (MaskedBytes) { 5674 case 1: 5675 case 2: 5676 case 4: break; 5677 default: return Result; // All one mask, or 5-byte mask. 5678 } 5679 5680 // Verify that the first bit starts at a multiple of mask so that the access 5681 // is aligned the same as the access width. 5682 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5683 5684 Result.first = MaskedBytes; 5685 Result.second = NotMaskTZ/8; 5686 return Result; 5687} 5688 5689 5690/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5691/// provides a value as specified by MaskInfo. If so, replace the specified 5692/// store with a narrower store of truncated IVal. 5693static SDNode * 5694ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5695 SDValue IVal, StoreSDNode *St, 5696 DAGCombiner *DC) { 5697 unsigned NumBytes = MaskInfo.first; 5698 unsigned ByteShift = MaskInfo.second; 5699 SelectionDAG &DAG = DC->getDAG(); 5700 5701 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5702 // that uses this. If not, this is not a replacement. 5703 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5704 ByteShift*8, (ByteShift+NumBytes)*8); 5705 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5706 5707 // Check that it is legal on the target to do this. It is legal if the new 5708 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5709 // legalization. 5710 MVT VT = MVT::getIntegerVT(NumBytes*8); 5711 if (!DC->isTypeLegal(VT)) 5712 return 0; 5713 5714 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5715 // shifted by ByteShift and truncated down to NumBytes. 5716 if (ByteShift) 5717 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5718 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5719 5720 // Figure out the offset for the store and the alignment of the access. 5721 unsigned StOffset; 5722 unsigned NewAlign = St->getAlignment(); 5723 5724 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5725 StOffset = ByteShift; 5726 else 5727 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5728 5729 SDValue Ptr = St->getBasePtr(); 5730 if (StOffset) { 5731 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5732 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5733 NewAlign = MinAlign(NewAlign, StOffset); 5734 } 5735 5736 // Truncate down to the new size. 5737 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5738 5739 ++OpsNarrowed; 5740 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5741 St->getSrcValue(), St->getSrcValueOffset()+StOffset, 5742 false, false, NewAlign).getNode(); 5743} 5744 5745 5746/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5747/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5748/// of the loaded bits, try narrowing the load and store if it would end up 5749/// being a win for performance or code size. 5750SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5751 StoreSDNode *ST = cast<StoreSDNode>(N); 5752 if (ST->isVolatile()) 5753 return SDValue(); 5754 5755 SDValue Chain = ST->getChain(); 5756 SDValue Value = ST->getValue(); 5757 SDValue Ptr = ST->getBasePtr(); 5758 EVT VT = Value.getValueType(); 5759 5760 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5761 return SDValue(); 5762 5763 unsigned Opc = Value.getOpcode(); 5764 5765 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5766 // is a byte mask indicating a consecutive number of bytes, check to see if 5767 // Y is known to provide just those bytes. If so, we try to replace the 5768 // load + replace + store sequence with a single (narrower) store, which makes 5769 // the load dead. 5770 if (Opc == ISD::OR) { 5771 std::pair<unsigned, unsigned> MaskedLoad; 5772 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5773 if (MaskedLoad.first) 5774 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5775 Value.getOperand(1), ST,this)) 5776 return SDValue(NewST, 0); 5777 5778 // Or is commutative, so try swapping X and Y. 5779 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5780 if (MaskedLoad.first) 5781 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5782 Value.getOperand(0), ST,this)) 5783 return SDValue(NewST, 0); 5784 } 5785 5786 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5787 Value.getOperand(1).getOpcode() != ISD::Constant) 5788 return SDValue(); 5789 5790 SDValue N0 = Value.getOperand(0); 5791 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5792 LoadSDNode *LD = cast<LoadSDNode>(N0); 5793 if (LD->getBasePtr() != Ptr) 5794 return SDValue(); 5795 5796 // Find the type to narrow it the load / op / store to. 5797 SDValue N1 = Value.getOperand(1); 5798 unsigned BitWidth = N1.getValueSizeInBits(); 5799 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5800 if (Opc == ISD::AND) 5801 Imm ^= APInt::getAllOnesValue(BitWidth); 5802 if (Imm == 0 || Imm.isAllOnesValue()) 5803 return SDValue(); 5804 unsigned ShAmt = Imm.countTrailingZeros(); 5805 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5806 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5807 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5808 while (NewBW < BitWidth && 5809 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5810 TLI.isNarrowingProfitable(VT, NewVT))) { 5811 NewBW = NextPowerOf2(NewBW); 5812 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5813 } 5814 if (NewBW >= BitWidth) 5815 return SDValue(); 5816 5817 // If the lsb changed does not start at the type bitwidth boundary, 5818 // start at the previous one. 5819 if (ShAmt % NewBW) 5820 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5821 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5822 if ((Imm & Mask) == Imm) { 5823 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5824 if (Opc == ISD::AND) 5825 NewImm ^= APInt::getAllOnesValue(NewBW); 5826 uint64_t PtrOff = ShAmt / 8; 5827 // For big endian targets, we need to adjust the offset to the pointer to 5828 // load the correct bytes. 5829 if (TLI.isBigEndian()) 5830 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5831 5832 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5833 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5834 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5835 return SDValue(); 5836 5837 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5838 Ptr.getValueType(), Ptr, 5839 DAG.getConstant(PtrOff, Ptr.getValueType())); 5840 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5841 LD->getChain(), NewPtr, 5842 LD->getSrcValue(), LD->getSrcValueOffset(), 5843 LD->isVolatile(), LD->isNonTemporal(), 5844 NewAlign); 5845 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5846 DAG.getConstant(NewImm, NewVT)); 5847 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5848 NewVal, NewPtr, 5849 ST->getSrcValue(), ST->getSrcValueOffset(), 5850 false, false, NewAlign); 5851 5852 AddToWorkList(NewPtr.getNode()); 5853 AddToWorkList(NewLD.getNode()); 5854 AddToWorkList(NewVal.getNode()); 5855 WorkListRemover DeadNodes(*this); 5856 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5857 &DeadNodes); 5858 ++OpsNarrowed; 5859 return NewST; 5860 } 5861 } 5862 5863 return SDValue(); 5864} 5865 5866SDValue DAGCombiner::visitSTORE(SDNode *N) { 5867 StoreSDNode *ST = cast<StoreSDNode>(N); 5868 SDValue Chain = ST->getChain(); 5869 SDValue Value = ST->getValue(); 5870 SDValue Ptr = ST->getBasePtr(); 5871 5872 // If this is a store of a bit convert, store the input value if the 5873 // resultant store does not need a higher alignment than the original. 5874 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5875 ST->isUnindexed()) { 5876 unsigned OrigAlign = ST->getAlignment(); 5877 EVT SVT = Value.getOperand(0).getValueType(); 5878 unsigned Align = TLI.getTargetData()-> 5879 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5880 if (Align <= OrigAlign && 5881 ((!LegalOperations && !ST->isVolatile()) || 5882 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5883 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5884 Ptr, ST->getSrcValue(), 5885 ST->getSrcValueOffset(), ST->isVolatile(), 5886 ST->isNonTemporal(), OrigAlign); 5887 } 5888 5889 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5890 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5891 // NOTE: If the original store is volatile, this transform must not increase 5892 // the number of stores. For example, on x86-32 an f64 can be stored in one 5893 // processor operation but an i64 (which is not legal) requires two. So the 5894 // transform should not be done in this case. 5895 if (Value.getOpcode() != ISD::TargetConstantFP) { 5896 SDValue Tmp; 5897 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5898 default: llvm_unreachable("Unknown FP type"); 5899 case MVT::f80: // We don't do this for these yet. 5900 case MVT::f128: 5901 case MVT::ppcf128: 5902 break; 5903 case MVT::f32: 5904 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5905 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5906 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5907 bitcastToAPInt().getZExtValue(), MVT::i32); 5908 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5909 Ptr, ST->getSrcValue(), 5910 ST->getSrcValueOffset(), ST->isVolatile(), 5911 ST->isNonTemporal(), ST->getAlignment()); 5912 } 5913 break; 5914 case MVT::f64: 5915 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5916 !ST->isVolatile()) || 5917 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5918 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5919 getZExtValue(), MVT::i64); 5920 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5921 Ptr, ST->getSrcValue(), 5922 ST->getSrcValueOffset(), ST->isVolatile(), 5923 ST->isNonTemporal(), ST->getAlignment()); 5924 } else if (!ST->isVolatile() && 5925 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5926 // Many FP stores are not made apparent until after legalize, e.g. for 5927 // argument passing. Since this is so common, custom legalize the 5928 // 64-bit integer store into two 32-bit stores. 5929 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5930 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5931 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5932 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5933 5934 int SVOffset = ST->getSrcValueOffset(); 5935 unsigned Alignment = ST->getAlignment(); 5936 bool isVolatile = ST->isVolatile(); 5937 bool isNonTemporal = ST->isNonTemporal(); 5938 5939 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5940 Ptr, ST->getSrcValue(), 5941 ST->getSrcValueOffset(), 5942 isVolatile, isNonTemporal, 5943 ST->getAlignment()); 5944 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5945 DAG.getConstant(4, Ptr.getValueType())); 5946 SVOffset += 4; 5947 Alignment = MinAlign(Alignment, 4U); 5948 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5949 Ptr, ST->getSrcValue(), 5950 SVOffset, isVolatile, isNonTemporal, 5951 Alignment); 5952 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5953 St0, St1); 5954 } 5955 5956 break; 5957 } 5958 } 5959 } 5960 5961 // Try to infer better alignment information than the store already has. 5962 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5963 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5964 if (Align > ST->getAlignment()) 5965 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5966 Ptr, ST->getSrcValue(), 5967 ST->getSrcValueOffset(), ST->getMemoryVT(), 5968 ST->isVolatile(), ST->isNonTemporal(), Align); 5969 } 5970 } 5971 5972 if (CombinerAA) { 5973 // Walk up chain skipping non-aliasing memory nodes. 5974 SDValue BetterChain = FindBetterChain(N, Chain); 5975 5976 // If there is a better chain. 5977 if (Chain != BetterChain) { 5978 SDValue ReplStore; 5979 5980 // Replace the chain to avoid dependency. 5981 if (ST->isTruncatingStore()) { 5982 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5983 ST->getSrcValue(),ST->getSrcValueOffset(), 5984 ST->getMemoryVT(), ST->isVolatile(), 5985 ST->isNonTemporal(), ST->getAlignment()); 5986 } else { 5987 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5988 ST->getSrcValue(), ST->getSrcValueOffset(), 5989 ST->isVolatile(), ST->isNonTemporal(), 5990 ST->getAlignment()); 5991 } 5992 5993 // Create token to keep both nodes around. 5994 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5995 MVT::Other, Chain, ReplStore); 5996 5997 // Make sure the new and old chains are cleaned up. 5998 AddToWorkList(Token.getNode()); 5999 6000 // Don't add users to work list. 6001 return CombineTo(N, Token, false); 6002 } 6003 } 6004 6005 // Try transforming N to an indexed store. 6006 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6007 return SDValue(N, 0); 6008 6009 // FIXME: is there such a thing as a truncating indexed store? 6010 if (ST->isTruncatingStore() && ST->isUnindexed() && 6011 Value.getValueType().isInteger()) { 6012 // See if we can simplify the input to this truncstore with knowledge that 6013 // only the low bits are being used. For example: 6014 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6015 SDValue Shorter = 6016 GetDemandedBits(Value, 6017 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6018 ST->getMemoryVT().getSizeInBits())); 6019 AddToWorkList(Value.getNode()); 6020 if (Shorter.getNode()) 6021 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6022 Ptr, ST->getSrcValue(), 6023 ST->getSrcValueOffset(), ST->getMemoryVT(), 6024 ST->isVolatile(), ST->isNonTemporal(), 6025 ST->getAlignment()); 6026 6027 // Otherwise, see if we can simplify the operation with 6028 // SimplifyDemandedBits, which only works if the value has a single use. 6029 if (SimplifyDemandedBits(Value, 6030 APInt::getLowBitsSet( 6031 Value.getValueType().getScalarType().getSizeInBits(), 6032 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6033 return SDValue(N, 0); 6034 } 6035 6036 // If this is a load followed by a store to the same location, then the store 6037 // is dead/noop. 6038 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6039 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6040 ST->isUnindexed() && !ST->isVolatile() && 6041 // There can't be any side effects between the load and store, such as 6042 // a call or store. 6043 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6044 // The store is dead, remove it. 6045 return Chain; 6046 } 6047 } 6048 6049 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6050 // truncating store. We can do this even if this is already a truncstore. 6051 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6052 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6053 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6054 ST->getMemoryVT())) { 6055 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6056 Ptr, ST->getSrcValue(), 6057 ST->getSrcValueOffset(), ST->getMemoryVT(), 6058 ST->isVolatile(), ST->isNonTemporal(), 6059 ST->getAlignment()); 6060 } 6061 6062 return ReduceLoadOpStoreWidth(N); 6063} 6064 6065SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6066 SDValue InVec = N->getOperand(0); 6067 SDValue InVal = N->getOperand(1); 6068 SDValue EltNo = N->getOperand(2); 6069 6070 // If the inserted element is an UNDEF, just use the input vector. 6071 if (InVal.getOpcode() == ISD::UNDEF) 6072 return InVec; 6073 6074 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6075 // vector with the inserted element. 6076 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6077 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6078 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6079 InVec.getNode()->op_end()); 6080 if (Elt < Ops.size()) 6081 Ops[Elt] = InVal; 6082 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6083 InVec.getValueType(), &Ops[0], Ops.size()); 6084 } 6085 // If the invec is an UNDEF and if EltNo is a constant, create a new 6086 // BUILD_VECTOR with undef elements and the inserted element. 6087 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6088 isa<ConstantSDNode>(EltNo)) { 6089 EVT VT = InVec.getValueType(); 6090 EVT EltVT = VT.getVectorElementType(); 6091 unsigned NElts = VT.getVectorNumElements(); 6092 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6093 6094 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6095 if (Elt < Ops.size()) 6096 Ops[Elt] = InVal; 6097 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6098 InVec.getValueType(), &Ops[0], Ops.size()); 6099 } 6100 return SDValue(); 6101} 6102 6103SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6104 // (vextract (scalar_to_vector val, 0) -> val 6105 SDValue InVec = N->getOperand(0); 6106 6107 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6108 // Check if the result type doesn't match the inserted element type. A 6109 // SCALAR_TO_VECTOR may truncate the inserted element and the 6110 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6111 EVT EltVT = InVec.getValueType().getVectorElementType(); 6112 SDValue InOp = InVec.getOperand(0); 6113 EVT NVT = N->getValueType(0); 6114 if (InOp.getValueType() != NVT) { 6115 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6116 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6117 } 6118 return InOp; 6119 } 6120 6121 // Perform only after legalization to ensure build_vector / vector_shuffle 6122 // optimizations have already been done. 6123 if (!LegalOperations) return SDValue(); 6124 6125 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6126 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6127 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6128 SDValue EltNo = N->getOperand(1); 6129 6130 if (isa<ConstantSDNode>(EltNo)) { 6131 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6132 bool NewLoad = false; 6133 bool BCNumEltsChanged = false; 6134 EVT VT = InVec.getValueType(); 6135 EVT ExtVT = VT.getVectorElementType(); 6136 EVT LVT = ExtVT; 6137 6138 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 6139 EVT BCVT = InVec.getOperand(0).getValueType(); 6140 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6141 return SDValue(); 6142 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6143 BCNumEltsChanged = true; 6144 InVec = InVec.getOperand(0); 6145 ExtVT = BCVT.getVectorElementType(); 6146 NewLoad = true; 6147 } 6148 6149 LoadSDNode *LN0 = NULL; 6150 const ShuffleVectorSDNode *SVN = NULL; 6151 if (ISD::isNormalLoad(InVec.getNode())) { 6152 LN0 = cast<LoadSDNode>(InVec); 6153 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6154 InVec.getOperand(0).getValueType() == ExtVT && 6155 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6156 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6157 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6158 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6159 // => 6160 // (load $addr+1*size) 6161 6162 // If the bit convert changed the number of elements, it is unsafe 6163 // to examine the mask. 6164 if (BCNumEltsChanged) 6165 return SDValue(); 6166 6167 // Select the input vector, guarding against out of range extract vector. 6168 unsigned NumElems = VT.getVectorNumElements(); 6169 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 6170 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6171 6172 if (InVec.getOpcode() == ISD::BIT_CONVERT) 6173 InVec = InVec.getOperand(0); 6174 if (ISD::isNormalLoad(InVec.getNode())) { 6175 LN0 = cast<LoadSDNode>(InVec); 6176 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6177 } 6178 } 6179 6180 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6181 return SDValue(); 6182 6183 unsigned Align = LN0->getAlignment(); 6184 if (NewLoad) { 6185 // Check the resultant load doesn't need a higher alignment than the 6186 // original load. 6187 unsigned NewAlign = 6188 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6189 6190 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6191 return SDValue(); 6192 6193 Align = NewAlign; 6194 } 6195 6196 SDValue NewPtr = LN0->getBasePtr(); 6197 if (Elt) { 6198 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 6199 EVT PtrType = NewPtr.getValueType(); 6200 if (TLI.isBigEndian()) 6201 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6202 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6203 DAG.getConstant(PtrOff, PtrType)); 6204 } 6205 6206 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6207 LN0->getSrcValue(), LN0->getSrcValueOffset(), 6208 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6209 } 6210 6211 return SDValue(); 6212} 6213 6214SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6215 unsigned NumInScalars = N->getNumOperands(); 6216 EVT VT = N->getValueType(0); 6217 6218 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6219 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6220 // at most two distinct vectors, turn this into a shuffle node. 6221 SDValue VecIn1, VecIn2; 6222 for (unsigned i = 0; i != NumInScalars; ++i) { 6223 // Ignore undef inputs. 6224 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6225 6226 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6227 // constant index, bail out. 6228 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6229 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6230 VecIn1 = VecIn2 = SDValue(0, 0); 6231 break; 6232 } 6233 6234 // If the input vector type disagrees with the result of the build_vector, 6235 // we can't make a shuffle. 6236 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6237 if (ExtractedFromVec.getValueType() != VT) { 6238 VecIn1 = VecIn2 = SDValue(0, 0); 6239 break; 6240 } 6241 6242 // Otherwise, remember this. We allow up to two distinct input vectors. 6243 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6244 continue; 6245 6246 if (VecIn1.getNode() == 0) { 6247 VecIn1 = ExtractedFromVec; 6248 } else if (VecIn2.getNode() == 0) { 6249 VecIn2 = ExtractedFromVec; 6250 } else { 6251 // Too many inputs. 6252 VecIn1 = VecIn2 = SDValue(0, 0); 6253 break; 6254 } 6255 } 6256 6257 // If everything is good, we can make a shuffle operation. 6258 if (VecIn1.getNode()) { 6259 SmallVector<int, 8> Mask; 6260 for (unsigned i = 0; i != NumInScalars; ++i) { 6261 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6262 Mask.push_back(-1); 6263 continue; 6264 } 6265 6266 // If extracting from the first vector, just use the index directly. 6267 SDValue Extract = N->getOperand(i); 6268 SDValue ExtVal = Extract.getOperand(1); 6269 if (Extract.getOperand(0) == VecIn1) { 6270 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6271 if (ExtIndex > VT.getVectorNumElements()) 6272 return SDValue(); 6273 6274 Mask.push_back(ExtIndex); 6275 continue; 6276 } 6277 6278 // Otherwise, use InIdx + VecSize 6279 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6280 Mask.push_back(Idx+NumInScalars); 6281 } 6282 6283 // Add count and size info. 6284 if (!isTypeLegal(VT)) 6285 return SDValue(); 6286 6287 // Return the new VECTOR_SHUFFLE node. 6288 SDValue Ops[2]; 6289 Ops[0] = VecIn1; 6290 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6291 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6292 } 6293 6294 return SDValue(); 6295} 6296 6297SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6298 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6299 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6300 // inputs come from at most two distinct vectors, turn this into a shuffle 6301 // node. 6302 6303 // If we only have one input vector, we don't need to do any concatenation. 6304 if (N->getNumOperands() == 1) 6305 return N->getOperand(0); 6306 6307 return SDValue(); 6308} 6309 6310SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6311 return SDValue(); 6312 6313 EVT VT = N->getValueType(0); 6314 unsigned NumElts = VT.getVectorNumElements(); 6315 6316 SDValue N0 = N->getOperand(0); 6317 6318 assert(N0.getValueType().getVectorNumElements() == NumElts && 6319 "Vector shuffle must be normalized in DAG"); 6320 6321 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6322 6323 // If it is a splat, check if the argument vector is a build_vector with 6324 // all scalar elements the same. 6325 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 6326 SDNode *V = N0.getNode(); 6327 6328 // If this is a bit convert that changes the element type of the vector but 6329 // not the number of vector elements, look through it. Be careful not to 6330 // look though conversions that change things like v4f32 to v2f64. 6331 if (V->getOpcode() == ISD::BIT_CONVERT) { 6332 SDValue ConvInput = V->getOperand(0); 6333 if (ConvInput.getValueType().isVector() && 6334 ConvInput.getValueType().getVectorNumElements() == NumElts) 6335 V = ConvInput.getNode(); 6336 } 6337 6338 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6339 unsigned NumElems = V->getNumOperands(); 6340 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 6341 if (NumElems > BaseIdx) { 6342 SDValue Base; 6343 bool AllSame = true; 6344 for (unsigned i = 0; i != NumElems; ++i) { 6345 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6346 Base = V->getOperand(i); 6347 break; 6348 } 6349 } 6350 // Splat of <u, u, u, u>, return <u, u, u, u> 6351 if (!Base.getNode()) 6352 return N0; 6353 for (unsigned i = 0; i != NumElems; ++i) { 6354 if (V->getOperand(i) != Base) { 6355 AllSame = false; 6356 break; 6357 } 6358 } 6359 // Splat of <x, x, x, x>, return <x, x, x, x> 6360 if (AllSame) 6361 return N0; 6362 } 6363 } 6364 } 6365 return SDValue(); 6366} 6367 6368SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6369 if (!TLI.getShouldFoldAtomicFences()) 6370 return SDValue(); 6371 6372 SDValue atomic = N->getOperand(0); 6373 switch (atomic.getOpcode()) { 6374 case ISD::ATOMIC_CMP_SWAP: 6375 case ISD::ATOMIC_SWAP: 6376 case ISD::ATOMIC_LOAD_ADD: 6377 case ISD::ATOMIC_LOAD_SUB: 6378 case ISD::ATOMIC_LOAD_AND: 6379 case ISD::ATOMIC_LOAD_OR: 6380 case ISD::ATOMIC_LOAD_XOR: 6381 case ISD::ATOMIC_LOAD_NAND: 6382 case ISD::ATOMIC_LOAD_MIN: 6383 case ISD::ATOMIC_LOAD_MAX: 6384 case ISD::ATOMIC_LOAD_UMIN: 6385 case ISD::ATOMIC_LOAD_UMAX: 6386 break; 6387 default: 6388 return SDValue(); 6389 } 6390 6391 SDValue fence = atomic.getOperand(0); 6392 if (fence.getOpcode() != ISD::MEMBARRIER) 6393 return SDValue(); 6394 6395 switch (atomic.getOpcode()) { 6396 case ISD::ATOMIC_CMP_SWAP: 6397 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6398 fence.getOperand(0), 6399 atomic.getOperand(1), atomic.getOperand(2), 6400 atomic.getOperand(3)), atomic.getResNo()); 6401 case ISD::ATOMIC_SWAP: 6402 case ISD::ATOMIC_LOAD_ADD: 6403 case ISD::ATOMIC_LOAD_SUB: 6404 case ISD::ATOMIC_LOAD_AND: 6405 case ISD::ATOMIC_LOAD_OR: 6406 case ISD::ATOMIC_LOAD_XOR: 6407 case ISD::ATOMIC_LOAD_NAND: 6408 case ISD::ATOMIC_LOAD_MIN: 6409 case ISD::ATOMIC_LOAD_MAX: 6410 case ISD::ATOMIC_LOAD_UMIN: 6411 case ISD::ATOMIC_LOAD_UMAX: 6412 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6413 fence.getOperand(0), 6414 atomic.getOperand(1), atomic.getOperand(2)), 6415 atomic.getResNo()); 6416 default: 6417 return SDValue(); 6418 } 6419} 6420 6421/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6422/// an AND to a vector_shuffle with the destination vector and a zero vector. 6423/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6424/// vector_shuffle V, Zero, <0, 4, 2, 4> 6425SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6426 EVT VT = N->getValueType(0); 6427 DebugLoc dl = N->getDebugLoc(); 6428 SDValue LHS = N->getOperand(0); 6429 SDValue RHS = N->getOperand(1); 6430 if (N->getOpcode() == ISD::AND) { 6431 if (RHS.getOpcode() == ISD::BIT_CONVERT) 6432 RHS = RHS.getOperand(0); 6433 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6434 SmallVector<int, 8> Indices; 6435 unsigned NumElts = RHS.getNumOperands(); 6436 for (unsigned i = 0; i != NumElts; ++i) { 6437 SDValue Elt = RHS.getOperand(i); 6438 if (!isa<ConstantSDNode>(Elt)) 6439 return SDValue(); 6440 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6441 Indices.push_back(i); 6442 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6443 Indices.push_back(NumElts); 6444 else 6445 return SDValue(); 6446 } 6447 6448 // Let's see if the target supports this vector_shuffle. 6449 EVT RVT = RHS.getValueType(); 6450 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6451 return SDValue(); 6452 6453 // Return the new VECTOR_SHUFFLE node. 6454 EVT EltVT = RVT.getVectorElementType(); 6455 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6456 DAG.getConstant(0, EltVT)); 6457 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6458 RVT, &ZeroOps[0], ZeroOps.size()); 6459 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 6460 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6461 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 6462 } 6463 } 6464 6465 return SDValue(); 6466} 6467 6468/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6469SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6470 // After legalize, the target may be depending on adds and other 6471 // binary ops to provide legal ways to construct constants or other 6472 // things. Simplifying them may result in a loss of legality. 6473 if (LegalOperations) return SDValue(); 6474 6475 EVT VT = N->getValueType(0); 6476 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 6477 6478 EVT EltType = VT.getVectorElementType(); 6479 SDValue LHS = N->getOperand(0); 6480 SDValue RHS = N->getOperand(1); 6481 SDValue Shuffle = XformToShuffleWithZero(N); 6482 if (Shuffle.getNode()) return Shuffle; 6483 6484 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6485 // this operation. 6486 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6487 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6488 SmallVector<SDValue, 8> Ops; 6489 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6490 SDValue LHSOp = LHS.getOperand(i); 6491 SDValue RHSOp = RHS.getOperand(i); 6492 // If these two elements can't be folded, bail out. 6493 if ((LHSOp.getOpcode() != ISD::UNDEF && 6494 LHSOp.getOpcode() != ISD::Constant && 6495 LHSOp.getOpcode() != ISD::ConstantFP) || 6496 (RHSOp.getOpcode() != ISD::UNDEF && 6497 RHSOp.getOpcode() != ISD::Constant && 6498 RHSOp.getOpcode() != ISD::ConstantFP)) 6499 break; 6500 6501 // Can't fold divide by zero. 6502 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6503 N->getOpcode() == ISD::FDIV) { 6504 if ((RHSOp.getOpcode() == ISD::Constant && 6505 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6506 (RHSOp.getOpcode() == ISD::ConstantFP && 6507 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6508 break; 6509 } 6510 6511 // If the vector element type is not legal, the BUILD_VECTOR operands 6512 // are promoted and implicitly truncated. Make that explicit here. 6513 if (LHSOp.getValueType() != EltType) 6514 LHSOp = DAG.getNode(ISD::TRUNCATE, LHS.getDebugLoc(), EltType, LHSOp); 6515 if (RHSOp.getValueType() != EltType) 6516 RHSOp = DAG.getNode(ISD::TRUNCATE, RHS.getDebugLoc(), EltType, RHSOp); 6517 6518 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), EltType, 6519 LHSOp, RHSOp); 6520 if (FoldOp.getOpcode() != ISD::UNDEF && 6521 FoldOp.getOpcode() != ISD::Constant && 6522 FoldOp.getOpcode() != ISD::ConstantFP) 6523 break; 6524 Ops.push_back(FoldOp); 6525 AddToWorkList(FoldOp.getNode()); 6526 } 6527 6528 if (Ops.size() == LHS.getNumOperands()) { 6529 EVT VT = LHS.getValueType(); 6530 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6531 &Ops[0], Ops.size()); 6532 } 6533 } 6534 6535 return SDValue(); 6536} 6537 6538SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6539 SDValue N1, SDValue N2){ 6540 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6541 6542 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6543 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6544 6545 // If we got a simplified select_cc node back from SimplifySelectCC, then 6546 // break it down into a new SETCC node, and a new SELECT node, and then return 6547 // the SELECT node, since we were called with a SELECT node. 6548 if (SCC.getNode()) { 6549 // Check to see if we got a select_cc back (to turn into setcc/select). 6550 // Otherwise, just return whatever node we got back, like fabs. 6551 if (SCC.getOpcode() == ISD::SELECT_CC) { 6552 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6553 N0.getValueType(), 6554 SCC.getOperand(0), SCC.getOperand(1), 6555 SCC.getOperand(4)); 6556 AddToWorkList(SETCC.getNode()); 6557 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6558 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6559 } 6560 6561 return SCC; 6562 } 6563 return SDValue(); 6564} 6565 6566/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6567/// are the two values being selected between, see if we can simplify the 6568/// select. Callers of this should assume that TheSelect is deleted if this 6569/// returns true. As such, they should return the appropriate thing (e.g. the 6570/// node) back to the top-level of the DAG combiner loop to avoid it being 6571/// looked at. 6572bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6573 SDValue RHS) { 6574 6575 // If this is a select from two identical things, try to pull the operation 6576 // through the select. 6577 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 6578 // If this is a load and the token chain is identical, replace the select 6579 // of two loads with a load through a select of the address to load from. 6580 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6581 // constants have been dropped into the constant pool. 6582 if (LHS.getOpcode() == ISD::LOAD && 6583 // Do not let this transformation reduce the number of volatile loads. 6584 !cast<LoadSDNode>(LHS)->isVolatile() && 6585 !cast<LoadSDNode>(RHS)->isVolatile() && 6586 // Token chains must be identical. 6587 LHS.getOperand(0) == RHS.getOperand(0)) { 6588 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6589 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6590 6591 // If this is an EXTLOAD, the VT's must match. 6592 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 6593 // FIXME: this discards src value information. This is 6594 // over-conservative. It would be beneficial to be able to remember 6595 // both potential memory locations. Since we are discarding 6596 // src value info, don't do the transformation if the memory 6597 // locations are not in the default address space. 6598 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 6599 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 6600 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 6601 LLDAddrSpace = PT->getAddressSpace(); 6602 } 6603 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 6604 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 6605 RLDAddrSpace = PT->getAddressSpace(); 6606 } 6607 SDValue Addr; 6608 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 6609 if (TheSelect->getOpcode() == ISD::SELECT) { 6610 // Check that the condition doesn't reach either load. If so, folding 6611 // this will induce a cycle into the DAG. 6612 if ((!LLD->hasAnyUseOfValue(1) || 6613 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 6614 (!RLD->hasAnyUseOfValue(1) || 6615 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 6616 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6617 LLD->getBasePtr().getValueType(), 6618 TheSelect->getOperand(0), LLD->getBasePtr(), 6619 RLD->getBasePtr()); 6620 } 6621 } else { 6622 // Check that the condition doesn't reach either load. If so, folding 6623 // this will induce a cycle into the DAG. 6624 if ((!LLD->hasAnyUseOfValue(1) || 6625 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6626 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 6627 (!RLD->hasAnyUseOfValue(1) || 6628 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6629 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 6630 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6631 LLD->getBasePtr().getValueType(), 6632 TheSelect->getOperand(0), 6633 TheSelect->getOperand(1), 6634 LLD->getBasePtr(), RLD->getBasePtr(), 6635 TheSelect->getOperand(4)); 6636 } 6637 } 6638 } 6639 6640 if (Addr.getNode()) { 6641 SDValue Load; 6642 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6643 Load = DAG.getLoad(TheSelect->getValueType(0), 6644 TheSelect->getDebugLoc(), 6645 LLD->getChain(), 6646 Addr, 0, 0, 6647 LLD->isVolatile(), 6648 LLD->isNonTemporal(), 6649 LLD->getAlignment()); 6650 } else { 6651 Load = DAG.getExtLoad(LLD->getExtensionType(), 6652 TheSelect->getDebugLoc(), 6653 TheSelect->getValueType(0), 6654 LLD->getChain(), Addr, 0, 0, 6655 LLD->getMemoryVT(), 6656 LLD->isVolatile(), 6657 LLD->isNonTemporal(), 6658 LLD->getAlignment()); 6659 } 6660 6661 // Users of the select now use the result of the load. 6662 CombineTo(TheSelect, Load); 6663 6664 // Users of the old loads now use the new load's chain. We know the 6665 // old-load value is dead now. 6666 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6667 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6668 return true; 6669 } 6670 } 6671 } 6672 } 6673 6674 return false; 6675} 6676 6677/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6678/// where 'cond' is the comparison specified by CC. 6679SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6680 SDValue N2, SDValue N3, 6681 ISD::CondCode CC, bool NotExtCompare) { 6682 // (x ? y : y) -> y. 6683 if (N2 == N3) return N2; 6684 6685 EVT VT = N2.getValueType(); 6686 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6687 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6688 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6689 6690 // Determine if the condition we're dealing with is constant 6691 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6692 N0, N1, CC, DL, false); 6693 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6694 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6695 6696 // fold select_cc true, x, y -> x 6697 if (SCCC && !SCCC->isNullValue()) 6698 return N2; 6699 // fold select_cc false, x, y -> y 6700 if (SCCC && SCCC->isNullValue()) 6701 return N3; 6702 6703 // Check to see if we can simplify the select into an fabs node 6704 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6705 // Allow either -0.0 or 0.0 6706 if (CFP->getValueAPF().isZero()) { 6707 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6708 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6709 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6710 N2 == N3.getOperand(0)) 6711 return DAG.getNode(ISD::FABS, DL, VT, N0); 6712 6713 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6714 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6715 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6716 N2.getOperand(0) == N3) 6717 return DAG.getNode(ISD::FABS, DL, VT, N3); 6718 } 6719 } 6720 6721 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6722 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6723 // in it. This is a win when the constant is not otherwise available because 6724 // it replaces two constant pool loads with one. We only do this if the FP 6725 // type is known to be legal, because if it isn't, then we are before legalize 6726 // types an we want the other legalization to happen first (e.g. to avoid 6727 // messing with soft float) and if the ConstantFP is not legal, because if 6728 // it is legal, we may not need to store the FP constant in a constant pool. 6729 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6730 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6731 if (TLI.isTypeLegal(N2.getValueType()) && 6732 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6733 TargetLowering::Legal) && 6734 // If both constants have multiple uses, then we won't need to do an 6735 // extra load, they are likely around in registers for other users. 6736 (TV->hasOneUse() || FV->hasOneUse())) { 6737 Constant *Elts[] = { 6738 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6739 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6740 }; 6741 const Type *FPTy = Elts[0]->getType(); 6742 const TargetData &TD = *TLI.getTargetData(); 6743 6744 // Create a ConstantArray of the two constants. 6745 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6746 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6747 TD.getPrefTypeAlignment(FPTy)); 6748 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6749 6750 // Get the offsets to the 0 and 1 element of the array so that we can 6751 // select between them. 6752 SDValue Zero = DAG.getIntPtrConstant(0); 6753 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6754 SDValue One = DAG.getIntPtrConstant(EltSize); 6755 6756 SDValue Cond = DAG.getSetCC(DL, 6757 TLI.getSetCCResultType(N0.getValueType()), 6758 N0, N1, CC); 6759 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6760 Cond, One, Zero); 6761 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6762 CstOffset); 6763 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6764 PseudoSourceValue::getConstantPool(), 0, false, 6765 false, Alignment); 6766 6767 } 6768 } 6769 6770 // Check to see if we can perform the "gzip trick", transforming 6771 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6772 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6773 N0.getValueType().isInteger() && 6774 N2.getValueType().isInteger() && 6775 (N1C->isNullValue() || // (a < 0) ? b : 0 6776 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6777 EVT XType = N0.getValueType(); 6778 EVT AType = N2.getValueType(); 6779 if (XType.bitsGE(AType)) { 6780 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6781 // single-bit constant. 6782 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6783 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6784 ShCtV = XType.getSizeInBits()-ShCtV-1; 6785 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6786 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6787 XType, N0, ShCt); 6788 AddToWorkList(Shift.getNode()); 6789 6790 if (XType.bitsGT(AType)) { 6791 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6792 AddToWorkList(Shift.getNode()); 6793 } 6794 6795 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6796 } 6797 6798 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6799 XType, N0, 6800 DAG.getConstant(XType.getSizeInBits()-1, 6801 getShiftAmountTy())); 6802 AddToWorkList(Shift.getNode()); 6803 6804 if (XType.bitsGT(AType)) { 6805 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6806 AddToWorkList(Shift.getNode()); 6807 } 6808 6809 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6810 } 6811 } 6812 6813 // fold select C, 16, 0 -> shl C, 4 6814 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6815 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6816 6817 // If the caller doesn't want us to simplify this into a zext of a compare, 6818 // don't do it. 6819 if (NotExtCompare && N2C->getAPIntValue() == 1) 6820 return SDValue(); 6821 6822 // Get a SetCC of the condition 6823 // FIXME: Should probably make sure that setcc is legal if we ever have a 6824 // target where it isn't. 6825 SDValue Temp, SCC; 6826 // cast from setcc result type to select result type 6827 if (LegalTypes) { 6828 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6829 N0, N1, CC); 6830 if (N2.getValueType().bitsLT(SCC.getValueType())) 6831 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6832 else 6833 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6834 N2.getValueType(), SCC); 6835 } else { 6836 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6837 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6838 N2.getValueType(), SCC); 6839 } 6840 6841 AddToWorkList(SCC.getNode()); 6842 AddToWorkList(Temp.getNode()); 6843 6844 if (N2C->getAPIntValue() == 1) 6845 return Temp; 6846 6847 // shl setcc result by log2 n2c 6848 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6849 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6850 getShiftAmountTy())); 6851 } 6852 6853 // Check to see if this is the equivalent of setcc 6854 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6855 // otherwise, go ahead with the folds. 6856 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6857 EVT XType = N0.getValueType(); 6858 if (!LegalOperations || 6859 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6860 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6861 if (Res.getValueType() != VT) 6862 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6863 return Res; 6864 } 6865 6866 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6867 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6868 (!LegalOperations || 6869 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6870 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6871 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6872 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6873 getShiftAmountTy())); 6874 } 6875 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6876 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6877 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6878 XType, DAG.getConstant(0, XType), N0); 6879 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6880 return DAG.getNode(ISD::SRL, DL, XType, 6881 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6882 DAG.getConstant(XType.getSizeInBits()-1, 6883 getShiftAmountTy())); 6884 } 6885 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6886 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6887 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6888 DAG.getConstant(XType.getSizeInBits()-1, 6889 getShiftAmountTy())); 6890 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6891 } 6892 } 6893 6894 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6895 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6896 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6897 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6898 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6899 EVT XType = N0.getValueType(); 6900 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6901 DAG.getConstant(XType.getSizeInBits()-1, 6902 getShiftAmountTy())); 6903 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6904 N0, Shift); 6905 AddToWorkList(Shift.getNode()); 6906 AddToWorkList(Add.getNode()); 6907 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6908 } 6909 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6910 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6911 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6912 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6913 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6914 EVT XType = N0.getValueType(); 6915 if (SubC->isNullValue() && XType.isInteger()) { 6916 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6917 N0, 6918 DAG.getConstant(XType.getSizeInBits()-1, 6919 getShiftAmountTy())); 6920 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6921 XType, N0, Shift); 6922 AddToWorkList(Shift.getNode()); 6923 AddToWorkList(Add.getNode()); 6924 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6925 } 6926 } 6927 } 6928 6929 return SDValue(); 6930} 6931 6932/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6933SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6934 SDValue N1, ISD::CondCode Cond, 6935 DebugLoc DL, bool foldBooleans) { 6936 TargetLowering::DAGCombinerInfo 6937 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6938 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6939} 6940 6941/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6942/// return a DAG expression to select that will generate the same value by 6943/// multiplying by a magic number. See: 6944/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6945SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6946 std::vector<SDNode*> Built; 6947 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6948 6949 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6950 ii != ee; ++ii) 6951 AddToWorkList(*ii); 6952 return S; 6953} 6954 6955/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6956/// return a DAG expression to select that will generate the same value by 6957/// multiplying by a magic number. See: 6958/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6959SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6960 std::vector<SDNode*> Built; 6961 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6962 6963 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6964 ii != ee; ++ii) 6965 AddToWorkList(*ii); 6966 return S; 6967} 6968 6969/// FindBaseOffset - Return true if base is a frame index, which is known not 6970// to alias with anything but itself. Provides base object and offset as results. 6971static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6972 const GlobalValue *&GV, void *&CV) { 6973 // Assume it is a primitive operation. 6974 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6975 6976 // If it's an adding a simple constant then integrate the offset. 6977 if (Base.getOpcode() == ISD::ADD) { 6978 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6979 Base = Base.getOperand(0); 6980 Offset += C->getZExtValue(); 6981 } 6982 } 6983 6984 // Return the underlying GlobalValue, and update the Offset. Return false 6985 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6986 // by multiple nodes with different offsets. 6987 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6988 GV = G->getGlobal(); 6989 Offset += G->getOffset(); 6990 return false; 6991 } 6992 6993 // Return the underlying Constant value, and update the Offset. Return false 6994 // for ConstantSDNodes since the same constant pool entry may be represented 6995 // by multiple nodes with different offsets. 6996 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6997 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6998 : (void *)C->getConstVal(); 6999 Offset += C->getOffset(); 7000 return false; 7001 } 7002 // If it's any of the following then it can't alias with anything but itself. 7003 return isa<FrameIndexSDNode>(Base); 7004} 7005 7006/// isAlias - Return true if there is any possibility that the two addresses 7007/// overlap. 7008bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7009 const Value *SrcValue1, int SrcValueOffset1, 7010 unsigned SrcValueAlign1, 7011 SDValue Ptr2, int64_t Size2, 7012 const Value *SrcValue2, int SrcValueOffset2, 7013 unsigned SrcValueAlign2) const { 7014 // If they are the same then they must be aliases. 7015 if (Ptr1 == Ptr2) return true; 7016 7017 // Gather base node and offset information. 7018 SDValue Base1, Base2; 7019 int64_t Offset1, Offset2; 7020 const GlobalValue *GV1, *GV2; 7021 void *CV1, *CV2; 7022 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7023 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7024 7025 // If they have a same base address then check to see if they overlap. 7026 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7027 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7028 7029 // If we know what the bases are, and they aren't identical, then we know they 7030 // cannot alias. 7031 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7032 return false; 7033 7034 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7035 // compared to the size and offset of the access, we may be able to prove they 7036 // do not alias. This check is conservative for now to catch cases created by 7037 // splitting vector types. 7038 if ((SrcValueAlign1 == SrcValueAlign2) && 7039 (SrcValueOffset1 != SrcValueOffset2) && 7040 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7041 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7042 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7043 7044 // There is no overlap between these relatively aligned accesses of similar 7045 // size, return no alias. 7046 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7047 return false; 7048 } 7049 7050 if (CombinerGlobalAA) { 7051 // Use alias analysis information. 7052 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7053 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7054 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7055 AliasAnalysis::AliasResult AAResult = 7056 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 7057 if (AAResult == AliasAnalysis::NoAlias) 7058 return false; 7059 } 7060 7061 // Otherwise we have to assume they alias. 7062 return true; 7063} 7064 7065/// FindAliasInfo - Extracts the relevant alias information from the memory 7066/// node. Returns true if the operand was a load. 7067bool DAGCombiner::FindAliasInfo(SDNode *N, 7068 SDValue &Ptr, int64_t &Size, 7069 const Value *&SrcValue, 7070 int &SrcValueOffset, 7071 unsigned &SrcValueAlign) const { 7072 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7073 Ptr = LD->getBasePtr(); 7074 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7075 SrcValue = LD->getSrcValue(); 7076 SrcValueOffset = LD->getSrcValueOffset(); 7077 SrcValueAlign = LD->getOriginalAlignment(); 7078 return true; 7079 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7080 Ptr = ST->getBasePtr(); 7081 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7082 SrcValue = ST->getSrcValue(); 7083 SrcValueOffset = ST->getSrcValueOffset(); 7084 SrcValueAlign = ST->getOriginalAlignment(); 7085 } else { 7086 llvm_unreachable("FindAliasInfo expected a memory operand"); 7087 } 7088 7089 return false; 7090} 7091 7092/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7093/// looking for aliasing nodes and adding them to the Aliases vector. 7094void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7095 SmallVector<SDValue, 8> &Aliases) { 7096 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7097 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7098 7099 // Get alias information for node. 7100 SDValue Ptr; 7101 int64_t Size; 7102 const Value *SrcValue; 7103 int SrcValueOffset; 7104 unsigned SrcValueAlign; 7105 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7106 SrcValueAlign); 7107 7108 // Starting off. 7109 Chains.push_back(OriginalChain); 7110 unsigned Depth = 0; 7111 7112 // Look at each chain and determine if it is an alias. If so, add it to the 7113 // aliases list. If not, then continue up the chain looking for the next 7114 // candidate. 7115 while (!Chains.empty()) { 7116 SDValue Chain = Chains.back(); 7117 Chains.pop_back(); 7118 7119 // For TokenFactor nodes, look at each operand and only continue up the 7120 // chain until we find two aliases. If we've seen two aliases, assume we'll 7121 // find more and revert to original chain since the xform is unlikely to be 7122 // profitable. 7123 // 7124 // FIXME: The depth check could be made to return the last non-aliasing 7125 // chain we found before we hit a tokenfactor rather than the original 7126 // chain. 7127 if (Depth > 6 || Aliases.size() == 2) { 7128 Aliases.clear(); 7129 Aliases.push_back(OriginalChain); 7130 break; 7131 } 7132 7133 // Don't bother if we've been before. 7134 if (!Visited.insert(Chain.getNode())) 7135 continue; 7136 7137 switch (Chain.getOpcode()) { 7138 case ISD::EntryToken: 7139 // Entry token is ideal chain operand, but handled in FindBetterChain. 7140 break; 7141 7142 case ISD::LOAD: 7143 case ISD::STORE: { 7144 // Get alias information for Chain. 7145 SDValue OpPtr; 7146 int64_t OpSize; 7147 const Value *OpSrcValue; 7148 int OpSrcValueOffset; 7149 unsigned OpSrcValueAlign; 7150 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7151 OpSrcValue, OpSrcValueOffset, 7152 OpSrcValueAlign); 7153 7154 // If chain is alias then stop here. 7155 if (!(IsLoad && IsOpLoad) && 7156 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7157 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7158 OpSrcValueAlign)) { 7159 Aliases.push_back(Chain); 7160 } else { 7161 // Look further up the chain. 7162 Chains.push_back(Chain.getOperand(0)); 7163 ++Depth; 7164 } 7165 break; 7166 } 7167 7168 case ISD::TokenFactor: 7169 // We have to check each of the operands of the token factor for "small" 7170 // token factors, so we queue them up. Adding the operands to the queue 7171 // (stack) in reverse order maintains the original order and increases the 7172 // likelihood that getNode will find a matching token factor (CSE.) 7173 if (Chain.getNumOperands() > 16) { 7174 Aliases.push_back(Chain); 7175 break; 7176 } 7177 for (unsigned n = Chain.getNumOperands(); n;) 7178 Chains.push_back(Chain.getOperand(--n)); 7179 ++Depth; 7180 break; 7181 7182 default: 7183 // For all other instructions we will just have to take what we can get. 7184 Aliases.push_back(Chain); 7185 break; 7186 } 7187 } 7188} 7189 7190/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7191/// for a better chain (aliasing node.) 7192SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7193 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7194 7195 // Accumulate all the aliases to this node. 7196 GatherAllAliases(N, OldChain, Aliases); 7197 7198 if (Aliases.size() == 0) { 7199 // If no operands then chain to entry token. 7200 return DAG.getEntryNode(); 7201 } else if (Aliases.size() == 1) { 7202 // If a single operand then chain to it. We don't need to revisit it. 7203 return Aliases[0]; 7204 } 7205 7206 // Construct a custom tailored token factor. 7207 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7208 &Aliases[0], Aliases.size()); 7209} 7210 7211// SelectionDAG::Combine - This is the entry point for the file. 7212// 7213void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7214 CodeGenOpt::Level OptLevel) { 7215 /// run - This is the main entry point to this class. 7216 /// 7217 DAGCombiner(*this, AA, OptLevel).Run(Level); 7218} 7219