DAGCombiner.cpp revision 9ab2b98ba586b366ad49ea141d83b9821f91d8f3
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 /// getShiftAmountTy - Returns a type large enough to hold any valid 258 /// shift amount - before type legalization these can be huge. 259 EVT getShiftAmountTy() { 260 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 261 } 262 263public: 264 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 265 : DAG(D), 266 TLI(D.getTargetLoweringInfo()), 267 Level(Unrestricted), 268 OptLevel(OL), 269 LegalOperations(false), 270 LegalTypes(false), 271 AA(A) {} 272 273 /// Run - runs the dag combiner on all nodes in the work list 274 void Run(CombineLevel AtLevel); 275 }; 276} 277 278 279namespace { 280/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 281/// nodes from the worklist. 282class WorkListRemover : public SelectionDAG::DAGUpdateListener { 283 DAGCombiner &DC; 284public: 285 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 286 287 virtual void NodeDeleted(SDNode *N, SDNode *E) { 288 DC.removeFromWorkList(N); 289 } 290 291 virtual void NodeUpdated(SDNode *N) { 292 // Ignore updates. 293 } 294}; 295} 296 297//===----------------------------------------------------------------------===// 298// TargetLowering::DAGCombinerInfo implementation 299//===----------------------------------------------------------------------===// 300 301void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 302 ((DAGCombiner*)DC)->AddToWorkList(N); 303} 304 305SDValue TargetLowering::DAGCombinerInfo:: 306CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 307 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 308} 309 310SDValue TargetLowering::DAGCombinerInfo:: 311CombineTo(SDNode *N, SDValue Res, bool AddTo) { 312 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 313} 314 315 316SDValue TargetLowering::DAGCombinerInfo:: 317CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 318 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 319} 320 321void TargetLowering::DAGCombinerInfo:: 322CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 323 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 324} 325 326//===----------------------------------------------------------------------===// 327// Helper Functions 328//===----------------------------------------------------------------------===// 329 330/// isNegatibleForFree - Return 1 if we can compute the negated form of the 331/// specified expression for the same cost as the expression itself, or 2 if we 332/// can compute the negated form more cheaply than the expression itself. 333static char isNegatibleForFree(SDValue Op, bool LegalOperations, 334 unsigned Depth = 0) { 335 // No compile time optimizations on this type. 336 if (Op.getValueType() == MVT::ppcf128) 337 return 0; 338 339 // fneg is removable even if it has multiple uses. 340 if (Op.getOpcode() == ISD::FNEG) return 2; 341 342 // Don't allow anything with multiple uses. 343 if (!Op.hasOneUse()) return 0; 344 345 // Don't recurse exponentially. 346 if (Depth > 6) return 0; 347 348 switch (Op.getOpcode()) { 349 default: return false; 350 case ISD::ConstantFP: 351 // Don't invert constant FP values after legalize. The negated constant 352 // isn't necessarily legal. 353 return LegalOperations ? 0 : 1; 354 case ISD::FADD: 355 // FIXME: determine better conditions for this xform. 356 if (!UnsafeFPMath) return 0; 357 358 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 359 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 360 return V; 361 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 362 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 363 case ISD::FSUB: 364 // We can't turn -(A-B) into B-A when we honor signed zeros. 365 if (!UnsafeFPMath) return 0; 366 367 // fold (fneg (fsub A, B)) -> (fsub B, A) 368 return 1; 369 370 case ISD::FMUL: 371 case ISD::FDIV: 372 if (HonorSignDependentRoundingFPMath()) return 0; 373 374 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 380 case ISD::FP_EXTEND: 381 case ISD::FP_ROUND: 382 case ISD::FSIN: 383 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 384 } 385} 386 387/// GetNegatedExpression - If isNegatibleForFree returns true, this function 388/// returns the newly negated expression. 389static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 390 bool LegalOperations, unsigned Depth = 0) { 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 393 394 // Don't allow anything with multiple uses. 395 assert(Op.hasOneUse() && "Unknown reuse!"); 396 397 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 398 switch (Op.getOpcode()) { 399 default: llvm_unreachable("Unknown code"); 400 case ISD::ConstantFP: { 401 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 402 V.changeSign(); 403 return DAG.getConstantFP(V, Op.getValueType()); 404 } 405 case ISD::FADD: 406 // FIXME: determine better conditions for this xform. 407 assert(UnsafeFPMath); 408 409 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 410 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 411 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 LegalOperations, Depth+1), 414 Op.getOperand(1)); 415 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 417 GetNegatedExpression(Op.getOperand(1), DAG, 418 LegalOperations, Depth+1), 419 Op.getOperand(0)); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 assert(UnsafeFPMath); 423 424 // fold (fneg (fsub 0, B)) -> B 425 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 426 if (N0CFP->getValueAPF().isZero()) 427 return Op.getOperand(1); 428 429 // fold (fneg (fsub A, B)) -> (fsub B, A) 430 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 431 Op.getOperand(1), Op.getOperand(0)); 432 433 case ISD::FMUL: 434 case ISD::FDIV: 435 assert(!HonorSignDependentRoundingFPMath()); 436 437 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 438 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 439 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 440 GetNegatedExpression(Op.getOperand(0), DAG, 441 LegalOperations, Depth+1), 442 Op.getOperand(1)); 443 444 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 445 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 446 Op.getOperand(0), 447 GetNegatedExpression(Op.getOperand(1), DAG, 448 LegalOperations, Depth+1)); 449 450 case ISD::FP_EXTEND: 451 case ISD::FSIN: 452 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1)); 455 case ISD::FP_ROUND: 456 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1), 459 Op.getOperand(1)); 460 } 461} 462 463 464// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 465// that selects between the values 1 and 0, making it equivalent to a setcc. 466// Also, set the incoming LHS, RHS, and CC references to the appropriate 467// nodes based on the type of node we are checking. This simplifies life a 468// bit for the callers. 469static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 470 SDValue &CC) { 471 if (N.getOpcode() == ISD::SETCC) { 472 LHS = N.getOperand(0); 473 RHS = N.getOperand(1); 474 CC = N.getOperand(2); 475 return true; 476 } 477 if (N.getOpcode() == ISD::SELECT_CC && 478 N.getOperand(2).getOpcode() == ISD::Constant && 479 N.getOperand(3).getOpcode() == ISD::Constant && 480 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 481 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 482 LHS = N.getOperand(0); 483 RHS = N.getOperand(1); 484 CC = N.getOperand(4); 485 return true; 486 } 487 return false; 488} 489 490// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 491// one use. If this is true, it allows the users to invert the operation for 492// free when it is profitable to do so. 493static bool isOneUseSetCC(SDValue N) { 494 SDValue N0, N1, N2; 495 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 496 return true; 497 return false; 498} 499 500SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 501 SDValue N0, SDValue N1) { 502 EVT VT = N0.getValueType(); 503 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 504 if (isa<ConstantSDNode>(N1)) { 505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 506 SDValue OpNode = 507 DAG.FoldConstantArithmetic(Opc, VT, 508 cast<ConstantSDNode>(N0.getOperand(1)), 509 cast<ConstantSDNode>(N1)); 510 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 511 } else if (N0.hasOneUse()) { 512 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 513 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 514 N0.getOperand(0), N1); 515 AddToWorkList(OpNode.getNode()); 516 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 517 } 518 } 519 520 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 521 if (isa<ConstantSDNode>(N0)) { 522 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 523 SDValue OpNode = 524 DAG.FoldConstantArithmetic(Opc, VT, 525 cast<ConstantSDNode>(N1.getOperand(1)), 526 cast<ConstantSDNode>(N0)); 527 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 528 } else if (N1.hasOneUse()) { 529 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 530 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 531 N1.getOperand(0), N0); 532 AddToWorkList(OpNode.getNode()); 533 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 534 } 535 } 536 537 return SDValue(); 538} 539 540SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 541 bool AddTo) { 542 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 543 ++NodesCombined; 544 DEBUG(errs() << "\nReplacing.1 "; 545 N->dump(&DAG); 546 errs() << "\nWith: "; 547 To[0].getNode()->dump(&DAG); 548 errs() << " and " << NumTo-1 << " other values\n"; 549 for (unsigned i = 0, e = NumTo; i != e; ++i) 550 assert((!To[i].getNode() || 551 N->getValueType(i) == To[i].getValueType()) && 552 "Cannot combine value to value of different type!")); 553 WorkListRemover DeadNodes(*this); 554 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 555 556 if (AddTo) { 557 // Push the new nodes and any users onto the worklist 558 for (unsigned i = 0, e = NumTo; i != e; ++i) { 559 if (To[i].getNode()) { 560 AddToWorkList(To[i].getNode()); 561 AddUsersToWorkList(To[i].getNode()); 562 } 563 } 564 } 565 566 // Finally, if the node is now dead, remove it from the graph. The node 567 // may not be dead if the replacement process recursively simplified to 568 // something else needing this node. 569 if (N->use_empty()) { 570 // Nodes can be reintroduced into the worklist. Make sure we do not 571 // process a node that has been replaced. 572 removeFromWorkList(N); 573 574 // Finally, since the node is now dead, remove it from the graph. 575 DAG.DeleteNode(N); 576 } 577 return SDValue(N, 0); 578} 579 580void 581DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 582 TLO) { 583 // Replace all uses. If any nodes become isomorphic to other nodes and 584 // are deleted, make sure to remove them from our worklist. 585 WorkListRemover DeadNodes(*this); 586 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 587 588 // Push the new node and any (possibly new) users onto the worklist. 589 AddToWorkList(TLO.New.getNode()); 590 AddUsersToWorkList(TLO.New.getNode()); 591 592 // Finally, if the node is now dead, remove it from the graph. The node 593 // may not be dead if the replacement process recursively simplified to 594 // something else needing this node. 595 if (TLO.Old.getNode()->use_empty()) { 596 removeFromWorkList(TLO.Old.getNode()); 597 598 // If the operands of this node are only used by the node, they will now 599 // be dead. Make sure to visit them first to delete dead nodes early. 600 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 601 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 602 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 603 604 DAG.DeleteNode(TLO.Old.getNode()); 605 } 606} 607 608/// SimplifyDemandedBits - Check the specified integer node value to see if 609/// it can be simplified or if things it uses can be simplified by bit 610/// propagation. If so, return true. 611bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 612 TargetLowering::TargetLoweringOpt TLO(DAG); 613 APInt KnownZero, KnownOne; 614 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 615 return false; 616 617 // Revisit the node. 618 AddToWorkList(Op.getNode()); 619 620 // Replace the old value with the new one. 621 ++NodesCombined; 622 DEBUG(errs() << "\nReplacing.2 "; 623 TLO.Old.getNode()->dump(&DAG); 624 errs() << "\nWith: "; 625 TLO.New.getNode()->dump(&DAG); 626 errs() << '\n'); 627 628 CommitTargetLoweringOpt(TLO); 629 return true; 630} 631 632//===----------------------------------------------------------------------===// 633// Main DAG Combiner implementation 634//===----------------------------------------------------------------------===// 635 636void DAGCombiner::Run(CombineLevel AtLevel) { 637 // set the instance variables, so that the various visit routines may use it. 638 Level = AtLevel; 639 LegalOperations = Level >= NoIllegalOperations; 640 LegalTypes = Level >= NoIllegalTypes; 641 642 // Add all the dag nodes to the worklist. 643 WorkList.reserve(DAG.allnodes_size()); 644 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 645 E = DAG.allnodes_end(); I != E; ++I) 646 WorkList.push_back(I); 647 648 // Create a dummy node (which is not added to allnodes), that adds a reference 649 // to the root node, preventing it from being deleted, and tracking any 650 // changes of the root. 651 HandleSDNode Dummy(DAG.getRoot()); 652 653 // The root of the dag may dangle to deleted nodes until the dag combiner is 654 // done. Set it to null to avoid confusion. 655 DAG.setRoot(SDValue()); 656 657 // while the worklist isn't empty, inspect the node on the end of it and 658 // try and combine it. 659 while (!WorkList.empty()) { 660 SDNode *N = WorkList.back(); 661 WorkList.pop_back(); 662 663 // If N has no uses, it is dead. Make sure to revisit all N's operands once 664 // N is deleted from the DAG, since they too may now be dead or may have a 665 // reduced number of uses, allowing other xforms. 666 if (N->use_empty() && N != &Dummy) { 667 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 668 AddToWorkList(N->getOperand(i).getNode()); 669 670 DAG.DeleteNode(N); 671 continue; 672 } 673 674 SDValue RV = combine(N); 675 676 if (RV.getNode() == 0) 677 continue; 678 679 ++NodesCombined; 680 681 // If we get back the same node we passed in, rather than a new node or 682 // zero, we know that the node must have defined multiple values and 683 // CombineTo was used. Since CombineTo takes care of the worklist 684 // mechanics for us, we have no work to do in this case. 685 if (RV.getNode() == N) 686 continue; 687 688 assert(N->getOpcode() != ISD::DELETED_NODE && 689 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 690 "Node was deleted but visit returned new node!"); 691 692 DEBUG(errs() << "\nReplacing.3 "; 693 N->dump(&DAG); 694 errs() << "\nWith: "; 695 RV.getNode()->dump(&DAG); 696 errs() << '\n'); 697 WorkListRemover DeadNodes(*this); 698 if (N->getNumValues() == RV.getNode()->getNumValues()) 699 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 700 else { 701 assert(N->getValueType(0) == RV.getValueType() && 702 N->getNumValues() == 1 && "Type mismatch"); 703 SDValue OpV = RV; 704 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 705 } 706 707 // Push the new node and any users onto the worklist 708 AddToWorkList(RV.getNode()); 709 AddUsersToWorkList(RV.getNode()); 710 711 // Add any uses of the old node to the worklist in case this node is the 712 // last one that uses them. They may become dead after this node is 713 // deleted. 714 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 715 AddToWorkList(N->getOperand(i).getNode()); 716 717 // Finally, if the node is now dead, remove it from the graph. The node 718 // may not be dead if the replacement process recursively simplified to 719 // something else needing this node. 720 if (N->use_empty()) { 721 // Nodes can be reintroduced into the worklist. Make sure we do not 722 // process a node that has been replaced. 723 removeFromWorkList(N); 724 725 // Finally, since the node is now dead, remove it from the graph. 726 DAG.DeleteNode(N); 727 } 728 } 729 730 // If the root changed (e.g. it was a dead load, update the root). 731 DAG.setRoot(Dummy.getValue()); 732} 733 734SDValue DAGCombiner::visit(SDNode *N) { 735 switch(N->getOpcode()) { 736 default: break; 737 case ISD::TokenFactor: return visitTokenFactor(N); 738 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 739 case ISD::ADD: return visitADD(N); 740 case ISD::SUB: return visitSUB(N); 741 case ISD::ADDC: return visitADDC(N); 742 case ISD::ADDE: return visitADDE(N); 743 case ISD::MUL: return visitMUL(N); 744 case ISD::SDIV: return visitSDIV(N); 745 case ISD::UDIV: return visitUDIV(N); 746 case ISD::SREM: return visitSREM(N); 747 case ISD::UREM: return visitUREM(N); 748 case ISD::MULHU: return visitMULHU(N); 749 case ISD::MULHS: return visitMULHS(N); 750 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 751 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 752 case ISD::SDIVREM: return visitSDIVREM(N); 753 case ISD::UDIVREM: return visitUDIVREM(N); 754 case ISD::AND: return visitAND(N); 755 case ISD::OR: return visitOR(N); 756 case ISD::XOR: return visitXOR(N); 757 case ISD::SHL: return visitSHL(N); 758 case ISD::SRA: return visitSRA(N); 759 case ISD::SRL: return visitSRL(N); 760 case ISD::CTLZ: return visitCTLZ(N); 761 case ISD::CTTZ: return visitCTTZ(N); 762 case ISD::CTPOP: return visitCTPOP(N); 763 case ISD::SELECT: return visitSELECT(N); 764 case ISD::SELECT_CC: return visitSELECT_CC(N); 765 case ISD::SETCC: return visitSETCC(N); 766 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 767 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 768 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 769 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 770 case ISD::TRUNCATE: return visitTRUNCATE(N); 771 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 772 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 773 case ISD::FADD: return visitFADD(N); 774 case ISD::FSUB: return visitFSUB(N); 775 case ISD::FMUL: return visitFMUL(N); 776 case ISD::FDIV: return visitFDIV(N); 777 case ISD::FREM: return visitFREM(N); 778 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 779 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 780 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 781 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 782 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 783 case ISD::FP_ROUND: return visitFP_ROUND(N); 784 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 785 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 786 case ISD::FNEG: return visitFNEG(N); 787 case ISD::FABS: return visitFABS(N); 788 case ISD::BRCOND: return visitBRCOND(N); 789 case ISD::BR_CC: return visitBR_CC(N); 790 case ISD::LOAD: return visitLOAD(N); 791 case ISD::STORE: return visitSTORE(N); 792 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 793 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 794 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 795 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 796 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 797 } 798 return SDValue(); 799} 800 801SDValue DAGCombiner::combine(SDNode *N) { 802 SDValue RV = visit(N); 803 804 // If nothing happened, try a target-specific DAG combine. 805 if (RV.getNode() == 0) { 806 assert(N->getOpcode() != ISD::DELETED_NODE && 807 "Node was deleted but visit returned NULL!"); 808 809 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 810 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 811 812 // Expose the DAG combiner to the target combiner impls. 813 TargetLowering::DAGCombinerInfo 814 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 815 816 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 817 } 818 } 819 820 // If N is a commutative binary node, try commuting it to enable more 821 // sdisel CSE. 822 if (RV.getNode() == 0 && 823 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 824 N->getNumValues() == 1) { 825 SDValue N0 = N->getOperand(0); 826 SDValue N1 = N->getOperand(1); 827 828 // Constant operands are canonicalized to RHS. 829 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 830 SDValue Ops[] = { N1, N0 }; 831 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 832 Ops, 2); 833 if (CSENode) 834 return SDValue(CSENode, 0); 835 } 836 } 837 838 return RV; 839} 840 841/// getInputChainForNode - Given a node, return its input chain if it has one, 842/// otherwise return a null sd operand. 843static SDValue getInputChainForNode(SDNode *N) { 844 if (unsigned NumOps = N->getNumOperands()) { 845 if (N->getOperand(0).getValueType() == MVT::Other) 846 return N->getOperand(0); 847 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 848 return N->getOperand(NumOps-1); 849 for (unsigned i = 1; i < NumOps-1; ++i) 850 if (N->getOperand(i).getValueType() == MVT::Other) 851 return N->getOperand(i); 852 } 853 return SDValue(); 854} 855 856SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 857 // If N has two operands, where one has an input chain equal to the other, 858 // the 'other' chain is redundant. 859 if (N->getNumOperands() == 2) { 860 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 861 return N->getOperand(0); 862 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 863 return N->getOperand(1); 864 } 865 866 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 867 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 868 SmallPtrSet<SDNode*, 16> SeenOps; 869 bool Changed = false; // If we should replace this token factor. 870 871 // Start out with this token factor. 872 TFs.push_back(N); 873 874 // Iterate through token factors. The TFs grows when new token factors are 875 // encountered. 876 for (unsigned i = 0; i < TFs.size(); ++i) { 877 SDNode *TF = TFs[i]; 878 879 // Check each of the operands. 880 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 881 SDValue Op = TF->getOperand(i); 882 883 switch (Op.getOpcode()) { 884 case ISD::EntryToken: 885 // Entry tokens don't need to be added to the list. They are 886 // rededundant. 887 Changed = true; 888 break; 889 890 case ISD::TokenFactor: 891 if (Op.hasOneUse() && 892 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 893 // Queue up for processing. 894 TFs.push_back(Op.getNode()); 895 // Clean up in case the token factor is removed. 896 AddToWorkList(Op.getNode()); 897 Changed = true; 898 break; 899 } 900 // Fall thru 901 902 default: 903 // Only add if it isn't already in the list. 904 if (SeenOps.insert(Op.getNode())) 905 Ops.push_back(Op); 906 else 907 Changed = true; 908 break; 909 } 910 } 911 } 912 913 SDValue Result; 914 915 // If we've change things around then replace token factor. 916 if (Changed) { 917 if (Ops.empty()) { 918 // The entry token is the only possible outcome. 919 Result = DAG.getEntryNode(); 920 } else { 921 // New and improved token factor. 922 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 923 MVT::Other, &Ops[0], Ops.size()); 924 } 925 926 // Don't add users to work list. 927 return CombineTo(N, Result, false); 928 } 929 930 return Result; 931} 932 933/// MERGE_VALUES can always be eliminated. 934SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 935 WorkListRemover DeadNodes(*this); 936 // Replacing results may cause a different MERGE_VALUES to suddenly 937 // be CSE'd with N, and carry its uses with it. Iterate until no 938 // uses remain, to ensure that the node can be safely deleted. 939 do { 940 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 942 &DeadNodes); 943 } while (!N->use_empty()); 944 removeFromWorkList(N); 945 DAG.DeleteNode(N); 946 return SDValue(N, 0); // Return N so it doesn't get rechecked! 947} 948 949static 950SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 951 SelectionDAG &DAG) { 952 EVT VT = N0.getValueType(); 953 SDValue N00 = N0.getOperand(0); 954 SDValue N01 = N0.getOperand(1); 955 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 956 957 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 958 isa<ConstantSDNode>(N00.getOperand(1))) { 959 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 960 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 961 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 962 N00.getOperand(0), N01), 963 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 964 N00.getOperand(1), N01)); 965 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 966 } 967 968 return SDValue(); 969} 970 971SDValue DAGCombiner::visitADD(SDNode *N) { 972 SDValue N0 = N->getOperand(0); 973 SDValue N1 = N->getOperand(1); 974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 976 EVT VT = N0.getValueType(); 977 978 // fold vector ops 979 if (VT.isVector()) { 980 SDValue FoldedVOp = SimplifyVBinOp(N); 981 if (FoldedVOp.getNode()) return FoldedVOp; 982 } 983 984 // fold (add x, undef) -> undef 985 if (N0.getOpcode() == ISD::UNDEF) 986 return N0; 987 if (N1.getOpcode() == ISD::UNDEF) 988 return N1; 989 // fold (add c1, c2) -> c1+c2 990 if (N0C && N1C) 991 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 992 // canonicalize constant to RHS 993 if (N0C && !N1C) 994 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 995 // fold (add x, 0) -> x 996 if (N1C && N1C->isNullValue()) 997 return N0; 998 // fold (add Sym, c) -> Sym+c 999 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1000 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1001 GA->getOpcode() == ISD::GlobalAddress) 1002 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1003 GA->getOffset() + 1004 (uint64_t)N1C->getSExtValue()); 1005 // fold ((c1-A)+c2) -> (c1+c2)-A 1006 if (N1C && N0.getOpcode() == ISD::SUB) 1007 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1008 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1009 DAG.getConstant(N1C->getAPIntValue()+ 1010 N0C->getAPIntValue(), VT), 1011 N0.getOperand(1)); 1012 // reassociate add 1013 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1014 if (RADD.getNode() != 0) 1015 return RADD; 1016 // fold ((0-A) + B) -> B-A 1017 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1018 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1020 // fold (A + (0-B)) -> A-B 1021 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1022 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1024 // fold (A+(B-A)) -> B 1025 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1026 return N1.getOperand(0); 1027 // fold ((B-A)+A) -> B 1028 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1029 return N0.getOperand(0); 1030 // fold (A+(B-(A+C))) to (B-C) 1031 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1032 N0 == N1.getOperand(1).getOperand(0)) 1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1034 N1.getOperand(1).getOperand(1)); 1035 // fold (A+(B-(C+A))) to (B-C) 1036 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1037 N0 == N1.getOperand(1).getOperand(1)) 1038 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1039 N1.getOperand(1).getOperand(0)); 1040 // fold (A+((B-A)+or-C)) to (B+or-C) 1041 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1042 N1.getOperand(0).getOpcode() == ISD::SUB && 1043 N0 == N1.getOperand(0).getOperand(1)) 1044 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1045 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1046 1047 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1048 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1049 SDValue N00 = N0.getOperand(0); 1050 SDValue N01 = N0.getOperand(1); 1051 SDValue N10 = N1.getOperand(0); 1052 SDValue N11 = N1.getOperand(1); 1053 1054 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1055 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1056 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1057 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1058 } 1059 1060 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1061 return SDValue(N, 0); 1062 1063 // fold (a+b) -> (a|b) iff a and b share no bits. 1064 if (VT.isInteger() && !VT.isVector()) { 1065 APInt LHSZero, LHSOne; 1066 APInt RHSZero, RHSOne; 1067 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1068 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1069 1070 if (LHSZero.getBoolValue()) { 1071 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1072 1073 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1074 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1075 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1076 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1077 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1078 } 1079 } 1080 1081 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1082 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1083 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1084 if (Result.getNode()) return Result; 1085 } 1086 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 1091 return SDValue(); 1092} 1093 1094SDValue DAGCombiner::visitADDC(SDNode *N) { 1095 SDValue N0 = N->getOperand(0); 1096 SDValue N1 = N->getOperand(1); 1097 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1098 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1099 EVT VT = N0.getValueType(); 1100 1101 // If the flag result is dead, turn this into an ADD. 1102 if (N->hasNUsesOfValue(0, 1)) 1103 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1104 DAG.getNode(ISD::CARRY_FALSE, 1105 N->getDebugLoc(), MVT::Flag)); 1106 1107 // canonicalize constant to RHS. 1108 if (N0C && !N1C) 1109 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1110 1111 // fold (addc x, 0) -> x + no carry out 1112 if (N1C && N1C->isNullValue()) 1113 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1114 N->getDebugLoc(), MVT::Flag)); 1115 1116 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1117 APInt LHSZero, LHSOne; 1118 APInt RHSZero, RHSOne; 1119 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1120 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1121 1122 if (LHSZero.getBoolValue()) { 1123 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1124 1125 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1126 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1127 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1128 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1129 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1130 DAG.getNode(ISD::CARRY_FALSE, 1131 N->getDebugLoc(), MVT::Flag)); 1132 } 1133 1134 return SDValue(); 1135} 1136 1137SDValue DAGCombiner::visitADDE(SDNode *N) { 1138 SDValue N0 = N->getOperand(0); 1139 SDValue N1 = N->getOperand(1); 1140 SDValue CarryIn = N->getOperand(2); 1141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1143 1144 // canonicalize constant to RHS 1145 if (N0C && !N1C) 1146 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1147 N1, N0, CarryIn); 1148 1149 // fold (adde x, y, false) -> (addc x, y) 1150 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1151 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1152 1153 return SDValue(); 1154} 1155 1156SDValue DAGCombiner::visitSUB(SDNode *N) { 1157 SDValue N0 = N->getOperand(0); 1158 SDValue N1 = N->getOperand(1); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1161 EVT VT = N0.getValueType(); 1162 1163 // fold vector ops 1164 if (VT.isVector()) { 1165 SDValue FoldedVOp = SimplifyVBinOp(N); 1166 if (FoldedVOp.getNode()) return FoldedVOp; 1167 } 1168 1169 // fold (sub x, x) -> 0 1170 if (N0 == N1) 1171 return DAG.getConstant(0, N->getValueType(0)); 1172 // fold (sub c1, c2) -> c1-c2 1173 if (N0C && N1C) 1174 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1175 // fold (sub x, c) -> (add x, -c) 1176 if (N1C) 1177 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1178 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1179 // fold (A+B)-A -> B 1180 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1181 return N0.getOperand(1); 1182 // fold (A+B)-B -> A 1183 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1184 return N0.getOperand(0); 1185 // fold ((A+(B+or-C))-B) -> A+or-C 1186 if (N0.getOpcode() == ISD::ADD && 1187 (N0.getOperand(1).getOpcode() == ISD::SUB || 1188 N0.getOperand(1).getOpcode() == ISD::ADD) && 1189 N0.getOperand(1).getOperand(0) == N1) 1190 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1191 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1192 // fold ((A+(C+B))-B) -> A+C 1193 if (N0.getOpcode() == ISD::ADD && 1194 N0.getOperand(1).getOpcode() == ISD::ADD && 1195 N0.getOperand(1).getOperand(1) == N1) 1196 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1197 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1198 // fold ((A-(B-C))-C) -> A-B 1199 if (N0.getOpcode() == ISD::SUB && 1200 N0.getOperand(1).getOpcode() == ISD::SUB && 1201 N0.getOperand(1).getOperand(1) == N1) 1202 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1203 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1204 1205 // If either operand of a sub is undef, the result is undef 1206 if (N0.getOpcode() == ISD::UNDEF) 1207 return N0; 1208 if (N1.getOpcode() == ISD::UNDEF) 1209 return N1; 1210 1211 // If the relocation model supports it, consider symbol offsets. 1212 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1213 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1214 // fold (sub Sym, c) -> Sym-c 1215 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1216 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1217 GA->getOffset() - 1218 (uint64_t)N1C->getSExtValue()); 1219 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1220 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1221 if (GA->getGlobal() == GB->getGlobal()) 1222 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1223 VT); 1224 } 1225 1226 return SDValue(); 1227} 1228 1229SDValue DAGCombiner::visitMUL(SDNode *N) { 1230 SDValue N0 = N->getOperand(0); 1231 SDValue N1 = N->getOperand(1); 1232 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1233 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1234 EVT VT = N0.getValueType(); 1235 1236 // fold vector ops 1237 if (VT.isVector()) { 1238 SDValue FoldedVOp = SimplifyVBinOp(N); 1239 if (FoldedVOp.getNode()) return FoldedVOp; 1240 } 1241 1242 // fold (mul x, undef) -> 0 1243 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1244 return DAG.getConstant(0, VT); 1245 // fold (mul c1, c2) -> c1*c2 1246 if (N0C && N1C) 1247 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1248 // canonicalize constant to RHS 1249 if (N0C && !N1C) 1250 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1251 // fold (mul x, 0) -> 0 1252 if (N1C && N1C->isNullValue()) 1253 return N1; 1254 // fold (mul x, -1) -> 0-x 1255 if (N1C && N1C->isAllOnesValue()) 1256 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1257 DAG.getConstant(0, VT), N0); 1258 // fold (mul x, (1 << c)) -> x << c 1259 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1260 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1261 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1262 getShiftAmountTy())); 1263 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1264 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1265 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1266 // FIXME: If the input is something that is easily negated (e.g. a 1267 // single-use add), we should put the negate there. 1268 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1269 DAG.getConstant(0, VT), 1270 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1271 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1272 } 1273 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1274 if (N1C && N0.getOpcode() == ISD::SHL && 1275 isa<ConstantSDNode>(N0.getOperand(1))) { 1276 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1277 N1, N0.getOperand(1)); 1278 AddToWorkList(C3.getNode()); 1279 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1280 N0.getOperand(0), C3); 1281 } 1282 1283 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1284 // use. 1285 { 1286 SDValue Sh(0,0), Y(0,0); 1287 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1288 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1289 N0.getNode()->hasOneUse()) { 1290 Sh = N0; Y = N1; 1291 } else if (N1.getOpcode() == ISD::SHL && 1292 isa<ConstantSDNode>(N1.getOperand(1)) && 1293 N1.getNode()->hasOneUse()) { 1294 Sh = N1; Y = N0; 1295 } 1296 1297 if (Sh.getNode()) { 1298 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1299 Sh.getOperand(0), Y); 1300 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1301 Mul, Sh.getOperand(1)); 1302 } 1303 } 1304 1305 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1306 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1307 isa<ConstantSDNode>(N0.getOperand(1))) 1308 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1309 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1310 N0.getOperand(0), N1), 1311 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1312 N0.getOperand(1), N1)); 1313 1314 // reassociate mul 1315 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1316 if (RMUL.getNode() != 0) 1317 return RMUL; 1318 1319 return SDValue(); 1320} 1321 1322SDValue DAGCombiner::visitSDIV(SDNode *N) { 1323 SDValue N0 = N->getOperand(0); 1324 SDValue N1 = N->getOperand(1); 1325 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1327 EVT VT = N->getValueType(0); 1328 1329 // fold vector ops 1330 if (VT.isVector()) { 1331 SDValue FoldedVOp = SimplifyVBinOp(N); 1332 if (FoldedVOp.getNode()) return FoldedVOp; 1333 } 1334 1335 // fold (sdiv c1, c2) -> c1/c2 1336 if (N0C && N1C && !N1C->isNullValue()) 1337 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1338 // fold (sdiv X, 1) -> X 1339 if (N1C && N1C->getSExtValue() == 1LL) 1340 return N0; 1341 // fold (sdiv X, -1) -> 0-X 1342 if (N1C && N1C->isAllOnesValue()) 1343 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1344 DAG.getConstant(0, VT), N0); 1345 // If we know the sign bits of both operands are zero, strength reduce to a 1346 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1347 if (!VT.isVector()) { 1348 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1349 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1350 N0, N1); 1351 } 1352 // fold (sdiv X, pow2) -> simple ops after legalize 1353 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1354 (isPowerOf2_64(N1C->getSExtValue()) || 1355 isPowerOf2_64(-N1C->getSExtValue()))) { 1356 // If dividing by powers of two is cheap, then don't perform the following 1357 // fold. 1358 if (TLI.isPow2DivCheap()) 1359 return SDValue(); 1360 1361 int64_t pow2 = N1C->getSExtValue(); 1362 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1363 unsigned lg2 = Log2_64(abs2); 1364 1365 // Splat the sign bit into the register 1366 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1367 DAG.getConstant(VT.getSizeInBits()-1, 1368 getShiftAmountTy())); 1369 AddToWorkList(SGN.getNode()); 1370 1371 // Add (N0 < 0) ? abs2 - 1 : 0; 1372 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1373 DAG.getConstant(VT.getSizeInBits() - lg2, 1374 getShiftAmountTy())); 1375 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1376 AddToWorkList(SRL.getNode()); 1377 AddToWorkList(ADD.getNode()); // Divide by pow2 1378 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1379 DAG.getConstant(lg2, getShiftAmountTy())); 1380 1381 // If we're dividing by a positive value, we're done. Otherwise, we must 1382 // negate the result. 1383 if (pow2 > 0) 1384 return SRA; 1385 1386 AddToWorkList(SRA.getNode()); 1387 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1388 DAG.getConstant(0, VT), SRA); 1389 } 1390 1391 // if integer divide is expensive and we satisfy the requirements, emit an 1392 // alternate sequence. 1393 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1394 !TLI.isIntDivCheap()) { 1395 SDValue Op = BuildSDIV(N); 1396 if (Op.getNode()) return Op; 1397 } 1398 1399 // undef / X -> 0 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return DAG.getConstant(0, VT); 1402 // X / undef -> undef 1403 if (N1.getOpcode() == ISD::UNDEF) 1404 return N1; 1405 1406 return SDValue(); 1407} 1408 1409SDValue DAGCombiner::visitUDIV(SDNode *N) { 1410 SDValue N0 = N->getOperand(0); 1411 SDValue N1 = N->getOperand(1); 1412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1414 EVT VT = N->getValueType(0); 1415 1416 // fold vector ops 1417 if (VT.isVector()) { 1418 SDValue FoldedVOp = SimplifyVBinOp(N); 1419 if (FoldedVOp.getNode()) return FoldedVOp; 1420 } 1421 1422 // fold (udiv c1, c2) -> c1/c2 1423 if (N0C && N1C && !N1C->isNullValue()) 1424 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1425 // fold (udiv x, (1 << c)) -> x >>u c 1426 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1428 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1429 getShiftAmountTy())); 1430 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1431 if (N1.getOpcode() == ISD::SHL) { 1432 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1433 if (SHC->getAPIntValue().isPowerOf2()) { 1434 EVT ADDVT = N1.getOperand(1).getValueType(); 1435 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1436 N1.getOperand(1), 1437 DAG.getConstant(SHC->getAPIntValue() 1438 .logBase2(), 1439 ADDVT)); 1440 AddToWorkList(Add.getNode()); 1441 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1442 } 1443 } 1444 } 1445 // fold (udiv x, c) -> alternate 1446 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1447 SDValue Op = BuildUDIV(N); 1448 if (Op.getNode()) return Op; 1449 } 1450 1451 // undef / X -> 0 1452 if (N0.getOpcode() == ISD::UNDEF) 1453 return DAG.getConstant(0, VT); 1454 // X / undef -> undef 1455 if (N1.getOpcode() == ISD::UNDEF) 1456 return N1; 1457 1458 return SDValue(); 1459} 1460 1461SDValue DAGCombiner::visitSREM(SDNode *N) { 1462 SDValue N0 = N->getOperand(0); 1463 SDValue N1 = N->getOperand(1); 1464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1466 EVT VT = N->getValueType(0); 1467 1468 // fold (srem c1, c2) -> c1%c2 1469 if (N0C && N1C && !N1C->isNullValue()) 1470 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1471 // If we know the sign bits of both operands are zero, strength reduce to a 1472 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1473 if (!VT.isVector()) { 1474 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1475 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1476 } 1477 1478 // If X/C can be simplified by the division-by-constant logic, lower 1479 // X%C to the equivalent of X-X/C*C. 1480 if (N1C && !N1C->isNullValue()) { 1481 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1482 AddToWorkList(Div.getNode()); 1483 SDValue OptimizedDiv = combine(Div.getNode()); 1484 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1485 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1486 OptimizedDiv, N1); 1487 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1488 AddToWorkList(Mul.getNode()); 1489 return Sub; 1490 } 1491 } 1492 1493 // undef % X -> 0 1494 if (N0.getOpcode() == ISD::UNDEF) 1495 return DAG.getConstant(0, VT); 1496 // X % undef -> undef 1497 if (N1.getOpcode() == ISD::UNDEF) 1498 return N1; 1499 1500 return SDValue(); 1501} 1502 1503SDValue DAGCombiner::visitUREM(SDNode *N) { 1504 SDValue N0 = N->getOperand(0); 1505 SDValue N1 = N->getOperand(1); 1506 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1507 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1508 EVT VT = N->getValueType(0); 1509 1510 // fold (urem c1, c2) -> c1%c2 1511 if (N0C && N1C && !N1C->isNullValue()) 1512 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1513 // fold (urem x, pow2) -> (and x, pow2-1) 1514 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1515 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1516 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1517 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1518 if (N1.getOpcode() == ISD::SHL) { 1519 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1520 if (SHC->getAPIntValue().isPowerOf2()) { 1521 SDValue Add = 1522 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1523 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1524 VT)); 1525 AddToWorkList(Add.getNode()); 1526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1527 } 1528 } 1529 } 1530 1531 // If X/C can be simplified by the division-by-constant logic, lower 1532 // X%C to the equivalent of X-X/C*C. 1533 if (N1C && !N1C->isNullValue()) { 1534 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1535 AddToWorkList(Div.getNode()); 1536 SDValue OptimizedDiv = combine(Div.getNode()); 1537 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1538 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1539 OptimizedDiv, N1); 1540 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1541 AddToWorkList(Mul.getNode()); 1542 return Sub; 1543 } 1544 } 1545 1546 // undef % X -> 0 1547 if (N0.getOpcode() == ISD::UNDEF) 1548 return DAG.getConstant(0, VT); 1549 // X % undef -> undef 1550 if (N1.getOpcode() == ISD::UNDEF) 1551 return N1; 1552 1553 return SDValue(); 1554} 1555 1556SDValue DAGCombiner::visitMULHS(SDNode *N) { 1557 SDValue N0 = N->getOperand(0); 1558 SDValue N1 = N->getOperand(1); 1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1560 EVT VT = N->getValueType(0); 1561 1562 // fold (mulhs x, 0) -> 0 1563 if (N1C && N1C->isNullValue()) 1564 return N1; 1565 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1566 if (N1C && N1C->getAPIntValue() == 1) 1567 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1568 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1569 getShiftAmountTy())); 1570 // fold (mulhs x, undef) -> 0 1571 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1572 return DAG.getConstant(0, VT); 1573 1574 return SDValue(); 1575} 1576 1577SDValue DAGCombiner::visitMULHU(SDNode *N) { 1578 SDValue N0 = N->getOperand(0); 1579 SDValue N1 = N->getOperand(1); 1580 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1581 EVT VT = N->getValueType(0); 1582 1583 // fold (mulhu x, 0) -> 0 1584 if (N1C && N1C->isNullValue()) 1585 return N1; 1586 // fold (mulhu x, 1) -> 0 1587 if (N1C && N1C->getAPIntValue() == 1) 1588 return DAG.getConstant(0, N0.getValueType()); 1589 // fold (mulhu x, undef) -> 0 1590 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1591 return DAG.getConstant(0, VT); 1592 1593 return SDValue(); 1594} 1595 1596/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1597/// compute two values. LoOp and HiOp give the opcodes for the two computations 1598/// that are being performed. Return true if a simplification was made. 1599/// 1600SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1601 unsigned HiOp) { 1602 // If the high half is not needed, just compute the low half. 1603 bool HiExists = N->hasAnyUseOfValue(1); 1604 if (!HiExists && 1605 (!LegalOperations || 1606 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1607 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1608 N->op_begin(), N->getNumOperands()); 1609 return CombineTo(N, Res, Res); 1610 } 1611 1612 // If the low half is not needed, just compute the high half. 1613 bool LoExists = N->hasAnyUseOfValue(0); 1614 if (!LoExists && 1615 (!LegalOperations || 1616 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1617 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1618 N->op_begin(), N->getNumOperands()); 1619 return CombineTo(N, Res, Res); 1620 } 1621 1622 // If both halves are used, return as it is. 1623 if (LoExists && HiExists) 1624 return SDValue(); 1625 1626 // If the two computed results can be simplified separately, separate them. 1627 if (LoExists) { 1628 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1629 N->op_begin(), N->getNumOperands()); 1630 AddToWorkList(Lo.getNode()); 1631 SDValue LoOpt = combine(Lo.getNode()); 1632 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1633 (!LegalOperations || 1634 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1635 return CombineTo(N, LoOpt, LoOpt); 1636 } 1637 1638 if (HiExists) { 1639 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1640 N->op_begin(), N->getNumOperands()); 1641 AddToWorkList(Hi.getNode()); 1642 SDValue HiOpt = combine(Hi.getNode()); 1643 if (HiOpt.getNode() && HiOpt != Hi && 1644 (!LegalOperations || 1645 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1646 return CombineTo(N, HiOpt, HiOpt); 1647 } 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1667 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1668 if (Res.getNode()) return Res; 1669 1670 return SDValue(); 1671} 1672 1673SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1674 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1675 if (Res.getNode()) return Res; 1676 1677 return SDValue(); 1678} 1679 1680/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1681/// two operands of the same opcode, try to simplify it. 1682SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1683 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1684 EVT VT = N0.getValueType(); 1685 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1686 1687 // For each of OP in AND/OR/XOR: 1688 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1689 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1690 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1691 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1692 // 1693 // do not sink logical op inside of a vector extend, since it may combine 1694 // into a vsetcc. 1695 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1696 N0.getOpcode() == ISD::SIGN_EXTEND || 1697 (N0.getOpcode() == ISD::TRUNCATE && 1698 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1699 !VT.isVector() && 1700 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && 1701 (!LegalOperations || 1702 TLI.isOperationLegal(N->getOpcode(), N0.getOperand(0).getValueType()))) { 1703 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1704 N0.getOperand(0).getValueType(), 1705 N0.getOperand(0), N1.getOperand(0)); 1706 AddToWorkList(ORNode.getNode()); 1707 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1708 } 1709 1710 // For each of OP in SHL/SRL/SRA/AND... 1711 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1712 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1713 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1714 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1715 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1716 N0.getOperand(1) == N1.getOperand(1)) { 1717 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1718 N0.getOperand(0).getValueType(), 1719 N0.getOperand(0), N1.getOperand(0)); 1720 AddToWorkList(ORNode.getNode()); 1721 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1722 ORNode, N0.getOperand(1)); 1723 } 1724 1725 return SDValue(); 1726} 1727 1728SDValue DAGCombiner::visitAND(SDNode *N) { 1729 SDValue N0 = N->getOperand(0); 1730 SDValue N1 = N->getOperand(1); 1731 SDValue LL, LR, RL, RR, CC0, CC1; 1732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1734 EVT VT = N1.getValueType(); 1735 unsigned BitWidth = VT.getSizeInBits(); 1736 1737 // fold vector ops 1738 if (VT.isVector()) { 1739 SDValue FoldedVOp = SimplifyVBinOp(N); 1740 if (FoldedVOp.getNode()) return FoldedVOp; 1741 } 1742 1743 // fold (and x, undef) -> 0 1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1745 return DAG.getConstant(0, VT); 1746 // fold (and c1, c2) -> c1&c2 1747 if (N0C && N1C) 1748 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1749 // canonicalize constant to RHS 1750 if (N0C && !N1C) 1751 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1752 // fold (and x, -1) -> x 1753 if (N1C && N1C->isAllOnesValue()) 1754 return N0; 1755 // if (and x, c) is known to be zero, return 0 1756 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1757 APInt::getAllOnesValue(BitWidth))) 1758 return DAG.getConstant(0, VT); 1759 // reassociate and 1760 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1761 if (RAND.getNode() != 0) 1762 return RAND; 1763 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1764 if (N1C && N0.getOpcode() == ISD::OR) 1765 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1766 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1767 return N1; 1768 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1769 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1770 SDValue N0Op0 = N0.getOperand(0); 1771 APInt Mask = ~N1C->getAPIntValue(); 1772 Mask.trunc(N0Op0.getValueSizeInBits()); 1773 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1774 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1775 N0.getValueType(), N0Op0); 1776 1777 // Replace uses of the AND with uses of the Zero extend node. 1778 CombineTo(N, Zext); 1779 1780 // We actually want to replace all uses of the any_extend with the 1781 // zero_extend, to avoid duplicating things. This will later cause this 1782 // AND to be folded. 1783 CombineTo(N0.getNode(), Zext); 1784 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1785 } 1786 } 1787 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1788 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1789 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1790 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1791 1792 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1793 LL.getValueType().isInteger()) { 1794 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1795 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1796 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1797 LR.getValueType(), LL, RL); 1798 AddToWorkList(ORNode.getNode()); 1799 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1800 } 1801 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1803 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1804 LR.getValueType(), LL, RL); 1805 AddToWorkList(ANDNode.getNode()); 1806 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1807 } 1808 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1809 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1810 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1811 LR.getValueType(), LL, RL); 1812 AddToWorkList(ORNode.getNode()); 1813 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1814 } 1815 } 1816 // canonicalize equivalent to ll == rl 1817 if (LL == RR && LR == RL) { 1818 Op1 = ISD::getSetCCSwappedOperands(Op1); 1819 std::swap(RL, RR); 1820 } 1821 if (LL == RL && LR == RR) { 1822 bool isInteger = LL.getValueType().isInteger(); 1823 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1824 if (Result != ISD::SETCC_INVALID && 1825 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1826 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1827 LL, LR, Result); 1828 } 1829 } 1830 1831 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1832 if (N0.getOpcode() == N1.getOpcode()) { 1833 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1834 if (Tmp.getNode()) return Tmp; 1835 } 1836 1837 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1838 // fold (and (sra)) -> (and (srl)) when possible. 1839 if (!VT.isVector() && 1840 SimplifyDemandedBits(SDValue(N, 0))) 1841 return SDValue(N, 0); 1842 // fold (zext_inreg (extload x)) -> (zextload x) 1843 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1844 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1845 EVT MemVT = LN0->getMemoryVT(); 1846 // If we zero all the possible extended bits, then we can turn this into 1847 // a zextload if we are running before legalize or the operation is legal. 1848 unsigned BitWidth = N1.getValueSizeInBits(); 1849 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1850 BitWidth - MemVT.getSizeInBits())) && 1851 ((!LegalOperations && !LN0->isVolatile()) || 1852 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1853 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1854 LN0->getChain(), LN0->getBasePtr(), 1855 LN0->getSrcValue(), 1856 LN0->getSrcValueOffset(), MemVT, 1857 LN0->isVolatile(), LN0->getAlignment()); 1858 AddToWorkList(N); 1859 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1860 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1861 } 1862 } 1863 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1864 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1865 N0.hasOneUse()) { 1866 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1867 EVT MemVT = LN0->getMemoryVT(); 1868 // If we zero all the possible extended bits, then we can turn this into 1869 // a zextload if we are running before legalize or the operation is legal. 1870 unsigned BitWidth = N1.getValueSizeInBits(); 1871 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1872 BitWidth - MemVT.getSizeInBits())) && 1873 ((!LegalOperations && !LN0->isVolatile()) || 1874 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1875 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1876 LN0->getChain(), 1877 LN0->getBasePtr(), LN0->getSrcValue(), 1878 LN0->getSrcValueOffset(), MemVT, 1879 LN0->isVolatile(), LN0->getAlignment()); 1880 AddToWorkList(N); 1881 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1882 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1883 } 1884 } 1885 1886 // fold (and (load x), 255) -> (zextload x, i8) 1887 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1888 if (N1C && N0.getOpcode() == ISD::LOAD) { 1889 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1890 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1891 LN0->isUnindexed() && N0.hasOneUse() && 1892 // Do not change the width of a volatile load. 1893 !LN0->isVolatile()) { 1894 EVT ExtVT = MVT::Other; 1895 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1896 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1897 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1898 1899 EVT LoadedVT = LN0->getMemoryVT(); 1900 1901 // Do not generate loads of non-round integer types since these can 1902 // be expensive (and would be wrong if the type is not byte sized). 1903 if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1904 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1905 EVT PtrType = N0.getOperand(1).getValueType(); 1906 1907 // For big endian targets, we need to add an offset to the pointer to 1908 // load the correct bytes. For little endian systems, we merely need to 1909 // read fewer bytes from the same pointer. 1910 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1911 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1912 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1913 unsigned Alignment = LN0->getAlignment(); 1914 SDValue NewPtr = LN0->getBasePtr(); 1915 1916 if (TLI.isBigEndian()) { 1917 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1918 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1919 Alignment = MinAlign(Alignment, PtrOff); 1920 } 1921 1922 AddToWorkList(NewPtr.getNode()); 1923 SDValue Load = 1924 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1925 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1926 ExtVT, LN0->isVolatile(), Alignment); 1927 AddToWorkList(N); 1928 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1929 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1930 } 1931 } 1932 } 1933 1934 return SDValue(); 1935} 1936 1937SDValue DAGCombiner::visitOR(SDNode *N) { 1938 SDValue N0 = N->getOperand(0); 1939 SDValue N1 = N->getOperand(1); 1940 SDValue LL, LR, RL, RR, CC0, CC1; 1941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1943 EVT VT = N1.getValueType(); 1944 1945 // fold vector ops 1946 if (VT.isVector()) { 1947 SDValue FoldedVOp = SimplifyVBinOp(N); 1948 if (FoldedVOp.getNode()) return FoldedVOp; 1949 } 1950 1951 // fold (or x, undef) -> -1 1952 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 1953 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 1954 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 1955 } 1956 // fold (or c1, c2) -> c1|c2 1957 if (N0C && N1C) 1958 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1959 // canonicalize constant to RHS 1960 if (N0C && !N1C) 1961 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1962 // fold (or x, 0) -> x 1963 if (N1C && N1C->isNullValue()) 1964 return N0; 1965 // fold (or x, -1) -> -1 1966 if (N1C && N1C->isAllOnesValue()) 1967 return N1; 1968 // fold (or x, c) -> c iff (x & ~c) == 0 1969 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1970 return N1; 1971 // reassociate or 1972 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1973 if (ROR.getNode() != 0) 1974 return ROR; 1975 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1976 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1977 isa<ConstantSDNode>(N0.getOperand(1))) { 1978 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1979 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1980 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1981 N0.getOperand(0), N1), 1982 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1983 } 1984 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1985 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1986 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1987 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1988 1989 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1990 LL.getValueType().isInteger()) { 1991 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1992 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1993 if (cast<ConstantSDNode>(LR)->isNullValue() && 1994 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1995 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1996 LR.getValueType(), LL, RL); 1997 AddToWorkList(ORNode.getNode()); 1998 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1999 } 2000 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2001 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2002 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2003 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2004 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2005 LR.getValueType(), LL, RL); 2006 AddToWorkList(ANDNode.getNode()); 2007 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2008 } 2009 } 2010 // canonicalize equivalent to ll == rl 2011 if (LL == RR && LR == RL) { 2012 Op1 = ISD::getSetCCSwappedOperands(Op1); 2013 std::swap(RL, RR); 2014 } 2015 if (LL == RL && LR == RR) { 2016 bool isInteger = LL.getValueType().isInteger(); 2017 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2018 if (Result != ISD::SETCC_INVALID && 2019 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2020 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2021 LL, LR, Result); 2022 } 2023 } 2024 2025 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2026 if (N0.getOpcode() == N1.getOpcode()) { 2027 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2028 if (Tmp.getNode()) return Tmp; 2029 } 2030 2031 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2032 if (N0.getOpcode() == ISD::AND && 2033 N1.getOpcode() == ISD::AND && 2034 N0.getOperand(1).getOpcode() == ISD::Constant && 2035 N1.getOperand(1).getOpcode() == ISD::Constant && 2036 // Don't increase # computations. 2037 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2038 // We can only do this xform if we know that bits from X that are set in C2 2039 // but not in C1 are already zero. Likewise for Y. 2040 const APInt &LHSMask = 2041 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2042 const APInt &RHSMask = 2043 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2044 2045 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2046 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2047 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2048 N0.getOperand(0), N1.getOperand(0)); 2049 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2050 DAG.getConstant(LHSMask | RHSMask, VT)); 2051 } 2052 } 2053 2054 // See if this is some rotate idiom. 2055 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2056 return SDValue(Rot, 0); 2057 2058 return SDValue(); 2059} 2060 2061/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2062static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2063 if (Op.getOpcode() == ISD::AND) { 2064 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2065 Mask = Op.getOperand(1); 2066 Op = Op.getOperand(0); 2067 } else { 2068 return false; 2069 } 2070 } 2071 2072 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2073 Shift = Op; 2074 return true; 2075 } 2076 2077 return false; 2078} 2079 2080// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2081// idioms for rotate, and if the target supports rotation instructions, generate 2082// a rot[lr]. 2083SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2084 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2085 EVT VT = LHS.getValueType(); 2086 if (!TLI.isTypeLegal(VT)) return 0; 2087 2088 // The target must have at least one rotate flavor. 2089 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2090 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2091 if (!HasROTL && !HasROTR) return 0; 2092 2093 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2094 SDValue LHSShift; // The shift. 2095 SDValue LHSMask; // AND value if any. 2096 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2097 return 0; // Not part of a rotate. 2098 2099 SDValue RHSShift; // The shift. 2100 SDValue RHSMask; // AND value if any. 2101 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2102 return 0; // Not part of a rotate. 2103 2104 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2105 return 0; // Not shifting the same value. 2106 2107 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2108 return 0; // Shifts must disagree. 2109 2110 // Canonicalize shl to left side in a shl/srl pair. 2111 if (RHSShift.getOpcode() == ISD::SHL) { 2112 std::swap(LHS, RHS); 2113 std::swap(LHSShift, RHSShift); 2114 std::swap(LHSMask , RHSMask ); 2115 } 2116 2117 unsigned OpSizeInBits = VT.getSizeInBits(); 2118 SDValue LHSShiftArg = LHSShift.getOperand(0); 2119 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2120 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2121 2122 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2123 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2124 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2125 RHSShiftAmt.getOpcode() == ISD::Constant) { 2126 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2127 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2128 if ((LShVal + RShVal) != OpSizeInBits) 2129 return 0; 2130 2131 SDValue Rot; 2132 if (HasROTL) 2133 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2134 else 2135 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2136 2137 // If there is an AND of either shifted operand, apply it to the result. 2138 if (LHSMask.getNode() || RHSMask.getNode()) { 2139 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2140 2141 if (LHSMask.getNode()) { 2142 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2143 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2144 } 2145 if (RHSMask.getNode()) { 2146 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2147 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2148 } 2149 2150 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2151 } 2152 2153 return Rot.getNode(); 2154 } 2155 2156 // If there is a mask here, and we have a variable shift, we can't be sure 2157 // that we're masking out the right stuff. 2158 if (LHSMask.getNode() || RHSMask.getNode()) 2159 return 0; 2160 2161 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2162 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2163 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2164 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2165 if (ConstantSDNode *SUBC = 2166 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2167 if (SUBC->getAPIntValue() == OpSizeInBits) { 2168 if (HasROTL) 2169 return DAG.getNode(ISD::ROTL, DL, VT, 2170 LHSShiftArg, LHSShiftAmt).getNode(); 2171 else 2172 return DAG.getNode(ISD::ROTR, DL, VT, 2173 LHSShiftArg, RHSShiftAmt).getNode(); 2174 } 2175 } 2176 } 2177 2178 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2179 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2180 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2181 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2182 if (ConstantSDNode *SUBC = 2183 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2184 if (SUBC->getAPIntValue() == OpSizeInBits) { 2185 if (HasROTR) 2186 return DAG.getNode(ISD::ROTR, DL, VT, 2187 LHSShiftArg, RHSShiftAmt).getNode(); 2188 else 2189 return DAG.getNode(ISD::ROTL, DL, VT, 2190 LHSShiftArg, LHSShiftAmt).getNode(); 2191 } 2192 } 2193 } 2194 2195 // Look for sign/zext/any-extended or truncate cases: 2196 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2197 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2198 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2199 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2200 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2201 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2202 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2203 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2204 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2205 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2206 if (RExtOp0.getOpcode() == ISD::SUB && 2207 RExtOp0.getOperand(1) == LExtOp0) { 2208 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2209 // (rotl x, y) 2210 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2211 // (rotr x, (sub 32, y)) 2212 if (ConstantSDNode *SUBC = 2213 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2214 if (SUBC->getAPIntValue() == OpSizeInBits) { 2215 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2216 LHSShiftArg, 2217 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2218 } 2219 } 2220 } else if (LExtOp0.getOpcode() == ISD::SUB && 2221 RExtOp0 == LExtOp0.getOperand(1)) { 2222 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2223 // (rotr x, y) 2224 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2225 // (rotl x, (sub 32, y)) 2226 if (ConstantSDNode *SUBC = 2227 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2228 if (SUBC->getAPIntValue() == OpSizeInBits) { 2229 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2230 LHSShiftArg, 2231 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2232 } 2233 } 2234 } 2235 } 2236 2237 return 0; 2238} 2239 2240SDValue DAGCombiner::visitXOR(SDNode *N) { 2241 SDValue N0 = N->getOperand(0); 2242 SDValue N1 = N->getOperand(1); 2243 SDValue LHS, RHS, CC; 2244 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2245 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2246 EVT VT = N0.getValueType(); 2247 2248 // fold vector ops 2249 if (VT.isVector()) { 2250 SDValue FoldedVOp = SimplifyVBinOp(N); 2251 if (FoldedVOp.getNode()) return FoldedVOp; 2252 } 2253 2254 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2255 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2256 return DAG.getConstant(0, VT); 2257 // fold (xor x, undef) -> undef 2258 if (N0.getOpcode() == ISD::UNDEF) 2259 return N0; 2260 if (N1.getOpcode() == ISD::UNDEF) 2261 return N1; 2262 // fold (xor c1, c2) -> c1^c2 2263 if (N0C && N1C) 2264 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2265 // canonicalize constant to RHS 2266 if (N0C && !N1C) 2267 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2268 // fold (xor x, 0) -> x 2269 if (N1C && N1C->isNullValue()) 2270 return N0; 2271 // reassociate xor 2272 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2273 if (RXOR.getNode() != 0) 2274 return RXOR; 2275 2276 // fold !(x cc y) -> (x !cc y) 2277 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2278 bool isInt = LHS.getValueType().isInteger(); 2279 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2280 isInt); 2281 2282 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2283 switch (N0.getOpcode()) { 2284 default: 2285 llvm_unreachable("Unhandled SetCC Equivalent!"); 2286 case ISD::SETCC: 2287 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2288 case ISD::SELECT_CC: 2289 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2290 N0.getOperand(3), NotCC); 2291 } 2292 } 2293 } 2294 2295 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2296 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2297 N0.getNode()->hasOneUse() && 2298 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2299 SDValue V = N0.getOperand(0); 2300 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2301 DAG.getConstant(1, V.getValueType())); 2302 AddToWorkList(V.getNode()); 2303 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2304 } 2305 2306 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2307 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2308 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2309 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2310 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2311 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2312 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2313 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2314 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2315 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2316 } 2317 } 2318 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2319 if (N1C && N1C->isAllOnesValue() && 2320 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2321 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2322 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2323 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2324 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2325 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2326 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2327 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2328 } 2329 } 2330 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2331 if (N1C && N0.getOpcode() == ISD::XOR) { 2332 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2333 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2334 if (N00C) 2335 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2336 DAG.getConstant(N1C->getAPIntValue() ^ 2337 N00C->getAPIntValue(), VT)); 2338 if (N01C) 2339 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2340 DAG.getConstant(N1C->getAPIntValue() ^ 2341 N01C->getAPIntValue(), VT)); 2342 } 2343 // fold (xor x, x) -> 0 2344 if (N0 == N1) { 2345 if (!VT.isVector()) { 2346 return DAG.getConstant(0, VT); 2347 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2348 // Produce a vector of zeros. 2349 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2350 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2351 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2352 &Ops[0], Ops.size()); 2353 } 2354 } 2355 2356 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2357 if (N0.getOpcode() == N1.getOpcode()) { 2358 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2359 if (Tmp.getNode()) return Tmp; 2360 } 2361 2362 // Simplify the expression using non-local knowledge. 2363 if (!VT.isVector() && 2364 SimplifyDemandedBits(SDValue(N, 0))) 2365 return SDValue(N, 0); 2366 2367 return SDValue(); 2368} 2369 2370/// visitShiftByConstant - Handle transforms common to the three shifts, when 2371/// the shift amount is a constant. 2372SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2373 SDNode *LHS = N->getOperand(0).getNode(); 2374 if (!LHS->hasOneUse()) return SDValue(); 2375 2376 // We want to pull some binops through shifts, so that we have (and (shift)) 2377 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2378 // thing happens with address calculations, so it's important to canonicalize 2379 // it. 2380 bool HighBitSet = false; // Can we transform this if the high bit is set? 2381 2382 switch (LHS->getOpcode()) { 2383 default: return SDValue(); 2384 case ISD::OR: 2385 case ISD::XOR: 2386 HighBitSet = false; // We can only transform sra if the high bit is clear. 2387 break; 2388 case ISD::AND: 2389 HighBitSet = true; // We can only transform sra if the high bit is set. 2390 break; 2391 case ISD::ADD: 2392 if (N->getOpcode() != ISD::SHL) 2393 return SDValue(); // only shl(add) not sr[al](add). 2394 HighBitSet = false; // We can only transform sra if the high bit is clear. 2395 break; 2396 } 2397 2398 // We require the RHS of the binop to be a constant as well. 2399 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2400 if (!BinOpCst) return SDValue(); 2401 2402 // FIXME: disable this unless the input to the binop is a shift by a constant. 2403 // If it is not a shift, it pessimizes some common cases like: 2404 // 2405 // void foo(int *X, int i) { X[i & 1235] = 1; } 2406 // int bar(int *X, int i) { return X[i & 255]; } 2407 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2408 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2409 BinOpLHSVal->getOpcode() != ISD::SRA && 2410 BinOpLHSVal->getOpcode() != ISD::SRL) || 2411 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2412 return SDValue(); 2413 2414 EVT VT = N->getValueType(0); 2415 2416 // If this is a signed shift right, and the high bit is modified by the 2417 // logical operation, do not perform the transformation. The highBitSet 2418 // boolean indicates the value of the high bit of the constant which would 2419 // cause it to be modified for this operation. 2420 if (N->getOpcode() == ISD::SRA) { 2421 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2422 if (BinOpRHSSignSet != HighBitSet) 2423 return SDValue(); 2424 } 2425 2426 // Fold the constants, shifting the binop RHS by the shift amount. 2427 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2428 N->getValueType(0), 2429 LHS->getOperand(1), N->getOperand(1)); 2430 2431 // Create the new shift. 2432 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2433 VT, LHS->getOperand(0), N->getOperand(1)); 2434 2435 // Create the new binop. 2436 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2437} 2438 2439SDValue DAGCombiner::visitSHL(SDNode *N) { 2440 SDValue N0 = N->getOperand(0); 2441 SDValue N1 = N->getOperand(1); 2442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2444 EVT VT = N0.getValueType(); 2445 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2446 2447 // fold (shl c1, c2) -> c1<<c2 2448 if (N0C && N1C) 2449 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2450 // fold (shl 0, x) -> 0 2451 if (N0C && N0C->isNullValue()) 2452 return N0; 2453 // fold (shl x, c >= size(x)) -> undef 2454 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2455 return DAG.getUNDEF(VT); 2456 // fold (shl x, 0) -> x 2457 if (N1C && N1C->isNullValue()) 2458 return N0; 2459 // if (shl x, c) is known to be zero, return 0 2460 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2461 APInt::getAllOnesValue(OpSizeInBits))) 2462 return DAG.getConstant(0, VT); 2463 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2464 if (N1.getOpcode() == ISD::TRUNCATE && 2465 N1.getOperand(0).getOpcode() == ISD::AND && 2466 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2467 SDValue N101 = N1.getOperand(0).getOperand(1); 2468 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2469 EVT TruncVT = N1.getValueType(); 2470 SDValue N100 = N1.getOperand(0).getOperand(0); 2471 APInt TruncC = N101C->getAPIntValue(); 2472 TruncC.trunc(TruncVT.getSizeInBits()); 2473 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2474 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2475 DAG.getNode(ISD::TRUNCATE, 2476 N->getDebugLoc(), 2477 TruncVT, N100), 2478 DAG.getConstant(TruncC, TruncVT))); 2479 } 2480 } 2481 2482 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2483 return SDValue(N, 0); 2484 2485 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2486 if (N1C && N0.getOpcode() == ISD::SHL && 2487 N0.getOperand(1).getOpcode() == ISD::Constant) { 2488 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2489 uint64_t c2 = N1C->getZExtValue(); 2490 if (c1 + c2 > OpSizeInBits) 2491 return DAG.getConstant(0, VT); 2492 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2493 DAG.getConstant(c1 + c2, N1.getValueType())); 2494 } 2495 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2496 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2497 if (N1C && N0.getOpcode() == ISD::SRL && 2498 N0.getOperand(1).getOpcode() == ISD::Constant) { 2499 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2500 if (c1 < VT.getSizeInBits()) { 2501 uint64_t c2 = N1C->getZExtValue(); 2502 SDValue HiBitsMask = 2503 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2504 VT.getSizeInBits() - c1), 2505 VT); 2506 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2507 N0.getOperand(0), 2508 HiBitsMask); 2509 if (c2 > c1) 2510 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2511 DAG.getConstant(c2-c1, N1.getValueType())); 2512 else 2513 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2514 DAG.getConstant(c1-c2, N1.getValueType())); 2515 } 2516 } 2517 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2518 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2519 SDValue HiBitsMask = 2520 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2521 VT.getSizeInBits() - 2522 N1C->getZExtValue()), 2523 VT); 2524 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2525 HiBitsMask); 2526 } 2527 2528 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2529} 2530 2531SDValue DAGCombiner::visitSRA(SDNode *N) { 2532 SDValue N0 = N->getOperand(0); 2533 SDValue N1 = N->getOperand(1); 2534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2536 EVT VT = N0.getValueType(); 2537 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2538 2539 // fold (sra c1, c2) -> (sra c1, c2) 2540 if (N0C && N1C) 2541 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2542 // fold (sra 0, x) -> 0 2543 if (N0C && N0C->isNullValue()) 2544 return N0; 2545 // fold (sra -1, x) -> -1 2546 if (N0C && N0C->isAllOnesValue()) 2547 return N0; 2548 // fold (sra x, (setge c, size(x))) -> undef 2549 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2550 return DAG.getUNDEF(VT); 2551 // fold (sra x, 0) -> x 2552 if (N1C && N1C->isNullValue()) 2553 return N0; 2554 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2555 // sext_inreg. 2556 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2557 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2558 EVT EVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2559 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2560 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2561 N0.getOperand(0), DAG.getValueType(EVT)); 2562 } 2563 2564 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2565 if (N1C && N0.getOpcode() == ISD::SRA) { 2566 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2567 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2568 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2569 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2570 DAG.getConstant(Sum, N1C->getValueType(0))); 2571 } 2572 } 2573 2574 // fold (sra (shl X, m), (sub result_size, n)) 2575 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2576 // result_size - n != m. 2577 // If truncate is free for the target sext(shl) is likely to result in better 2578 // code. 2579 if (N0.getOpcode() == ISD::SHL) { 2580 // Get the two constanst of the shifts, CN0 = m, CN = n. 2581 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2582 if (N01C && N1C) { 2583 // Determine what the truncate's result bitsize and type would be. 2584 EVT TruncVT = 2585 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2586 // Determine the residual right-shift amount. 2587 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2588 2589 // If the shift is not a no-op (in which case this should be just a sign 2590 // extend already), the truncated to type is legal, sign_extend is legal 2591 // on that type, and the the truncate to that type is both legal and free, 2592 // perform the transform. 2593 if ((ShiftAmt > 0) && 2594 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2595 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2596 TLI.isTruncateFree(VT, TruncVT)) { 2597 2598 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2599 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2600 N0.getOperand(0), Amt); 2601 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2602 Shift); 2603 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2604 N->getValueType(0), Trunc); 2605 } 2606 } 2607 } 2608 2609 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2610 if (N1.getOpcode() == ISD::TRUNCATE && 2611 N1.getOperand(0).getOpcode() == ISD::AND && 2612 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2613 SDValue N101 = N1.getOperand(0).getOperand(1); 2614 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2615 EVT TruncVT = N1.getValueType(); 2616 SDValue N100 = N1.getOperand(0).getOperand(0); 2617 APInt TruncC = N101C->getAPIntValue(); 2618 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2619 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2620 DAG.getNode(ISD::AND, N->getDebugLoc(), 2621 TruncVT, 2622 DAG.getNode(ISD::TRUNCATE, 2623 N->getDebugLoc(), 2624 TruncVT, N100), 2625 DAG.getConstant(TruncC, TruncVT))); 2626 } 2627 } 2628 2629 // Simplify, based on bits shifted out of the LHS. 2630 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2631 return SDValue(N, 0); 2632 2633 2634 // If the sign bit is known to be zero, switch this to a SRL. 2635 if (DAG.SignBitIsZero(N0)) 2636 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2637 2638 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2639} 2640 2641SDValue DAGCombiner::visitSRL(SDNode *N) { 2642 SDValue N0 = N->getOperand(0); 2643 SDValue N1 = N->getOperand(1); 2644 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2645 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2646 EVT VT = N0.getValueType(); 2647 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2648 2649 // fold (srl c1, c2) -> c1 >>u c2 2650 if (N0C && N1C) 2651 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2652 // fold (srl 0, x) -> 0 2653 if (N0C && N0C->isNullValue()) 2654 return N0; 2655 // fold (srl x, c >= size(x)) -> undef 2656 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2657 return DAG.getUNDEF(VT); 2658 // fold (srl x, 0) -> x 2659 if (N1C && N1C->isNullValue()) 2660 return N0; 2661 // if (srl x, c) is known to be zero, return 0 2662 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2663 APInt::getAllOnesValue(OpSizeInBits))) 2664 return DAG.getConstant(0, VT); 2665 2666 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2667 if (N1C && N0.getOpcode() == ISD::SRL && 2668 N0.getOperand(1).getOpcode() == ISD::Constant) { 2669 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2670 uint64_t c2 = N1C->getZExtValue(); 2671 if (c1 + c2 > OpSizeInBits) 2672 return DAG.getConstant(0, VT); 2673 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2674 DAG.getConstant(c1 + c2, N1.getValueType())); 2675 } 2676 2677 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2678 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2679 // Shifting in all undef bits? 2680 EVT SmallVT = N0.getOperand(0).getValueType(); 2681 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2682 return DAG.getUNDEF(VT); 2683 2684 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2685 N0.getOperand(0), N1); 2686 AddToWorkList(SmallShift.getNode()); 2687 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2688 } 2689 2690 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2691 // bit, which is unmodified by sra. 2692 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2693 if (N0.getOpcode() == ISD::SRA) 2694 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2695 } 2696 2697 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2698 if (N1C && N0.getOpcode() == ISD::CTLZ && 2699 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2700 APInt KnownZero, KnownOne; 2701 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2702 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2703 2704 // If any of the input bits are KnownOne, then the input couldn't be all 2705 // zeros, thus the result of the srl will always be zero. 2706 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2707 2708 // If all of the bits input the to ctlz node are known to be zero, then 2709 // the result of the ctlz is "32" and the result of the shift is one. 2710 APInt UnknownBits = ~KnownZero & Mask; 2711 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2712 2713 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2714 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2715 // Okay, we know that only that the single bit specified by UnknownBits 2716 // could be set on input to the CTLZ node. If this bit is set, the SRL 2717 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2718 // to an SRL/XOR pair, which is likely to simplify more. 2719 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2720 SDValue Op = N0.getOperand(0); 2721 2722 if (ShAmt) { 2723 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2724 DAG.getConstant(ShAmt, getShiftAmountTy())); 2725 AddToWorkList(Op.getNode()); 2726 } 2727 2728 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2729 Op, DAG.getConstant(1, VT)); 2730 } 2731 } 2732 2733 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2734 if (N1.getOpcode() == ISD::TRUNCATE && 2735 N1.getOperand(0).getOpcode() == ISD::AND && 2736 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2737 SDValue N101 = N1.getOperand(0).getOperand(1); 2738 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2739 EVT TruncVT = N1.getValueType(); 2740 SDValue N100 = N1.getOperand(0).getOperand(0); 2741 APInt TruncC = N101C->getAPIntValue(); 2742 TruncC.trunc(TruncVT.getSizeInBits()); 2743 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2744 DAG.getNode(ISD::AND, N->getDebugLoc(), 2745 TruncVT, 2746 DAG.getNode(ISD::TRUNCATE, 2747 N->getDebugLoc(), 2748 TruncVT, N100), 2749 DAG.getConstant(TruncC, TruncVT))); 2750 } 2751 } 2752 2753 // fold operands of srl based on knowledge that the low bits are not 2754 // demanded. 2755 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2756 return SDValue(N, 0); 2757 2758 if (N1C) { 2759 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2760 if (NewSRL.getNode()) 2761 return NewSRL; 2762 } 2763 2764 // Here is a common situation. We want to optimize: 2765 // 2766 // %a = ... 2767 // %b = and i32 %a, 2 2768 // %c = srl i32 %b, 1 2769 // brcond i32 %c ... 2770 // 2771 // into 2772 // 2773 // %a = ... 2774 // %b = and %a, 2 2775 // %c = setcc eq %b, 0 2776 // brcond %c ... 2777 // 2778 // However when after the source operand of SRL is optimized into AND, the SRL 2779 // itself may not be optimized further. Look for it and add the BRCOND into 2780 // the worklist. 2781 if (N->hasOneUse() && 2782 N->use_begin()->getOpcode() == ISD::BRCOND) 2783 AddToWorkList(*N->use_begin()); 2784 2785 return SDValue(); 2786} 2787 2788SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2789 SDValue N0 = N->getOperand(0); 2790 EVT VT = N->getValueType(0); 2791 2792 // fold (ctlz c1) -> c2 2793 if (isa<ConstantSDNode>(N0)) 2794 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2795 return SDValue(); 2796} 2797 2798SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2799 SDValue N0 = N->getOperand(0); 2800 EVT VT = N->getValueType(0); 2801 2802 // fold (cttz c1) -> c2 2803 if (isa<ConstantSDNode>(N0)) 2804 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2805 return SDValue(); 2806} 2807 2808SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2809 SDValue N0 = N->getOperand(0); 2810 EVT VT = N->getValueType(0); 2811 2812 // fold (ctpop c1) -> c2 2813 if (isa<ConstantSDNode>(N0)) 2814 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2815 return SDValue(); 2816} 2817 2818SDValue DAGCombiner::visitSELECT(SDNode *N) { 2819 SDValue N0 = N->getOperand(0); 2820 SDValue N1 = N->getOperand(1); 2821 SDValue N2 = N->getOperand(2); 2822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2824 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2825 EVT VT = N->getValueType(0); 2826 EVT VT0 = N0.getValueType(); 2827 2828 // fold (select C, X, X) -> X 2829 if (N1 == N2) 2830 return N1; 2831 // fold (select true, X, Y) -> X 2832 if (N0C && !N0C->isNullValue()) 2833 return N1; 2834 // fold (select false, X, Y) -> Y 2835 if (N0C && N0C->isNullValue()) 2836 return N2; 2837 // fold (select C, 1, X) -> (or C, X) 2838 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2839 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2840 // fold (select C, 0, 1) -> (xor C, 1) 2841 if (VT.isInteger() && 2842 (VT0 == MVT::i1 || 2843 (VT0.isInteger() && 2844 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2845 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2846 SDValue XORNode; 2847 if (VT == VT0) 2848 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2849 N0, DAG.getConstant(1, VT0)); 2850 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2851 N0, DAG.getConstant(1, VT0)); 2852 AddToWorkList(XORNode.getNode()); 2853 if (VT.bitsGT(VT0)) 2854 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2855 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2856 } 2857 // fold (select C, 0, X) -> (and (not C), X) 2858 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2859 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2860 AddToWorkList(NOTNode.getNode()); 2861 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2862 } 2863 // fold (select C, X, 1) -> (or (not C), X) 2864 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2865 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2866 AddToWorkList(NOTNode.getNode()); 2867 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2868 } 2869 // fold (select C, X, 0) -> (and C, X) 2870 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2871 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2872 // fold (select X, X, Y) -> (or X, Y) 2873 // fold (select X, 1, Y) -> (or X, Y) 2874 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2875 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2876 // fold (select X, Y, X) -> (and X, Y) 2877 // fold (select X, Y, 0) -> (and X, Y) 2878 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2879 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2880 2881 // If we can fold this based on the true/false value, do so. 2882 if (SimplifySelectOps(N, N1, N2)) 2883 return SDValue(N, 0); // Don't revisit N. 2884 2885 // fold selects based on a setcc into other things, such as min/max/abs 2886 if (N0.getOpcode() == ISD::SETCC) { 2887 // FIXME: 2888 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2889 // having to say they don't support SELECT_CC on every type the DAG knows 2890 // about, since there is no way to mark an opcode illegal at all value types 2891 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2892 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2893 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2894 N0.getOperand(0), N0.getOperand(1), 2895 N1, N2, N0.getOperand(2)); 2896 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2897 } 2898 2899 return SDValue(); 2900} 2901 2902SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2903 SDValue N0 = N->getOperand(0); 2904 SDValue N1 = N->getOperand(1); 2905 SDValue N2 = N->getOperand(2); 2906 SDValue N3 = N->getOperand(3); 2907 SDValue N4 = N->getOperand(4); 2908 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2909 2910 // fold select_cc lhs, rhs, x, x, cc -> x 2911 if (N2 == N3) 2912 return N2; 2913 2914 // Determine if the condition we're dealing with is constant 2915 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2916 N0, N1, CC, N->getDebugLoc(), false); 2917 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2918 2919 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2920 if (!SCCC->isNullValue()) 2921 return N2; // cond always true -> true val 2922 else 2923 return N3; // cond always false -> false val 2924 } 2925 2926 // Fold to a simpler select_cc 2927 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2928 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2929 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2930 SCC.getOperand(2)); 2931 2932 // If we can fold this based on the true/false value, do so. 2933 if (SimplifySelectOps(N, N2, N3)) 2934 return SDValue(N, 0); // Don't revisit N. 2935 2936 // fold select_cc into other things, such as min/max/abs 2937 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2938} 2939 2940SDValue DAGCombiner::visitSETCC(SDNode *N) { 2941 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2942 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2943 N->getDebugLoc()); 2944} 2945 2946// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2947// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2948// transformation. Returns true if extension are possible and the above 2949// mentioned transformation is profitable. 2950static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2951 unsigned ExtOpc, 2952 SmallVector<SDNode*, 4> &ExtendNodes, 2953 const TargetLowering &TLI) { 2954 bool HasCopyToRegUses = false; 2955 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2956 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2957 UE = N0.getNode()->use_end(); 2958 UI != UE; ++UI) { 2959 SDNode *User = *UI; 2960 if (User == N) 2961 continue; 2962 if (UI.getUse().getResNo() != N0.getResNo()) 2963 continue; 2964 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2965 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2966 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2967 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2968 // Sign bits will be lost after a zext. 2969 return false; 2970 bool Add = false; 2971 for (unsigned i = 0; i != 2; ++i) { 2972 SDValue UseOp = User->getOperand(i); 2973 if (UseOp == N0) 2974 continue; 2975 if (!isa<ConstantSDNode>(UseOp)) 2976 return false; 2977 Add = true; 2978 } 2979 if (Add) 2980 ExtendNodes.push_back(User); 2981 continue; 2982 } 2983 // If truncates aren't free and there are users we can't 2984 // extend, it isn't worthwhile. 2985 if (!isTruncFree) 2986 return false; 2987 // Remember if this value is live-out. 2988 if (User->getOpcode() == ISD::CopyToReg) 2989 HasCopyToRegUses = true; 2990 } 2991 2992 if (HasCopyToRegUses) { 2993 bool BothLiveOut = false; 2994 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2995 UI != UE; ++UI) { 2996 SDUse &Use = UI.getUse(); 2997 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2998 BothLiveOut = true; 2999 break; 3000 } 3001 } 3002 if (BothLiveOut) 3003 // Both unextended and extended values are live out. There had better be 3004 // good a reason for the transformation. 3005 return ExtendNodes.size(); 3006 } 3007 return true; 3008} 3009 3010SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3011 SDValue N0 = N->getOperand(0); 3012 EVT VT = N->getValueType(0); 3013 3014 // fold (sext c1) -> c1 3015 if (isa<ConstantSDNode>(N0)) 3016 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3017 3018 // fold (sext (sext x)) -> (sext x) 3019 // fold (sext (aext x)) -> (sext x) 3020 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3021 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3022 N0.getOperand(0)); 3023 3024 if (N0.getOpcode() == ISD::TRUNCATE) { 3025 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3026 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3027 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3028 if (NarrowLoad.getNode()) { 3029 if (NarrowLoad.getNode() != N0.getNode()) 3030 CombineTo(N0.getNode(), NarrowLoad); 3031 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3032 } 3033 3034 // See if the value being truncated is already sign extended. If so, just 3035 // eliminate the trunc/sext pair. 3036 SDValue Op = N0.getOperand(0); 3037 unsigned OpBits = Op.getValueType().getSizeInBits(); 3038 unsigned MidBits = N0.getValueType().getSizeInBits(); 3039 unsigned DestBits = VT.getSizeInBits(); 3040 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3041 3042 if (OpBits == DestBits) { 3043 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3044 // bits, it is already ready. 3045 if (NumSignBits > DestBits-MidBits) 3046 return Op; 3047 } else if (OpBits < DestBits) { 3048 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3049 // bits, just sext from i32. 3050 if (NumSignBits > OpBits-MidBits) 3051 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3052 } else { 3053 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3054 // bits, just truncate to i32. 3055 if (NumSignBits > OpBits-MidBits) 3056 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3057 } 3058 3059 // fold (sext (truncate x)) -> (sextinreg x). 3060 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3061 N0.getValueType())) { 3062 if (Op.getValueType().bitsLT(VT)) 3063 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3064 else if (Op.getValueType().bitsGT(VT)) 3065 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3066 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3067 DAG.getValueType(N0.getValueType().getScalarType())); 3068 } 3069 } 3070 3071 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3072 if (ISD::isNON_EXTLoad(N0.getNode()) && 3073 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3074 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3075 bool DoXform = true; 3076 SmallVector<SDNode*, 4> SetCCs; 3077 if (!N0.hasOneUse()) 3078 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3079 if (DoXform) { 3080 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3081 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3082 LN0->getChain(), 3083 LN0->getBasePtr(), LN0->getSrcValue(), 3084 LN0->getSrcValueOffset(), 3085 N0.getValueType(), 3086 LN0->isVolatile(), LN0->getAlignment()); 3087 CombineTo(N, ExtLoad); 3088 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3089 N0.getValueType(), ExtLoad); 3090 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3091 3092 // Extend SetCC uses if necessary. 3093 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3094 SDNode *SetCC = SetCCs[i]; 3095 SmallVector<SDValue, 4> Ops; 3096 3097 for (unsigned j = 0; j != 2; ++j) { 3098 SDValue SOp = SetCC->getOperand(j); 3099 if (SOp == Trunc) 3100 Ops.push_back(ExtLoad); 3101 else 3102 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3103 N->getDebugLoc(), VT, SOp)); 3104 } 3105 3106 Ops.push_back(SetCC->getOperand(2)); 3107 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3108 SetCC->getValueType(0), 3109 &Ops[0], Ops.size())); 3110 } 3111 3112 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3113 } 3114 } 3115 3116 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3117 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3118 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3119 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3120 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3121 EVT MemVT = LN0->getMemoryVT(); 3122 if ((!LegalOperations && !LN0->isVolatile()) || 3123 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3124 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3125 LN0->getChain(), 3126 LN0->getBasePtr(), LN0->getSrcValue(), 3127 LN0->getSrcValueOffset(), MemVT, 3128 LN0->isVolatile(), LN0->getAlignment()); 3129 CombineTo(N, ExtLoad); 3130 CombineTo(N0.getNode(), 3131 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3132 N0.getValueType(), ExtLoad), 3133 ExtLoad.getValue(1)); 3134 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3135 } 3136 } 3137 3138 if (N0.getOpcode() == ISD::SETCC) { 3139 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3140 if (VT.isVector() && 3141 // We know that the # elements of the results is the same as the 3142 // # elements of the compare (and the # elements of the compare result 3143 // for that matter). Check to see that they are the same size. If so, 3144 // we know that the element size of the sext'd result matches the 3145 // element size of the compare operands. 3146 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3147 3148 // Only do this before legalize for now. 3149 !LegalOperations) { 3150 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3151 N0.getOperand(1), 3152 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3153 } 3154 3155 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3156 SDValue NegOne = 3157 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3158 SDValue SCC = 3159 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3160 NegOne, DAG.getConstant(0, VT), 3161 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3162 if (SCC.getNode()) return SCC; 3163 } 3164 3165 3166 3167 // fold (sext x) -> (zext x) if the sign bit is known zero. 3168 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3169 DAG.SignBitIsZero(N0)) 3170 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3171 3172 return SDValue(); 3173} 3174 3175SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3176 SDValue N0 = N->getOperand(0); 3177 EVT VT = N->getValueType(0); 3178 3179 // fold (zext c1) -> c1 3180 if (isa<ConstantSDNode>(N0)) 3181 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3182 // fold (zext (zext x)) -> (zext x) 3183 // fold (zext (aext x)) -> (zext x) 3184 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3185 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3186 N0.getOperand(0)); 3187 3188 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3189 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3190 if (N0.getOpcode() == ISD::TRUNCATE) { 3191 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3192 if (NarrowLoad.getNode()) { 3193 if (NarrowLoad.getNode() != N0.getNode()) 3194 CombineTo(N0.getNode(), NarrowLoad); 3195 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3196 } 3197 } 3198 3199 // fold (zext (truncate x)) -> (and x, mask) 3200 if (N0.getOpcode() == ISD::TRUNCATE && 3201 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3202 SDValue Op = N0.getOperand(0); 3203 if (Op.getValueType().bitsLT(VT)) { 3204 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3205 } else if (Op.getValueType().bitsGT(VT)) { 3206 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3207 } 3208 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3209 N0.getValueType().getScalarType()); 3210 } 3211 3212 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3213 // if either of the casts is not free. 3214 if (N0.getOpcode() == ISD::AND && 3215 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3216 N0.getOperand(1).getOpcode() == ISD::Constant && 3217 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3218 N0.getValueType()) || 3219 !TLI.isZExtFree(N0.getValueType(), VT))) { 3220 SDValue X = N0.getOperand(0).getOperand(0); 3221 if (X.getValueType().bitsLT(VT)) { 3222 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3223 } else if (X.getValueType().bitsGT(VT)) { 3224 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3225 } 3226 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3227 Mask.zext(VT.getSizeInBits()); 3228 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3229 X, DAG.getConstant(Mask, VT)); 3230 } 3231 3232 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3233 if (ISD::isNON_EXTLoad(N0.getNode()) && 3234 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3235 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3236 bool DoXform = true; 3237 SmallVector<SDNode*, 4> SetCCs; 3238 if (!N0.hasOneUse()) 3239 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3240 if (DoXform) { 3241 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3242 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3243 LN0->getChain(), 3244 LN0->getBasePtr(), LN0->getSrcValue(), 3245 LN0->getSrcValueOffset(), 3246 N0.getValueType(), 3247 LN0->isVolatile(), LN0->getAlignment()); 3248 CombineTo(N, ExtLoad); 3249 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3250 N0.getValueType(), ExtLoad); 3251 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3252 3253 // Extend SetCC uses if necessary. 3254 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3255 SDNode *SetCC = SetCCs[i]; 3256 SmallVector<SDValue, 4> Ops; 3257 3258 for (unsigned j = 0; j != 2; ++j) { 3259 SDValue SOp = SetCC->getOperand(j); 3260 if (SOp == Trunc) 3261 Ops.push_back(ExtLoad); 3262 else 3263 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3264 N->getDebugLoc(), VT, SOp)); 3265 } 3266 3267 Ops.push_back(SetCC->getOperand(2)); 3268 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3269 SetCC->getValueType(0), 3270 &Ops[0], Ops.size())); 3271 } 3272 3273 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3274 } 3275 } 3276 3277 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3278 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3279 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3280 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3281 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3282 EVT MemVT = LN0->getMemoryVT(); 3283 if ((!LegalOperations && !LN0->isVolatile()) || 3284 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3285 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3286 LN0->getChain(), 3287 LN0->getBasePtr(), LN0->getSrcValue(), 3288 LN0->getSrcValueOffset(), MemVT, 3289 LN0->isVolatile(), LN0->getAlignment()); 3290 CombineTo(N, ExtLoad); 3291 CombineTo(N0.getNode(), 3292 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3293 ExtLoad), 3294 ExtLoad.getValue(1)); 3295 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3296 } 3297 } 3298 3299 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3300 if (N0.getOpcode() == ISD::SETCC) { 3301 SDValue SCC = 3302 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3303 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3304 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3305 if (SCC.getNode()) return SCC; 3306 } 3307 3308 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3309 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3310 isa<ConstantSDNode>(N0.getOperand(1)) && 3311 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3312 N0.hasOneUse()) { 3313 if (N0.getOpcode() == ISD::SHL) { 3314 // If the original shl may be shifting out bits, do not perform this 3315 // transformation. 3316 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3317 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3318 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3319 if (ShAmt > KnownZeroBits) 3320 return SDValue(); 3321 } 3322 DebugLoc dl = N->getDebugLoc(); 3323 return DAG.getNode(N0.getOpcode(), dl, VT, 3324 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3325 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1))); 3326 } 3327 3328 return SDValue(); 3329} 3330 3331SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3332 SDValue N0 = N->getOperand(0); 3333 EVT VT = N->getValueType(0); 3334 3335 // fold (aext c1) -> c1 3336 if (isa<ConstantSDNode>(N0)) 3337 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3338 // fold (aext (aext x)) -> (aext x) 3339 // fold (aext (zext x)) -> (zext x) 3340 // fold (aext (sext x)) -> (sext x) 3341 if (N0.getOpcode() == ISD::ANY_EXTEND || 3342 N0.getOpcode() == ISD::ZERO_EXTEND || 3343 N0.getOpcode() == ISD::SIGN_EXTEND) 3344 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3345 3346 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3347 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3348 if (N0.getOpcode() == ISD::TRUNCATE) { 3349 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3350 if (NarrowLoad.getNode()) { 3351 if (NarrowLoad.getNode() != N0.getNode()) 3352 CombineTo(N0.getNode(), NarrowLoad); 3353 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3354 } 3355 } 3356 3357 // fold (aext (truncate x)) 3358 if (N0.getOpcode() == ISD::TRUNCATE) { 3359 SDValue TruncOp = N0.getOperand(0); 3360 if (TruncOp.getValueType() == VT) 3361 return TruncOp; // x iff x size == zext size. 3362 if (TruncOp.getValueType().bitsGT(VT)) 3363 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3364 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3365 } 3366 3367 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3368 // if the trunc is not free. 3369 if (N0.getOpcode() == ISD::AND && 3370 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3371 N0.getOperand(1).getOpcode() == ISD::Constant && 3372 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3373 N0.getValueType())) { 3374 SDValue X = N0.getOperand(0).getOperand(0); 3375 if (X.getValueType().bitsLT(VT)) { 3376 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3377 } else if (X.getValueType().bitsGT(VT)) { 3378 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3379 } 3380 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3381 Mask.zext(VT.getSizeInBits()); 3382 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3383 X, DAG.getConstant(Mask, VT)); 3384 } 3385 3386 // fold (aext (load x)) -> (aext (truncate (extload x))) 3387 if (ISD::isNON_EXTLoad(N0.getNode()) && 3388 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3389 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3390 bool DoXform = true; 3391 SmallVector<SDNode*, 4> SetCCs; 3392 if (!N0.hasOneUse()) 3393 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3394 if (DoXform) { 3395 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3396 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3397 LN0->getChain(), 3398 LN0->getBasePtr(), LN0->getSrcValue(), 3399 LN0->getSrcValueOffset(), 3400 N0.getValueType(), 3401 LN0->isVolatile(), LN0->getAlignment()); 3402 CombineTo(N, ExtLoad); 3403 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3404 N0.getValueType(), ExtLoad); 3405 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3406 3407 // Extend SetCC uses if necessary. 3408 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3409 SDNode *SetCC = SetCCs[i]; 3410 SmallVector<SDValue, 4> Ops; 3411 3412 for (unsigned j = 0; j != 2; ++j) { 3413 SDValue SOp = SetCC->getOperand(j); 3414 if (SOp == Trunc) 3415 Ops.push_back(ExtLoad); 3416 else 3417 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3418 N->getDebugLoc(), VT, SOp)); 3419 } 3420 3421 Ops.push_back(SetCC->getOperand(2)); 3422 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3423 SetCC->getValueType(0), 3424 &Ops[0], Ops.size())); 3425 } 3426 3427 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3428 } 3429 } 3430 3431 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3432 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3433 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3434 if (N0.getOpcode() == ISD::LOAD && 3435 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3436 N0.hasOneUse()) { 3437 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3438 EVT MemVT = LN0->getMemoryVT(); 3439 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3440 VT, LN0->getChain(), LN0->getBasePtr(), 3441 LN0->getSrcValue(), 3442 LN0->getSrcValueOffset(), MemVT, 3443 LN0->isVolatile(), LN0->getAlignment()); 3444 CombineTo(N, ExtLoad); 3445 CombineTo(N0.getNode(), 3446 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3447 N0.getValueType(), ExtLoad), 3448 ExtLoad.getValue(1)); 3449 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3450 } 3451 3452 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3453 if (N0.getOpcode() == ISD::SETCC) { 3454 SDValue SCC = 3455 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3456 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3457 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3458 if (SCC.getNode()) 3459 return SCC; 3460 } 3461 3462 return SDValue(); 3463} 3464 3465/// GetDemandedBits - See if the specified operand can be simplified with the 3466/// knowledge that only the bits specified by Mask are used. If so, return the 3467/// simpler operand, otherwise return a null SDValue. 3468SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3469 switch (V.getOpcode()) { 3470 default: break; 3471 case ISD::OR: 3472 case ISD::XOR: 3473 // If the LHS or RHS don't contribute bits to the or, drop them. 3474 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3475 return V.getOperand(1); 3476 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3477 return V.getOperand(0); 3478 break; 3479 case ISD::SRL: 3480 // Only look at single-use SRLs. 3481 if (!V.getNode()->hasOneUse()) 3482 break; 3483 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3484 // See if we can recursively simplify the LHS. 3485 unsigned Amt = RHSC->getZExtValue(); 3486 3487 // Watch out for shift count overflow though. 3488 if (Amt >= Mask.getBitWidth()) break; 3489 APInt NewMask = Mask << Amt; 3490 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3491 if (SimplifyLHS.getNode()) 3492 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3493 SimplifyLHS, V.getOperand(1)); 3494 } 3495 } 3496 return SDValue(); 3497} 3498 3499/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3500/// bits and then truncated to a narrower type and where N is a multiple 3501/// of number of bits of the narrower type, transform it to a narrower load 3502/// from address + N / num of bits of new type. If the result is to be 3503/// extended, also fold the extension to form a extending load. 3504SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3505 unsigned Opc = N->getOpcode(); 3506 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3507 SDValue N0 = N->getOperand(0); 3508 EVT VT = N->getValueType(0); 3509 EVT ExtVT = VT; 3510 3511 // This transformation isn't valid for vector loads. 3512 if (VT.isVector()) 3513 return SDValue(); 3514 3515 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3516 // extended to VT. 3517 if (Opc == ISD::SIGN_EXTEND_INREG) { 3518 ExtType = ISD::SEXTLOAD; 3519 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3520 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3521 return SDValue(); 3522 } 3523 3524 unsigned EVTBits = ExtVT.getSizeInBits(); 3525 unsigned ShAmt = 0; 3526 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3527 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3528 ShAmt = N01->getZExtValue(); 3529 // Is the shift amount a multiple of size of VT? 3530 if ((ShAmt & (EVTBits-1)) == 0) { 3531 N0 = N0.getOperand(0); 3532 // Is the load width a multiple of size of VT? 3533 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3534 return SDValue(); 3535 } 3536 } 3537 } 3538 3539 // Do not generate loads of non-round integer types since these can 3540 // be expensive (and would be wrong if the type is not byte sized). 3541 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3542 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3543 // Do not change the width of a volatile load. 3544 !cast<LoadSDNode>(N0)->isVolatile()) { 3545 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3546 EVT PtrType = N0.getOperand(1).getValueType(); 3547 3548 // For big endian targets, we need to adjust the offset to the pointer to 3549 // load the correct bytes. 3550 if (TLI.isBigEndian()) { 3551 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3552 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3553 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3554 } 3555 3556 uint64_t PtrOff = ShAmt / 8; 3557 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3558 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3559 PtrType, LN0->getBasePtr(), 3560 DAG.getConstant(PtrOff, PtrType)); 3561 AddToWorkList(NewPtr.getNode()); 3562 3563 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3564 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3565 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3566 LN0->isVolatile(), NewAlign) 3567 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3568 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3569 ExtVT, LN0->isVolatile(), NewAlign); 3570 3571 // Replace the old load's chain with the new load's chain. 3572 WorkListRemover DeadNodes(*this); 3573 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3574 &DeadNodes); 3575 3576 // Return the new loaded value. 3577 return Load; 3578 } 3579 3580 return SDValue(); 3581} 3582 3583SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3584 SDValue N0 = N->getOperand(0); 3585 SDValue N1 = N->getOperand(1); 3586 EVT VT = N->getValueType(0); 3587 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3588 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3589 unsigned EVTBits = EVT.getSizeInBits(); 3590 3591 // fold (sext_in_reg c1) -> c1 3592 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3593 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3594 3595 // If the input is already sign extended, just drop the extension. 3596 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3597 return N0; 3598 3599 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3600 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3601 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3602 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3603 N0.getOperand(0), N1); 3604 } 3605 3606 // fold (sext_in_reg (sext x)) -> (sext x) 3607 // fold (sext_in_reg (aext x)) -> (sext x) 3608 // if x is small enough. 3609 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3610 SDValue N00 = N0.getOperand(0); 3611 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3612 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3613 } 3614 3615 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3616 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3617 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3618 3619 // fold operands of sext_in_reg based on knowledge that the top bits are not 3620 // demanded. 3621 if (SimplifyDemandedBits(SDValue(N, 0))) 3622 return SDValue(N, 0); 3623 3624 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3625 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3626 SDValue NarrowLoad = ReduceLoadWidth(N); 3627 if (NarrowLoad.getNode()) 3628 return NarrowLoad; 3629 3630 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3631 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3632 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3633 if (N0.getOpcode() == ISD::SRL) { 3634 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3635 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3636 // We can turn this into an SRA iff the input to the SRL is already sign 3637 // extended enough. 3638 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3639 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3640 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3641 N0.getOperand(0), N0.getOperand(1)); 3642 } 3643 } 3644 3645 // fold (sext_inreg (extload x)) -> (sextload x) 3646 if (ISD::isEXTLoad(N0.getNode()) && 3647 ISD::isUNINDEXEDLoad(N0.getNode()) && 3648 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3649 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3650 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3651 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3652 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3653 LN0->getChain(), 3654 LN0->getBasePtr(), LN0->getSrcValue(), 3655 LN0->getSrcValueOffset(), EVT, 3656 LN0->isVolatile(), LN0->getAlignment()); 3657 CombineTo(N, ExtLoad); 3658 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3659 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3660 } 3661 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3662 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3663 N0.hasOneUse() && 3664 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3665 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3666 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3667 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3668 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3669 LN0->getChain(), 3670 LN0->getBasePtr(), LN0->getSrcValue(), 3671 LN0->getSrcValueOffset(), EVT, 3672 LN0->isVolatile(), LN0->getAlignment()); 3673 CombineTo(N, ExtLoad); 3674 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3675 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3676 } 3677 return SDValue(); 3678} 3679 3680SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3681 SDValue N0 = N->getOperand(0); 3682 EVT VT = N->getValueType(0); 3683 3684 // noop truncate 3685 if (N0.getValueType() == N->getValueType(0)) 3686 return N0; 3687 // fold (truncate c1) -> c1 3688 if (isa<ConstantSDNode>(N0)) 3689 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3690 // fold (truncate (truncate x)) -> (truncate x) 3691 if (N0.getOpcode() == ISD::TRUNCATE) 3692 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3693 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3694 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3695 N0.getOpcode() == ISD::ANY_EXTEND) { 3696 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3697 // if the source is smaller than the dest, we still need an extend 3698 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3699 N0.getOperand(0)); 3700 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3701 // if the source is larger than the dest, than we just need the truncate 3702 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3703 else 3704 // if the source and dest are the same type, we can drop both the extend 3705 // and the truncate 3706 return N0.getOperand(0); 3707 } 3708 3709 // See if we can simplify the input to this truncate through knowledge that 3710 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3711 // -> trunc y 3712 SDValue Shorter = 3713 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3714 VT.getSizeInBits())); 3715 if (Shorter.getNode()) 3716 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3717 3718 // fold (truncate (load x)) -> (smaller load x) 3719 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3720 return ReduceLoadWidth(N); 3721} 3722 3723static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3724 SDValue Elt = N->getOperand(i); 3725 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3726 return Elt.getNode(); 3727 return Elt.getOperand(Elt.getResNo()).getNode(); 3728} 3729 3730/// CombineConsecutiveLoads - build_pair (load, load) -> load 3731/// if load locations are consecutive. 3732SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3733 assert(N->getOpcode() == ISD::BUILD_PAIR); 3734 3735 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3736 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3737 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3738 return SDValue(); 3739 EVT LD1VT = LD1->getValueType(0); 3740 3741 if (ISD::isNON_EXTLoad(LD2) && 3742 LD2->hasOneUse() && 3743 // If both are volatile this would reduce the number of volatile loads. 3744 // If one is volatile it might be ok, but play conservative and bail out. 3745 !LD1->isVolatile() && 3746 !LD2->isVolatile() && 3747 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3748 unsigned Align = LD1->getAlignment(); 3749 unsigned NewAlign = TLI.getTargetData()-> 3750 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3751 3752 if (NewAlign <= Align && 3753 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3754 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3755 LD1->getBasePtr(), LD1->getSrcValue(), 3756 LD1->getSrcValueOffset(), false, Align); 3757 } 3758 3759 return SDValue(); 3760} 3761 3762SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3763 SDValue N0 = N->getOperand(0); 3764 EVT VT = N->getValueType(0); 3765 3766 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3767 // Only do this before legalize, since afterward the target may be depending 3768 // on the bitconvert. 3769 // First check to see if this is all constant. 3770 if (!LegalTypes && 3771 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3772 VT.isVector()) { 3773 bool isSimple = true; 3774 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3775 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3776 N0.getOperand(i).getOpcode() != ISD::Constant && 3777 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3778 isSimple = false; 3779 break; 3780 } 3781 3782 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3783 assert(!DestEltVT.isVector() && 3784 "Element type of vector ValueType must not be vector!"); 3785 if (isSimple) 3786 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3787 } 3788 3789 // If the input is a constant, let getNode fold it. 3790 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3791 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3792 if (Res.getNode() != N) { 3793 if (!LegalOperations || 3794 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3795 return Res; 3796 3797 // Folding it resulted in an illegal node, and it's too late to 3798 // do that. Clean up the old node and forego the transformation. 3799 // Ideally this won't happen very often, because instcombine 3800 // and the earlier dagcombine runs (where illegal nodes are 3801 // permitted) should have folded most of them already. 3802 DAG.DeleteNode(Res.getNode()); 3803 } 3804 } 3805 3806 // (conv (conv x, t1), t2) -> (conv x, t2) 3807 if (N0.getOpcode() == ISD::BIT_CONVERT) 3808 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3809 N0.getOperand(0)); 3810 3811 // fold (conv (load x)) -> (load (conv*)x) 3812 // If the resultant load doesn't need a higher alignment than the original! 3813 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3814 // Do not change the width of a volatile load. 3815 !cast<LoadSDNode>(N0)->isVolatile() && 3816 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3817 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3818 unsigned Align = TLI.getTargetData()-> 3819 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3820 unsigned OrigAlign = LN0->getAlignment(); 3821 3822 if (Align <= OrigAlign) { 3823 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3824 LN0->getBasePtr(), 3825 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3826 LN0->isVolatile(), OrigAlign); 3827 AddToWorkList(N); 3828 CombineTo(N0.getNode(), 3829 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3830 N0.getValueType(), Load), 3831 Load.getValue(1)); 3832 return Load; 3833 } 3834 } 3835 3836 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3837 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3838 // This often reduces constant pool loads. 3839 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3840 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3841 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3842 N0.getOperand(0)); 3843 AddToWorkList(NewConv.getNode()); 3844 3845 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3846 if (N0.getOpcode() == ISD::FNEG) 3847 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3848 NewConv, DAG.getConstant(SignBit, VT)); 3849 assert(N0.getOpcode() == ISD::FABS); 3850 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3851 NewConv, DAG.getConstant(~SignBit, VT)); 3852 } 3853 3854 // fold (bitconvert (fcopysign cst, x)) -> 3855 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3856 // Note that we don't handle (copysign x, cst) because this can always be 3857 // folded to an fneg or fabs. 3858 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3859 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3860 VT.isInteger() && !VT.isVector()) { 3861 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3862 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3863 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3864 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3865 IntXVT, N0.getOperand(1)); 3866 AddToWorkList(X.getNode()); 3867 3868 // If X has a different width than the result/lhs, sext it or truncate it. 3869 unsigned VTWidth = VT.getSizeInBits(); 3870 if (OrigXWidth < VTWidth) { 3871 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3872 AddToWorkList(X.getNode()); 3873 } else if (OrigXWidth > VTWidth) { 3874 // To get the sign bit in the right place, we have to shift it right 3875 // before truncating. 3876 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3877 X.getValueType(), X, 3878 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3879 AddToWorkList(X.getNode()); 3880 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3881 AddToWorkList(X.getNode()); 3882 } 3883 3884 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3885 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3886 X, DAG.getConstant(SignBit, VT)); 3887 AddToWorkList(X.getNode()); 3888 3889 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3890 VT, N0.getOperand(0)); 3891 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3892 Cst, DAG.getConstant(~SignBit, VT)); 3893 AddToWorkList(Cst.getNode()); 3894 3895 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3896 } 3897 } 3898 3899 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3900 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3901 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3902 if (CombineLD.getNode()) 3903 return CombineLD; 3904 } 3905 3906 return SDValue(); 3907} 3908 3909SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3910 EVT VT = N->getValueType(0); 3911 return CombineConsecutiveLoads(N, VT); 3912} 3913 3914/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3915/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3916/// destination element value type. 3917SDValue DAGCombiner:: 3918ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 3919 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3920 3921 // If this is already the right type, we're done. 3922 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3923 3924 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3925 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3926 3927 // If this is a conversion of N elements of one type to N elements of another 3928 // type, convert each element. This handles FP<->INT cases. 3929 if (SrcBitSize == DstBitSize) { 3930 SmallVector<SDValue, 8> Ops; 3931 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3932 SDValue Op = BV->getOperand(i); 3933 // If the vector element type is not legal, the BUILD_VECTOR operands 3934 // are promoted and implicitly truncated. Make that explicit here. 3935 if (Op.getValueType() != SrcEltVT) 3936 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3937 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3938 DstEltVT, Op)); 3939 AddToWorkList(Ops.back().getNode()); 3940 } 3941 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 3942 BV->getValueType(0).getVectorNumElements()); 3943 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3944 &Ops[0], Ops.size()); 3945 } 3946 3947 // Otherwise, we're growing or shrinking the elements. To avoid having to 3948 // handle annoying details of growing/shrinking FP values, we convert them to 3949 // int first. 3950 if (SrcEltVT.isFloatingPoint()) { 3951 // Convert the input float vector to a int vector where the elements are the 3952 // same sizes. 3953 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3954 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 3955 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3956 SrcEltVT = IntVT; 3957 } 3958 3959 // Now we know the input is an integer vector. If the output is a FP type, 3960 // convert to integer first, then to FP of the right size. 3961 if (DstEltVT.isFloatingPoint()) { 3962 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3963 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 3964 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3965 3966 // Next, convert to FP elements of the same size. 3967 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3968 } 3969 3970 // Okay, we know the src/dst types are both integers of differing types. 3971 // Handling growing first. 3972 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3973 if (SrcBitSize < DstBitSize) { 3974 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3975 3976 SmallVector<SDValue, 8> Ops; 3977 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3978 i += NumInputsPerOutput) { 3979 bool isLE = TLI.isLittleEndian(); 3980 APInt NewBits = APInt(DstBitSize, 0); 3981 bool EltIsUndef = true; 3982 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3983 // Shift the previously computed bits over. 3984 NewBits <<= SrcBitSize; 3985 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3986 if (Op.getOpcode() == ISD::UNDEF) continue; 3987 EltIsUndef = false; 3988 3989 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3990 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3991 } 3992 3993 if (EltIsUndef) 3994 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3995 else 3996 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3997 } 3998 3999 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4000 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4001 &Ops[0], Ops.size()); 4002 } 4003 4004 // Finally, this must be the case where we are shrinking elements: each input 4005 // turns into multiple outputs. 4006 bool isS2V = ISD::isScalarToVector(BV); 4007 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4008 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4009 NumOutputsPerInput*BV->getNumOperands()); 4010 SmallVector<SDValue, 8> Ops; 4011 4012 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4013 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4014 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4015 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4016 continue; 4017 } 4018 4019 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4020 getAPIntValue()).zextOrTrunc(SrcBitSize); 4021 4022 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4023 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4024 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4025 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4026 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4027 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4028 Ops[0]); 4029 OpVal = OpVal.lshr(DstBitSize); 4030 } 4031 4032 // For big endian targets, swap the order of the pieces of each element. 4033 if (TLI.isBigEndian()) 4034 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4035 } 4036 4037 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4038 &Ops[0], Ops.size()); 4039} 4040 4041SDValue DAGCombiner::visitFADD(SDNode *N) { 4042 SDValue N0 = N->getOperand(0); 4043 SDValue N1 = N->getOperand(1); 4044 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4045 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4046 EVT VT = N->getValueType(0); 4047 4048 // fold vector ops 4049 if (VT.isVector()) { 4050 SDValue FoldedVOp = SimplifyVBinOp(N); 4051 if (FoldedVOp.getNode()) return FoldedVOp; 4052 } 4053 4054 // fold (fadd c1, c2) -> (fadd c1, c2) 4055 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4056 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4057 // canonicalize constant to RHS 4058 if (N0CFP && !N1CFP) 4059 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4060 // fold (fadd A, 0) -> A 4061 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4062 return N0; 4063 // fold (fadd A, (fneg B)) -> (fsub A, B) 4064 if (isNegatibleForFree(N1, LegalOperations) == 2) 4065 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4066 GetNegatedExpression(N1, DAG, LegalOperations)); 4067 // fold (fadd (fneg A), B) -> (fsub B, A) 4068 if (isNegatibleForFree(N0, LegalOperations) == 2) 4069 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4070 GetNegatedExpression(N0, DAG, LegalOperations)); 4071 4072 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4073 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4074 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4075 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4076 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4077 N0.getOperand(1), N1)); 4078 4079 return SDValue(); 4080} 4081 4082SDValue DAGCombiner::visitFSUB(SDNode *N) { 4083 SDValue N0 = N->getOperand(0); 4084 SDValue N1 = N->getOperand(1); 4085 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4086 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4087 EVT VT = N->getValueType(0); 4088 4089 // fold vector ops 4090 if (VT.isVector()) { 4091 SDValue FoldedVOp = SimplifyVBinOp(N); 4092 if (FoldedVOp.getNode()) return FoldedVOp; 4093 } 4094 4095 // fold (fsub c1, c2) -> c1-c2 4096 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4097 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4098 // fold (fsub A, 0) -> A 4099 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4100 return N0; 4101 // fold (fsub 0, B) -> -B 4102 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4103 if (isNegatibleForFree(N1, LegalOperations)) 4104 return GetNegatedExpression(N1, DAG, LegalOperations); 4105 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4106 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4107 } 4108 // fold (fsub A, (fneg B)) -> (fadd A, B) 4109 if (isNegatibleForFree(N1, LegalOperations)) 4110 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4111 GetNegatedExpression(N1, DAG, LegalOperations)); 4112 4113 return SDValue(); 4114} 4115 4116SDValue DAGCombiner::visitFMUL(SDNode *N) { 4117 SDValue N0 = N->getOperand(0); 4118 SDValue N1 = N->getOperand(1); 4119 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4120 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4121 EVT VT = N->getValueType(0); 4122 4123 // fold vector ops 4124 if (VT.isVector()) { 4125 SDValue FoldedVOp = SimplifyVBinOp(N); 4126 if (FoldedVOp.getNode()) return FoldedVOp; 4127 } 4128 4129 // fold (fmul c1, c2) -> c1*c2 4130 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4131 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4132 // canonicalize constant to RHS 4133 if (N0CFP && !N1CFP) 4134 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4135 // fold (fmul A, 0) -> 0 4136 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4137 return N1; 4138 // fold (fmul A, 0) -> 0, vector edition. 4139 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4140 return N1; 4141 // fold (fmul X, 2.0) -> (fadd X, X) 4142 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4143 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4144 // fold (fmul X, -1.0) -> (fneg X) 4145 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4146 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4147 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4148 4149 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4150 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4151 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4152 // Both can be negated for free, check to see if at least one is cheaper 4153 // negated. 4154 if (LHSNeg == 2 || RHSNeg == 2) 4155 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4156 GetNegatedExpression(N0, DAG, LegalOperations), 4157 GetNegatedExpression(N1, DAG, LegalOperations)); 4158 } 4159 } 4160 4161 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4162 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4163 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4164 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4165 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4166 N0.getOperand(1), N1)); 4167 4168 return SDValue(); 4169} 4170 4171SDValue DAGCombiner::visitFDIV(SDNode *N) { 4172 SDValue N0 = N->getOperand(0); 4173 SDValue N1 = N->getOperand(1); 4174 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4175 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4176 EVT VT = N->getValueType(0); 4177 4178 // fold vector ops 4179 if (VT.isVector()) { 4180 SDValue FoldedVOp = SimplifyVBinOp(N); 4181 if (FoldedVOp.getNode()) return FoldedVOp; 4182 } 4183 4184 // fold (fdiv c1, c2) -> c1/c2 4185 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4186 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4187 4188 4189 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4190 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4191 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4192 // Both can be negated for free, check to see if at least one is cheaper 4193 // negated. 4194 if (LHSNeg == 2 || RHSNeg == 2) 4195 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4196 GetNegatedExpression(N0, DAG, LegalOperations), 4197 GetNegatedExpression(N1, DAG, LegalOperations)); 4198 } 4199 } 4200 4201 return SDValue(); 4202} 4203 4204SDValue DAGCombiner::visitFREM(SDNode *N) { 4205 SDValue N0 = N->getOperand(0); 4206 SDValue N1 = N->getOperand(1); 4207 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4208 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4209 EVT VT = N->getValueType(0); 4210 4211 // fold (frem c1, c2) -> fmod(c1,c2) 4212 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4213 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4214 4215 return SDValue(); 4216} 4217 4218SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4219 SDValue N0 = N->getOperand(0); 4220 SDValue N1 = N->getOperand(1); 4221 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4222 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4223 EVT VT = N->getValueType(0); 4224 4225 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4226 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4227 4228 if (N1CFP) { 4229 const APFloat& V = N1CFP->getValueAPF(); 4230 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4231 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4232 if (!V.isNegative()) { 4233 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4234 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4235 } else { 4236 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4237 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4238 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4239 } 4240 } 4241 4242 // copysign(fabs(x), y) -> copysign(x, y) 4243 // copysign(fneg(x), y) -> copysign(x, y) 4244 // copysign(copysign(x,z), y) -> copysign(x, y) 4245 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4246 N0.getOpcode() == ISD::FCOPYSIGN) 4247 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4248 N0.getOperand(0), N1); 4249 4250 // copysign(x, abs(y)) -> abs(x) 4251 if (N1.getOpcode() == ISD::FABS) 4252 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4253 4254 // copysign(x, copysign(y,z)) -> copysign(x, z) 4255 if (N1.getOpcode() == ISD::FCOPYSIGN) 4256 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4257 N0, N1.getOperand(1)); 4258 4259 // copysign(x, fp_extend(y)) -> copysign(x, y) 4260 // copysign(x, fp_round(y)) -> copysign(x, y) 4261 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4262 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4263 N0, N1.getOperand(0)); 4264 4265 return SDValue(); 4266} 4267 4268SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4269 SDValue N0 = N->getOperand(0); 4270 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4271 EVT VT = N->getValueType(0); 4272 EVT OpVT = N0.getValueType(); 4273 4274 // fold (sint_to_fp c1) -> c1fp 4275 if (N0C && OpVT != MVT::ppcf128) 4276 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4277 4278 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4279 // but UINT_TO_FP is legal on this target, try to convert. 4280 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4281 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4282 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4283 if (DAG.SignBitIsZero(N0)) 4284 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4285 } 4286 4287 return SDValue(); 4288} 4289 4290SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4291 SDValue N0 = N->getOperand(0); 4292 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4293 EVT VT = N->getValueType(0); 4294 EVT OpVT = N0.getValueType(); 4295 4296 // fold (uint_to_fp c1) -> c1fp 4297 if (N0C && OpVT != MVT::ppcf128) 4298 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4299 4300 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4301 // but SINT_TO_FP is legal on this target, try to convert. 4302 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4303 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4304 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4305 if (DAG.SignBitIsZero(N0)) 4306 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4307 } 4308 4309 return SDValue(); 4310} 4311 4312SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4313 SDValue N0 = N->getOperand(0); 4314 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4315 EVT VT = N->getValueType(0); 4316 4317 // fold (fp_to_sint c1fp) -> c1 4318 if (N0CFP) 4319 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4320 4321 return SDValue(); 4322} 4323 4324SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4325 SDValue N0 = N->getOperand(0); 4326 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4327 EVT VT = N->getValueType(0); 4328 4329 // fold (fp_to_uint c1fp) -> c1 4330 if (N0CFP && VT != MVT::ppcf128) 4331 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4332 4333 return SDValue(); 4334} 4335 4336SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4337 SDValue N0 = N->getOperand(0); 4338 SDValue N1 = N->getOperand(1); 4339 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4340 EVT VT = N->getValueType(0); 4341 4342 // fold (fp_round c1fp) -> c1fp 4343 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4344 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4345 4346 // fold (fp_round (fp_extend x)) -> x 4347 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4348 return N0.getOperand(0); 4349 4350 // fold (fp_round (fp_round x)) -> (fp_round x) 4351 if (N0.getOpcode() == ISD::FP_ROUND) { 4352 // This is a value preserving truncation if both round's are. 4353 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4354 N0.getNode()->getConstantOperandVal(1) == 1; 4355 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4356 DAG.getIntPtrConstant(IsTrunc)); 4357 } 4358 4359 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4360 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4361 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4362 N0.getOperand(0), N1); 4363 AddToWorkList(Tmp.getNode()); 4364 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4365 Tmp, N0.getOperand(1)); 4366 } 4367 4368 return SDValue(); 4369} 4370 4371SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4372 SDValue N0 = N->getOperand(0); 4373 EVT VT = N->getValueType(0); 4374 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4375 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4376 4377 // fold (fp_round_inreg c1fp) -> c1fp 4378 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4379 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4380 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4381 } 4382 4383 return SDValue(); 4384} 4385 4386SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4387 SDValue N0 = N->getOperand(0); 4388 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4389 EVT VT = N->getValueType(0); 4390 4391 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4392 if (N->hasOneUse() && 4393 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4394 return SDValue(); 4395 4396 // fold (fp_extend c1fp) -> c1fp 4397 if (N0CFP && VT != MVT::ppcf128) 4398 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4399 4400 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4401 // value of X. 4402 if (N0.getOpcode() == ISD::FP_ROUND 4403 && N0.getNode()->getConstantOperandVal(1) == 1) { 4404 SDValue In = N0.getOperand(0); 4405 if (In.getValueType() == VT) return In; 4406 if (VT.bitsLT(In.getValueType())) 4407 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4408 In, N0.getOperand(1)); 4409 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4410 } 4411 4412 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4413 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4414 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4415 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4416 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4417 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4418 LN0->getChain(), 4419 LN0->getBasePtr(), LN0->getSrcValue(), 4420 LN0->getSrcValueOffset(), 4421 N0.getValueType(), 4422 LN0->isVolatile(), LN0->getAlignment()); 4423 CombineTo(N, ExtLoad); 4424 CombineTo(N0.getNode(), 4425 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4426 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4427 ExtLoad.getValue(1)); 4428 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4429 } 4430 4431 return SDValue(); 4432} 4433 4434SDValue DAGCombiner::visitFNEG(SDNode *N) { 4435 SDValue N0 = N->getOperand(0); 4436 EVT VT = N->getValueType(0); 4437 4438 if (isNegatibleForFree(N0, LegalOperations)) 4439 return GetNegatedExpression(N0, DAG, LegalOperations); 4440 4441 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4442 // constant pool values. 4443 if (N0.getOpcode() == ISD::BIT_CONVERT && 4444 !VT.isVector() && 4445 N0.getNode()->hasOneUse() && 4446 N0.getOperand(0).getValueType().isInteger()) { 4447 SDValue Int = N0.getOperand(0); 4448 EVT IntVT = Int.getValueType(); 4449 if (IntVT.isInteger() && !IntVT.isVector()) { 4450 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4451 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4452 AddToWorkList(Int.getNode()); 4453 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4454 VT, Int); 4455 } 4456 } 4457 4458 return SDValue(); 4459} 4460 4461SDValue DAGCombiner::visitFABS(SDNode *N) { 4462 SDValue N0 = N->getOperand(0); 4463 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4464 EVT VT = N->getValueType(0); 4465 4466 // fold (fabs c1) -> fabs(c1) 4467 if (N0CFP && VT != MVT::ppcf128) 4468 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4469 // fold (fabs (fabs x)) -> (fabs x) 4470 if (N0.getOpcode() == ISD::FABS) 4471 return N->getOperand(0); 4472 // fold (fabs (fneg x)) -> (fabs x) 4473 // fold (fabs (fcopysign x, y)) -> (fabs x) 4474 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4475 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4476 4477 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4478 // constant pool values. 4479 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4480 N0.getOperand(0).getValueType().isInteger() && 4481 !N0.getOperand(0).getValueType().isVector()) { 4482 SDValue Int = N0.getOperand(0); 4483 EVT IntVT = Int.getValueType(); 4484 if (IntVT.isInteger() && !IntVT.isVector()) { 4485 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4486 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4487 AddToWorkList(Int.getNode()); 4488 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4489 N->getValueType(0), Int); 4490 } 4491 } 4492 4493 return SDValue(); 4494} 4495 4496SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4497 SDValue Chain = N->getOperand(0); 4498 SDValue N1 = N->getOperand(1); 4499 SDValue N2 = N->getOperand(2); 4500 4501 // If N is a constant we could fold this into a fallthrough or unconditional 4502 // branch. However that doesn't happen very often in normal code, because 4503 // Instcombine/SimplifyCFG should have handled the available opportunities. 4504 // If we did this folding here, it would be necessary to update the 4505 // MachineBasicBlock CFG, which is awkward. 4506 4507 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4508 // on the target. 4509 if (N1.getOpcode() == ISD::SETCC && 4510 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4511 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4512 Chain, N1.getOperand(2), 4513 N1.getOperand(0), N1.getOperand(1), N2); 4514 } 4515 4516 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4517 // Match this pattern so that we can generate simpler code: 4518 // 4519 // %a = ... 4520 // %b = and i32 %a, 2 4521 // %c = srl i32 %b, 1 4522 // brcond i32 %c ... 4523 // 4524 // into 4525 // 4526 // %a = ... 4527 // %b = and %a, 2 4528 // %c = setcc eq %b, 0 4529 // brcond %c ... 4530 // 4531 // This applies only when the AND constant value has one bit set and the 4532 // SRL constant is equal to the log2 of the AND constant. The back-end is 4533 // smart enough to convert the result into a TEST/JMP sequence. 4534 SDValue Op0 = N1.getOperand(0); 4535 SDValue Op1 = N1.getOperand(1); 4536 4537 if (Op0.getOpcode() == ISD::AND && 4538 Op0.hasOneUse() && 4539 Op1.getOpcode() == ISD::Constant) { 4540 SDValue AndOp1 = Op0.getOperand(1); 4541 4542 if (AndOp1.getOpcode() == ISD::Constant) { 4543 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4544 4545 if (AndConst.isPowerOf2() && 4546 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4547 SDValue SetCC = 4548 DAG.getSetCC(N->getDebugLoc(), 4549 TLI.getSetCCResultType(Op0.getValueType()), 4550 Op0, DAG.getConstant(0, Op0.getValueType()), 4551 ISD::SETNE); 4552 4553 // Replace the uses of SRL with SETCC 4554 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4555 removeFromWorkList(N1.getNode()); 4556 DAG.DeleteNode(N1.getNode()); 4557 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4558 MVT::Other, Chain, SetCC, N2); 4559 } 4560 } 4561 } 4562 } 4563 4564 return SDValue(); 4565} 4566 4567// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4568// 4569SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4570 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4571 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4572 4573 // If N is a constant we could fold this into a fallthrough or unconditional 4574 // branch. However that doesn't happen very often in normal code, because 4575 // Instcombine/SimplifyCFG should have handled the available opportunities. 4576 // If we did this folding here, it would be necessary to update the 4577 // MachineBasicBlock CFG, which is awkward. 4578 4579 // Use SimplifySetCC to simplify SETCC's. 4580 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4581 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4582 false); 4583 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4584 4585 // fold to a simpler setcc 4586 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4587 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4588 N->getOperand(0), Simp.getOperand(2), 4589 Simp.getOperand(0), Simp.getOperand(1), 4590 N->getOperand(4)); 4591 4592 return SDValue(); 4593} 4594 4595/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4596/// pre-indexed load / store when the base pointer is an add or subtract 4597/// and it has other uses besides the load / store. After the 4598/// transformation, the new indexed load / store has effectively folded 4599/// the add / subtract in and all of its other uses are redirected to the 4600/// new load / store. 4601bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4602 if (!LegalOperations) 4603 return false; 4604 4605 bool isLoad = true; 4606 SDValue Ptr; 4607 EVT VT; 4608 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4609 if (LD->isIndexed()) 4610 return false; 4611 VT = LD->getMemoryVT(); 4612 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4613 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4614 return false; 4615 Ptr = LD->getBasePtr(); 4616 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4617 if (ST->isIndexed()) 4618 return false; 4619 VT = ST->getMemoryVT(); 4620 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4621 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4622 return false; 4623 Ptr = ST->getBasePtr(); 4624 isLoad = false; 4625 } else { 4626 return false; 4627 } 4628 4629 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4630 // out. There is no reason to make this a preinc/predec. 4631 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4632 Ptr.getNode()->hasOneUse()) 4633 return false; 4634 4635 // Ask the target to do addressing mode selection. 4636 SDValue BasePtr; 4637 SDValue Offset; 4638 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4639 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4640 return false; 4641 // Don't create a indexed load / store with zero offset. 4642 if (isa<ConstantSDNode>(Offset) && 4643 cast<ConstantSDNode>(Offset)->isNullValue()) 4644 return false; 4645 4646 // Try turning it into a pre-indexed load / store except when: 4647 // 1) The new base ptr is a frame index. 4648 // 2) If N is a store and the new base ptr is either the same as or is a 4649 // predecessor of the value being stored. 4650 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4651 // that would create a cycle. 4652 // 4) All uses are load / store ops that use it as old base ptr. 4653 4654 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4655 // (plus the implicit offset) to a register to preinc anyway. 4656 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4657 return false; 4658 4659 // Check #2. 4660 if (!isLoad) { 4661 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4662 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4663 return false; 4664 } 4665 4666 // Now check for #3 and #4. 4667 bool RealUse = false; 4668 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4669 E = Ptr.getNode()->use_end(); I != E; ++I) { 4670 SDNode *Use = *I; 4671 if (Use == N) 4672 continue; 4673 if (Use->isPredecessorOf(N)) 4674 return false; 4675 4676 if (!((Use->getOpcode() == ISD::LOAD && 4677 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4678 (Use->getOpcode() == ISD::STORE && 4679 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4680 RealUse = true; 4681 } 4682 4683 if (!RealUse) 4684 return false; 4685 4686 SDValue Result; 4687 if (isLoad) 4688 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4689 BasePtr, Offset, AM); 4690 else 4691 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4692 BasePtr, Offset, AM); 4693 ++PreIndexedNodes; 4694 ++NodesCombined; 4695 DEBUG(errs() << "\nReplacing.4 "; 4696 N->dump(&DAG); 4697 errs() << "\nWith: "; 4698 Result.getNode()->dump(&DAG); 4699 errs() << '\n'); 4700 WorkListRemover DeadNodes(*this); 4701 if (isLoad) { 4702 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4703 &DeadNodes); 4704 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4705 &DeadNodes); 4706 } else { 4707 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4708 &DeadNodes); 4709 } 4710 4711 // Finally, since the node is now dead, remove it from the graph. 4712 DAG.DeleteNode(N); 4713 4714 // Replace the uses of Ptr with uses of the updated base value. 4715 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4716 &DeadNodes); 4717 removeFromWorkList(Ptr.getNode()); 4718 DAG.DeleteNode(Ptr.getNode()); 4719 4720 return true; 4721} 4722 4723/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4724/// add / sub of the base pointer node into a post-indexed load / store. 4725/// The transformation folded the add / subtract into the new indexed 4726/// load / store effectively and all of its uses are redirected to the 4727/// new load / store. 4728bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4729 if (!LegalOperations) 4730 return false; 4731 4732 bool isLoad = true; 4733 SDValue Ptr; 4734 EVT VT; 4735 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4736 if (LD->isIndexed()) 4737 return false; 4738 VT = LD->getMemoryVT(); 4739 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4740 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4741 return false; 4742 Ptr = LD->getBasePtr(); 4743 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4744 if (ST->isIndexed()) 4745 return false; 4746 VT = ST->getMemoryVT(); 4747 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4748 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4749 return false; 4750 Ptr = ST->getBasePtr(); 4751 isLoad = false; 4752 } else { 4753 return false; 4754 } 4755 4756 if (Ptr.getNode()->hasOneUse()) 4757 return false; 4758 4759 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4760 E = Ptr.getNode()->use_end(); I != E; ++I) { 4761 SDNode *Op = *I; 4762 if (Op == N || 4763 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4764 continue; 4765 4766 SDValue BasePtr; 4767 SDValue Offset; 4768 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4769 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4770 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4771 std::swap(BasePtr, Offset); 4772 if (Ptr != BasePtr) 4773 continue; 4774 // Don't create a indexed load / store with zero offset. 4775 if (isa<ConstantSDNode>(Offset) && 4776 cast<ConstantSDNode>(Offset)->isNullValue()) 4777 continue; 4778 4779 // Try turning it into a post-indexed load / store except when 4780 // 1) All uses are load / store ops that use it as base ptr. 4781 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4782 // nor a successor of N. Otherwise, if Op is folded that would 4783 // create a cycle. 4784 4785 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4786 continue; 4787 4788 // Check for #1. 4789 bool TryNext = false; 4790 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4791 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4792 SDNode *Use = *II; 4793 if (Use == Ptr.getNode()) 4794 continue; 4795 4796 // If all the uses are load / store addresses, then don't do the 4797 // transformation. 4798 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4799 bool RealUse = false; 4800 for (SDNode::use_iterator III = Use->use_begin(), 4801 EEE = Use->use_end(); III != EEE; ++III) { 4802 SDNode *UseUse = *III; 4803 if (!((UseUse->getOpcode() == ISD::LOAD && 4804 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4805 (UseUse->getOpcode() == ISD::STORE && 4806 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4807 RealUse = true; 4808 } 4809 4810 if (!RealUse) { 4811 TryNext = true; 4812 break; 4813 } 4814 } 4815 } 4816 4817 if (TryNext) 4818 continue; 4819 4820 // Check for #2 4821 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4822 SDValue Result = isLoad 4823 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4824 BasePtr, Offset, AM) 4825 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4826 BasePtr, Offset, AM); 4827 ++PostIndexedNodes; 4828 ++NodesCombined; 4829 DEBUG(errs() << "\nReplacing.5 "; 4830 N->dump(&DAG); 4831 errs() << "\nWith: "; 4832 Result.getNode()->dump(&DAG); 4833 errs() << '\n'); 4834 WorkListRemover DeadNodes(*this); 4835 if (isLoad) { 4836 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4837 &DeadNodes); 4838 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4839 &DeadNodes); 4840 } else { 4841 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4842 &DeadNodes); 4843 } 4844 4845 // Finally, since the node is now dead, remove it from the graph. 4846 DAG.DeleteNode(N); 4847 4848 // Replace the uses of Use with uses of the updated base value. 4849 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4850 Result.getValue(isLoad ? 1 : 0), 4851 &DeadNodes); 4852 removeFromWorkList(Op); 4853 DAG.DeleteNode(Op); 4854 return true; 4855 } 4856 } 4857 } 4858 4859 return false; 4860} 4861 4862SDValue DAGCombiner::visitLOAD(SDNode *N) { 4863 LoadSDNode *LD = cast<LoadSDNode>(N); 4864 SDValue Chain = LD->getChain(); 4865 SDValue Ptr = LD->getBasePtr(); 4866 4867 // Try to infer better alignment information than the load already has. 4868 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4869 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 4870 if (Align > LD->getAlignment()) 4871 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4872 LD->getValueType(0), 4873 Chain, Ptr, LD->getSrcValue(), 4874 LD->getSrcValueOffset(), LD->getMemoryVT(), 4875 LD->isVolatile(), Align); 4876 } 4877 } 4878 4879 // If load is not volatile and there are no uses of the loaded value (and 4880 // the updated indexed value in case of indexed loads), change uses of the 4881 // chain value into uses of the chain input (i.e. delete the dead load). 4882 if (!LD->isVolatile()) { 4883 if (N->getValueType(1) == MVT::Other) { 4884 // Unindexed loads. 4885 if (N->hasNUsesOfValue(0, 0)) { 4886 // It's not safe to use the two value CombineTo variant here. e.g. 4887 // v1, chain2 = load chain1, loc 4888 // v2, chain3 = load chain2, loc 4889 // v3 = add v2, c 4890 // Now we replace use of chain2 with chain1. This makes the second load 4891 // isomorphic to the one we are deleting, and thus makes this load live. 4892 DEBUG(errs() << "\nReplacing.6 "; 4893 N->dump(&DAG); 4894 errs() << "\nWith chain: "; 4895 Chain.getNode()->dump(&DAG); 4896 errs() << "\n"); 4897 WorkListRemover DeadNodes(*this); 4898 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4899 4900 if (N->use_empty()) { 4901 removeFromWorkList(N); 4902 DAG.DeleteNode(N); 4903 } 4904 4905 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4906 } 4907 } else { 4908 // Indexed loads. 4909 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4910 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4911 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4912 DEBUG(errs() << "\nReplacing.6 "; 4913 N->dump(&DAG); 4914 errs() << "\nWith: "; 4915 Undef.getNode()->dump(&DAG); 4916 errs() << " and 2 other values\n"); 4917 WorkListRemover DeadNodes(*this); 4918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4919 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4920 DAG.getUNDEF(N->getValueType(1)), 4921 &DeadNodes); 4922 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4923 removeFromWorkList(N); 4924 DAG.DeleteNode(N); 4925 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4926 } 4927 } 4928 } 4929 4930 // If this load is directly stored, replace the load value with the stored 4931 // value. 4932 // TODO: Handle store large -> read small portion. 4933 // TODO: Handle TRUNCSTORE/LOADEXT 4934 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4935 !LD->isVolatile()) { 4936 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4937 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4938 if (PrevST->getBasePtr() == Ptr && 4939 PrevST->getValue().getValueType() == N->getValueType(0)) 4940 return CombineTo(N, Chain.getOperand(1), Chain); 4941 } 4942 } 4943 4944 if (CombinerAA) { 4945 // Walk up chain skipping non-aliasing memory nodes. 4946 SDValue BetterChain = FindBetterChain(N, Chain); 4947 4948 // If there is a better chain. 4949 if (Chain != BetterChain) { 4950 SDValue ReplLoad; 4951 4952 // Replace the chain to void dependency. 4953 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4954 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4955 BetterChain, Ptr, 4956 LD->getSrcValue(), LD->getSrcValueOffset(), 4957 LD->isVolatile(), LD->getAlignment()); 4958 } else { 4959 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4960 LD->getValueType(0), 4961 BetterChain, Ptr, LD->getSrcValue(), 4962 LD->getSrcValueOffset(), 4963 LD->getMemoryVT(), 4964 LD->isVolatile(), 4965 LD->getAlignment()); 4966 } 4967 4968 // Create token factor to keep old chain connected. 4969 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4970 MVT::Other, Chain, ReplLoad.getValue(1)); 4971 4972 // Make sure the new and old chains are cleaned up. 4973 AddToWorkList(Token.getNode()); 4974 4975 // Replace uses with load result and token factor. Don't add users 4976 // to work list. 4977 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4978 } 4979 } 4980 4981 // Try transforming N to an indexed load. 4982 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4983 return SDValue(N, 0); 4984 4985 return SDValue(); 4986} 4987 4988 4989/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4990/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4991/// of the loaded bits, try narrowing the load and store if it would end up 4992/// being a win for performance or code size. 4993SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4994 StoreSDNode *ST = cast<StoreSDNode>(N); 4995 if (ST->isVolatile()) 4996 return SDValue(); 4997 4998 SDValue Chain = ST->getChain(); 4999 SDValue Value = ST->getValue(); 5000 SDValue Ptr = ST->getBasePtr(); 5001 EVT VT = Value.getValueType(); 5002 5003 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5004 return SDValue(); 5005 5006 unsigned Opc = Value.getOpcode(); 5007 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5008 Value.getOperand(1).getOpcode() != ISD::Constant) 5009 return SDValue(); 5010 5011 SDValue N0 = Value.getOperand(0); 5012 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5013 LoadSDNode *LD = cast<LoadSDNode>(N0); 5014 if (LD->getBasePtr() != Ptr) 5015 return SDValue(); 5016 5017 // Find the type to narrow it the load / op / store to. 5018 SDValue N1 = Value.getOperand(1); 5019 unsigned BitWidth = N1.getValueSizeInBits(); 5020 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5021 if (Opc == ISD::AND) 5022 Imm ^= APInt::getAllOnesValue(BitWidth); 5023 if (Imm == 0 || Imm.isAllOnesValue()) 5024 return SDValue(); 5025 unsigned ShAmt = Imm.countTrailingZeros(); 5026 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5027 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5028 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5029 while (NewBW < BitWidth && 5030 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5031 TLI.isNarrowingProfitable(VT, NewVT))) { 5032 NewBW = NextPowerOf2(NewBW); 5033 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5034 } 5035 if (NewBW >= BitWidth) 5036 return SDValue(); 5037 5038 // If the lsb changed does not start at the type bitwidth boundary, 5039 // start at the previous one. 5040 if (ShAmt % NewBW) 5041 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5042 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5043 if ((Imm & Mask) == Imm) { 5044 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5045 if (Opc == ISD::AND) 5046 NewImm ^= APInt::getAllOnesValue(NewBW); 5047 uint64_t PtrOff = ShAmt / 8; 5048 // For big endian targets, we need to adjust the offset to the pointer to 5049 // load the correct bytes. 5050 if (TLI.isBigEndian()) 5051 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5052 5053 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5054 if (NewAlign < 5055 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT(*DAG.getContext()))) 5056 return SDValue(); 5057 5058 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5059 Ptr.getValueType(), Ptr, 5060 DAG.getConstant(PtrOff, Ptr.getValueType())); 5061 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5062 LD->getChain(), NewPtr, 5063 LD->getSrcValue(), LD->getSrcValueOffset(), 5064 LD->isVolatile(), NewAlign); 5065 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5066 DAG.getConstant(NewImm, NewVT)); 5067 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5068 NewVal, NewPtr, 5069 ST->getSrcValue(), ST->getSrcValueOffset(), 5070 false, NewAlign); 5071 5072 AddToWorkList(NewPtr.getNode()); 5073 AddToWorkList(NewLD.getNode()); 5074 AddToWorkList(NewVal.getNode()); 5075 WorkListRemover DeadNodes(*this); 5076 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5077 &DeadNodes); 5078 ++OpsNarrowed; 5079 return NewST; 5080 } 5081 } 5082 5083 return SDValue(); 5084} 5085 5086SDValue DAGCombiner::visitSTORE(SDNode *N) { 5087 StoreSDNode *ST = cast<StoreSDNode>(N); 5088 SDValue Chain = ST->getChain(); 5089 SDValue Value = ST->getValue(); 5090 SDValue Ptr = ST->getBasePtr(); 5091 5092 // Try to infer better alignment information than the store already has. 5093 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5094 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5095 if (Align > ST->getAlignment()) 5096 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5097 Ptr, ST->getSrcValue(), 5098 ST->getSrcValueOffset(), ST->getMemoryVT(), 5099 ST->isVolatile(), Align); 5100 } 5101 } 5102 5103 // If this is a store of a bit convert, store the input value if the 5104 // resultant store does not need a higher alignment than the original. 5105 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5106 ST->isUnindexed()) { 5107 unsigned OrigAlign = ST->getAlignment(); 5108 EVT SVT = Value.getOperand(0).getValueType(); 5109 unsigned Align = TLI.getTargetData()-> 5110 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5111 if (Align <= OrigAlign && 5112 ((!LegalOperations && !ST->isVolatile()) || 5113 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5114 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5115 Ptr, ST->getSrcValue(), 5116 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5117 } 5118 5119 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5120 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5121 // NOTE: If the original store is volatile, this transform must not increase 5122 // the number of stores. For example, on x86-32 an f64 can be stored in one 5123 // processor operation but an i64 (which is not legal) requires two. So the 5124 // transform should not be done in this case. 5125 if (Value.getOpcode() != ISD::TargetConstantFP) { 5126 SDValue Tmp; 5127 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5128 default: llvm_unreachable("Unknown FP type"); 5129 case MVT::f80: // We don't do this for these yet. 5130 case MVT::f128: 5131 case MVT::ppcf128: 5132 break; 5133 case MVT::f32: 5134 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5135 !ST->isVolatile()) || 5136 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5137 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5138 bitcastToAPInt().getZExtValue(), MVT::i32); 5139 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5140 Ptr, ST->getSrcValue(), 5141 ST->getSrcValueOffset(), ST->isVolatile(), 5142 ST->getAlignment()); 5143 } 5144 break; 5145 case MVT::f64: 5146 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5147 !ST->isVolatile()) || 5148 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5149 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5150 getZExtValue(), MVT::i64); 5151 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5152 Ptr, ST->getSrcValue(), 5153 ST->getSrcValueOffset(), ST->isVolatile(), 5154 ST->getAlignment()); 5155 } else if (!ST->isVolatile() && 5156 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5157 // Many FP stores are not made apparent until after legalize, e.g. for 5158 // argument passing. Since this is so common, custom legalize the 5159 // 64-bit integer store into two 32-bit stores. 5160 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5161 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5162 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5163 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5164 5165 int SVOffset = ST->getSrcValueOffset(); 5166 unsigned Alignment = ST->getAlignment(); 5167 bool isVolatile = ST->isVolatile(); 5168 5169 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5170 Ptr, ST->getSrcValue(), 5171 ST->getSrcValueOffset(), 5172 isVolatile, ST->getAlignment()); 5173 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5174 DAG.getConstant(4, Ptr.getValueType())); 5175 SVOffset += 4; 5176 Alignment = MinAlign(Alignment, 4U); 5177 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5178 Ptr, ST->getSrcValue(), 5179 SVOffset, isVolatile, Alignment); 5180 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5181 St0, St1); 5182 } 5183 5184 break; 5185 } 5186 } 5187 } 5188 5189 if (CombinerAA) { 5190 // Walk up chain skipping non-aliasing memory nodes. 5191 SDValue BetterChain = FindBetterChain(N, Chain); 5192 5193 // If there is a better chain. 5194 if (Chain != BetterChain) { 5195 SDValue ReplStore; 5196 5197 // Replace the chain to avoid dependency. 5198 if (ST->isTruncatingStore()) { 5199 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5200 ST->getSrcValue(),ST->getSrcValueOffset(), 5201 ST->getMemoryVT(), 5202 ST->isVolatile(), ST->getAlignment()); 5203 } else { 5204 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5205 ST->getSrcValue(), ST->getSrcValueOffset(), 5206 ST->isVolatile(), ST->getAlignment()); 5207 } 5208 5209 // Create token to keep both nodes around. 5210 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5211 MVT::Other, Chain, ReplStore); 5212 5213 // Make sure the new and old chains are cleaned up. 5214 AddToWorkList(Token.getNode()); 5215 5216 // Don't add users to work list. 5217 return CombineTo(N, Token, false); 5218 } 5219 } 5220 5221 // Try transforming N to an indexed store. 5222 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5223 return SDValue(N, 0); 5224 5225 // FIXME: is there such a thing as a truncating indexed store? 5226 if (ST->isTruncatingStore() && ST->isUnindexed() && 5227 Value.getValueType().isInteger()) { 5228 // See if we can simplify the input to this truncstore with knowledge that 5229 // only the low bits are being used. For example: 5230 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5231 SDValue Shorter = 5232 GetDemandedBits(Value, 5233 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5234 ST->getMemoryVT().getSizeInBits())); 5235 AddToWorkList(Value.getNode()); 5236 if (Shorter.getNode()) 5237 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5238 Ptr, ST->getSrcValue(), 5239 ST->getSrcValueOffset(), ST->getMemoryVT(), 5240 ST->isVolatile(), ST->getAlignment()); 5241 5242 // Otherwise, see if we can simplify the operation with 5243 // SimplifyDemandedBits, which only works if the value has a single use. 5244 if (SimplifyDemandedBits(Value, 5245 APInt::getLowBitsSet( 5246 Value.getValueType().getScalarType().getSizeInBits(), 5247 ST->getMemoryVT().getSizeInBits()))) 5248 return SDValue(N, 0); 5249 } 5250 5251 // If this is a load followed by a store to the same location, then the store 5252 // is dead/noop. 5253 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5254 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5255 ST->isUnindexed() && !ST->isVolatile() && 5256 // There can't be any side effects between the load and store, such as 5257 // a call or store. 5258 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5259 // The store is dead, remove it. 5260 return Chain; 5261 } 5262 } 5263 5264 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5265 // truncating store. We can do this even if this is already a truncstore. 5266 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5267 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5268 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5269 ST->getMemoryVT())) { 5270 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5271 Ptr, ST->getSrcValue(), 5272 ST->getSrcValueOffset(), ST->getMemoryVT(), 5273 ST->isVolatile(), ST->getAlignment()); 5274 } 5275 5276 return ReduceLoadOpStoreWidth(N); 5277} 5278 5279SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5280 SDValue InVec = N->getOperand(0); 5281 SDValue InVal = N->getOperand(1); 5282 SDValue EltNo = N->getOperand(2); 5283 5284 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5285 // vector with the inserted element. 5286 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5287 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5288 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5289 InVec.getNode()->op_end()); 5290 if (Elt < Ops.size()) 5291 Ops[Elt] = InVal; 5292 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5293 InVec.getValueType(), &Ops[0], Ops.size()); 5294 } 5295 // If the invec is an UNDEF and if EltNo is a constant, create a new 5296 // BUILD_VECTOR with undef elements and the inserted element. 5297 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5298 isa<ConstantSDNode>(EltNo)) { 5299 EVT VT = InVec.getValueType(); 5300 EVT EltVT = VT.getVectorElementType(); 5301 unsigned NElts = VT.getVectorNumElements(); 5302 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5303 5304 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5305 if (Elt < Ops.size()) 5306 Ops[Elt] = InVal; 5307 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5308 InVec.getValueType(), &Ops[0], Ops.size()); 5309 } 5310 return SDValue(); 5311} 5312 5313SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5314 // (vextract (scalar_to_vector val, 0) -> val 5315 SDValue InVec = N->getOperand(0); 5316 5317 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5318 // If the operand is wider than the vector element type then it is implicitly 5319 // truncated. Make that explicit here. 5320 EVT EltVT = InVec.getValueType().getVectorElementType(); 5321 SDValue InOp = InVec.getOperand(0); 5322 if (InOp.getValueType() != EltVT) 5323 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5324 return InOp; 5325 } 5326 5327 // Perform only after legalization to ensure build_vector / vector_shuffle 5328 // optimizations have already been done. 5329 if (!LegalOperations) return SDValue(); 5330 5331 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5332 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5333 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5334 SDValue EltNo = N->getOperand(1); 5335 5336 if (isa<ConstantSDNode>(EltNo)) { 5337 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5338 bool NewLoad = false; 5339 bool BCNumEltsChanged = false; 5340 EVT VT = InVec.getValueType(); 5341 EVT ExtVT = VT.getVectorElementType(); 5342 EVT LVT = ExtVT; 5343 5344 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5345 EVT BCVT = InVec.getOperand(0).getValueType(); 5346 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5347 return SDValue(); 5348 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5349 BCNumEltsChanged = true; 5350 InVec = InVec.getOperand(0); 5351 ExtVT = BCVT.getVectorElementType(); 5352 NewLoad = true; 5353 } 5354 5355 LoadSDNode *LN0 = NULL; 5356 const ShuffleVectorSDNode *SVN = NULL; 5357 if (ISD::isNormalLoad(InVec.getNode())) { 5358 LN0 = cast<LoadSDNode>(InVec); 5359 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5360 InVec.getOperand(0).getValueType() == ExtVT && 5361 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5362 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5363 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5364 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5365 // => 5366 // (load $addr+1*size) 5367 5368 // If the bit convert changed the number of elements, it is unsafe 5369 // to examine the mask. 5370 if (BCNumEltsChanged) 5371 return SDValue(); 5372 5373 // Select the input vector, guarding against out of range extract vector. 5374 unsigned NumElems = VT.getVectorNumElements(); 5375 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5376 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5377 5378 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5379 InVec = InVec.getOperand(0); 5380 if (ISD::isNormalLoad(InVec.getNode())) { 5381 LN0 = cast<LoadSDNode>(InVec); 5382 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5383 } 5384 } 5385 5386 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5387 return SDValue(); 5388 5389 unsigned Align = LN0->getAlignment(); 5390 if (NewLoad) { 5391 // Check the resultant load doesn't need a higher alignment than the 5392 // original load. 5393 unsigned NewAlign = 5394 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5395 5396 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5397 return SDValue(); 5398 5399 Align = NewAlign; 5400 } 5401 5402 SDValue NewPtr = LN0->getBasePtr(); 5403 if (Elt) { 5404 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5405 EVT PtrType = NewPtr.getValueType(); 5406 if (TLI.isBigEndian()) 5407 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5408 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5409 DAG.getConstant(PtrOff, PtrType)); 5410 } 5411 5412 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5413 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5414 LN0->isVolatile(), Align); 5415 } 5416 5417 return SDValue(); 5418} 5419 5420SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5421 unsigned NumInScalars = N->getNumOperands(); 5422 EVT VT = N->getValueType(0); 5423 5424 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5425 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5426 // at most two distinct vectors, turn this into a shuffle node. 5427 SDValue VecIn1, VecIn2; 5428 for (unsigned i = 0; i != NumInScalars; ++i) { 5429 // Ignore undef inputs. 5430 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5431 5432 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5433 // constant index, bail out. 5434 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5435 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5436 VecIn1 = VecIn2 = SDValue(0, 0); 5437 break; 5438 } 5439 5440 // If the input vector type disagrees with the result of the build_vector, 5441 // we can't make a shuffle. 5442 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5443 if (ExtractedFromVec.getValueType() != VT) { 5444 VecIn1 = VecIn2 = SDValue(0, 0); 5445 break; 5446 } 5447 5448 // Otherwise, remember this. We allow up to two distinct input vectors. 5449 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5450 continue; 5451 5452 if (VecIn1.getNode() == 0) { 5453 VecIn1 = ExtractedFromVec; 5454 } else if (VecIn2.getNode() == 0) { 5455 VecIn2 = ExtractedFromVec; 5456 } else { 5457 // Too many inputs. 5458 VecIn1 = VecIn2 = SDValue(0, 0); 5459 break; 5460 } 5461 } 5462 5463 // If everything is good, we can make a shuffle operation. 5464 if (VecIn1.getNode()) { 5465 SmallVector<int, 8> Mask; 5466 for (unsigned i = 0; i != NumInScalars; ++i) { 5467 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5468 Mask.push_back(-1); 5469 continue; 5470 } 5471 5472 // If extracting from the first vector, just use the index directly. 5473 SDValue Extract = N->getOperand(i); 5474 SDValue ExtVal = Extract.getOperand(1); 5475 if (Extract.getOperand(0) == VecIn1) { 5476 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5477 if (ExtIndex > VT.getVectorNumElements()) 5478 return SDValue(); 5479 5480 Mask.push_back(ExtIndex); 5481 continue; 5482 } 5483 5484 // Otherwise, use InIdx + VecSize 5485 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5486 Mask.push_back(Idx+NumInScalars); 5487 } 5488 5489 // Add count and size info. 5490 if (!TLI.isTypeLegal(VT) && LegalTypes) 5491 return SDValue(); 5492 5493 // Return the new VECTOR_SHUFFLE node. 5494 SDValue Ops[2]; 5495 Ops[0] = VecIn1; 5496 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5497 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5498 } 5499 5500 return SDValue(); 5501} 5502 5503SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5504 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5505 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5506 // inputs come from at most two distinct vectors, turn this into a shuffle 5507 // node. 5508 5509 // If we only have one input vector, we don't need to do any concatenation. 5510 if (N->getNumOperands() == 1) 5511 return N->getOperand(0); 5512 5513 return SDValue(); 5514} 5515 5516SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5517 return SDValue(); 5518 5519 EVT VT = N->getValueType(0); 5520 unsigned NumElts = VT.getVectorNumElements(); 5521 5522 SDValue N0 = N->getOperand(0); 5523 5524 assert(N0.getValueType().getVectorNumElements() == NumElts && 5525 "Vector shuffle must be normalized in DAG"); 5526 5527 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5528 5529 // If it is a splat, check if the argument vector is a build_vector with 5530 // all scalar elements the same. 5531 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5532 SDNode *V = N0.getNode(); 5533 5534 5535 // If this is a bit convert that changes the element type of the vector but 5536 // not the number of vector elements, look through it. Be careful not to 5537 // look though conversions that change things like v4f32 to v2f64. 5538 if (V->getOpcode() == ISD::BIT_CONVERT) { 5539 SDValue ConvInput = V->getOperand(0); 5540 if (ConvInput.getValueType().isVector() && 5541 ConvInput.getValueType().getVectorNumElements() == NumElts) 5542 V = ConvInput.getNode(); 5543 } 5544 5545 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5546 unsigned NumElems = V->getNumOperands(); 5547 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5548 if (NumElems > BaseIdx) { 5549 SDValue Base; 5550 bool AllSame = true; 5551 for (unsigned i = 0; i != NumElems; ++i) { 5552 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5553 Base = V->getOperand(i); 5554 break; 5555 } 5556 } 5557 // Splat of <u, u, u, u>, return <u, u, u, u> 5558 if (!Base.getNode()) 5559 return N0; 5560 for (unsigned i = 0; i != NumElems; ++i) { 5561 if (V->getOperand(i) != Base) { 5562 AllSame = false; 5563 break; 5564 } 5565 } 5566 // Splat of <x, x, x, x>, return <x, x, x, x> 5567 if (AllSame) 5568 return N0; 5569 } 5570 } 5571 } 5572 return SDValue(); 5573} 5574 5575/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5576/// an AND to a vector_shuffle with the destination vector and a zero vector. 5577/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5578/// vector_shuffle V, Zero, <0, 4, 2, 4> 5579SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5580 EVT VT = N->getValueType(0); 5581 DebugLoc dl = N->getDebugLoc(); 5582 SDValue LHS = N->getOperand(0); 5583 SDValue RHS = N->getOperand(1); 5584 if (N->getOpcode() == ISD::AND) { 5585 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5586 RHS = RHS.getOperand(0); 5587 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5588 SmallVector<int, 8> Indices; 5589 unsigned NumElts = RHS.getNumOperands(); 5590 for (unsigned i = 0; i != NumElts; ++i) { 5591 SDValue Elt = RHS.getOperand(i); 5592 if (!isa<ConstantSDNode>(Elt)) 5593 return SDValue(); 5594 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5595 Indices.push_back(i); 5596 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5597 Indices.push_back(NumElts); 5598 else 5599 return SDValue(); 5600 } 5601 5602 // Let's see if the target supports this vector_shuffle. 5603 EVT RVT = RHS.getValueType(); 5604 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5605 return SDValue(); 5606 5607 // Return the new VECTOR_SHUFFLE node. 5608 EVT EltVT = RVT.getVectorElementType(); 5609 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5610 DAG.getConstant(0, EltVT)); 5611 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5612 RVT, &ZeroOps[0], ZeroOps.size()); 5613 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5614 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5615 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5616 } 5617 } 5618 5619 return SDValue(); 5620} 5621 5622/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5623SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5624 // After legalize, the target may be depending on adds and other 5625 // binary ops to provide legal ways to construct constants or other 5626 // things. Simplifying them may result in a loss of legality. 5627 if (LegalOperations) return SDValue(); 5628 5629 EVT VT = N->getValueType(0); 5630 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5631 5632 EVT EltType = VT.getVectorElementType(); 5633 SDValue LHS = N->getOperand(0); 5634 SDValue RHS = N->getOperand(1); 5635 SDValue Shuffle = XformToShuffleWithZero(N); 5636 if (Shuffle.getNode()) return Shuffle; 5637 5638 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5639 // this operation. 5640 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5641 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5642 SmallVector<SDValue, 8> Ops; 5643 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5644 SDValue LHSOp = LHS.getOperand(i); 5645 SDValue RHSOp = RHS.getOperand(i); 5646 // If these two elements can't be folded, bail out. 5647 if ((LHSOp.getOpcode() != ISD::UNDEF && 5648 LHSOp.getOpcode() != ISD::Constant && 5649 LHSOp.getOpcode() != ISD::ConstantFP) || 5650 (RHSOp.getOpcode() != ISD::UNDEF && 5651 RHSOp.getOpcode() != ISD::Constant && 5652 RHSOp.getOpcode() != ISD::ConstantFP)) 5653 break; 5654 5655 // Can't fold divide by zero. 5656 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5657 N->getOpcode() == ISD::FDIV) { 5658 if ((RHSOp.getOpcode() == ISD::Constant && 5659 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5660 (RHSOp.getOpcode() == ISD::ConstantFP && 5661 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5662 break; 5663 } 5664 5665 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5666 EltType, LHSOp, RHSOp)); 5667 AddToWorkList(Ops.back().getNode()); 5668 assert((Ops.back().getOpcode() == ISD::UNDEF || 5669 Ops.back().getOpcode() == ISD::Constant || 5670 Ops.back().getOpcode() == ISD::ConstantFP) && 5671 "Scalar binop didn't fold!"); 5672 } 5673 5674 if (Ops.size() == LHS.getNumOperands()) { 5675 EVT VT = LHS.getValueType(); 5676 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5677 &Ops[0], Ops.size()); 5678 } 5679 } 5680 5681 return SDValue(); 5682} 5683 5684SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5685 SDValue N1, SDValue N2){ 5686 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5687 5688 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5689 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5690 5691 // If we got a simplified select_cc node back from SimplifySelectCC, then 5692 // break it down into a new SETCC node, and a new SELECT node, and then return 5693 // the SELECT node, since we were called with a SELECT node. 5694 if (SCC.getNode()) { 5695 // Check to see if we got a select_cc back (to turn into setcc/select). 5696 // Otherwise, just return whatever node we got back, like fabs. 5697 if (SCC.getOpcode() == ISD::SELECT_CC) { 5698 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5699 N0.getValueType(), 5700 SCC.getOperand(0), SCC.getOperand(1), 5701 SCC.getOperand(4)); 5702 AddToWorkList(SETCC.getNode()); 5703 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5704 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5705 } 5706 5707 return SCC; 5708 } 5709 return SDValue(); 5710} 5711 5712/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5713/// are the two values being selected between, see if we can simplify the 5714/// select. Callers of this should assume that TheSelect is deleted if this 5715/// returns true. As such, they should return the appropriate thing (e.g. the 5716/// node) back to the top-level of the DAG combiner loop to avoid it being 5717/// looked at. 5718bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5719 SDValue RHS) { 5720 5721 // If this is a select from two identical things, try to pull the operation 5722 // through the select. 5723 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5724 // If this is a load and the token chain is identical, replace the select 5725 // of two loads with a load through a select of the address to load from. 5726 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5727 // constants have been dropped into the constant pool. 5728 if (LHS.getOpcode() == ISD::LOAD && 5729 // Do not let this transformation reduce the number of volatile loads. 5730 !cast<LoadSDNode>(LHS)->isVolatile() && 5731 !cast<LoadSDNode>(RHS)->isVolatile() && 5732 // Token chains must be identical. 5733 LHS.getOperand(0) == RHS.getOperand(0)) { 5734 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5735 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5736 5737 // If this is an EXTLOAD, the VT's must match. 5738 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5739 // FIXME: this discards src value information. This is 5740 // over-conservative. It would be beneficial to be able to remember 5741 // both potential memory locations. 5742 SDValue Addr; 5743 if (TheSelect->getOpcode() == ISD::SELECT) { 5744 // Check that the condition doesn't reach either load. If so, folding 5745 // this will induce a cycle into the DAG. 5746 if ((!LLD->hasAnyUseOfValue(1) || 5747 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 5748 (!RLD->hasAnyUseOfValue(1) || 5749 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 5750 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5751 LLD->getBasePtr().getValueType(), 5752 TheSelect->getOperand(0), LLD->getBasePtr(), 5753 RLD->getBasePtr()); 5754 } 5755 } else { 5756 // Check that the condition doesn't reach either load. If so, folding 5757 // this will induce a cycle into the DAG. 5758 if ((!LLD->hasAnyUseOfValue(1) || 5759 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5760 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 5761 (!RLD->hasAnyUseOfValue(1) || 5762 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5763 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 5764 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5765 LLD->getBasePtr().getValueType(), 5766 TheSelect->getOperand(0), 5767 TheSelect->getOperand(1), 5768 LLD->getBasePtr(), RLD->getBasePtr(), 5769 TheSelect->getOperand(4)); 5770 } 5771 } 5772 5773 if (Addr.getNode()) { 5774 SDValue Load; 5775 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5776 Load = DAG.getLoad(TheSelect->getValueType(0), 5777 TheSelect->getDebugLoc(), 5778 LLD->getChain(), 5779 Addr, 0, 0, 5780 LLD->isVolatile(), 5781 LLD->getAlignment()); 5782 } else { 5783 Load = DAG.getExtLoad(LLD->getExtensionType(), 5784 TheSelect->getDebugLoc(), 5785 TheSelect->getValueType(0), 5786 LLD->getChain(), Addr, 0, 0, 5787 LLD->getMemoryVT(), 5788 LLD->isVolatile(), 5789 LLD->getAlignment()); 5790 } 5791 5792 // Users of the select now use the result of the load. 5793 CombineTo(TheSelect, Load); 5794 5795 // Users of the old loads now use the new load's chain. We know the 5796 // old-load value is dead now. 5797 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5798 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5799 return true; 5800 } 5801 } 5802 } 5803 } 5804 5805 return false; 5806} 5807 5808/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5809/// where 'cond' is the comparison specified by CC. 5810SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5811 SDValue N2, SDValue N3, 5812 ISD::CondCode CC, bool NotExtCompare) { 5813 // (x ? y : y) -> y. 5814 if (N2 == N3) return N2; 5815 5816 EVT VT = N2.getValueType(); 5817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5818 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5819 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5820 5821 // Determine if the condition we're dealing with is constant 5822 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5823 N0, N1, CC, DL, false); 5824 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5825 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5826 5827 // fold select_cc true, x, y -> x 5828 if (SCCC && !SCCC->isNullValue()) 5829 return N2; 5830 // fold select_cc false, x, y -> y 5831 if (SCCC && SCCC->isNullValue()) 5832 return N3; 5833 5834 // Check to see if we can simplify the select into an fabs node 5835 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5836 // Allow either -0.0 or 0.0 5837 if (CFP->getValueAPF().isZero()) { 5838 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5839 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5840 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5841 N2 == N3.getOperand(0)) 5842 return DAG.getNode(ISD::FABS, DL, VT, N0); 5843 5844 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5845 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5846 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5847 N2.getOperand(0) == N3) 5848 return DAG.getNode(ISD::FABS, DL, VT, N3); 5849 } 5850 } 5851 5852 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5853 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5854 // in it. This is a win when the constant is not otherwise available because 5855 // it replaces two constant pool loads with one. We only do this if the FP 5856 // type is known to be legal, because if it isn't, then we are before legalize 5857 // types an we want the other legalization to happen first (e.g. to avoid 5858 // messing with soft float) and if the ConstantFP is not legal, because if 5859 // it is legal, we may not need to store the FP constant in a constant pool. 5860 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5861 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5862 if (TLI.isTypeLegal(N2.getValueType()) && 5863 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5864 TargetLowering::Legal) && 5865 // If both constants have multiple uses, then we won't need to do an 5866 // extra load, they are likely around in registers for other users. 5867 (TV->hasOneUse() || FV->hasOneUse())) { 5868 Constant *Elts[] = { 5869 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5870 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5871 }; 5872 const Type *FPTy = Elts[0]->getType(); 5873 const TargetData &TD = *TLI.getTargetData(); 5874 5875 // Create a ConstantArray of the two constants. 5876 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 5877 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5878 TD.getPrefTypeAlignment(FPTy)); 5879 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5880 5881 // Get the offsets to the 0 and 1 element of the array so that we can 5882 // select between them. 5883 SDValue Zero = DAG.getIntPtrConstant(0); 5884 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5885 SDValue One = DAG.getIntPtrConstant(EltSize); 5886 5887 SDValue Cond = DAG.getSetCC(DL, 5888 TLI.getSetCCResultType(N0.getValueType()), 5889 N0, N1, CC); 5890 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5891 Cond, One, Zero); 5892 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5893 CstOffset); 5894 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5895 PseudoSourceValue::getConstantPool(), 0, false, 5896 Alignment); 5897 5898 } 5899 } 5900 5901 // Check to see if we can perform the "gzip trick", transforming 5902 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5903 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5904 N0.getValueType().isInteger() && 5905 N2.getValueType().isInteger() && 5906 (N1C->isNullValue() || // (a < 0) ? b : 0 5907 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5908 EVT XType = N0.getValueType(); 5909 EVT AType = N2.getValueType(); 5910 if (XType.bitsGE(AType)) { 5911 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5912 // single-bit constant. 5913 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5914 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5915 ShCtV = XType.getSizeInBits()-ShCtV-1; 5916 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5917 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5918 XType, N0, ShCt); 5919 AddToWorkList(Shift.getNode()); 5920 5921 if (XType.bitsGT(AType)) { 5922 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5923 AddToWorkList(Shift.getNode()); 5924 } 5925 5926 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5927 } 5928 5929 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5930 XType, N0, 5931 DAG.getConstant(XType.getSizeInBits()-1, 5932 getShiftAmountTy())); 5933 AddToWorkList(Shift.getNode()); 5934 5935 if (XType.bitsGT(AType)) { 5936 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5937 AddToWorkList(Shift.getNode()); 5938 } 5939 5940 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5941 } 5942 } 5943 5944 // fold select C, 16, 0 -> shl C, 4 5945 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5946 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5947 5948 // If the caller doesn't want us to simplify this into a zext of a compare, 5949 // don't do it. 5950 if (NotExtCompare && N2C->getAPIntValue() == 1) 5951 return SDValue(); 5952 5953 // Get a SetCC of the condition 5954 // FIXME: Should probably make sure that setcc is legal if we ever have a 5955 // target where it isn't. 5956 SDValue Temp, SCC; 5957 // cast from setcc result type to select result type 5958 if (LegalTypes) { 5959 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5960 N0, N1, CC); 5961 if (N2.getValueType().bitsLT(SCC.getValueType())) 5962 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5963 else 5964 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5965 N2.getValueType(), SCC); 5966 } else { 5967 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5968 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5969 N2.getValueType(), SCC); 5970 } 5971 5972 AddToWorkList(SCC.getNode()); 5973 AddToWorkList(Temp.getNode()); 5974 5975 if (N2C->getAPIntValue() == 1) 5976 return Temp; 5977 5978 // shl setcc result by log2 n2c 5979 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5980 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5981 getShiftAmountTy())); 5982 } 5983 5984 // Check to see if this is the equivalent of setcc 5985 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5986 // otherwise, go ahead with the folds. 5987 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5988 EVT XType = N0.getValueType(); 5989 if (!LegalOperations || 5990 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5991 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5992 if (Res.getValueType() != VT) 5993 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5994 return Res; 5995 } 5996 5997 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5998 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5999 (!LegalOperations || 6000 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6001 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6002 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6003 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6004 getShiftAmountTy())); 6005 } 6006 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6007 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6008 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6009 XType, DAG.getConstant(0, XType), N0); 6010 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6011 return DAG.getNode(ISD::SRL, DL, XType, 6012 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6013 DAG.getConstant(XType.getSizeInBits()-1, 6014 getShiftAmountTy())); 6015 } 6016 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6017 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6018 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6019 DAG.getConstant(XType.getSizeInBits()-1, 6020 getShiftAmountTy())); 6021 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6022 } 6023 } 6024 6025 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6026 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6027 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6028 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6029 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6030 EVT XType = N0.getValueType(); 6031 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6032 DAG.getConstant(XType.getSizeInBits()-1, 6033 getShiftAmountTy())); 6034 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6035 N0, Shift); 6036 AddToWorkList(Shift.getNode()); 6037 AddToWorkList(Add.getNode()); 6038 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6039 } 6040 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6041 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6042 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6043 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6044 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6045 EVT XType = N0.getValueType(); 6046 if (SubC->isNullValue() && XType.isInteger()) { 6047 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6048 N0, 6049 DAG.getConstant(XType.getSizeInBits()-1, 6050 getShiftAmountTy())); 6051 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6052 XType, N0, Shift); 6053 AddToWorkList(Shift.getNode()); 6054 AddToWorkList(Add.getNode()); 6055 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6056 } 6057 } 6058 } 6059 6060 return SDValue(); 6061} 6062 6063/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6064SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6065 SDValue N1, ISD::CondCode Cond, 6066 DebugLoc DL, bool foldBooleans) { 6067 TargetLowering::DAGCombinerInfo 6068 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6069 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6070} 6071 6072/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6073/// return a DAG expression to select that will generate the same value by 6074/// multiplying by a magic number. See: 6075/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6076SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6077 std::vector<SDNode*> Built; 6078 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6079 6080 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6081 ii != ee; ++ii) 6082 AddToWorkList(*ii); 6083 return S; 6084} 6085 6086/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6087/// return a DAG expression to select that will generate the same value by 6088/// multiplying by a magic number. See: 6089/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6090SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6091 std::vector<SDNode*> Built; 6092 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6093 6094 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6095 ii != ee; ++ii) 6096 AddToWorkList(*ii); 6097 return S; 6098} 6099 6100/// FindBaseOffset - Return true if base is a frame index, which is known not 6101// to alias with anything but itself. Provides base object and offset as results. 6102static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6103 GlobalValue *&GV, void *&CV) { 6104 // Assume it is a primitive operation. 6105 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6106 6107 // If it's an adding a simple constant then integrate the offset. 6108 if (Base.getOpcode() == ISD::ADD) { 6109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6110 Base = Base.getOperand(0); 6111 Offset += C->getZExtValue(); 6112 } 6113 } 6114 6115 // Return the underlying GlobalValue, and update the Offset. Return false 6116 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6117 // by multiple nodes with different offsets. 6118 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6119 GV = G->getGlobal(); 6120 Offset += G->getOffset(); 6121 return false; 6122 } 6123 6124 // Return the underlying Constant value, and update the Offset. Return false 6125 // for ConstantSDNodes since the same constant pool entry may be represented 6126 // by multiple nodes with different offsets. 6127 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6128 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6129 : (void *)C->getConstVal(); 6130 Offset += C->getOffset(); 6131 return false; 6132 } 6133 // If it's any of the following then it can't alias with anything but itself. 6134 return isa<FrameIndexSDNode>(Base); 6135} 6136 6137/// isAlias - Return true if there is any possibility that the two addresses 6138/// overlap. 6139bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6140 const Value *SrcValue1, int SrcValueOffset1, 6141 unsigned SrcValueAlign1, 6142 SDValue Ptr2, int64_t Size2, 6143 const Value *SrcValue2, int SrcValueOffset2, 6144 unsigned SrcValueAlign2) const { 6145 // If they are the same then they must be aliases. 6146 if (Ptr1 == Ptr2) return true; 6147 6148 // Gather base node and offset information. 6149 SDValue Base1, Base2; 6150 int64_t Offset1, Offset2; 6151 GlobalValue *GV1, *GV2; 6152 void *CV1, *CV2; 6153 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6154 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6155 6156 // If they have a same base address then check to see if they overlap. 6157 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6158 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6159 6160 // If we know what the bases are, and they aren't identical, then we know they 6161 // cannot alias. 6162 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6163 return false; 6164 6165 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6166 // compared to the size and offset of the access, we may be able to prove they 6167 // do not alias. This check is conservative for now to catch cases created by 6168 // splitting vector types. 6169 if ((SrcValueAlign1 == SrcValueAlign2) && 6170 (SrcValueOffset1 != SrcValueOffset2) && 6171 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6172 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6173 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6174 6175 // There is no overlap between these relatively aligned accesses of similar 6176 // size, return no alias. 6177 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6178 return false; 6179 } 6180 6181 if (CombinerGlobalAA) { 6182 // Use alias analysis information. 6183 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6184 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6185 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6186 AliasAnalysis::AliasResult AAResult = 6187 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6188 if (AAResult == AliasAnalysis::NoAlias) 6189 return false; 6190 } 6191 6192 // Otherwise we have to assume they alias. 6193 return true; 6194} 6195 6196/// FindAliasInfo - Extracts the relevant alias information from the memory 6197/// node. Returns true if the operand was a load. 6198bool DAGCombiner::FindAliasInfo(SDNode *N, 6199 SDValue &Ptr, int64_t &Size, 6200 const Value *&SrcValue, 6201 int &SrcValueOffset, 6202 unsigned &SrcValueAlign) const { 6203 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6204 Ptr = LD->getBasePtr(); 6205 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6206 SrcValue = LD->getSrcValue(); 6207 SrcValueOffset = LD->getSrcValueOffset(); 6208 SrcValueAlign = LD->getOriginalAlignment(); 6209 return true; 6210 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6211 Ptr = ST->getBasePtr(); 6212 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6213 SrcValue = ST->getSrcValue(); 6214 SrcValueOffset = ST->getSrcValueOffset(); 6215 SrcValueAlign = ST->getOriginalAlignment(); 6216 } else { 6217 llvm_unreachable("FindAliasInfo expected a memory operand"); 6218 } 6219 6220 return false; 6221} 6222 6223/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6224/// looking for aliasing nodes and adding them to the Aliases vector. 6225void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6226 SmallVector<SDValue, 8> &Aliases) { 6227 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6228 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6229 6230 // Get alias information for node. 6231 SDValue Ptr; 6232 int64_t Size; 6233 const Value *SrcValue; 6234 int SrcValueOffset; 6235 unsigned SrcValueAlign; 6236 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6237 SrcValueAlign); 6238 6239 // Starting off. 6240 Chains.push_back(OriginalChain); 6241 unsigned Depth = 0; 6242 6243 // Look at each chain and determine if it is an alias. If so, add it to the 6244 // aliases list. If not, then continue up the chain looking for the next 6245 // candidate. 6246 while (!Chains.empty()) { 6247 SDValue Chain = Chains.back(); 6248 Chains.pop_back(); 6249 6250 // For TokenFactor nodes, look at each operand and only continue up the 6251 // chain until we find two aliases. If we've seen two aliases, assume we'll 6252 // find more and revert to original chain since the xform is unlikely to be 6253 // profitable. 6254 // 6255 // FIXME: The depth check could be made to return the last non-aliasing 6256 // chain we found before we hit a tokenfactor rather than the original 6257 // chain. 6258 if (Depth > 6 || Aliases.size() == 2) { 6259 Aliases.clear(); 6260 Aliases.push_back(OriginalChain); 6261 break; 6262 } 6263 6264 // Don't bother if we've been before. 6265 if (!Visited.insert(Chain.getNode())) 6266 continue; 6267 6268 switch (Chain.getOpcode()) { 6269 case ISD::EntryToken: 6270 // Entry token is ideal chain operand, but handled in FindBetterChain. 6271 break; 6272 6273 case ISD::LOAD: 6274 case ISD::STORE: { 6275 // Get alias information for Chain. 6276 SDValue OpPtr; 6277 int64_t OpSize; 6278 const Value *OpSrcValue; 6279 int OpSrcValueOffset; 6280 unsigned OpSrcValueAlign; 6281 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6282 OpSrcValue, OpSrcValueOffset, 6283 OpSrcValueAlign); 6284 6285 // If chain is alias then stop here. 6286 if (!(IsLoad && IsOpLoad) && 6287 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6288 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6289 OpSrcValueAlign)) { 6290 Aliases.push_back(Chain); 6291 } else { 6292 // Look further up the chain. 6293 Chains.push_back(Chain.getOperand(0)); 6294 ++Depth; 6295 } 6296 break; 6297 } 6298 6299 case ISD::TokenFactor: 6300 // We have to check each of the operands of the token factor for "small" 6301 // token factors, so we queue them up. Adding the operands to the queue 6302 // (stack) in reverse order maintains the original order and increases the 6303 // likelihood that getNode will find a matching token factor (CSE.) 6304 if (Chain.getNumOperands() > 16) { 6305 Aliases.push_back(Chain); 6306 break; 6307 } 6308 for (unsigned n = Chain.getNumOperands(); n;) 6309 Chains.push_back(Chain.getOperand(--n)); 6310 ++Depth; 6311 break; 6312 6313 default: 6314 // For all other instructions we will just have to take what we can get. 6315 Aliases.push_back(Chain); 6316 break; 6317 } 6318 } 6319} 6320 6321/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6322/// for a better chain (aliasing node.) 6323SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6324 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6325 6326 // Accumulate all the aliases to this node. 6327 GatherAllAliases(N, OldChain, Aliases); 6328 6329 if (Aliases.size() == 0) { 6330 // If no operands then chain to entry token. 6331 return DAG.getEntryNode(); 6332 } else if (Aliases.size() == 1) { 6333 // If a single operand then chain to it. We don't need to revisit it. 6334 return Aliases[0]; 6335 } 6336 6337 // Construct a custom tailored token factor. 6338 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6339 &Aliases[0], Aliases.size()); 6340} 6341 6342// SelectionDAG::Combine - This is the entry point for the file. 6343// 6344void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6345 CodeGenOpt::Level OptLevel) { 6346 /// run - This is the main entry point to this class. 6347 /// 6348 DAGCombiner(*this, AA, OptLevel).Run(Level); 6349} 6350