DAGCombiner.cpp revision de1631bc85380857b11240eb22ddff2bfa5b7104
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/CodeGen/SelectionDAG.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/Target/TargetData.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/SmallPtrSet.h" 39#include "llvm/ADT/Statistic.h" 40#include "llvm/Support/Alignment.h" 41#include "llvm/Support/Compiler.h" 42#include "llvm/Support/CommandLine.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/MathExtras.h" 45#include <algorithm> 46using namespace llvm; 47 48STATISTIC(NodesCombined , "Number of dag nodes combined"); 49STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 50STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 51 52namespace { 53#ifndef NDEBUG 54 static cl::opt<bool> 55 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the first " 57 "dag combine pass")); 58 static cl::opt<bool> 59 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 60 cl::desc("Pop up a window to show dags before the second " 61 "dag combine pass")); 62#else 63 static const bool ViewDAGCombine1 = false; 64 static const bool ViewDAGCombine2 = false; 65#endif 66 67 static cl::opt<bool> 68 CombinerAA("combiner-alias-analysis", cl::Hidden, 69 cl::desc("Turn on alias analysis during testing")); 70 71 static cl::opt<bool> 72 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 73 cl::desc("Include global information in alias analysis")); 74 75//------------------------------ DAGCombiner ---------------------------------// 76 77 class VISIBILITY_HIDDEN DAGCombiner { 78 SelectionDAG &DAG; 79 TargetLowering &TLI; 80 bool AfterLegalize; 81 82 // Worklist of all of the nodes that need to be simplified. 83 std::vector<SDNode*> WorkList; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// removeFromWorkList - remove all instances of N from the worklist. 99 /// 100 void removeFromWorkList(SDNode *N) { 101 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 102 WorkList.end()); 103 } 104 105 /// visit - call the node-specific routine that knows how to fold each 106 /// particular type of node. 107 SDOperand visit(SDNode *N); 108 109 public: 110 /// AddToWorkList - Add to the work list making sure it's instance is at the 111 /// the back (next to be processed.) 112 void AddToWorkList(SDNode *N) { 113 removeFromWorkList(N); 114 WorkList.push_back(N); 115 } 116 117 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 118 bool AddTo = true) { 119 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 120 ++NodesCombined; 121 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 122 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 123 DOUT << " and " << NumTo-1 << " other values\n"; 124 std::vector<SDNode*> NowDead; 125 DAG.ReplaceAllUsesWith(N, To, &NowDead); 126 127 if (AddTo) { 128 // Push the new nodes and any users onto the worklist 129 for (unsigned i = 0, e = NumTo; i != e; ++i) { 130 AddToWorkList(To[i].Val); 131 AddUsersToWorkList(To[i].Val); 132 } 133 } 134 135 // Nodes can be reintroduced into the worklist. Make sure we do not 136 // process a node that has been replaced. 137 removeFromWorkList(N); 138 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 139 removeFromWorkList(NowDead[i]); 140 141 // Finally, since the node is now dead, remove it from the graph. 142 DAG.DeleteNode(N); 143 return SDOperand(N, 0); 144 } 145 146 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 147 return CombineTo(N, &Res, 1, AddTo); 148 } 149 150 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 151 bool AddTo = true) { 152 SDOperand To[] = { Res0, Res1 }; 153 return CombineTo(N, To, 2, AddTo); 154 } 155 private: 156 157 /// SimplifyDemandedBits - Check the specified integer node value to see if 158 /// it can be simplified or if things it uses can be simplified by bit 159 /// propagation. If so, return true. 160 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL) { 161 TargetLowering::TargetLoweringOpt TLO(DAG); 162 uint64_t KnownZero, KnownOne; 163 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 164 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 165 return false; 166 167 // Revisit the node. 168 AddToWorkList(Op.Val); 169 170 // Replace the old value with the new one. 171 ++NodesCombined; 172 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 173 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 174 DOUT << '\n'; 175 176 std::vector<SDNode*> NowDead; 177 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &NowDead); 178 179 // Push the new node and any (possibly new) users onto the worklist. 180 AddToWorkList(TLO.New.Val); 181 AddUsersToWorkList(TLO.New.Val); 182 183 // Nodes can end up on the worklist more than once. Make sure we do 184 // not process a node that has been replaced. 185 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 186 removeFromWorkList(NowDead[i]); 187 188 // Finally, if the node is now dead, remove it from the graph. The node 189 // may not be dead if the replacement process recursively simplified to 190 // something else needing this node. 191 if (TLO.Old.Val->use_empty()) { 192 removeFromWorkList(TLO.Old.Val); 193 194 // If the operands of this node are only used by the node, they will now 195 // be dead. Make sure to visit them first to delete dead nodes early. 196 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 197 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 198 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 199 200 DAG.DeleteNode(TLO.Old.Val); 201 } 202 return true; 203 } 204 205 bool CombineToPreIndexedLoadStore(SDNode *N); 206 bool CombineToPostIndexedLoadStore(SDNode *N); 207 208 209 /// combine - call the node-specific routine that knows how to fold each 210 /// particular type of node. If that doesn't do anything, try the 211 /// target-specific DAG combines. 212 SDOperand combine(SDNode *N); 213 214 // Visitation implementation - Implement dag node combining for different 215 // node types. The semantics are as follows: 216 // Return Value: 217 // SDOperand.Val == 0 - No change was made 218 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 219 // otherwise - N should be replaced by the returned Operand. 220 // 221 SDOperand visitTokenFactor(SDNode *N); 222 SDOperand visitADD(SDNode *N); 223 SDOperand visitSUB(SDNode *N); 224 SDOperand visitADDC(SDNode *N); 225 SDOperand visitADDE(SDNode *N); 226 SDOperand visitMUL(SDNode *N); 227 SDOperand visitSDIV(SDNode *N); 228 SDOperand visitUDIV(SDNode *N); 229 SDOperand visitSREM(SDNode *N); 230 SDOperand visitUREM(SDNode *N); 231 SDOperand visitMULHU(SDNode *N); 232 SDOperand visitMULHS(SDNode *N); 233 SDOperand visitSMUL_LOHI(SDNode *N); 234 SDOperand visitUMUL_LOHI(SDNode *N); 235 SDOperand visitSDIVREM(SDNode *N); 236 SDOperand visitUDIVREM(SDNode *N); 237 SDOperand visitAND(SDNode *N); 238 SDOperand visitOR(SDNode *N); 239 SDOperand visitXOR(SDNode *N); 240 SDOperand SimplifyVBinOp(SDNode *N); 241 SDOperand visitSHL(SDNode *N); 242 SDOperand visitSRA(SDNode *N); 243 SDOperand visitSRL(SDNode *N); 244 SDOperand visitCTLZ(SDNode *N); 245 SDOperand visitCTTZ(SDNode *N); 246 SDOperand visitCTPOP(SDNode *N); 247 SDOperand visitSELECT(SDNode *N); 248 SDOperand visitSELECT_CC(SDNode *N); 249 SDOperand visitSETCC(SDNode *N); 250 SDOperand visitSIGN_EXTEND(SDNode *N); 251 SDOperand visitZERO_EXTEND(SDNode *N); 252 SDOperand visitANY_EXTEND(SDNode *N); 253 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 254 SDOperand visitTRUNCATE(SDNode *N); 255 SDOperand visitBIT_CONVERT(SDNode *N); 256 SDOperand visitFADD(SDNode *N); 257 SDOperand visitFSUB(SDNode *N); 258 SDOperand visitFMUL(SDNode *N); 259 SDOperand visitFDIV(SDNode *N); 260 SDOperand visitFREM(SDNode *N); 261 SDOperand visitFCOPYSIGN(SDNode *N); 262 SDOperand visitSINT_TO_FP(SDNode *N); 263 SDOperand visitUINT_TO_FP(SDNode *N); 264 SDOperand visitFP_TO_SINT(SDNode *N); 265 SDOperand visitFP_TO_UINT(SDNode *N); 266 SDOperand visitFP_ROUND(SDNode *N); 267 SDOperand visitFP_ROUND_INREG(SDNode *N); 268 SDOperand visitFP_EXTEND(SDNode *N); 269 SDOperand visitFNEG(SDNode *N); 270 SDOperand visitFABS(SDNode *N); 271 SDOperand visitBRCOND(SDNode *N); 272 SDOperand visitBR_CC(SDNode *N); 273 SDOperand visitLOAD(SDNode *N); 274 SDOperand visitSTORE(SDNode *N); 275 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 276 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 277 SDOperand visitBUILD_VECTOR(SDNode *N); 278 SDOperand visitCONCAT_VECTORS(SDNode *N); 279 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 280 281 SDOperand XformToShuffleWithZero(SDNode *N); 282 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 283 284 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 285 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 286 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 287 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 288 SDOperand N3, ISD::CondCode CC, 289 bool NotExtCompare = false); 290 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 291 ISD::CondCode Cond, bool foldBooleans = true); 292 bool SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); 293 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 294 SDOperand BuildSDIV(SDNode *N); 295 SDOperand BuildUDIV(SDNode *N); 296 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 297 SDOperand ReduceLoadWidth(SDNode *N); 298 299 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 300 301 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 302 /// looking for aliasing nodes and adding them to the Aliases vector. 303 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 304 SmallVector<SDOperand, 8> &Aliases); 305 306 /// isAlias - Return true if there is any possibility that the two addresses 307 /// overlap. 308 bool isAlias(SDOperand Ptr1, int64_t Size1, 309 const Value *SrcValue1, int SrcValueOffset1, 310 SDOperand Ptr2, int64_t Size2, 311 const Value *SrcValue2, int SrcValueOffset2); 312 313 /// FindAliasInfo - Extracts the relevant alias information from the memory 314 /// node. Returns true if the operand was a load. 315 bool FindAliasInfo(SDNode *N, 316 SDOperand &Ptr, int64_t &Size, 317 const Value *&SrcValue, int &SrcValueOffset); 318 319 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 320 /// looking for a better chain (aliasing node.) 321 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 322 323public: 324 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 325 : DAG(D), 326 TLI(D.getTargetLoweringInfo()), 327 AfterLegalize(false), 328 AA(A) {} 329 330 /// Run - runs the dag combiner on all nodes in the work list 331 void Run(bool RunningAfterLegalize); 332 }; 333} 334 335//===----------------------------------------------------------------------===// 336// TargetLowering::DAGCombinerInfo implementation 337//===----------------------------------------------------------------------===// 338 339void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 340 ((DAGCombiner*)DC)->AddToWorkList(N); 341} 342 343SDOperand TargetLowering::DAGCombinerInfo:: 344CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 345 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 346} 347 348SDOperand TargetLowering::DAGCombinerInfo:: 349CombineTo(SDNode *N, SDOperand Res) { 350 return ((DAGCombiner*)DC)->CombineTo(N, Res); 351} 352 353 354SDOperand TargetLowering::DAGCombinerInfo:: 355CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 356 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 357} 358 359 360//===----------------------------------------------------------------------===// 361// Helper Functions 362//===----------------------------------------------------------------------===// 363 364/// isNegatibleForFree - Return 1 if we can compute the negated form of the 365/// specified expression for the same cost as the expression itself, or 2 if we 366/// can compute the negated form more cheaply than the expression itself. 367static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 368 // No compile time optimizations on this type. 369 if (Op.getValueType() == MVT::ppcf128) 370 return 0; 371 372 // fneg is removable even if it has multiple uses. 373 if (Op.getOpcode() == ISD::FNEG) return 2; 374 375 // Don't allow anything with multiple uses. 376 if (!Op.hasOneUse()) return 0; 377 378 // Don't recurse exponentially. 379 if (Depth > 6) return 0; 380 381 switch (Op.getOpcode()) { 382 default: return false; 383 case ISD::ConstantFP: 384 return 1; 385 case ISD::FADD: 386 // FIXME: determine better conditions for this xform. 387 if (!UnsafeFPMath) return 0; 388 389 // -(A+B) -> -A - B 390 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 391 return V; 392 // -(A+B) -> -B - A 393 return isNegatibleForFree(Op.getOperand(1), Depth+1); 394 case ISD::FSUB: 395 // We can't turn -(A-B) into B-A when we honor signed zeros. 396 if (!UnsafeFPMath) return 0; 397 398 // -(A-B) -> B-A 399 return 1; 400 401 case ISD::FMUL: 402 case ISD::FDIV: 403 if (HonorSignDependentRoundingFPMath()) return 0; 404 405 // -(X*Y) -> (-X * Y) or (X*-Y) 406 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 407 return V; 408 409 return isNegatibleForFree(Op.getOperand(1), Depth+1); 410 411 case ISD::FP_EXTEND: 412 case ISD::FP_ROUND: 413 case ISD::FSIN: 414 return isNegatibleForFree(Op.getOperand(0), Depth+1); 415 } 416} 417 418/// GetNegatedExpression - If isNegatibleForFree returns true, this function 419/// returns the newly negated expression. 420static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 421 unsigned Depth = 0) { 422 // fneg is removable even if it has multiple uses. 423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 424 425 // Don't allow anything with multiple uses. 426 assert(Op.hasOneUse() && "Unknown reuse!"); 427 428 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 429 switch (Op.getOpcode()) { 430 default: assert(0 && "Unknown code"); 431 case ISD::ConstantFP: { 432 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 433 V.changeSign(); 434 return DAG.getConstantFP(V, Op.getValueType()); 435 } 436 case ISD::FADD: 437 // FIXME: determine better conditions for this xform. 438 assert(UnsafeFPMath); 439 440 // -(A+B) -> -A - B 441 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 442 return DAG.getNode(ISD::FSUB, Op.getValueType(), 443 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 444 Op.getOperand(1)); 445 // -(A+B) -> -B - A 446 return DAG.getNode(ISD::FSUB, Op.getValueType(), 447 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 448 Op.getOperand(0)); 449 case ISD::FSUB: 450 // We can't turn -(A-B) into B-A when we honor signed zeros. 451 assert(UnsafeFPMath); 452 453 // -(0-B) -> B 454 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 455 if (N0CFP->getValueAPF().isZero()) 456 return Op.getOperand(1); 457 458 // -(A-B) -> B-A 459 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 460 Op.getOperand(0)); 461 462 case ISD::FMUL: 463 case ISD::FDIV: 464 assert(!HonorSignDependentRoundingFPMath()); 465 466 // -(X*Y) -> -X * Y 467 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 468 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 469 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 470 Op.getOperand(1)); 471 472 // -(X*Y) -> X * -Y 473 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 474 Op.getOperand(0), 475 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 476 477 case ISD::FP_EXTEND: 478 case ISD::FP_ROUND: 479 case ISD::FSIN: 480 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 482 } 483} 484 485 486// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 487// that selects between the values 1 and 0, making it equivalent to a setcc. 488// Also, set the incoming LHS, RHS, and CC references to the appropriate 489// nodes based on the type of node we are checking. This simplifies life a 490// bit for the callers. 491static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 492 SDOperand &CC) { 493 if (N.getOpcode() == ISD::SETCC) { 494 LHS = N.getOperand(0); 495 RHS = N.getOperand(1); 496 CC = N.getOperand(2); 497 return true; 498 } 499 if (N.getOpcode() == ISD::SELECT_CC && 500 N.getOperand(2).getOpcode() == ISD::Constant && 501 N.getOperand(3).getOpcode() == ISD::Constant && 502 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 503 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 504 LHS = N.getOperand(0); 505 RHS = N.getOperand(1); 506 CC = N.getOperand(4); 507 return true; 508 } 509 return false; 510} 511 512// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 513// one use. If this is true, it allows the users to invert the operation for 514// free when it is profitable to do so. 515static bool isOneUseSetCC(SDOperand N) { 516 SDOperand N0, N1, N2; 517 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 518 return true; 519 return false; 520} 521 522SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 523 MVT::ValueType VT = N0.getValueType(); 524 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 525 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 526 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 527 if (isa<ConstantSDNode>(N1)) { 528 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 529 AddToWorkList(OpNode.Val); 530 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 531 } else if (N0.hasOneUse()) { 532 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 533 AddToWorkList(OpNode.Val); 534 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 535 } 536 } 537 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 538 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 539 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 540 if (isa<ConstantSDNode>(N0)) { 541 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 542 AddToWorkList(OpNode.Val); 543 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 544 } else if (N1.hasOneUse()) { 545 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 546 AddToWorkList(OpNode.Val); 547 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 548 } 549 } 550 return SDOperand(); 551} 552 553//===----------------------------------------------------------------------===// 554// Main DAG Combiner implementation 555//===----------------------------------------------------------------------===// 556 557void DAGCombiner::Run(bool RunningAfterLegalize) { 558 // set the instance variable, so that the various visit routines may use it. 559 AfterLegalize = RunningAfterLegalize; 560 561 // Add all the dag nodes to the worklist. 562 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 563 E = DAG.allnodes_end(); I != E; ++I) 564 WorkList.push_back(I); 565 566 // Create a dummy node (which is not added to allnodes), that adds a reference 567 // to the root node, preventing it from being deleted, and tracking any 568 // changes of the root. 569 HandleSDNode Dummy(DAG.getRoot()); 570 571 // The root of the dag may dangle to deleted nodes until the dag combiner is 572 // done. Set it to null to avoid confusion. 573 DAG.setRoot(SDOperand()); 574 575 // while the worklist isn't empty, inspect the node on the end of it and 576 // try and combine it. 577 while (!WorkList.empty()) { 578 SDNode *N = WorkList.back(); 579 WorkList.pop_back(); 580 581 // If N has no uses, it is dead. Make sure to revisit all N's operands once 582 // N is deleted from the DAG, since they too may now be dead or may have a 583 // reduced number of uses, allowing other xforms. 584 if (N->use_empty() && N != &Dummy) { 585 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 586 AddToWorkList(N->getOperand(i).Val); 587 588 DAG.DeleteNode(N); 589 continue; 590 } 591 592 SDOperand RV = combine(N); 593 594 if (RV.Val) { 595 ++NodesCombined; 596 // If we get back the same node we passed in, rather than a new node or 597 // zero, we know that the node must have defined multiple values and 598 // CombineTo was used. Since CombineTo takes care of the worklist 599 // mechanics for us, we have no work to do in this case. 600 if (RV.Val != N) { 601 assert(N->getOpcode() != ISD::DELETED_NODE && 602 RV.Val->getOpcode() != ISD::DELETED_NODE && 603 "Node was deleted but visit returned new node!"); 604 605 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 606 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 607 DOUT << '\n'; 608 std::vector<SDNode*> NowDead; 609 if (N->getNumValues() == RV.Val->getNumValues()) 610 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 611 else { 612 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 613 SDOperand OpV = RV; 614 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 615 } 616 617 // Push the new node and any users onto the worklist 618 AddToWorkList(RV.Val); 619 AddUsersToWorkList(RV.Val); 620 621 // Nodes can be reintroduced into the worklist. Make sure we do not 622 // process a node that has been replaced. 623 removeFromWorkList(N); 624 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 625 removeFromWorkList(NowDead[i]); 626 627 // Finally, since the node is now dead, remove it from the graph. 628 DAG.DeleteNode(N); 629 } 630 } 631 } 632 633 // If the root changed (e.g. it was a dead load, update the root). 634 DAG.setRoot(Dummy.getValue()); 635} 636 637SDOperand DAGCombiner::visit(SDNode *N) { 638 switch(N->getOpcode()) { 639 default: break; 640 case ISD::TokenFactor: return visitTokenFactor(N); 641 case ISD::ADD: return visitADD(N); 642 case ISD::SUB: return visitSUB(N); 643 case ISD::ADDC: return visitADDC(N); 644 case ISD::ADDE: return visitADDE(N); 645 case ISD::MUL: return visitMUL(N); 646 case ISD::SDIV: return visitSDIV(N); 647 case ISD::UDIV: return visitUDIV(N); 648 case ISD::SREM: return visitSREM(N); 649 case ISD::UREM: return visitUREM(N); 650 case ISD::MULHU: return visitMULHU(N); 651 case ISD::MULHS: return visitMULHS(N); 652 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 653 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 654 case ISD::SDIVREM: return visitSDIVREM(N); 655 case ISD::UDIVREM: return visitUDIVREM(N); 656 case ISD::AND: return visitAND(N); 657 case ISD::OR: return visitOR(N); 658 case ISD::XOR: return visitXOR(N); 659 case ISD::SHL: return visitSHL(N); 660 case ISD::SRA: return visitSRA(N); 661 case ISD::SRL: return visitSRL(N); 662 case ISD::CTLZ: return visitCTLZ(N); 663 case ISD::CTTZ: return visitCTTZ(N); 664 case ISD::CTPOP: return visitCTPOP(N); 665 case ISD::SELECT: return visitSELECT(N); 666 case ISD::SELECT_CC: return visitSELECT_CC(N); 667 case ISD::SETCC: return visitSETCC(N); 668 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 669 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 670 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 671 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 672 case ISD::TRUNCATE: return visitTRUNCATE(N); 673 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 674 case ISD::FADD: return visitFADD(N); 675 case ISD::FSUB: return visitFSUB(N); 676 case ISD::FMUL: return visitFMUL(N); 677 case ISD::FDIV: return visitFDIV(N); 678 case ISD::FREM: return visitFREM(N); 679 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 680 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 681 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 682 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 683 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 684 case ISD::FP_ROUND: return visitFP_ROUND(N); 685 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 686 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 687 case ISD::FNEG: return visitFNEG(N); 688 case ISD::FABS: return visitFABS(N); 689 case ISD::BRCOND: return visitBRCOND(N); 690 case ISD::BR_CC: return visitBR_CC(N); 691 case ISD::LOAD: return visitLOAD(N); 692 case ISD::STORE: return visitSTORE(N); 693 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 694 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 695 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 696 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 697 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 698 } 699 return SDOperand(); 700} 701 702SDOperand DAGCombiner::combine(SDNode *N) { 703 704 SDOperand RV = visit(N); 705 706 // If nothing happened, try a target-specific DAG combine. 707 if (RV.Val == 0) { 708 assert(N->getOpcode() != ISD::DELETED_NODE && 709 "Node was deleted but visit returned NULL!"); 710 711 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 712 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 713 714 // Expose the DAG combiner to the target combiner impls. 715 TargetLowering::DAGCombinerInfo 716 DagCombineInfo(DAG, !AfterLegalize, false, this); 717 718 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 719 } 720 } 721 722 return RV; 723} 724 725/// getInputChainForNode - Given a node, return its input chain if it has one, 726/// otherwise return a null sd operand. 727static SDOperand getInputChainForNode(SDNode *N) { 728 if (unsigned NumOps = N->getNumOperands()) { 729 if (N->getOperand(0).getValueType() == MVT::Other) 730 return N->getOperand(0); 731 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 732 return N->getOperand(NumOps-1); 733 for (unsigned i = 1; i < NumOps-1; ++i) 734 if (N->getOperand(i).getValueType() == MVT::Other) 735 return N->getOperand(i); 736 } 737 return SDOperand(0, 0); 738} 739 740SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 741 // If N has two operands, where one has an input chain equal to the other, 742 // the 'other' chain is redundant. 743 if (N->getNumOperands() == 2) { 744 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 745 return N->getOperand(0); 746 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 747 return N->getOperand(1); 748 } 749 750 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 751 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 752 SmallPtrSet<SDNode*, 16> SeenOps; 753 bool Changed = false; // If we should replace this token factor. 754 755 // Start out with this token factor. 756 TFs.push_back(N); 757 758 // Iterate through token factors. The TFs grows when new token factors are 759 // encountered. 760 for (unsigned i = 0; i < TFs.size(); ++i) { 761 SDNode *TF = TFs[i]; 762 763 // Check each of the operands. 764 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 765 SDOperand Op = TF->getOperand(i); 766 767 switch (Op.getOpcode()) { 768 case ISD::EntryToken: 769 // Entry tokens don't need to be added to the list. They are 770 // rededundant. 771 Changed = true; 772 break; 773 774 case ISD::TokenFactor: 775 if ((CombinerAA || Op.hasOneUse()) && 776 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 777 // Queue up for processing. 778 TFs.push_back(Op.Val); 779 // Clean up in case the token factor is removed. 780 AddToWorkList(Op.Val); 781 Changed = true; 782 break; 783 } 784 // Fall thru 785 786 default: 787 // Only add if it isn't already in the list. 788 if (SeenOps.insert(Op.Val)) 789 Ops.push_back(Op); 790 else 791 Changed = true; 792 break; 793 } 794 } 795 } 796 797 SDOperand Result; 798 799 // If we've change things around then replace token factor. 800 if (Changed) { 801 if (Ops.size() == 0) { 802 // The entry token is the only possible outcome. 803 Result = DAG.getEntryNode(); 804 } else { 805 // New and improved token factor. 806 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 807 } 808 809 // Don't add users to work list. 810 return CombineTo(N, Result, false); 811 } 812 813 return Result; 814} 815 816static 817SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 818 MVT::ValueType VT = N0.getValueType(); 819 SDOperand N00 = N0.getOperand(0); 820 SDOperand N01 = N0.getOperand(1); 821 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 822 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 823 isa<ConstantSDNode>(N00.getOperand(1))) { 824 N0 = DAG.getNode(ISD::ADD, VT, 825 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 826 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 827 return DAG.getNode(ISD::ADD, VT, N0, N1); 828 } 829 return SDOperand(); 830} 831 832static 833SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 834 SelectionDAG &DAG) { 835 MVT::ValueType VT = N->getValueType(0); 836 unsigned Opc = N->getOpcode(); 837 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 838 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 839 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 840 ISD::CondCode CC = ISD::SETCC_INVALID; 841 if (isSlctCC) 842 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 843 else { 844 SDOperand CCOp = Slct.getOperand(0); 845 if (CCOp.getOpcode() == ISD::SETCC) 846 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 847 } 848 849 bool DoXform = false; 850 bool InvCC = false; 851 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 852 "Bad input!"); 853 if (LHS.getOpcode() == ISD::Constant && 854 cast<ConstantSDNode>(LHS)->isNullValue()) 855 DoXform = true; 856 else if (CC != ISD::SETCC_INVALID && 857 RHS.getOpcode() == ISD::Constant && 858 cast<ConstantSDNode>(RHS)->isNullValue()) { 859 std::swap(LHS, RHS); 860 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType() 861 : Slct.getOperand(0).getOperand(0).getValueType()); 862 CC = ISD::getSetCCInverse(CC, isInt); 863 DoXform = true; 864 InvCC = true; 865 } 866 867 if (DoXform) { 868 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 869 if (isSlctCC) 870 return DAG.getSelectCC(OtherOp, Result, 871 Slct.getOperand(0), Slct.getOperand(1), CC); 872 SDOperand CCOp = Slct.getOperand(0); 873 if (InvCC) 874 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 875 CCOp.getOperand(1), CC); 876 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 877 } 878 return SDOperand(); 879} 880 881SDOperand DAGCombiner::visitADD(SDNode *N) { 882 SDOperand N0 = N->getOperand(0); 883 SDOperand N1 = N->getOperand(1); 884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 886 MVT::ValueType VT = N0.getValueType(); 887 888 // fold vector ops 889 if (MVT::isVector(VT)) { 890 SDOperand FoldedVOp = SimplifyVBinOp(N); 891 if (FoldedVOp.Val) return FoldedVOp; 892 } 893 894 // fold (add x, undef) -> undef 895 if (N0.getOpcode() == ISD::UNDEF) 896 return N0; 897 if (N1.getOpcode() == ISD::UNDEF) 898 return N1; 899 // fold (add c1, c2) -> c1+c2 900 if (N0C && N1C) 901 return DAG.getNode(ISD::ADD, VT, N0, N1); 902 // canonicalize constant to RHS 903 if (N0C && !N1C) 904 return DAG.getNode(ISD::ADD, VT, N1, N0); 905 // fold (add x, 0) -> x 906 if (N1C && N1C->isNullValue()) 907 return N0; 908 // fold ((c1-A)+c2) -> (c1+c2)-A 909 if (N1C && N0.getOpcode() == ISD::SUB) 910 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 911 return DAG.getNode(ISD::SUB, VT, 912 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 913 N0.getOperand(1)); 914 // reassociate add 915 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 916 if (RADD.Val != 0) 917 return RADD; 918 // fold ((0-A) + B) -> B-A 919 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 920 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 921 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 922 // fold (A + (0-B)) -> A-B 923 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 924 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 925 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 926 // fold (A+(B-A)) -> B 927 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 928 return N1.getOperand(0); 929 930 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 931 return SDOperand(N, 0); 932 933 // fold (a+b) -> (a|b) iff a and b share no bits. 934 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 935 uint64_t LHSZero, LHSOne; 936 uint64_t RHSZero, RHSOne; 937 uint64_t Mask = MVT::getIntVTBitMask(VT); 938 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 939 if (LHSZero) { 940 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 941 942 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 943 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 944 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 945 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 946 return DAG.getNode(ISD::OR, VT, N0, N1); 947 } 948 } 949 950 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 951 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 952 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 953 if (Result.Val) return Result; 954 } 955 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 956 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 957 if (Result.Val) return Result; 958 } 959 960 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 961 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 962 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 963 if (Result.Val) return Result; 964 } 965 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 966 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 967 if (Result.Val) return Result; 968 } 969 970 return SDOperand(); 971} 972 973SDOperand DAGCombiner::visitADDC(SDNode *N) { 974 SDOperand N0 = N->getOperand(0); 975 SDOperand N1 = N->getOperand(1); 976 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 977 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 978 MVT::ValueType VT = N0.getValueType(); 979 980 // If the flag result is dead, turn this into an ADD. 981 if (N->hasNUsesOfValue(0, 1)) 982 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 983 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 984 985 // canonicalize constant to RHS. 986 if (N0C && !N1C) { 987 SDOperand Ops[] = { N1, N0 }; 988 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 989 } 990 991 // fold (addc x, 0) -> x + no carry out 992 if (N1C && N1C->isNullValue()) 993 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 994 995 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 996 uint64_t LHSZero, LHSOne; 997 uint64_t RHSZero, RHSOne; 998 uint64_t Mask = MVT::getIntVTBitMask(VT); 999 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1000 if (LHSZero) { 1001 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1002 1003 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1004 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1005 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1006 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1007 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1008 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1009 } 1010 1011 return SDOperand(); 1012} 1013 1014SDOperand DAGCombiner::visitADDE(SDNode *N) { 1015 SDOperand N0 = N->getOperand(0); 1016 SDOperand N1 = N->getOperand(1); 1017 SDOperand CarryIn = N->getOperand(2); 1018 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1020 //MVT::ValueType VT = N0.getValueType(); 1021 1022 // canonicalize constant to RHS 1023 if (N0C && !N1C) { 1024 SDOperand Ops[] = { N1, N0, CarryIn }; 1025 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1026 } 1027 1028 // fold (adde x, y, false) -> (addc x, y) 1029 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1030 SDOperand Ops[] = { N1, N0 }; 1031 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1032 } 1033 1034 return SDOperand(); 1035} 1036 1037 1038 1039SDOperand DAGCombiner::visitSUB(SDNode *N) { 1040 SDOperand N0 = N->getOperand(0); 1041 SDOperand N1 = N->getOperand(1); 1042 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1043 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1044 MVT::ValueType VT = N0.getValueType(); 1045 1046 // fold vector ops 1047 if (MVT::isVector(VT)) { 1048 SDOperand FoldedVOp = SimplifyVBinOp(N); 1049 if (FoldedVOp.Val) return FoldedVOp; 1050 } 1051 1052 // fold (sub x, x) -> 0 1053 if (N0 == N1) 1054 return DAG.getConstant(0, N->getValueType(0)); 1055 // fold (sub c1, c2) -> c1-c2 1056 if (N0C && N1C) 1057 return DAG.getNode(ISD::SUB, VT, N0, N1); 1058 // fold (sub x, c) -> (add x, -c) 1059 if (N1C) 1060 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1061 // fold (A+B)-A -> B 1062 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1063 return N0.getOperand(1); 1064 // fold (A+B)-B -> A 1065 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1066 return N0.getOperand(0); 1067 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1068 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1069 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1070 if (Result.Val) return Result; 1071 } 1072 // If either operand of a sub is undef, the result is undef 1073 if (N0.getOpcode() == ISD::UNDEF) 1074 return N0; 1075 if (N1.getOpcode() == ISD::UNDEF) 1076 return N1; 1077 1078 return SDOperand(); 1079} 1080 1081SDOperand DAGCombiner::visitMUL(SDNode *N) { 1082 SDOperand N0 = N->getOperand(0); 1083 SDOperand N1 = N->getOperand(1); 1084 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1085 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1086 MVT::ValueType VT = N0.getValueType(); 1087 1088 // fold vector ops 1089 if (MVT::isVector(VT)) { 1090 SDOperand FoldedVOp = SimplifyVBinOp(N); 1091 if (FoldedVOp.Val) return FoldedVOp; 1092 } 1093 1094 // fold (mul x, undef) -> 0 1095 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1096 return DAG.getConstant(0, VT); 1097 // fold (mul c1, c2) -> c1*c2 1098 if (N0C && N1C) 1099 return DAG.getNode(ISD::MUL, VT, N0, N1); 1100 // canonicalize constant to RHS 1101 if (N0C && !N1C) 1102 return DAG.getNode(ISD::MUL, VT, N1, N0); 1103 // fold (mul x, 0) -> 0 1104 if (N1C && N1C->isNullValue()) 1105 return N1; 1106 // fold (mul x, -1) -> 0-x 1107 if (N1C && N1C->isAllOnesValue()) 1108 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1109 // fold (mul x, (1 << c)) -> x << c 1110 if (N1C && isPowerOf2_64(N1C->getValue())) 1111 return DAG.getNode(ISD::SHL, VT, N0, 1112 DAG.getConstant(Log2_64(N1C->getValue()), 1113 TLI.getShiftAmountTy())); 1114 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1115 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1116 // FIXME: If the input is something that is easily negated (e.g. a 1117 // single-use add), we should put the negate there. 1118 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1119 DAG.getNode(ISD::SHL, VT, N0, 1120 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1121 TLI.getShiftAmountTy()))); 1122 } 1123 1124 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1125 if (N1C && N0.getOpcode() == ISD::SHL && 1126 isa<ConstantSDNode>(N0.getOperand(1))) { 1127 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1128 AddToWorkList(C3.Val); 1129 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1130 } 1131 1132 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1133 // use. 1134 { 1135 SDOperand Sh(0,0), Y(0,0); 1136 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1137 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1138 N0.Val->hasOneUse()) { 1139 Sh = N0; Y = N1; 1140 } else if (N1.getOpcode() == ISD::SHL && 1141 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1142 Sh = N1; Y = N0; 1143 } 1144 if (Sh.Val) { 1145 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1146 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1147 } 1148 } 1149 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1150 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1151 isa<ConstantSDNode>(N0.getOperand(1))) { 1152 return DAG.getNode(ISD::ADD, VT, 1153 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1154 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1155 } 1156 1157 // reassociate mul 1158 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1159 if (RMUL.Val != 0) 1160 return RMUL; 1161 1162 return SDOperand(); 1163} 1164 1165SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1166 SDOperand N0 = N->getOperand(0); 1167 SDOperand N1 = N->getOperand(1); 1168 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1169 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1170 MVT::ValueType VT = N->getValueType(0); 1171 1172 // fold vector ops 1173 if (MVT::isVector(VT)) { 1174 SDOperand FoldedVOp = SimplifyVBinOp(N); 1175 if (FoldedVOp.Val) return FoldedVOp; 1176 } 1177 1178 // fold (sdiv c1, c2) -> c1/c2 1179 if (N0C && N1C && !N1C->isNullValue()) 1180 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1181 // fold (sdiv X, 1) -> X 1182 if (N1C && N1C->getSignExtended() == 1LL) 1183 return N0; 1184 // fold (sdiv X, -1) -> 0-X 1185 if (N1C && N1C->isAllOnesValue()) 1186 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1187 // If we know the sign bits of both operands are zero, strength reduce to a 1188 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1189 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1190 if (DAG.MaskedValueIsZero(N1, SignBit) && 1191 DAG.MaskedValueIsZero(N0, SignBit)) 1192 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1193 // fold (sdiv X, pow2) -> simple ops after legalize 1194 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1195 (isPowerOf2_64(N1C->getSignExtended()) || 1196 isPowerOf2_64(-N1C->getSignExtended()))) { 1197 // If dividing by powers of two is cheap, then don't perform the following 1198 // fold. 1199 if (TLI.isPow2DivCheap()) 1200 return SDOperand(); 1201 int64_t pow2 = N1C->getSignExtended(); 1202 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1203 unsigned lg2 = Log2_64(abs2); 1204 // Splat the sign bit into the register 1205 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1206 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1207 TLI.getShiftAmountTy())); 1208 AddToWorkList(SGN.Val); 1209 // Add (N0 < 0) ? abs2 - 1 : 0; 1210 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1211 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1212 TLI.getShiftAmountTy())); 1213 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1214 AddToWorkList(SRL.Val); 1215 AddToWorkList(ADD.Val); // Divide by pow2 1216 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1217 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1218 // If we're dividing by a positive value, we're done. Otherwise, we must 1219 // negate the result. 1220 if (pow2 > 0) 1221 return SRA; 1222 AddToWorkList(SRA.Val); 1223 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1224 } 1225 // if integer divide is expensive and we satisfy the requirements, emit an 1226 // alternate sequence. 1227 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1228 !TLI.isIntDivCheap()) { 1229 SDOperand Op = BuildSDIV(N); 1230 if (Op.Val) return Op; 1231 } 1232 1233 // undef / X -> 0 1234 if (N0.getOpcode() == ISD::UNDEF) 1235 return DAG.getConstant(0, VT); 1236 // X / undef -> undef 1237 if (N1.getOpcode() == ISD::UNDEF) 1238 return N1; 1239 1240 return SDOperand(); 1241} 1242 1243SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1244 SDOperand N0 = N->getOperand(0); 1245 SDOperand N1 = N->getOperand(1); 1246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1248 MVT::ValueType VT = N->getValueType(0); 1249 1250 // fold vector ops 1251 if (MVT::isVector(VT)) { 1252 SDOperand FoldedVOp = SimplifyVBinOp(N); 1253 if (FoldedVOp.Val) return FoldedVOp; 1254 } 1255 1256 // fold (udiv c1, c2) -> c1/c2 1257 if (N0C && N1C && !N1C->isNullValue()) 1258 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1259 // fold (udiv x, (1 << c)) -> x >>u c 1260 if (N1C && isPowerOf2_64(N1C->getValue())) 1261 return DAG.getNode(ISD::SRL, VT, N0, 1262 DAG.getConstant(Log2_64(N1C->getValue()), 1263 TLI.getShiftAmountTy())); 1264 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1265 if (N1.getOpcode() == ISD::SHL) { 1266 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1267 if (isPowerOf2_64(SHC->getValue())) { 1268 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1269 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1270 DAG.getConstant(Log2_64(SHC->getValue()), 1271 ADDVT)); 1272 AddToWorkList(Add.Val); 1273 return DAG.getNode(ISD::SRL, VT, N0, Add); 1274 } 1275 } 1276 } 1277 // fold (udiv x, c) -> alternate 1278 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1279 SDOperand Op = BuildUDIV(N); 1280 if (Op.Val) return Op; 1281 } 1282 1283 // undef / X -> 0 1284 if (N0.getOpcode() == ISD::UNDEF) 1285 return DAG.getConstant(0, VT); 1286 // X / undef -> undef 1287 if (N1.getOpcode() == ISD::UNDEF) 1288 return N1; 1289 1290 return SDOperand(); 1291} 1292 1293SDOperand DAGCombiner::visitSREM(SDNode *N) { 1294 SDOperand N0 = N->getOperand(0); 1295 SDOperand N1 = N->getOperand(1); 1296 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1297 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1298 MVT::ValueType VT = N->getValueType(0); 1299 1300 // fold (srem c1, c2) -> c1%c2 1301 if (N0C && N1C && !N1C->isNullValue()) 1302 return DAG.getNode(ISD::SREM, VT, N0, N1); 1303 // If we know the sign bits of both operands are zero, strength reduce to a 1304 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1305 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1306 if (DAG.MaskedValueIsZero(N1, SignBit) && 1307 DAG.MaskedValueIsZero(N0, SignBit)) 1308 return DAG.getNode(ISD::UREM, VT, N0, N1); 1309 1310 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1311 // the remainder operation. 1312 if (N1C && !N1C->isNullValue()) { 1313 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1314 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1315 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1316 AddToWorkList(Div.Val); 1317 AddToWorkList(Mul.Val); 1318 return Sub; 1319 } 1320 1321 // undef % X -> 0 1322 if (N0.getOpcode() == ISD::UNDEF) 1323 return DAG.getConstant(0, VT); 1324 // X % undef -> undef 1325 if (N1.getOpcode() == ISD::UNDEF) 1326 return N1; 1327 1328 return SDOperand(); 1329} 1330 1331SDOperand DAGCombiner::visitUREM(SDNode *N) { 1332 SDOperand N0 = N->getOperand(0); 1333 SDOperand N1 = N->getOperand(1); 1334 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1335 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1336 MVT::ValueType VT = N->getValueType(0); 1337 1338 // fold (urem c1, c2) -> c1%c2 1339 if (N0C && N1C && !N1C->isNullValue()) 1340 return DAG.getNode(ISD::UREM, VT, N0, N1); 1341 // fold (urem x, pow2) -> (and x, pow2-1) 1342 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1343 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1344 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1345 if (N1.getOpcode() == ISD::SHL) { 1346 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1347 if (isPowerOf2_64(SHC->getValue())) { 1348 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1349 AddToWorkList(Add.Val); 1350 return DAG.getNode(ISD::AND, VT, N0, Add); 1351 } 1352 } 1353 } 1354 1355 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1356 // the remainder operation. 1357 if (N1C && !N1C->isNullValue()) { 1358 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1359 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1360 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1361 AddToWorkList(Div.Val); 1362 AddToWorkList(Mul.Val); 1363 return Sub; 1364 } 1365 1366 // undef % X -> 0 1367 if (N0.getOpcode() == ISD::UNDEF) 1368 return DAG.getConstant(0, VT); 1369 // X % undef -> undef 1370 if (N1.getOpcode() == ISD::UNDEF) 1371 return N1; 1372 1373 return SDOperand(); 1374} 1375 1376SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1377 SDOperand N0 = N->getOperand(0); 1378 SDOperand N1 = N->getOperand(1); 1379 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1380 MVT::ValueType VT = N->getValueType(0); 1381 1382 // fold (mulhs x, 0) -> 0 1383 if (N1C && N1C->isNullValue()) 1384 return N1; 1385 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1386 if (N1C && N1C->getValue() == 1) 1387 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1388 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1389 TLI.getShiftAmountTy())); 1390 // fold (mulhs x, undef) -> 0 1391 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1392 return DAG.getConstant(0, VT); 1393 1394 return SDOperand(); 1395} 1396 1397SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1398 SDOperand N0 = N->getOperand(0); 1399 SDOperand N1 = N->getOperand(1); 1400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1401 MVT::ValueType VT = N->getValueType(0); 1402 1403 // fold (mulhu x, 0) -> 0 1404 if (N1C && N1C->isNullValue()) 1405 return N1; 1406 // fold (mulhu x, 1) -> 0 1407 if (N1C && N1C->getValue() == 1) 1408 return DAG.getConstant(0, N0.getValueType()); 1409 // fold (mulhu x, undef) -> 0 1410 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1411 return DAG.getConstant(0, VT); 1412 1413 return SDOperand(); 1414} 1415 1416/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1417/// compute two values. LoOp and HiOp give the opcodes for the two computations 1418/// that are being performed. Return true if a simplification was made. 1419/// 1420bool DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, 1421 unsigned LoOp, unsigned HiOp) { 1422 // If the high half is not needed, just compute the low half. 1423 if (!N->hasAnyUseOfValue(1) && 1424 (!AfterLegalize || 1425 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1426 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), 1427 DAG.getNode(LoOp, N->getValueType(0), 1428 N->op_begin(), 1429 N->getNumOperands())); 1430 return true; 1431 } 1432 1433 // If the low half is not needed, just compute the high half. 1434 if (!N->hasAnyUseOfValue(0) && 1435 (!AfterLegalize || 1436 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1437 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 1438 DAG.getNode(HiOp, N->getValueType(1), 1439 N->op_begin(), 1440 N->getNumOperands())); 1441 return true; 1442 } 1443 1444 // If the two computed results can be siplified separately, separate them. 1445 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1446 N->op_begin(), N->getNumOperands()); 1447 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1448 N->op_begin(), N->getNumOperands()); 1449 unsigned LoExists = !Lo.use_empty(); 1450 unsigned HiExists = !Hi.use_empty(); 1451 SDOperand LoOpt = Lo; 1452 SDOperand HiOpt = Hi; 1453 if (!LoExists || !HiExists) { 1454 SDOperand Pair = DAG.getNode(ISD::BUILD_PAIR, MVT::Other, Lo, Hi); 1455 assert(Pair.use_empty() && "Pair with type MVT::Other already exists!"); 1456 LoOpt = combine(Lo.Val); 1457 HiOpt = combine(Hi.Val); 1458 if (!LoOpt.Val) 1459 LoOpt = Pair.getOperand(0); 1460 if (!HiOpt.Val) 1461 HiOpt = Pair.getOperand(1); 1462 DAG.DeleteNode(Pair.Val); 1463 } 1464 if ((LoExists || LoOpt != Lo) && 1465 (HiExists || HiOpt != Hi) && 1466 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()) && 1467 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) { 1468 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), LoOpt); 1469 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), HiOpt); 1470 return true; 1471 } 1472 1473 return false; 1474} 1475 1476SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1477 1478 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS)) 1479 return SDOperand(); 1480 1481 return SDOperand(); 1482} 1483 1484SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1485 1486 if (SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU)) 1487 return SDOperand(); 1488 1489 return SDOperand(); 1490} 1491 1492SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1493 1494 if (SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM)) 1495 return SDOperand(); 1496 1497 return SDOperand(); 1498} 1499 1500SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1501 1502 if (SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM)) 1503 return SDOperand(); 1504 1505 return SDOperand(); 1506} 1507 1508/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1509/// two operands of the same opcode, try to simplify it. 1510SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1511 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1512 MVT::ValueType VT = N0.getValueType(); 1513 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1514 1515 // For each of OP in AND/OR/XOR: 1516 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1517 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1518 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1519 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1520 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1521 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1522 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1523 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1524 N0.getOperand(0).getValueType(), 1525 N0.getOperand(0), N1.getOperand(0)); 1526 AddToWorkList(ORNode.Val); 1527 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1528 } 1529 1530 // For each of OP in SHL/SRL/SRA/AND... 1531 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1532 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1533 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1534 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1535 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1536 N0.getOperand(1) == N1.getOperand(1)) { 1537 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1538 N0.getOperand(0).getValueType(), 1539 N0.getOperand(0), N1.getOperand(0)); 1540 AddToWorkList(ORNode.Val); 1541 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1542 } 1543 1544 return SDOperand(); 1545} 1546 1547SDOperand DAGCombiner::visitAND(SDNode *N) { 1548 SDOperand N0 = N->getOperand(0); 1549 SDOperand N1 = N->getOperand(1); 1550 SDOperand LL, LR, RL, RR, CC0, CC1; 1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1553 MVT::ValueType VT = N1.getValueType(); 1554 1555 // fold vector ops 1556 if (MVT::isVector(VT)) { 1557 SDOperand FoldedVOp = SimplifyVBinOp(N); 1558 if (FoldedVOp.Val) return FoldedVOp; 1559 } 1560 1561 // fold (and x, undef) -> 0 1562 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1563 return DAG.getConstant(0, VT); 1564 // fold (and c1, c2) -> c1&c2 1565 if (N0C && N1C) 1566 return DAG.getNode(ISD::AND, VT, N0, N1); 1567 // canonicalize constant to RHS 1568 if (N0C && !N1C) 1569 return DAG.getNode(ISD::AND, VT, N1, N0); 1570 // fold (and x, -1) -> x 1571 if (N1C && N1C->isAllOnesValue()) 1572 return N0; 1573 // if (and x, c) is known to be zero, return 0 1574 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1575 return DAG.getConstant(0, VT); 1576 // reassociate and 1577 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1578 if (RAND.Val != 0) 1579 return RAND; 1580 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1581 if (N1C && N0.getOpcode() == ISD::OR) 1582 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1583 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1584 return N1; 1585 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1586 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1587 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1588 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1589 ~N1C->getValue() & InMask)) { 1590 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1591 N0.getOperand(0)); 1592 1593 // Replace uses of the AND with uses of the Zero extend node. 1594 CombineTo(N, Zext); 1595 1596 // We actually want to replace all uses of the any_extend with the 1597 // zero_extend, to avoid duplicating things. This will later cause this 1598 // AND to be folded. 1599 CombineTo(N0.Val, Zext); 1600 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1601 } 1602 } 1603 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1604 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1605 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1606 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1607 1608 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1609 MVT::isInteger(LL.getValueType())) { 1610 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1611 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1612 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1613 AddToWorkList(ORNode.Val); 1614 return DAG.getSetCC(VT, ORNode, LR, Op1); 1615 } 1616 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1617 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1618 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1619 AddToWorkList(ANDNode.Val); 1620 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1621 } 1622 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1623 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1624 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1625 AddToWorkList(ORNode.Val); 1626 return DAG.getSetCC(VT, ORNode, LR, Op1); 1627 } 1628 } 1629 // canonicalize equivalent to ll == rl 1630 if (LL == RR && LR == RL) { 1631 Op1 = ISD::getSetCCSwappedOperands(Op1); 1632 std::swap(RL, RR); 1633 } 1634 if (LL == RL && LR == RR) { 1635 bool isInteger = MVT::isInteger(LL.getValueType()); 1636 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1637 if (Result != ISD::SETCC_INVALID) 1638 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1639 } 1640 } 1641 1642 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1643 if (N0.getOpcode() == N1.getOpcode()) { 1644 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1645 if (Tmp.Val) return Tmp; 1646 } 1647 1648 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1649 // fold (and (sra)) -> (and (srl)) when possible. 1650 if (!MVT::isVector(VT) && 1651 SimplifyDemandedBits(SDOperand(N, 0))) 1652 return SDOperand(N, 0); 1653 // fold (zext_inreg (extload x)) -> (zextload x) 1654 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1655 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1656 MVT::ValueType EVT = LN0->getLoadedVT(); 1657 // If we zero all the possible extended bits, then we can turn this into 1658 // a zextload if we are running before legalize or the operation is legal. 1659 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1660 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1661 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1662 LN0->getBasePtr(), LN0->getSrcValue(), 1663 LN0->getSrcValueOffset(), EVT, 1664 LN0->isVolatile(), 1665 LN0->getAlignment()); 1666 AddToWorkList(N); 1667 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1668 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1669 } 1670 } 1671 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1672 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1673 N0.hasOneUse()) { 1674 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1675 MVT::ValueType EVT = LN0->getLoadedVT(); 1676 // If we zero all the possible extended bits, then we can turn this into 1677 // a zextload if we are running before legalize or the operation is legal. 1678 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1679 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1680 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1681 LN0->getBasePtr(), LN0->getSrcValue(), 1682 LN0->getSrcValueOffset(), EVT, 1683 LN0->isVolatile(), 1684 LN0->getAlignment()); 1685 AddToWorkList(N); 1686 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1687 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1688 } 1689 } 1690 1691 // fold (and (load x), 255) -> (zextload x, i8) 1692 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1693 if (N1C && N0.getOpcode() == ISD::LOAD) { 1694 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1695 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1696 LN0->getAddressingMode() == ISD::UNINDEXED && 1697 N0.hasOneUse()) { 1698 MVT::ValueType EVT, LoadedVT; 1699 if (N1C->getValue() == 255) 1700 EVT = MVT::i8; 1701 else if (N1C->getValue() == 65535) 1702 EVT = MVT::i16; 1703 else if (N1C->getValue() == ~0U) 1704 EVT = MVT::i32; 1705 else 1706 EVT = MVT::Other; 1707 1708 LoadedVT = LN0->getLoadedVT(); 1709 if (EVT != MVT::Other && LoadedVT > EVT && 1710 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1711 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1712 // For big endian targets, we need to add an offset to the pointer to 1713 // load the correct bytes. For little endian systems, we merely need to 1714 // read fewer bytes from the same pointer. 1715 unsigned PtrOff = 1716 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1717 unsigned Alignment = LN0->getAlignment(); 1718 SDOperand NewPtr = LN0->getBasePtr(); 1719 if (!TLI.isLittleEndian()) { 1720 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1721 DAG.getConstant(PtrOff, PtrType)); 1722 Alignment = MinAlign(Alignment, PtrOff); 1723 } 1724 AddToWorkList(NewPtr.Val); 1725 SDOperand Load = 1726 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1727 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1728 LN0->isVolatile(), Alignment); 1729 AddToWorkList(N); 1730 CombineTo(N0.Val, Load, Load.getValue(1)); 1731 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1732 } 1733 } 1734 } 1735 1736 return SDOperand(); 1737} 1738 1739SDOperand DAGCombiner::visitOR(SDNode *N) { 1740 SDOperand N0 = N->getOperand(0); 1741 SDOperand N1 = N->getOperand(1); 1742 SDOperand LL, LR, RL, RR, CC0, CC1; 1743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1745 MVT::ValueType VT = N1.getValueType(); 1746 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1747 1748 // fold vector ops 1749 if (MVT::isVector(VT)) { 1750 SDOperand FoldedVOp = SimplifyVBinOp(N); 1751 if (FoldedVOp.Val) return FoldedVOp; 1752 } 1753 1754 // fold (or x, undef) -> -1 1755 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1756 return DAG.getConstant(~0ULL, VT); 1757 // fold (or c1, c2) -> c1|c2 1758 if (N0C && N1C) 1759 return DAG.getNode(ISD::OR, VT, N0, N1); 1760 // canonicalize constant to RHS 1761 if (N0C && !N1C) 1762 return DAG.getNode(ISD::OR, VT, N1, N0); 1763 // fold (or x, 0) -> x 1764 if (N1C && N1C->isNullValue()) 1765 return N0; 1766 // fold (or x, -1) -> -1 1767 if (N1C && N1C->isAllOnesValue()) 1768 return N1; 1769 // fold (or x, c) -> c iff (x & ~c) == 0 1770 if (N1C && 1771 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1772 return N1; 1773 // reassociate or 1774 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1775 if (ROR.Val != 0) 1776 return ROR; 1777 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1778 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1779 isa<ConstantSDNode>(N0.getOperand(1))) { 1780 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1781 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1782 N1), 1783 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1784 } 1785 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1786 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1787 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1788 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1789 1790 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1791 MVT::isInteger(LL.getValueType())) { 1792 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1793 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1794 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1795 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1796 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1797 AddToWorkList(ORNode.Val); 1798 return DAG.getSetCC(VT, ORNode, LR, Op1); 1799 } 1800 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1801 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1803 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1804 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1805 AddToWorkList(ANDNode.Val); 1806 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1807 } 1808 } 1809 // canonicalize equivalent to ll == rl 1810 if (LL == RR && LR == RL) { 1811 Op1 = ISD::getSetCCSwappedOperands(Op1); 1812 std::swap(RL, RR); 1813 } 1814 if (LL == RL && LR == RR) { 1815 bool isInteger = MVT::isInteger(LL.getValueType()); 1816 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1817 if (Result != ISD::SETCC_INVALID) 1818 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1819 } 1820 } 1821 1822 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1823 if (N0.getOpcode() == N1.getOpcode()) { 1824 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1825 if (Tmp.Val) return Tmp; 1826 } 1827 1828 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1829 if (N0.getOpcode() == ISD::AND && 1830 N1.getOpcode() == ISD::AND && 1831 N0.getOperand(1).getOpcode() == ISD::Constant && 1832 N1.getOperand(1).getOpcode() == ISD::Constant && 1833 // Don't increase # computations. 1834 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1835 // We can only do this xform if we know that bits from X that are set in C2 1836 // but not in C1 are already zero. Likewise for Y. 1837 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1838 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1839 1840 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1841 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1842 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1843 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1844 } 1845 } 1846 1847 1848 // See if this is some rotate idiom. 1849 if (SDNode *Rot = MatchRotate(N0, N1)) 1850 return SDOperand(Rot, 0); 1851 1852 return SDOperand(); 1853} 1854 1855 1856/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1857static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1858 if (Op.getOpcode() == ISD::AND) { 1859 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1860 Mask = Op.getOperand(1); 1861 Op = Op.getOperand(0); 1862 } else { 1863 return false; 1864 } 1865 } 1866 1867 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1868 Shift = Op; 1869 return true; 1870 } 1871 return false; 1872} 1873 1874 1875// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1876// idioms for rotate, and if the target supports rotation instructions, generate 1877// a rot[lr]. 1878SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1879 // Must be a legal type. Expanded an promoted things won't work with rotates. 1880 MVT::ValueType VT = LHS.getValueType(); 1881 if (!TLI.isTypeLegal(VT)) return 0; 1882 1883 // The target must have at least one rotate flavor. 1884 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1885 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1886 if (!HasROTL && !HasROTR) return 0; 1887 1888 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1889 SDOperand LHSShift; // The shift. 1890 SDOperand LHSMask; // AND value if any. 1891 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1892 return 0; // Not part of a rotate. 1893 1894 SDOperand RHSShift; // The shift. 1895 SDOperand RHSMask; // AND value if any. 1896 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1897 return 0; // Not part of a rotate. 1898 1899 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1900 return 0; // Not shifting the same value. 1901 1902 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1903 return 0; // Shifts must disagree. 1904 1905 // Canonicalize shl to left side in a shl/srl pair. 1906 if (RHSShift.getOpcode() == ISD::SHL) { 1907 std::swap(LHS, RHS); 1908 std::swap(LHSShift, RHSShift); 1909 std::swap(LHSMask , RHSMask ); 1910 } 1911 1912 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1913 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1914 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1915 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1916 1917 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1918 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1919 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1920 RHSShiftAmt.getOpcode() == ISD::Constant) { 1921 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1922 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1923 if ((LShVal + RShVal) != OpSizeInBits) 1924 return 0; 1925 1926 SDOperand Rot; 1927 if (HasROTL) 1928 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1929 else 1930 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1931 1932 // If there is an AND of either shifted operand, apply it to the result. 1933 if (LHSMask.Val || RHSMask.Val) { 1934 uint64_t Mask = MVT::getIntVTBitMask(VT); 1935 1936 if (LHSMask.Val) { 1937 uint64_t RHSBits = (1ULL << LShVal)-1; 1938 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1939 } 1940 if (RHSMask.Val) { 1941 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1942 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1943 } 1944 1945 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1946 } 1947 1948 return Rot.Val; 1949 } 1950 1951 // If there is a mask here, and we have a variable shift, we can't be sure 1952 // that we're masking out the right stuff. 1953 if (LHSMask.Val || RHSMask.Val) 1954 return 0; 1955 1956 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1957 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1958 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1959 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1960 if (ConstantSDNode *SUBC = 1961 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1962 if (SUBC->getValue() == OpSizeInBits) 1963 if (HasROTL) 1964 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1965 else 1966 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1967 } 1968 } 1969 1970 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1971 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1972 if (LHSShiftAmt.getOpcode() == ISD::SUB && 1973 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 1974 if (ConstantSDNode *SUBC = 1975 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 1976 if (SUBC->getValue() == OpSizeInBits) 1977 if (HasROTL) 1978 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 1979 else 1980 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 1981 } 1982 } 1983 1984 // Look for sign/zext/any-extended cases: 1985 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1986 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1987 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 1988 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 1989 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 1990 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 1991 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 1992 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 1993 if (RExtOp0.getOpcode() == ISD::SUB && 1994 RExtOp0.getOperand(1) == LExtOp0) { 1995 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1996 // (rotr x, y) 1997 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 1998 // (rotl x, (sub 32, y)) 1999 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2000 if (SUBC->getValue() == OpSizeInBits) { 2001 if (HasROTL) 2002 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2003 else 2004 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2005 } 2006 } 2007 } else if (LExtOp0.getOpcode() == ISD::SUB && 2008 RExtOp0 == LExtOp0.getOperand(1)) { 2009 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2010 // (rotl x, y) 2011 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2012 // (rotr x, (sub 32, y)) 2013 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2014 if (SUBC->getValue() == OpSizeInBits) { 2015 if (HasROTL) 2016 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2017 else 2018 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2019 } 2020 } 2021 } 2022 } 2023 2024 return 0; 2025} 2026 2027 2028SDOperand DAGCombiner::visitXOR(SDNode *N) { 2029 SDOperand N0 = N->getOperand(0); 2030 SDOperand N1 = N->getOperand(1); 2031 SDOperand LHS, RHS, CC; 2032 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2033 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2034 MVT::ValueType VT = N0.getValueType(); 2035 2036 // fold vector ops 2037 if (MVT::isVector(VT)) { 2038 SDOperand FoldedVOp = SimplifyVBinOp(N); 2039 if (FoldedVOp.Val) return FoldedVOp; 2040 } 2041 2042 // fold (xor x, undef) -> undef 2043 if (N0.getOpcode() == ISD::UNDEF) 2044 return N0; 2045 if (N1.getOpcode() == ISD::UNDEF) 2046 return N1; 2047 // fold (xor c1, c2) -> c1^c2 2048 if (N0C && N1C) 2049 return DAG.getNode(ISD::XOR, VT, N0, N1); 2050 // canonicalize constant to RHS 2051 if (N0C && !N1C) 2052 return DAG.getNode(ISD::XOR, VT, N1, N0); 2053 // fold (xor x, 0) -> x 2054 if (N1C && N1C->isNullValue()) 2055 return N0; 2056 // reassociate xor 2057 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2058 if (RXOR.Val != 0) 2059 return RXOR; 2060 // fold !(x cc y) -> (x !cc y) 2061 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2062 bool isInt = MVT::isInteger(LHS.getValueType()); 2063 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2064 isInt); 2065 if (N0.getOpcode() == ISD::SETCC) 2066 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2067 if (N0.getOpcode() == ISD::SELECT_CC) 2068 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2069 assert(0 && "Unhandled SetCC Equivalent!"); 2070 abort(); 2071 } 2072 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2073 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2074 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2075 SDOperand V = N0.getOperand(0); 2076 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2077 DAG.getConstant(1, V.getValueType())); 2078 AddToWorkList(V.Val); 2079 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2080 } 2081 2082 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2083 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2084 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2085 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2086 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2087 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2088 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2089 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2090 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2091 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2092 } 2093 } 2094 // fold !(x or y) -> (!x and !y) iff x or y are constants 2095 if (N1C && N1C->isAllOnesValue() && 2096 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2097 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2098 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2099 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2100 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2101 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2102 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2103 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2104 } 2105 } 2106 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2107 if (N1C && N0.getOpcode() == ISD::XOR) { 2108 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2109 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2110 if (N00C) 2111 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2112 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2113 if (N01C) 2114 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2115 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2116 } 2117 // fold (xor x, x) -> 0 2118 if (N0 == N1) { 2119 if (!MVT::isVector(VT)) { 2120 return DAG.getConstant(0, VT); 2121 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2122 // Produce a vector of zeros. 2123 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2124 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2125 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2126 } 2127 } 2128 2129 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2130 if (N0.getOpcode() == N1.getOpcode()) { 2131 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2132 if (Tmp.Val) return Tmp; 2133 } 2134 2135 // Simplify the expression using non-local knowledge. 2136 if (!MVT::isVector(VT) && 2137 SimplifyDemandedBits(SDOperand(N, 0))) 2138 return SDOperand(N, 0); 2139 2140 return SDOperand(); 2141} 2142 2143SDOperand DAGCombiner::visitSHL(SDNode *N) { 2144 SDOperand N0 = N->getOperand(0); 2145 SDOperand N1 = N->getOperand(1); 2146 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2147 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2148 MVT::ValueType VT = N0.getValueType(); 2149 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2150 2151 // fold (shl c1, c2) -> c1<<c2 2152 if (N0C && N1C) 2153 return DAG.getNode(ISD::SHL, VT, N0, N1); 2154 // fold (shl 0, x) -> 0 2155 if (N0C && N0C->isNullValue()) 2156 return N0; 2157 // fold (shl x, c >= size(x)) -> undef 2158 if (N1C && N1C->getValue() >= OpSizeInBits) 2159 return DAG.getNode(ISD::UNDEF, VT); 2160 // fold (shl x, 0) -> x 2161 if (N1C && N1C->isNullValue()) 2162 return N0; 2163 // if (shl x, c) is known to be zero, return 0 2164 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2165 return DAG.getConstant(0, VT); 2166 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2167 return SDOperand(N, 0); 2168 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2169 if (N1C && N0.getOpcode() == ISD::SHL && 2170 N0.getOperand(1).getOpcode() == ISD::Constant) { 2171 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2172 uint64_t c2 = N1C->getValue(); 2173 if (c1 + c2 > OpSizeInBits) 2174 return DAG.getConstant(0, VT); 2175 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2176 DAG.getConstant(c1 + c2, N1.getValueType())); 2177 } 2178 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2179 // (srl (and x, -1 << c1), c1-c2) 2180 if (N1C && N0.getOpcode() == ISD::SRL && 2181 N0.getOperand(1).getOpcode() == ISD::Constant) { 2182 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2183 uint64_t c2 = N1C->getValue(); 2184 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2185 DAG.getConstant(~0ULL << c1, VT)); 2186 if (c2 > c1) 2187 return DAG.getNode(ISD::SHL, VT, Mask, 2188 DAG.getConstant(c2-c1, N1.getValueType())); 2189 else 2190 return DAG.getNode(ISD::SRL, VT, Mask, 2191 DAG.getConstant(c1-c2, N1.getValueType())); 2192 } 2193 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2194 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2195 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2196 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2197 return SDOperand(); 2198} 2199 2200SDOperand DAGCombiner::visitSRA(SDNode *N) { 2201 SDOperand N0 = N->getOperand(0); 2202 SDOperand N1 = N->getOperand(1); 2203 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2204 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2205 MVT::ValueType VT = N0.getValueType(); 2206 2207 // fold (sra c1, c2) -> c1>>c2 2208 if (N0C && N1C) 2209 return DAG.getNode(ISD::SRA, VT, N0, N1); 2210 // fold (sra 0, x) -> 0 2211 if (N0C && N0C->isNullValue()) 2212 return N0; 2213 // fold (sra -1, x) -> -1 2214 if (N0C && N0C->isAllOnesValue()) 2215 return N0; 2216 // fold (sra x, c >= size(x)) -> undef 2217 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2218 return DAG.getNode(ISD::UNDEF, VT); 2219 // fold (sra x, 0) -> x 2220 if (N1C && N1C->isNullValue()) 2221 return N0; 2222 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2223 // sext_inreg. 2224 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2225 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2226 MVT::ValueType EVT; 2227 switch (LowBits) { 2228 default: EVT = MVT::Other; break; 2229 case 1: EVT = MVT::i1; break; 2230 case 8: EVT = MVT::i8; break; 2231 case 16: EVT = MVT::i16; break; 2232 case 32: EVT = MVT::i32; break; 2233 } 2234 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2235 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2236 DAG.getValueType(EVT)); 2237 } 2238 2239 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2240 if (N1C && N0.getOpcode() == ISD::SRA) { 2241 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2242 unsigned Sum = N1C->getValue() + C1->getValue(); 2243 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2244 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2245 DAG.getConstant(Sum, N1C->getValueType(0))); 2246 } 2247 } 2248 2249 // Simplify, based on bits shifted out of the LHS. 2250 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2251 return SDOperand(N, 0); 2252 2253 2254 // If the sign bit is known to be zero, switch this to a SRL. 2255 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2256 return DAG.getNode(ISD::SRL, VT, N0, N1); 2257 return SDOperand(); 2258} 2259 2260SDOperand DAGCombiner::visitSRL(SDNode *N) { 2261 SDOperand N0 = N->getOperand(0); 2262 SDOperand N1 = N->getOperand(1); 2263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2265 MVT::ValueType VT = N0.getValueType(); 2266 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2267 2268 // fold (srl c1, c2) -> c1 >>u c2 2269 if (N0C && N1C) 2270 return DAG.getNode(ISD::SRL, VT, N0, N1); 2271 // fold (srl 0, x) -> 0 2272 if (N0C && N0C->isNullValue()) 2273 return N0; 2274 // fold (srl x, c >= size(x)) -> undef 2275 if (N1C && N1C->getValue() >= OpSizeInBits) 2276 return DAG.getNode(ISD::UNDEF, VT); 2277 // fold (srl x, 0) -> x 2278 if (N1C && N1C->isNullValue()) 2279 return N0; 2280 // if (srl x, c) is known to be zero, return 0 2281 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2282 return DAG.getConstant(0, VT); 2283 2284 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2285 if (N1C && N0.getOpcode() == ISD::SRL && 2286 N0.getOperand(1).getOpcode() == ISD::Constant) { 2287 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2288 uint64_t c2 = N1C->getValue(); 2289 if (c1 + c2 > OpSizeInBits) 2290 return DAG.getConstant(0, VT); 2291 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2292 DAG.getConstant(c1 + c2, N1.getValueType())); 2293 } 2294 2295 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2296 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2297 // Shifting in all undef bits? 2298 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2299 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2300 return DAG.getNode(ISD::UNDEF, VT); 2301 2302 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2303 AddToWorkList(SmallShift.Val); 2304 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2305 } 2306 2307 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2308 // bit, which is unmodified by sra. 2309 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2310 if (N0.getOpcode() == ISD::SRA) 2311 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2312 } 2313 2314 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2315 if (N1C && N0.getOpcode() == ISD::CTLZ && 2316 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2317 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2318 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2319 2320 // If any of the input bits are KnownOne, then the input couldn't be all 2321 // zeros, thus the result of the srl will always be zero. 2322 if (KnownOne) return DAG.getConstant(0, VT); 2323 2324 // If all of the bits input the to ctlz node are known to be zero, then 2325 // the result of the ctlz is "32" and the result of the shift is one. 2326 uint64_t UnknownBits = ~KnownZero & Mask; 2327 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2328 2329 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2330 if ((UnknownBits & (UnknownBits-1)) == 0) { 2331 // Okay, we know that only that the single bit specified by UnknownBits 2332 // could be set on input to the CTLZ node. If this bit is set, the SRL 2333 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2334 // to an SRL,XOR pair, which is likely to simplify more. 2335 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2336 SDOperand Op = N0.getOperand(0); 2337 if (ShAmt) { 2338 Op = DAG.getNode(ISD::SRL, VT, Op, 2339 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2340 AddToWorkList(Op.Val); 2341 } 2342 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2343 } 2344 } 2345 2346 // fold operands of srl based on knowledge that the low bits are not 2347 // demanded. 2348 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2349 return SDOperand(N, 0); 2350 2351 return SDOperand(); 2352} 2353 2354SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2355 SDOperand N0 = N->getOperand(0); 2356 MVT::ValueType VT = N->getValueType(0); 2357 2358 // fold (ctlz c1) -> c2 2359 if (isa<ConstantSDNode>(N0)) 2360 return DAG.getNode(ISD::CTLZ, VT, N0); 2361 return SDOperand(); 2362} 2363 2364SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2365 SDOperand N0 = N->getOperand(0); 2366 MVT::ValueType VT = N->getValueType(0); 2367 2368 // fold (cttz c1) -> c2 2369 if (isa<ConstantSDNode>(N0)) 2370 return DAG.getNode(ISD::CTTZ, VT, N0); 2371 return SDOperand(); 2372} 2373 2374SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2375 SDOperand N0 = N->getOperand(0); 2376 MVT::ValueType VT = N->getValueType(0); 2377 2378 // fold (ctpop c1) -> c2 2379 if (isa<ConstantSDNode>(N0)) 2380 return DAG.getNode(ISD::CTPOP, VT, N0); 2381 return SDOperand(); 2382} 2383 2384SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2385 SDOperand N0 = N->getOperand(0); 2386 SDOperand N1 = N->getOperand(1); 2387 SDOperand N2 = N->getOperand(2); 2388 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2390 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2391 MVT::ValueType VT = N->getValueType(0); 2392 MVT::ValueType VT0 = N0.getValueType(); 2393 2394 // fold select C, X, X -> X 2395 if (N1 == N2) 2396 return N1; 2397 // fold select true, X, Y -> X 2398 if (N0C && !N0C->isNullValue()) 2399 return N1; 2400 // fold select false, X, Y -> Y 2401 if (N0C && N0C->isNullValue()) 2402 return N2; 2403 // fold select C, 1, X -> C | X 2404 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2405 return DAG.getNode(ISD::OR, VT, N0, N2); 2406 // fold select C, 0, 1 -> ~C 2407 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2408 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2409 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2410 if (VT == VT0) 2411 return XORNode; 2412 AddToWorkList(XORNode.Val); 2413 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2414 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2415 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2416 } 2417 // fold select C, 0, X -> ~C & X 2418 if (VT == VT0 && N1C && N1C->isNullValue()) { 2419 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2420 AddToWorkList(XORNode.Val); 2421 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2422 } 2423 // fold select C, X, 1 -> ~C | X 2424 if (VT == VT0 && N2C && N2C->getValue() == 1) { 2425 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2426 AddToWorkList(XORNode.Val); 2427 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2428 } 2429 // fold select C, X, 0 -> C & X 2430 // FIXME: this should check for C type == X type, not i1? 2431 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2432 return DAG.getNode(ISD::AND, VT, N0, N1); 2433 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2434 if (MVT::i1 == VT && N0 == N1) 2435 return DAG.getNode(ISD::OR, VT, N0, N2); 2436 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2437 if (MVT::i1 == VT && N0 == N2) 2438 return DAG.getNode(ISD::AND, VT, N0, N1); 2439 2440 // If we can fold this based on the true/false value, do so. 2441 if (SimplifySelectOps(N, N1, N2)) 2442 return SDOperand(N, 0); // Don't revisit N. 2443 2444 // fold selects based on a setcc into other things, such as min/max/abs 2445 if (N0.getOpcode() == ISD::SETCC) 2446 // FIXME: 2447 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2448 // having to say they don't support SELECT_CC on every type the DAG knows 2449 // about, since there is no way to mark an opcode illegal at all value types 2450 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2451 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2452 N1, N2, N0.getOperand(2)); 2453 else 2454 return SimplifySelect(N0, N1, N2); 2455 return SDOperand(); 2456} 2457 2458SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2459 SDOperand N0 = N->getOperand(0); 2460 SDOperand N1 = N->getOperand(1); 2461 SDOperand N2 = N->getOperand(2); 2462 SDOperand N3 = N->getOperand(3); 2463 SDOperand N4 = N->getOperand(4); 2464 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2465 2466 // fold select_cc lhs, rhs, x, x, cc -> x 2467 if (N2 == N3) 2468 return N2; 2469 2470 // Determine if the condition we're dealing with is constant 2471 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2472 if (SCC.Val) AddToWorkList(SCC.Val); 2473 2474 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2475 if (SCCC->getValue()) 2476 return N2; // cond always true -> true val 2477 else 2478 return N3; // cond always false -> false val 2479 } 2480 2481 // Fold to a simpler select_cc 2482 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2483 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2484 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2485 SCC.getOperand(2)); 2486 2487 // If we can fold this based on the true/false value, do so. 2488 if (SimplifySelectOps(N, N2, N3)) 2489 return SDOperand(N, 0); // Don't revisit N. 2490 2491 // fold select_cc into other things, such as min/max/abs 2492 return SimplifySelectCC(N0, N1, N2, N3, CC); 2493} 2494 2495SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2496 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2497 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2498} 2499 2500// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2501// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2502// transformation. Returns true if extension are possible and the above 2503// mentioned transformation is profitable. 2504static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2505 unsigned ExtOpc, 2506 SmallVector<SDNode*, 4> &ExtendNodes, 2507 TargetLowering &TLI) { 2508 bool HasCopyToRegUses = false; 2509 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2510 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2511 UI != UE; ++UI) { 2512 SDNode *User = *UI; 2513 if (User == N) 2514 continue; 2515 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2516 if (User->getOpcode() == ISD::SETCC) { 2517 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2518 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2519 // Sign bits will be lost after a zext. 2520 return false; 2521 bool Add = false; 2522 for (unsigned i = 0; i != 2; ++i) { 2523 SDOperand UseOp = User->getOperand(i); 2524 if (UseOp == N0) 2525 continue; 2526 if (!isa<ConstantSDNode>(UseOp)) 2527 return false; 2528 Add = true; 2529 } 2530 if (Add) 2531 ExtendNodes.push_back(User); 2532 } else { 2533 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2534 SDOperand UseOp = User->getOperand(i); 2535 if (UseOp == N0) { 2536 // If truncate from extended type to original load type is free 2537 // on this target, then it's ok to extend a CopyToReg. 2538 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2539 HasCopyToRegUses = true; 2540 else 2541 return false; 2542 } 2543 } 2544 } 2545 } 2546 2547 if (HasCopyToRegUses) { 2548 bool BothLiveOut = false; 2549 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2550 UI != UE; ++UI) { 2551 SDNode *User = *UI; 2552 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2553 SDOperand UseOp = User->getOperand(i); 2554 if (UseOp.Val == N && UseOp.ResNo == 0) { 2555 BothLiveOut = true; 2556 break; 2557 } 2558 } 2559 } 2560 if (BothLiveOut) 2561 // Both unextended and extended values are live out. There had better be 2562 // good a reason for the transformation. 2563 return ExtendNodes.size(); 2564 } 2565 return true; 2566} 2567 2568SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2569 SDOperand N0 = N->getOperand(0); 2570 MVT::ValueType VT = N->getValueType(0); 2571 2572 // fold (sext c1) -> c1 2573 if (isa<ConstantSDNode>(N0)) 2574 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2575 2576 // fold (sext (sext x)) -> (sext x) 2577 // fold (sext (aext x)) -> (sext x) 2578 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2579 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2580 2581 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2582 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2583 if (N0.getOpcode() == ISD::TRUNCATE) { 2584 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2585 if (NarrowLoad.Val) { 2586 if (NarrowLoad.Val != N0.Val) 2587 CombineTo(N0.Val, NarrowLoad); 2588 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2589 } 2590 } 2591 2592 // See if the value being truncated is already sign extended. If so, just 2593 // eliminate the trunc/sext pair. 2594 if (N0.getOpcode() == ISD::TRUNCATE) { 2595 SDOperand Op = N0.getOperand(0); 2596 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2597 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2598 unsigned DestBits = MVT::getSizeInBits(VT); 2599 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2600 2601 if (OpBits == DestBits) { 2602 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2603 // bits, it is already ready. 2604 if (NumSignBits > DestBits-MidBits) 2605 return Op; 2606 } else if (OpBits < DestBits) { 2607 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2608 // bits, just sext from i32. 2609 if (NumSignBits > OpBits-MidBits) 2610 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2611 } else { 2612 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2613 // bits, just truncate to i32. 2614 if (NumSignBits > OpBits-MidBits) 2615 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2616 } 2617 2618 // fold (sext (truncate x)) -> (sextinreg x). 2619 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2620 N0.getValueType())) { 2621 if (Op.getValueType() < VT) 2622 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2623 else if (Op.getValueType() > VT) 2624 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2625 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2626 DAG.getValueType(N0.getValueType())); 2627 } 2628 } 2629 2630 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2631 if (ISD::isNON_EXTLoad(N0.Val) && 2632 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2633 bool DoXform = true; 2634 SmallVector<SDNode*, 4> SetCCs; 2635 if (!N0.hasOneUse()) 2636 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2637 if (DoXform) { 2638 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2639 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2640 LN0->getBasePtr(), LN0->getSrcValue(), 2641 LN0->getSrcValueOffset(), 2642 N0.getValueType(), 2643 LN0->isVolatile(), 2644 LN0->getAlignment()); 2645 CombineTo(N, ExtLoad); 2646 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2647 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2648 // Extend SetCC uses if necessary. 2649 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2650 SDNode *SetCC = SetCCs[i]; 2651 SmallVector<SDOperand, 4> Ops; 2652 for (unsigned j = 0; j != 2; ++j) { 2653 SDOperand SOp = SetCC->getOperand(j); 2654 if (SOp == Trunc) 2655 Ops.push_back(ExtLoad); 2656 else 2657 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2658 } 2659 Ops.push_back(SetCC->getOperand(2)); 2660 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2661 &Ops[0], Ops.size())); 2662 } 2663 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2664 } 2665 } 2666 2667 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2668 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2669 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2670 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2671 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2672 MVT::ValueType EVT = LN0->getLoadedVT(); 2673 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2674 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2675 LN0->getBasePtr(), LN0->getSrcValue(), 2676 LN0->getSrcValueOffset(), EVT, 2677 LN0->isVolatile(), 2678 LN0->getAlignment()); 2679 CombineTo(N, ExtLoad); 2680 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2681 ExtLoad.getValue(1)); 2682 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2683 } 2684 } 2685 2686 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2687 if (N0.getOpcode() == ISD::SETCC) { 2688 SDOperand SCC = 2689 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2690 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2691 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2692 if (SCC.Val) return SCC; 2693 } 2694 2695 return SDOperand(); 2696} 2697 2698SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2699 SDOperand N0 = N->getOperand(0); 2700 MVT::ValueType VT = N->getValueType(0); 2701 2702 // fold (zext c1) -> c1 2703 if (isa<ConstantSDNode>(N0)) 2704 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2705 // fold (zext (zext x)) -> (zext x) 2706 // fold (zext (aext x)) -> (zext x) 2707 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2708 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2709 2710 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2711 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2712 if (N0.getOpcode() == ISD::TRUNCATE) { 2713 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2714 if (NarrowLoad.Val) { 2715 if (NarrowLoad.Val != N0.Val) 2716 CombineTo(N0.Val, NarrowLoad); 2717 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2718 } 2719 } 2720 2721 // fold (zext (truncate x)) -> (and x, mask) 2722 if (N0.getOpcode() == ISD::TRUNCATE && 2723 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2724 SDOperand Op = N0.getOperand(0); 2725 if (Op.getValueType() < VT) { 2726 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2727 } else if (Op.getValueType() > VT) { 2728 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2729 } 2730 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2731 } 2732 2733 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2734 if (N0.getOpcode() == ISD::AND && 2735 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2736 N0.getOperand(1).getOpcode() == ISD::Constant) { 2737 SDOperand X = N0.getOperand(0).getOperand(0); 2738 if (X.getValueType() < VT) { 2739 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2740 } else if (X.getValueType() > VT) { 2741 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2742 } 2743 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2744 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2745 } 2746 2747 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2748 if (ISD::isNON_EXTLoad(N0.Val) && 2749 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2750 bool DoXform = true; 2751 SmallVector<SDNode*, 4> SetCCs; 2752 if (!N0.hasOneUse()) 2753 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2754 if (DoXform) { 2755 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2756 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2757 LN0->getBasePtr(), LN0->getSrcValue(), 2758 LN0->getSrcValueOffset(), 2759 N0.getValueType(), 2760 LN0->isVolatile(), 2761 LN0->getAlignment()); 2762 CombineTo(N, ExtLoad); 2763 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2764 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2765 // Extend SetCC uses if necessary. 2766 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2767 SDNode *SetCC = SetCCs[i]; 2768 SmallVector<SDOperand, 4> Ops; 2769 for (unsigned j = 0; j != 2; ++j) { 2770 SDOperand SOp = SetCC->getOperand(j); 2771 if (SOp == Trunc) 2772 Ops.push_back(ExtLoad); 2773 else 2774 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2775 } 2776 Ops.push_back(SetCC->getOperand(2)); 2777 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2778 &Ops[0], Ops.size())); 2779 } 2780 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2781 } 2782 } 2783 2784 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2785 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2786 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2787 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2788 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2789 MVT::ValueType EVT = LN0->getLoadedVT(); 2790 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2791 LN0->getBasePtr(), LN0->getSrcValue(), 2792 LN0->getSrcValueOffset(), EVT, 2793 LN0->isVolatile(), 2794 LN0->getAlignment()); 2795 CombineTo(N, ExtLoad); 2796 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2797 ExtLoad.getValue(1)); 2798 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2799 } 2800 2801 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2802 if (N0.getOpcode() == ISD::SETCC) { 2803 SDOperand SCC = 2804 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2805 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2806 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2807 if (SCC.Val) return SCC; 2808 } 2809 2810 return SDOperand(); 2811} 2812 2813SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2814 SDOperand N0 = N->getOperand(0); 2815 MVT::ValueType VT = N->getValueType(0); 2816 2817 // fold (aext c1) -> c1 2818 if (isa<ConstantSDNode>(N0)) 2819 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2820 // fold (aext (aext x)) -> (aext x) 2821 // fold (aext (zext x)) -> (zext x) 2822 // fold (aext (sext x)) -> (sext x) 2823 if (N0.getOpcode() == ISD::ANY_EXTEND || 2824 N0.getOpcode() == ISD::ZERO_EXTEND || 2825 N0.getOpcode() == ISD::SIGN_EXTEND) 2826 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2827 2828 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2829 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2830 if (N0.getOpcode() == ISD::TRUNCATE) { 2831 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2832 if (NarrowLoad.Val) { 2833 if (NarrowLoad.Val != N0.Val) 2834 CombineTo(N0.Val, NarrowLoad); 2835 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2836 } 2837 } 2838 2839 // fold (aext (truncate x)) 2840 if (N0.getOpcode() == ISD::TRUNCATE) { 2841 SDOperand TruncOp = N0.getOperand(0); 2842 if (TruncOp.getValueType() == VT) 2843 return TruncOp; // x iff x size == zext size. 2844 if (TruncOp.getValueType() > VT) 2845 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2846 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2847 } 2848 2849 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2850 if (N0.getOpcode() == ISD::AND && 2851 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2852 N0.getOperand(1).getOpcode() == ISD::Constant) { 2853 SDOperand X = N0.getOperand(0).getOperand(0); 2854 if (X.getValueType() < VT) { 2855 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2856 } else if (X.getValueType() > VT) { 2857 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2858 } 2859 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2860 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2861 } 2862 2863 // fold (aext (load x)) -> (aext (truncate (extload x))) 2864 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2865 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2866 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2867 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2868 LN0->getBasePtr(), LN0->getSrcValue(), 2869 LN0->getSrcValueOffset(), 2870 N0.getValueType(), 2871 LN0->isVolatile(), 2872 LN0->getAlignment()); 2873 CombineTo(N, ExtLoad); 2874 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2875 ExtLoad.getValue(1)); 2876 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2877 } 2878 2879 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2880 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2881 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2882 if (N0.getOpcode() == ISD::LOAD && 2883 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2884 N0.hasOneUse()) { 2885 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2886 MVT::ValueType EVT = LN0->getLoadedVT(); 2887 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2888 LN0->getChain(), LN0->getBasePtr(), 2889 LN0->getSrcValue(), 2890 LN0->getSrcValueOffset(), EVT, 2891 LN0->isVolatile(), 2892 LN0->getAlignment()); 2893 CombineTo(N, ExtLoad); 2894 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2895 ExtLoad.getValue(1)); 2896 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2897 } 2898 2899 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2900 if (N0.getOpcode() == ISD::SETCC) { 2901 SDOperand SCC = 2902 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2903 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2904 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2905 if (SCC.Val) 2906 return SCC; 2907 } 2908 2909 return SDOperand(); 2910} 2911 2912/// GetDemandedBits - See if the specified operand can be simplified with the 2913/// knowledge that only the bits specified by Mask are used. If so, return the 2914/// simpler operand, otherwise return a null SDOperand. 2915SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 2916 switch (V.getOpcode()) { 2917 default: break; 2918 case ISD::OR: 2919 case ISD::XOR: 2920 // If the LHS or RHS don't contribute bits to the or, drop them. 2921 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 2922 return V.getOperand(1); 2923 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 2924 return V.getOperand(0); 2925 break; 2926 case ISD::SRL: 2927 // Only look at single-use SRLs. 2928 if (!V.Val->hasOneUse()) 2929 break; 2930 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 2931 // See if we can recursively simplify the LHS. 2932 unsigned Amt = RHSC->getValue(); 2933 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 2934 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 2935 if (SimplifyLHS.Val) { 2936 return DAG.getNode(ISD::SRL, V.getValueType(), 2937 SimplifyLHS, V.getOperand(1)); 2938 } 2939 } 2940 } 2941 return SDOperand(); 2942} 2943 2944/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 2945/// bits and then truncated to a narrower type and where N is a multiple 2946/// of number of bits of the narrower type, transform it to a narrower load 2947/// from address + N / num of bits of new type. If the result is to be 2948/// extended, also fold the extension to form a extending load. 2949SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 2950 unsigned Opc = N->getOpcode(); 2951 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 2952 SDOperand N0 = N->getOperand(0); 2953 MVT::ValueType VT = N->getValueType(0); 2954 MVT::ValueType EVT = N->getValueType(0); 2955 2956 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 2957 // extended to VT. 2958 if (Opc == ISD::SIGN_EXTEND_INREG) { 2959 ExtType = ISD::SEXTLOAD; 2960 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2961 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 2962 return SDOperand(); 2963 } 2964 2965 unsigned EVTBits = MVT::getSizeInBits(EVT); 2966 unsigned ShAmt = 0; 2967 bool CombineSRL = false; 2968 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 2969 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2970 ShAmt = N01->getValue(); 2971 // Is the shift amount a multiple of size of VT? 2972 if ((ShAmt & (EVTBits-1)) == 0) { 2973 N0 = N0.getOperand(0); 2974 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 2975 return SDOperand(); 2976 CombineSRL = true; 2977 } 2978 } 2979 } 2980 2981 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2982 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2983 // zero extended form: by shrinking the load, we lose track of the fact 2984 // that it is already zero extended. 2985 // FIXME: This should be reevaluated. 2986 VT != MVT::i1) { 2987 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 2988 "Cannot truncate to larger type!"); 2989 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2990 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2991 // For big endian targets, we need to adjust the offset to the pointer to 2992 // load the correct bytes. 2993 if (!TLI.isLittleEndian()) 2994 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; 2995 uint64_t PtrOff = ShAmt / 8; 2996 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 2997 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2998 DAG.getConstant(PtrOff, PtrType)); 2999 AddToWorkList(NewPtr.Val); 3000 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3001 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3002 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3003 LN0->isVolatile(), NewAlign) 3004 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3005 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3006 LN0->isVolatile(), NewAlign); 3007 AddToWorkList(N); 3008 if (CombineSRL) { 3009 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 3010 CombineTo(N->getOperand(0).Val, Load); 3011 } else 3012 CombineTo(N0.Val, Load, Load.getValue(1)); 3013 if (ShAmt) { 3014 if (Opc == ISD::SIGN_EXTEND_INREG) 3015 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3016 else 3017 return DAG.getNode(Opc, VT, Load); 3018 } 3019 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3020 } 3021 3022 return SDOperand(); 3023} 3024 3025 3026SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3027 SDOperand N0 = N->getOperand(0); 3028 SDOperand N1 = N->getOperand(1); 3029 MVT::ValueType VT = N->getValueType(0); 3030 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3031 unsigned EVTBits = MVT::getSizeInBits(EVT); 3032 3033 // fold (sext_in_reg c1) -> c1 3034 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3035 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3036 3037 // If the input is already sign extended, just drop the extension. 3038 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3039 return N0; 3040 3041 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3042 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3043 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3044 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3045 } 3046 3047 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3048 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3049 return DAG.getZeroExtendInReg(N0, EVT); 3050 3051 // fold operands of sext_in_reg based on knowledge that the top bits are not 3052 // demanded. 3053 if (SimplifyDemandedBits(SDOperand(N, 0))) 3054 return SDOperand(N, 0); 3055 3056 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3057 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3058 SDOperand NarrowLoad = ReduceLoadWidth(N); 3059 if (NarrowLoad.Val) 3060 return NarrowLoad; 3061 3062 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3063 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3064 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3065 if (N0.getOpcode() == ISD::SRL) { 3066 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3067 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3068 // We can turn this into an SRA iff the input to the SRL is already sign 3069 // extended enough. 3070 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3071 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3072 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3073 } 3074 } 3075 3076 // fold (sext_inreg (extload x)) -> (sextload x) 3077 if (ISD::isEXTLoad(N0.Val) && 3078 ISD::isUNINDEXEDLoad(N0.Val) && 3079 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3080 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3081 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3082 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3083 LN0->getBasePtr(), LN0->getSrcValue(), 3084 LN0->getSrcValueOffset(), EVT, 3085 LN0->isVolatile(), 3086 LN0->getAlignment()); 3087 CombineTo(N, ExtLoad); 3088 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3089 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3090 } 3091 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3092 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3093 N0.hasOneUse() && 3094 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 3095 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3096 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3097 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3098 LN0->getBasePtr(), LN0->getSrcValue(), 3099 LN0->getSrcValueOffset(), EVT, 3100 LN0->isVolatile(), 3101 LN0->getAlignment()); 3102 CombineTo(N, ExtLoad); 3103 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3104 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3105 } 3106 return SDOperand(); 3107} 3108 3109SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3110 SDOperand N0 = N->getOperand(0); 3111 MVT::ValueType VT = N->getValueType(0); 3112 3113 // noop truncate 3114 if (N0.getValueType() == N->getValueType(0)) 3115 return N0; 3116 // fold (truncate c1) -> c1 3117 if (isa<ConstantSDNode>(N0)) 3118 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3119 // fold (truncate (truncate x)) -> (truncate x) 3120 if (N0.getOpcode() == ISD::TRUNCATE) 3121 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3122 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3123 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3124 N0.getOpcode() == ISD::ANY_EXTEND) { 3125 if (N0.getOperand(0).getValueType() < VT) 3126 // if the source is smaller than the dest, we still need an extend 3127 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3128 else if (N0.getOperand(0).getValueType() > VT) 3129 // if the source is larger than the dest, than we just need the truncate 3130 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3131 else 3132 // if the source and dest are the same type, we can drop both the extend 3133 // and the truncate 3134 return N0.getOperand(0); 3135 } 3136 3137 // See if we can simplify the input to this truncate through knowledge that 3138 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3139 // -> trunc y 3140 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3141 if (Shorter.Val) 3142 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3143 3144 // fold (truncate (load x)) -> (smaller load x) 3145 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3146 return ReduceLoadWidth(N); 3147} 3148 3149SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3150 SDOperand N0 = N->getOperand(0); 3151 MVT::ValueType VT = N->getValueType(0); 3152 3153 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3154 // Only do this before legalize, since afterward the target may be depending 3155 // on the bitconvert. 3156 // First check to see if this is all constant. 3157 if (!AfterLegalize && 3158 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3159 MVT::isVector(VT)) { 3160 bool isSimple = true; 3161 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3162 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3163 N0.getOperand(i).getOpcode() != ISD::Constant && 3164 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3165 isSimple = false; 3166 break; 3167 } 3168 3169 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3170 assert(!MVT::isVector(DestEltVT) && 3171 "Element type of vector ValueType must not be vector!"); 3172 if (isSimple) { 3173 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3174 } 3175 } 3176 3177 // If the input is a constant, let getNode() fold it. 3178 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3179 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3180 if (Res.Val != N) return Res; 3181 } 3182 3183 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3184 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3185 3186 // fold (conv (load x)) -> (load (conv*)x) 3187 // If the resultant load doesn't need a higher alignment than the original! 3188 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3189 TLI.isOperationLegal(ISD::LOAD, VT)) { 3190 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3191 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3192 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3193 unsigned OrigAlign = LN0->getAlignment(); 3194 if (Align <= OrigAlign) { 3195 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3196 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3197 LN0->isVolatile(), Align); 3198 AddToWorkList(N); 3199 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3200 Load.getValue(1)); 3201 return Load; 3202 } 3203 } 3204 3205 return SDOperand(); 3206} 3207 3208/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3209/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3210/// destination element value type. 3211SDOperand DAGCombiner:: 3212ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3213 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3214 3215 // If this is already the right type, we're done. 3216 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3217 3218 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3219 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3220 3221 // If this is a conversion of N elements of one type to N elements of another 3222 // type, convert each element. This handles FP<->INT cases. 3223 if (SrcBitSize == DstBitSize) { 3224 SmallVector<SDOperand, 8> Ops; 3225 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3226 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3227 AddToWorkList(Ops.back().Val); 3228 } 3229 MVT::ValueType VT = 3230 MVT::getVectorType(DstEltVT, 3231 MVT::getVectorNumElements(BV->getValueType(0))); 3232 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3233 } 3234 3235 // Otherwise, we're growing or shrinking the elements. To avoid having to 3236 // handle annoying details of growing/shrinking FP values, we convert them to 3237 // int first. 3238 if (MVT::isFloatingPoint(SrcEltVT)) { 3239 // Convert the input float vector to a int vector where the elements are the 3240 // same sizes. 3241 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3242 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3243 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3244 SrcEltVT = IntVT; 3245 } 3246 3247 // Now we know the input is an integer vector. If the output is a FP type, 3248 // convert to integer first, then to FP of the right size. 3249 if (MVT::isFloatingPoint(DstEltVT)) { 3250 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3251 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3252 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3253 3254 // Next, convert to FP elements of the same size. 3255 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3256 } 3257 3258 // Okay, we know the src/dst types are both integers of differing types. 3259 // Handling growing first. 3260 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3261 if (SrcBitSize < DstBitSize) { 3262 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3263 3264 SmallVector<SDOperand, 8> Ops; 3265 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3266 i += NumInputsPerOutput) { 3267 bool isLE = TLI.isLittleEndian(); 3268 uint64_t NewBits = 0; 3269 bool EltIsUndef = true; 3270 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3271 // Shift the previously computed bits over. 3272 NewBits <<= SrcBitSize; 3273 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3274 if (Op.getOpcode() == ISD::UNDEF) continue; 3275 EltIsUndef = false; 3276 3277 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3278 } 3279 3280 if (EltIsUndef) 3281 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3282 else 3283 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3284 } 3285 3286 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3287 Ops.size()); 3288 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3289 } 3290 3291 // Finally, this must be the case where we are shrinking elements: each input 3292 // turns into multiple outputs. 3293 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3294 SmallVector<SDOperand, 8> Ops; 3295 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3296 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3297 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3298 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3299 continue; 3300 } 3301 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3302 3303 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3304 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3305 OpVal >>= DstBitSize; 3306 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3307 } 3308 3309 // For big endian targets, swap the order of the pieces of each element. 3310 if (!TLI.isLittleEndian()) 3311 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3312 } 3313 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3314 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3315} 3316 3317 3318 3319SDOperand DAGCombiner::visitFADD(SDNode *N) { 3320 SDOperand N0 = N->getOperand(0); 3321 SDOperand N1 = N->getOperand(1); 3322 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3323 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3324 MVT::ValueType VT = N->getValueType(0); 3325 3326 // fold vector ops 3327 if (MVT::isVector(VT)) { 3328 SDOperand FoldedVOp = SimplifyVBinOp(N); 3329 if (FoldedVOp.Val) return FoldedVOp; 3330 } 3331 3332 // fold (fadd c1, c2) -> c1+c2 3333 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3334 return DAG.getNode(ISD::FADD, VT, N0, N1); 3335 // canonicalize constant to RHS 3336 if (N0CFP && !N1CFP) 3337 return DAG.getNode(ISD::FADD, VT, N1, N0); 3338 // fold (A + (-B)) -> A-B 3339 if (isNegatibleForFree(N1) == 2) 3340 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3341 // fold ((-A) + B) -> B-A 3342 if (isNegatibleForFree(N0) == 2) 3343 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3344 3345 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3346 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3347 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3348 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3349 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3350 3351 return SDOperand(); 3352} 3353 3354SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3355 SDOperand N0 = N->getOperand(0); 3356 SDOperand N1 = N->getOperand(1); 3357 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3358 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3359 MVT::ValueType VT = N->getValueType(0); 3360 3361 // fold vector ops 3362 if (MVT::isVector(VT)) { 3363 SDOperand FoldedVOp = SimplifyVBinOp(N); 3364 if (FoldedVOp.Val) return FoldedVOp; 3365 } 3366 3367 // fold (fsub c1, c2) -> c1-c2 3368 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3369 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3370 // fold (0-B) -> -B 3371 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3372 if (isNegatibleForFree(N1)) 3373 return GetNegatedExpression(N1, DAG); 3374 return DAG.getNode(ISD::FNEG, VT, N1); 3375 } 3376 // fold (A-(-B)) -> A+B 3377 if (isNegatibleForFree(N1)) 3378 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3379 3380 return SDOperand(); 3381} 3382 3383SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3384 SDOperand N0 = N->getOperand(0); 3385 SDOperand N1 = N->getOperand(1); 3386 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3387 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3388 MVT::ValueType VT = N->getValueType(0); 3389 3390 // fold vector ops 3391 if (MVT::isVector(VT)) { 3392 SDOperand FoldedVOp = SimplifyVBinOp(N); 3393 if (FoldedVOp.Val) return FoldedVOp; 3394 } 3395 3396 // fold (fmul c1, c2) -> c1*c2 3397 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3398 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3399 // canonicalize constant to RHS 3400 if (N0CFP && !N1CFP) 3401 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3402 // fold (fmul X, 2.0) -> (fadd X, X) 3403 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3404 return DAG.getNode(ISD::FADD, VT, N0, N0); 3405 // fold (fmul X, -1.0) -> (fneg X) 3406 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3407 return DAG.getNode(ISD::FNEG, VT, N0); 3408 3409 // -X * -Y -> X*Y 3410 if (char LHSNeg = isNegatibleForFree(N0)) { 3411 if (char RHSNeg = isNegatibleForFree(N1)) { 3412 // Both can be negated for free, check to see if at least one is cheaper 3413 // negated. 3414 if (LHSNeg == 2 || RHSNeg == 2) 3415 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3416 GetNegatedExpression(N1, DAG)); 3417 } 3418 } 3419 3420 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3421 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3422 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3423 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3424 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3425 3426 return SDOperand(); 3427} 3428 3429SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3430 SDOperand N0 = N->getOperand(0); 3431 SDOperand N1 = N->getOperand(1); 3432 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3433 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3434 MVT::ValueType VT = N->getValueType(0); 3435 3436 // fold vector ops 3437 if (MVT::isVector(VT)) { 3438 SDOperand FoldedVOp = SimplifyVBinOp(N); 3439 if (FoldedVOp.Val) return FoldedVOp; 3440 } 3441 3442 // fold (fdiv c1, c2) -> c1/c2 3443 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3444 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3445 3446 3447 // -X / -Y -> X*Y 3448 if (char LHSNeg = isNegatibleForFree(N0)) { 3449 if (char RHSNeg = isNegatibleForFree(N1)) { 3450 // Both can be negated for free, check to see if at least one is cheaper 3451 // negated. 3452 if (LHSNeg == 2 || RHSNeg == 2) 3453 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3454 GetNegatedExpression(N1, DAG)); 3455 } 3456 } 3457 3458 return SDOperand(); 3459} 3460 3461SDOperand DAGCombiner::visitFREM(SDNode *N) { 3462 SDOperand N0 = N->getOperand(0); 3463 SDOperand N1 = N->getOperand(1); 3464 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3465 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3466 MVT::ValueType VT = N->getValueType(0); 3467 3468 // fold (frem c1, c2) -> fmod(c1,c2) 3469 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3470 return DAG.getNode(ISD::FREM, VT, N0, N1); 3471 3472 return SDOperand(); 3473} 3474 3475SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3476 SDOperand N0 = N->getOperand(0); 3477 SDOperand N1 = N->getOperand(1); 3478 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3479 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3480 MVT::ValueType VT = N->getValueType(0); 3481 3482 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3483 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3484 3485 if (N1CFP) { 3486 const APFloat& V = N1CFP->getValueAPF(); 3487 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3488 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3489 if (!V.isNegative()) 3490 return DAG.getNode(ISD::FABS, VT, N0); 3491 else 3492 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3493 } 3494 3495 // copysign(fabs(x), y) -> copysign(x, y) 3496 // copysign(fneg(x), y) -> copysign(x, y) 3497 // copysign(copysign(x,z), y) -> copysign(x, y) 3498 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3499 N0.getOpcode() == ISD::FCOPYSIGN) 3500 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3501 3502 // copysign(x, abs(y)) -> abs(x) 3503 if (N1.getOpcode() == ISD::FABS) 3504 return DAG.getNode(ISD::FABS, VT, N0); 3505 3506 // copysign(x, copysign(y,z)) -> copysign(x, z) 3507 if (N1.getOpcode() == ISD::FCOPYSIGN) 3508 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3509 3510 // copysign(x, fp_extend(y)) -> copysign(x, y) 3511 // copysign(x, fp_round(y)) -> copysign(x, y) 3512 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3513 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3514 3515 return SDOperand(); 3516} 3517 3518 3519 3520SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3521 SDOperand N0 = N->getOperand(0); 3522 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3523 MVT::ValueType VT = N->getValueType(0); 3524 3525 // fold (sint_to_fp c1) -> c1fp 3526 if (N0C && N0.getValueType() != MVT::ppcf128) 3527 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3528 return SDOperand(); 3529} 3530 3531SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3532 SDOperand N0 = N->getOperand(0); 3533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3534 MVT::ValueType VT = N->getValueType(0); 3535 3536 // fold (uint_to_fp c1) -> c1fp 3537 if (N0C && N0.getValueType() != MVT::ppcf128) 3538 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3539 return SDOperand(); 3540} 3541 3542SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3543 SDOperand N0 = N->getOperand(0); 3544 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3545 MVT::ValueType VT = N->getValueType(0); 3546 3547 // fold (fp_to_sint c1fp) -> c1 3548 if (N0CFP) 3549 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3550 return SDOperand(); 3551} 3552 3553SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3554 SDOperand N0 = N->getOperand(0); 3555 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3556 MVT::ValueType VT = N->getValueType(0); 3557 3558 // fold (fp_to_uint c1fp) -> c1 3559 if (N0CFP && VT != MVT::ppcf128) 3560 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3561 return SDOperand(); 3562} 3563 3564SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3565 SDOperand N0 = N->getOperand(0); 3566 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3567 MVT::ValueType VT = N->getValueType(0); 3568 3569 // fold (fp_round c1fp) -> c1fp 3570 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3571 return DAG.getNode(ISD::FP_ROUND, VT, N0); 3572 3573 // fold (fp_round (fp_extend x)) -> x 3574 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3575 return N0.getOperand(0); 3576 3577 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3578 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3579 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 3580 AddToWorkList(Tmp.Val); 3581 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3582 } 3583 3584 return SDOperand(); 3585} 3586 3587SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3588 SDOperand N0 = N->getOperand(0); 3589 MVT::ValueType VT = N->getValueType(0); 3590 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3591 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3592 3593 // fold (fp_round_inreg c1fp) -> c1fp 3594 if (N0CFP) { 3595 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3596 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3597 } 3598 return SDOperand(); 3599} 3600 3601SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3602 SDOperand N0 = N->getOperand(0); 3603 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3604 MVT::ValueType VT = N->getValueType(0); 3605 3606 // fold (fp_extend c1fp) -> c1fp 3607 if (N0CFP && VT != MVT::ppcf128) 3608 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3609 3610 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 3611 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3612 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3613 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3614 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3615 LN0->getBasePtr(), LN0->getSrcValue(), 3616 LN0->getSrcValueOffset(), 3617 N0.getValueType(), 3618 LN0->isVolatile(), 3619 LN0->getAlignment()); 3620 CombineTo(N, ExtLoad); 3621 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 3622 ExtLoad.getValue(1)); 3623 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3624 } 3625 3626 3627 return SDOperand(); 3628} 3629 3630SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3631 SDOperand N0 = N->getOperand(0); 3632 3633 if (isNegatibleForFree(N0)) 3634 return GetNegatedExpression(N0, DAG); 3635 3636 return SDOperand(); 3637} 3638 3639SDOperand DAGCombiner::visitFABS(SDNode *N) { 3640 SDOperand N0 = N->getOperand(0); 3641 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3642 MVT::ValueType VT = N->getValueType(0); 3643 3644 // fold (fabs c1) -> fabs(c1) 3645 if (N0CFP && VT != MVT::ppcf128) 3646 return DAG.getNode(ISD::FABS, VT, N0); 3647 // fold (fabs (fabs x)) -> (fabs x) 3648 if (N0.getOpcode() == ISD::FABS) 3649 return N->getOperand(0); 3650 // fold (fabs (fneg x)) -> (fabs x) 3651 // fold (fabs (fcopysign x, y)) -> (fabs x) 3652 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3653 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3654 3655 return SDOperand(); 3656} 3657 3658SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3659 SDOperand Chain = N->getOperand(0); 3660 SDOperand N1 = N->getOperand(1); 3661 SDOperand N2 = N->getOperand(2); 3662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3663 3664 // never taken branch, fold to chain 3665 if (N1C && N1C->isNullValue()) 3666 return Chain; 3667 // unconditional branch 3668 if (N1C && N1C->getValue() == 1) 3669 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3670 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3671 // on the target. 3672 if (N1.getOpcode() == ISD::SETCC && 3673 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3674 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3675 N1.getOperand(0), N1.getOperand(1), N2); 3676 } 3677 return SDOperand(); 3678} 3679 3680// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3681// 3682SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3683 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3684 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3685 3686 // Use SimplifySetCC to simplify SETCC's. 3687 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3688 if (Simp.Val) AddToWorkList(Simp.Val); 3689 3690 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3691 3692 // fold br_cc true, dest -> br dest (unconditional branch) 3693 if (SCCC && SCCC->getValue()) 3694 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3695 N->getOperand(4)); 3696 // fold br_cc false, dest -> unconditional fall through 3697 if (SCCC && SCCC->isNullValue()) 3698 return N->getOperand(0); 3699 3700 // fold to a simpler setcc 3701 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3702 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3703 Simp.getOperand(2), Simp.getOperand(0), 3704 Simp.getOperand(1), N->getOperand(4)); 3705 return SDOperand(); 3706} 3707 3708 3709/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3710/// pre-indexed load / store when the base pointer is a add or subtract 3711/// and it has other uses besides the load / store. After the 3712/// transformation, the new indexed load / store has effectively folded 3713/// the add / subtract in and all of its other uses are redirected to the 3714/// new load / store. 3715bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3716 if (!AfterLegalize) 3717 return false; 3718 3719 bool isLoad = true; 3720 SDOperand Ptr; 3721 MVT::ValueType VT; 3722 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3723 if (LD->getAddressingMode() != ISD::UNINDEXED) 3724 return false; 3725 VT = LD->getLoadedVT(); 3726 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3727 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3728 return false; 3729 Ptr = LD->getBasePtr(); 3730 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3731 if (ST->getAddressingMode() != ISD::UNINDEXED) 3732 return false; 3733 VT = ST->getStoredVT(); 3734 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3735 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3736 return false; 3737 Ptr = ST->getBasePtr(); 3738 isLoad = false; 3739 } else 3740 return false; 3741 3742 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3743 // out. There is no reason to make this a preinc/predec. 3744 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3745 Ptr.Val->hasOneUse()) 3746 return false; 3747 3748 // Ask the target to do addressing mode selection. 3749 SDOperand BasePtr; 3750 SDOperand Offset; 3751 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3752 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3753 return false; 3754 // Don't create a indexed load / store with zero offset. 3755 if (isa<ConstantSDNode>(Offset) && 3756 cast<ConstantSDNode>(Offset)->getValue() == 0) 3757 return false; 3758 3759 // Try turning it into a pre-indexed load / store except when: 3760 // 1) The new base ptr is a frame index. 3761 // 2) If N is a store and the new base ptr is either the same as or is a 3762 // predecessor of the value being stored. 3763 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3764 // that would create a cycle. 3765 // 4) All uses are load / store ops that use it as old base ptr. 3766 3767 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3768 // (plus the implicit offset) to a register to preinc anyway. 3769 if (isa<FrameIndexSDNode>(BasePtr)) 3770 return false; 3771 3772 // Check #2. 3773 if (!isLoad) { 3774 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3775 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3776 return false; 3777 } 3778 3779 // Now check for #3 and #4. 3780 bool RealUse = false; 3781 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3782 E = Ptr.Val->use_end(); I != E; ++I) { 3783 SDNode *Use = *I; 3784 if (Use == N) 3785 continue; 3786 if (Use->isPredecessor(N)) 3787 return false; 3788 3789 if (!((Use->getOpcode() == ISD::LOAD && 3790 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 3791 (Use->getOpcode() == ISD::STORE) && 3792 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 3793 RealUse = true; 3794 } 3795 if (!RealUse) 3796 return false; 3797 3798 SDOperand Result; 3799 if (isLoad) 3800 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 3801 else 3802 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3803 ++PreIndexedNodes; 3804 ++NodesCombined; 3805 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 3806 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3807 DOUT << '\n'; 3808 std::vector<SDNode*> NowDead; 3809 if (isLoad) { 3810 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3811 &NowDead); 3812 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3813 &NowDead); 3814 } else { 3815 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3816 &NowDead); 3817 } 3818 3819 // Nodes can end up on the worklist more than once. Make sure we do 3820 // not process a node that has been replaced. 3821 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3822 removeFromWorkList(NowDead[i]); 3823 // Finally, since the node is now dead, remove it from the graph. 3824 DAG.DeleteNode(N); 3825 3826 // Replace the uses of Ptr with uses of the updated base value. 3827 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 3828 &NowDead); 3829 removeFromWorkList(Ptr.Val); 3830 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3831 removeFromWorkList(NowDead[i]); 3832 DAG.DeleteNode(Ptr.Val); 3833 3834 return true; 3835} 3836 3837/// CombineToPostIndexedLoadStore - Try combine a load / store with a 3838/// add / sub of the base pointer node into a post-indexed load / store. 3839/// The transformation folded the add / subtract into the new indexed 3840/// load / store effectively and all of its uses are redirected to the 3841/// new load / store. 3842bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 3843 if (!AfterLegalize) 3844 return false; 3845 3846 bool isLoad = true; 3847 SDOperand Ptr; 3848 MVT::ValueType VT; 3849 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3850 if (LD->getAddressingMode() != ISD::UNINDEXED) 3851 return false; 3852 VT = LD->getLoadedVT(); 3853 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 3854 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 3855 return false; 3856 Ptr = LD->getBasePtr(); 3857 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3858 if (ST->getAddressingMode() != ISD::UNINDEXED) 3859 return false; 3860 VT = ST->getStoredVT(); 3861 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 3862 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 3863 return false; 3864 Ptr = ST->getBasePtr(); 3865 isLoad = false; 3866 } else 3867 return false; 3868 3869 if (Ptr.Val->hasOneUse()) 3870 return false; 3871 3872 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 3873 E = Ptr.Val->use_end(); I != E; ++I) { 3874 SDNode *Op = *I; 3875 if (Op == N || 3876 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 3877 continue; 3878 3879 SDOperand BasePtr; 3880 SDOperand Offset; 3881 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3882 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3883 if (Ptr == Offset) 3884 std::swap(BasePtr, Offset); 3885 if (Ptr != BasePtr) 3886 continue; 3887 // Don't create a indexed load / store with zero offset. 3888 if (isa<ConstantSDNode>(Offset) && 3889 cast<ConstantSDNode>(Offset)->getValue() == 0) 3890 continue; 3891 3892 // Try turning it into a post-indexed load / store except when 3893 // 1) All uses are load / store ops that use it as base ptr. 3894 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3895 // nor a successor of N. Otherwise, if Op is folded that would 3896 // create a cycle. 3897 3898 // Check for #1. 3899 bool TryNext = false; 3900 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3901 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3902 SDNode *Use = *II; 3903 if (Use == Ptr.Val) 3904 continue; 3905 3906 // If all the uses are load / store addresses, then don't do the 3907 // transformation. 3908 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3909 bool RealUse = false; 3910 for (SDNode::use_iterator III = Use->use_begin(), 3911 EEE = Use->use_end(); III != EEE; ++III) { 3912 SDNode *UseUse = *III; 3913 if (!((UseUse->getOpcode() == ISD::LOAD && 3914 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3915 (UseUse->getOpcode() == ISD::STORE) && 3916 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3917 RealUse = true; 3918 } 3919 3920 if (!RealUse) { 3921 TryNext = true; 3922 break; 3923 } 3924 } 3925 } 3926 if (TryNext) 3927 continue; 3928 3929 // Check for #2 3930 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3931 SDOperand Result = isLoad 3932 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3933 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3934 ++PostIndexedNodes; 3935 ++NodesCombined; 3936 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 3937 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3938 DOUT << '\n'; 3939 std::vector<SDNode*> NowDead; 3940 if (isLoad) { 3941 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3942 &NowDead); 3943 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3944 &NowDead); 3945 } else { 3946 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3947 &NowDead); 3948 } 3949 3950 // Nodes can end up on the worklist more than once. Make sure we do 3951 // not process a node that has been replaced. 3952 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3953 removeFromWorkList(NowDead[i]); 3954 // Finally, since the node is now dead, remove it from the graph. 3955 DAG.DeleteNode(N); 3956 3957 // Replace the uses of Use with uses of the updated base value. 3958 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3959 Result.getValue(isLoad ? 1 : 0), 3960 &NowDead); 3961 removeFromWorkList(Op); 3962 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3963 removeFromWorkList(NowDead[i]); 3964 DAG.DeleteNode(Op); 3965 3966 return true; 3967 } 3968 } 3969 } 3970 return false; 3971} 3972 3973 3974SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3975 LoadSDNode *LD = cast<LoadSDNode>(N); 3976 SDOperand Chain = LD->getChain(); 3977 SDOperand Ptr = LD->getBasePtr(); 3978 3979 // If load is not volatile and there are no uses of the loaded value (and 3980 // the updated indexed value in case of indexed loads), change uses of the 3981 // chain value into uses of the chain input (i.e. delete the dead load). 3982 if (!LD->isVolatile()) { 3983 if (N->getValueType(1) == MVT::Other) { 3984 // Unindexed loads. 3985 if (N->hasNUsesOfValue(0, 0)) 3986 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3987 } else { 3988 // Indexed loads. 3989 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 3990 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 3991 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3992 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1)); 3993 SDOperand To[] = { Undef0, Undef1, Chain }; 3994 return CombineTo(N, To, 3); 3995 } 3996 } 3997 } 3998 3999 // If this load is directly stored, replace the load value with the stored 4000 // value. 4001 // TODO: Handle store large -> read small portion. 4002 // TODO: Handle TRUNCSTORE/LOADEXT 4003 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4004 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4005 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4006 if (PrevST->getBasePtr() == Ptr && 4007 PrevST->getValue().getValueType() == N->getValueType(0)) 4008 return CombineTo(N, Chain.getOperand(1), Chain); 4009 } 4010 } 4011 4012 if (CombinerAA) { 4013 // Walk up chain skipping non-aliasing memory nodes. 4014 SDOperand BetterChain = FindBetterChain(N, Chain); 4015 4016 // If there is a better chain. 4017 if (Chain != BetterChain) { 4018 SDOperand ReplLoad; 4019 4020 // Replace the chain to void dependency. 4021 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4022 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4023 LD->getSrcValue(), LD->getSrcValueOffset(), 4024 LD->isVolatile(), LD->getAlignment()); 4025 } else { 4026 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4027 LD->getValueType(0), 4028 BetterChain, Ptr, LD->getSrcValue(), 4029 LD->getSrcValueOffset(), 4030 LD->getLoadedVT(), 4031 LD->isVolatile(), 4032 LD->getAlignment()); 4033 } 4034 4035 // Create token factor to keep old chain connected. 4036 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4037 Chain, ReplLoad.getValue(1)); 4038 4039 // Replace uses with load result and token factor. Don't add users 4040 // to work list. 4041 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4042 } 4043 } 4044 4045 // Try transforming N to an indexed load. 4046 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4047 return SDOperand(N, 0); 4048 4049 return SDOperand(); 4050} 4051 4052SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4053 StoreSDNode *ST = cast<StoreSDNode>(N); 4054 SDOperand Chain = ST->getChain(); 4055 SDOperand Value = ST->getValue(); 4056 SDOperand Ptr = ST->getBasePtr(); 4057 4058 // If this is a store of a bit convert, store the input value if the 4059 // resultant store does not need a higher alignment than the original. 4060 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4061 ST->getAddressingMode() == ISD::UNINDEXED) { 4062 unsigned Align = ST->getAlignment(); 4063 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4064 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4065 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4066 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4067 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4068 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4069 } 4070 4071 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4072 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4073 if (Value.getOpcode() != ISD::TargetConstantFP) { 4074 SDOperand Tmp; 4075 switch (CFP->getValueType(0)) { 4076 default: assert(0 && "Unknown FP type"); 4077 case MVT::f80: // We don't do this for these yet. 4078 case MVT::f128: 4079 case MVT::ppcf128: 4080 break; 4081 case MVT::f32: 4082 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4083 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4084 convertToAPInt().getZExtValue(), MVT::i32); 4085 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4086 ST->getSrcValueOffset(), ST->isVolatile(), 4087 ST->getAlignment()); 4088 } 4089 break; 4090 case MVT::f64: 4091 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4092 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4093 getZExtValue(), MVT::i64); 4094 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4095 ST->getSrcValueOffset(), ST->isVolatile(), 4096 ST->getAlignment()); 4097 } else if (TLI.isTypeLegal(MVT::i32)) { 4098 // Many FP stores are not made apparent until after legalize, e.g. for 4099 // argument passing. Since this is so common, custom legalize the 4100 // 64-bit integer store into two 32-bit stores. 4101 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4102 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4103 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4104 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 4105 4106 int SVOffset = ST->getSrcValueOffset(); 4107 unsigned Alignment = ST->getAlignment(); 4108 bool isVolatile = ST->isVolatile(); 4109 4110 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4111 ST->getSrcValueOffset(), 4112 isVolatile, ST->getAlignment()); 4113 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4114 DAG.getConstant(4, Ptr.getValueType())); 4115 SVOffset += 4; 4116 Alignment = MinAlign(Alignment, 4U); 4117 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4118 SVOffset, isVolatile, Alignment); 4119 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4120 } 4121 break; 4122 } 4123 } 4124 } 4125 4126 if (CombinerAA) { 4127 // Walk up chain skipping non-aliasing memory nodes. 4128 SDOperand BetterChain = FindBetterChain(N, Chain); 4129 4130 // If there is a better chain. 4131 if (Chain != BetterChain) { 4132 // Replace the chain to avoid dependency. 4133 SDOperand ReplStore; 4134 if (ST->isTruncatingStore()) { 4135 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4136 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(), 4137 ST->isVolatile(), ST->getAlignment()); 4138 } else { 4139 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4140 ST->getSrcValue(), ST->getSrcValueOffset(), 4141 ST->isVolatile(), ST->getAlignment()); 4142 } 4143 4144 // Create token to keep both nodes around. 4145 SDOperand Token = 4146 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4147 4148 // Don't add users to work list. 4149 return CombineTo(N, Token, false); 4150 } 4151 } 4152 4153 // Try transforming N to an indexed store. 4154 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4155 return SDOperand(N, 0); 4156 4157 // FIXME: is there such a think as a truncating indexed store? 4158 if (ST->isTruncatingStore() && ST->getAddressingMode() == ISD::UNINDEXED && 4159 MVT::isInteger(Value.getValueType())) { 4160 // See if we can simplify the input to this truncstore with knowledge that 4161 // only the low bits are being used. For example: 4162 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4163 SDOperand Shorter = 4164 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT())); 4165 AddToWorkList(Value.Val); 4166 if (Shorter.Val) 4167 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4168 ST->getSrcValueOffset(), ST->getStoredVT(), 4169 ST->isVolatile(), ST->getAlignment()); 4170 4171 // Otherwise, see if we can simplify the operation with 4172 // SimplifyDemandedBits, which only works if the value has a single use. 4173 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getStoredVT()))) 4174 return SDOperand(N, 0); 4175 } 4176 4177 return SDOperand(); 4178} 4179 4180SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4181 SDOperand InVec = N->getOperand(0); 4182 SDOperand InVal = N->getOperand(1); 4183 SDOperand EltNo = N->getOperand(2); 4184 4185 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4186 // vector with the inserted element. 4187 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4188 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4189 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4190 if (Elt < Ops.size()) 4191 Ops[Elt] = InVal; 4192 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4193 &Ops[0], Ops.size()); 4194 } 4195 4196 return SDOperand(); 4197} 4198 4199SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4200 SDOperand InVec = N->getOperand(0); 4201 SDOperand EltNo = N->getOperand(1); 4202 4203 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4204 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4205 if (isa<ConstantSDNode>(EltNo)) { 4206 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4207 bool NewLoad = false; 4208 if (Elt == 0) { 4209 MVT::ValueType VT = InVec.getValueType(); 4210 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4211 MVT::ValueType LVT = EVT; 4212 unsigned NumElts = MVT::getVectorNumElements(VT); 4213 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4214 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4215 if (!MVT::isVector(BCVT) || 4216 NumElts != MVT::getVectorNumElements(BCVT)) 4217 return SDOperand(); 4218 InVec = InVec.getOperand(0); 4219 EVT = MVT::getVectorElementType(BCVT); 4220 NewLoad = true; 4221 } 4222 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4223 InVec.getOperand(0).getValueType() == EVT && 4224 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4225 InVec.getOperand(0).hasOneUse()) { 4226 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4227 unsigned Align = LN0->getAlignment(); 4228 if (NewLoad) { 4229 // Check the resultant load doesn't need a higher alignment than the 4230 // original load. 4231 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4232 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4233 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4234 return SDOperand(); 4235 Align = NewAlign; 4236 } 4237 4238 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4239 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4240 LN0->isVolatile(), Align); 4241 } 4242 } 4243 } 4244 return SDOperand(); 4245} 4246 4247 4248SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4249 unsigned NumInScalars = N->getNumOperands(); 4250 MVT::ValueType VT = N->getValueType(0); 4251 unsigned NumElts = MVT::getVectorNumElements(VT); 4252 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4253 4254 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4255 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4256 // at most two distinct vectors, turn this into a shuffle node. 4257 SDOperand VecIn1, VecIn2; 4258 for (unsigned i = 0; i != NumInScalars; ++i) { 4259 // Ignore undef inputs. 4260 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4261 4262 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4263 // constant index, bail out. 4264 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4265 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4266 VecIn1 = VecIn2 = SDOperand(0, 0); 4267 break; 4268 } 4269 4270 // If the input vector type disagrees with the result of the build_vector, 4271 // we can't make a shuffle. 4272 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4273 if (ExtractedFromVec.getValueType() != VT) { 4274 VecIn1 = VecIn2 = SDOperand(0, 0); 4275 break; 4276 } 4277 4278 // Otherwise, remember this. We allow up to two distinct input vectors. 4279 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4280 continue; 4281 4282 if (VecIn1.Val == 0) { 4283 VecIn1 = ExtractedFromVec; 4284 } else if (VecIn2.Val == 0) { 4285 VecIn2 = ExtractedFromVec; 4286 } else { 4287 // Too many inputs. 4288 VecIn1 = VecIn2 = SDOperand(0, 0); 4289 break; 4290 } 4291 } 4292 4293 // If everything is good, we can make a shuffle operation. 4294 if (VecIn1.Val) { 4295 SmallVector<SDOperand, 8> BuildVecIndices; 4296 for (unsigned i = 0; i != NumInScalars; ++i) { 4297 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4298 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4299 continue; 4300 } 4301 4302 SDOperand Extract = N->getOperand(i); 4303 4304 // If extracting from the first vector, just use the index directly. 4305 if (Extract.getOperand(0) == VecIn1) { 4306 BuildVecIndices.push_back(Extract.getOperand(1)); 4307 continue; 4308 } 4309 4310 // Otherwise, use InIdx + VecSize 4311 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4312 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 4313 TLI.getPointerTy())); 4314 } 4315 4316 // Add count and size info. 4317 MVT::ValueType BuildVecVT = 4318 MVT::getVectorType(TLI.getPointerTy(), NumElts); 4319 4320 // Return the new VECTOR_SHUFFLE node. 4321 SDOperand Ops[5]; 4322 Ops[0] = VecIn1; 4323 if (VecIn2.Val) { 4324 Ops[1] = VecIn2; 4325 } else { 4326 // Use an undef build_vector as input for the second operand. 4327 std::vector<SDOperand> UnOps(NumInScalars, 4328 DAG.getNode(ISD::UNDEF, 4329 EltType)); 4330 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4331 &UnOps[0], UnOps.size()); 4332 AddToWorkList(Ops[1].Val); 4333 } 4334 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4335 &BuildVecIndices[0], BuildVecIndices.size()); 4336 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4337 } 4338 4339 return SDOperand(); 4340} 4341 4342SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4343 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4344 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4345 // inputs come from at most two distinct vectors, turn this into a shuffle 4346 // node. 4347 4348 // If we only have one input vector, we don't need to do any concatenation. 4349 if (N->getNumOperands() == 1) { 4350 return N->getOperand(0); 4351 } 4352 4353 return SDOperand(); 4354} 4355 4356SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4357 SDOperand ShufMask = N->getOperand(2); 4358 unsigned NumElts = ShufMask.getNumOperands(); 4359 4360 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4361 bool isIdentity = true; 4362 for (unsigned i = 0; i != NumElts; ++i) { 4363 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4364 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4365 isIdentity = false; 4366 break; 4367 } 4368 } 4369 if (isIdentity) return N->getOperand(0); 4370 4371 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4372 isIdentity = true; 4373 for (unsigned i = 0; i != NumElts; ++i) { 4374 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4375 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4376 isIdentity = false; 4377 break; 4378 } 4379 } 4380 if (isIdentity) return N->getOperand(1); 4381 4382 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4383 // needed at all. 4384 bool isUnary = true; 4385 bool isSplat = true; 4386 int VecNum = -1; 4387 unsigned BaseIdx = 0; 4388 for (unsigned i = 0; i != NumElts; ++i) 4389 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4390 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4391 int V = (Idx < NumElts) ? 0 : 1; 4392 if (VecNum == -1) { 4393 VecNum = V; 4394 BaseIdx = Idx; 4395 } else { 4396 if (BaseIdx != Idx) 4397 isSplat = false; 4398 if (VecNum != V) { 4399 isUnary = false; 4400 break; 4401 } 4402 } 4403 } 4404 4405 SDOperand N0 = N->getOperand(0); 4406 SDOperand N1 = N->getOperand(1); 4407 // Normalize unary shuffle so the RHS is undef. 4408 if (isUnary && VecNum == 1) 4409 std::swap(N0, N1); 4410 4411 // If it is a splat, check if the argument vector is a build_vector with 4412 // all scalar elements the same. 4413 if (isSplat) { 4414 SDNode *V = N0.Val; 4415 4416 // If this is a bit convert that changes the element type of the vector but 4417 // not the number of vector elements, look through it. Be careful not to 4418 // look though conversions that change things like v4f32 to v2f64. 4419 if (V->getOpcode() == ISD::BIT_CONVERT) { 4420 SDOperand ConvInput = V->getOperand(0); 4421 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4422 V = ConvInput.Val; 4423 } 4424 4425 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4426 unsigned NumElems = V->getNumOperands(); 4427 if (NumElems > BaseIdx) { 4428 SDOperand Base; 4429 bool AllSame = true; 4430 for (unsigned i = 0; i != NumElems; ++i) { 4431 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4432 Base = V->getOperand(i); 4433 break; 4434 } 4435 } 4436 // Splat of <u, u, u, u>, return <u, u, u, u> 4437 if (!Base.Val) 4438 return N0; 4439 for (unsigned i = 0; i != NumElems; ++i) { 4440 if (V->getOperand(i) != Base) { 4441 AllSame = false; 4442 break; 4443 } 4444 } 4445 // Splat of <x, x, x, x>, return <x, x, x, x> 4446 if (AllSame) 4447 return N0; 4448 } 4449 } 4450 } 4451 4452 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4453 // into an undef. 4454 if (isUnary || N0 == N1) { 4455 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4456 // first operand. 4457 SmallVector<SDOperand, 8> MappedOps; 4458 for (unsigned i = 0; i != NumElts; ++i) { 4459 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4460 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4461 MappedOps.push_back(ShufMask.getOperand(i)); 4462 } else { 4463 unsigned NewIdx = 4464 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4465 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4466 } 4467 } 4468 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4469 &MappedOps[0], MappedOps.size()); 4470 AddToWorkList(ShufMask.Val); 4471 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4472 N0, 4473 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4474 ShufMask); 4475 } 4476 4477 return SDOperand(); 4478} 4479 4480/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4481/// an AND to a vector_shuffle with the destination vector and a zero vector. 4482/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4483/// vector_shuffle V, Zero, <0, 4, 2, 4> 4484SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4485 SDOperand LHS = N->getOperand(0); 4486 SDOperand RHS = N->getOperand(1); 4487 if (N->getOpcode() == ISD::AND) { 4488 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4489 RHS = RHS.getOperand(0); 4490 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4491 std::vector<SDOperand> IdxOps; 4492 unsigned NumOps = RHS.getNumOperands(); 4493 unsigned NumElts = NumOps; 4494 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4495 for (unsigned i = 0; i != NumElts; ++i) { 4496 SDOperand Elt = RHS.getOperand(i); 4497 if (!isa<ConstantSDNode>(Elt)) 4498 return SDOperand(); 4499 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4500 IdxOps.push_back(DAG.getConstant(i, EVT)); 4501 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4502 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4503 else 4504 return SDOperand(); 4505 } 4506 4507 // Let's see if the target supports this vector_shuffle. 4508 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4509 return SDOperand(); 4510 4511 // Return the new VECTOR_SHUFFLE node. 4512 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4513 std::vector<SDOperand> Ops; 4514 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4515 Ops.push_back(LHS); 4516 AddToWorkList(LHS.Val); 4517 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4518 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4519 &ZeroOps[0], ZeroOps.size())); 4520 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4521 &IdxOps[0], IdxOps.size())); 4522 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4523 &Ops[0], Ops.size()); 4524 if (VT != LHS.getValueType()) { 4525 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4526 } 4527 return Result; 4528 } 4529 } 4530 return SDOperand(); 4531} 4532 4533/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4534SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4535 // After legalize, the target may be depending on adds and other 4536 // binary ops to provide legal ways to construct constants or other 4537 // things. Simplifying them may result in a loss of legality. 4538 if (AfterLegalize) return SDOperand(); 4539 4540 MVT::ValueType VT = N->getValueType(0); 4541 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4542 4543 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4544 SDOperand LHS = N->getOperand(0); 4545 SDOperand RHS = N->getOperand(1); 4546 SDOperand Shuffle = XformToShuffleWithZero(N); 4547 if (Shuffle.Val) return Shuffle; 4548 4549 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4550 // this operation. 4551 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4552 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4553 SmallVector<SDOperand, 8> Ops; 4554 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4555 SDOperand LHSOp = LHS.getOperand(i); 4556 SDOperand RHSOp = RHS.getOperand(i); 4557 // If these two elements can't be folded, bail out. 4558 if ((LHSOp.getOpcode() != ISD::UNDEF && 4559 LHSOp.getOpcode() != ISD::Constant && 4560 LHSOp.getOpcode() != ISD::ConstantFP) || 4561 (RHSOp.getOpcode() != ISD::UNDEF && 4562 RHSOp.getOpcode() != ISD::Constant && 4563 RHSOp.getOpcode() != ISD::ConstantFP)) 4564 break; 4565 // Can't fold divide by zero. 4566 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4567 N->getOpcode() == ISD::FDIV) { 4568 if ((RHSOp.getOpcode() == ISD::Constant && 4569 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4570 (RHSOp.getOpcode() == ISD::ConstantFP && 4571 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4572 break; 4573 } 4574 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4575 AddToWorkList(Ops.back().Val); 4576 assert((Ops.back().getOpcode() == ISD::UNDEF || 4577 Ops.back().getOpcode() == ISD::Constant || 4578 Ops.back().getOpcode() == ISD::ConstantFP) && 4579 "Scalar binop didn't fold!"); 4580 } 4581 4582 if (Ops.size() == LHS.getNumOperands()) { 4583 MVT::ValueType VT = LHS.getValueType(); 4584 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4585 } 4586 } 4587 4588 return SDOperand(); 4589} 4590 4591SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4592 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4593 4594 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4595 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4596 // If we got a simplified select_cc node back from SimplifySelectCC, then 4597 // break it down into a new SETCC node, and a new SELECT node, and then return 4598 // the SELECT node, since we were called with a SELECT node. 4599 if (SCC.Val) { 4600 // Check to see if we got a select_cc back (to turn into setcc/select). 4601 // Otherwise, just return whatever node we got back, like fabs. 4602 if (SCC.getOpcode() == ISD::SELECT_CC) { 4603 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4604 SCC.getOperand(0), SCC.getOperand(1), 4605 SCC.getOperand(4)); 4606 AddToWorkList(SETCC.Val); 4607 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4608 SCC.getOperand(3), SETCC); 4609 } 4610 return SCC; 4611 } 4612 return SDOperand(); 4613} 4614 4615/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4616/// are the two values being selected between, see if we can simplify the 4617/// select. Callers of this should assume that TheSelect is deleted if this 4618/// returns true. As such, they should return the appropriate thing (e.g. the 4619/// node) back to the top-level of the DAG combiner loop to avoid it being 4620/// looked at. 4621/// 4622bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4623 SDOperand RHS) { 4624 4625 // If this is a select from two identical things, try to pull the operation 4626 // through the select. 4627 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4628 // If this is a load and the token chain is identical, replace the select 4629 // of two loads with a load through a select of the address to load from. 4630 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4631 // constants have been dropped into the constant pool. 4632 if (LHS.getOpcode() == ISD::LOAD && 4633 // Token chains must be identical. 4634 LHS.getOperand(0) == RHS.getOperand(0)) { 4635 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4636 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4637 4638 // If this is an EXTLOAD, the VT's must match. 4639 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 4640 // FIXME: this conflates two src values, discarding one. This is not 4641 // the right thing to do, but nothing uses srcvalues now. When they do, 4642 // turn SrcValue into a list of locations. 4643 SDOperand Addr; 4644 if (TheSelect->getOpcode() == ISD::SELECT) { 4645 // Check that the condition doesn't reach either load. If so, folding 4646 // this will induce a cycle into the DAG. 4647 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4648 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4649 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4650 TheSelect->getOperand(0), LLD->getBasePtr(), 4651 RLD->getBasePtr()); 4652 } 4653 } else { 4654 // Check that the condition doesn't reach either load. If so, folding 4655 // this will induce a cycle into the DAG. 4656 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4657 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4658 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4659 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4660 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4661 TheSelect->getOperand(0), 4662 TheSelect->getOperand(1), 4663 LLD->getBasePtr(), RLD->getBasePtr(), 4664 TheSelect->getOperand(4)); 4665 } 4666 } 4667 4668 if (Addr.Val) { 4669 SDOperand Load; 4670 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4671 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4672 Addr,LLD->getSrcValue(), 4673 LLD->getSrcValueOffset(), 4674 LLD->isVolatile(), 4675 LLD->getAlignment()); 4676 else { 4677 Load = DAG.getExtLoad(LLD->getExtensionType(), 4678 TheSelect->getValueType(0), 4679 LLD->getChain(), Addr, LLD->getSrcValue(), 4680 LLD->getSrcValueOffset(), 4681 LLD->getLoadedVT(), 4682 LLD->isVolatile(), 4683 LLD->getAlignment()); 4684 } 4685 // Users of the select now use the result of the load. 4686 CombineTo(TheSelect, Load); 4687 4688 // Users of the old loads now use the new load's chain. We know the 4689 // old-load value is dead now. 4690 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 4691 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 4692 return true; 4693 } 4694 } 4695 } 4696 } 4697 4698 return false; 4699} 4700 4701SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 4702 SDOperand N2, SDOperand N3, 4703 ISD::CondCode CC, bool NotExtCompare) { 4704 4705 MVT::ValueType VT = N2.getValueType(); 4706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 4707 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 4708 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 4709 4710 // Determine if the condition we're dealing with is constant 4711 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 4712 if (SCC.Val) AddToWorkList(SCC.Val); 4713 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 4714 4715 // fold select_cc true, x, y -> x 4716 if (SCCC && SCCC->getValue()) 4717 return N2; 4718 // fold select_cc false, x, y -> y 4719 if (SCCC && SCCC->getValue() == 0) 4720 return N3; 4721 4722 // Check to see if we can simplify the select into an fabs node 4723 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 4724 // Allow either -0.0 or 0.0 4725 if (CFP->getValueAPF().isZero()) { 4726 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 4727 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 4728 N0 == N2 && N3.getOpcode() == ISD::FNEG && 4729 N2 == N3.getOperand(0)) 4730 return DAG.getNode(ISD::FABS, VT, N0); 4731 4732 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 4733 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 4734 N0 == N3 && N2.getOpcode() == ISD::FNEG && 4735 N2.getOperand(0) == N3) 4736 return DAG.getNode(ISD::FABS, VT, N3); 4737 } 4738 } 4739 4740 // Check to see if we can perform the "gzip trick", transforming 4741 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 4742 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 4743 MVT::isInteger(N0.getValueType()) && 4744 MVT::isInteger(N2.getValueType()) && 4745 (N1C->isNullValue() || // (a < 0) ? b : 0 4746 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 4747 MVT::ValueType XType = N0.getValueType(); 4748 MVT::ValueType AType = N2.getValueType(); 4749 if (XType >= AType) { 4750 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 4751 // single-bit constant. 4752 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 4753 unsigned ShCtV = Log2_64(N2C->getValue()); 4754 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 4755 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 4756 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 4757 AddToWorkList(Shift.Val); 4758 if (XType > AType) { 4759 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4760 AddToWorkList(Shift.Val); 4761 } 4762 return DAG.getNode(ISD::AND, AType, Shift, N2); 4763 } 4764 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4765 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4766 TLI.getShiftAmountTy())); 4767 AddToWorkList(Shift.Val); 4768 if (XType > AType) { 4769 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 4770 AddToWorkList(Shift.Val); 4771 } 4772 return DAG.getNode(ISD::AND, AType, Shift, N2); 4773 } 4774 } 4775 4776 // fold select C, 16, 0 -> shl C, 4 4777 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 4778 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 4779 4780 // If the caller doesn't want us to simplify this into a zext of a compare, 4781 // don't do it. 4782 if (NotExtCompare && N2C->getValue() == 1) 4783 return SDOperand(); 4784 4785 // Get a SetCC of the condition 4786 // FIXME: Should probably make sure that setcc is legal if we ever have a 4787 // target where it isn't. 4788 SDOperand Temp, SCC; 4789 // cast from setcc result type to select result type 4790 if (AfterLegalize) { 4791 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4792 if (N2.getValueType() < SCC.getValueType()) 4793 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 4794 else 4795 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4796 } else { 4797 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 4798 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 4799 } 4800 AddToWorkList(SCC.Val); 4801 AddToWorkList(Temp.Val); 4802 4803 if (N2C->getValue() == 1) 4804 return Temp; 4805 // shl setcc result by log2 n2c 4806 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 4807 DAG.getConstant(Log2_64(N2C->getValue()), 4808 TLI.getShiftAmountTy())); 4809 } 4810 4811 // Check to see if this is the equivalent of setcc 4812 // FIXME: Turn all of these into setcc if setcc if setcc is legal 4813 // otherwise, go ahead with the folds. 4814 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 4815 MVT::ValueType XType = N0.getValueType(); 4816 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 4817 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 4818 if (Res.getValueType() != VT) 4819 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 4820 return Res; 4821 } 4822 4823 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 4824 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 4825 TLI.isOperationLegal(ISD::CTLZ, XType)) { 4826 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 4827 return DAG.getNode(ISD::SRL, XType, Ctlz, 4828 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 4829 TLI.getShiftAmountTy())); 4830 } 4831 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 4832 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 4833 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 4834 N0); 4835 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 4836 DAG.getConstant(~0ULL, XType)); 4837 return DAG.getNode(ISD::SRL, XType, 4838 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 4839 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4840 TLI.getShiftAmountTy())); 4841 } 4842 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 4843 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 4844 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 4845 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4846 TLI.getShiftAmountTy())); 4847 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 4848 } 4849 } 4850 4851 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 4852 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4853 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4854 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 4855 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 4856 MVT::ValueType XType = N0.getValueType(); 4857 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4858 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4859 TLI.getShiftAmountTy())); 4860 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4861 AddToWorkList(Shift.Val); 4862 AddToWorkList(Add.Val); 4863 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4864 } 4865 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 4866 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4867 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 4868 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 4869 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 4870 MVT::ValueType XType = N0.getValueType(); 4871 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4872 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4873 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4874 TLI.getShiftAmountTy())); 4875 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4876 AddToWorkList(Shift.Val); 4877 AddToWorkList(Add.Val); 4878 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4879 } 4880 } 4881 } 4882 4883 return SDOperand(); 4884} 4885 4886/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4887SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4888 SDOperand N1, ISD::CondCode Cond, 4889 bool foldBooleans) { 4890 TargetLowering::DAGCombinerInfo 4891 DagCombineInfo(DAG, !AfterLegalize, false, this); 4892 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4893} 4894 4895/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4896/// return a DAG expression to select that will generate the same value by 4897/// multiplying by a magic number. See: 4898/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4899SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4900 std::vector<SDNode*> Built; 4901 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4902 4903 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4904 ii != ee; ++ii) 4905 AddToWorkList(*ii); 4906 return S; 4907} 4908 4909/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4910/// return a DAG expression to select that will generate the same value by 4911/// multiplying by a magic number. See: 4912/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4913SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4914 std::vector<SDNode*> Built; 4915 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4916 4917 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4918 ii != ee; ++ii) 4919 AddToWorkList(*ii); 4920 return S; 4921} 4922 4923/// FindBaseOffset - Return true if base is known not to alias with anything 4924/// but itself. Provides base object and offset as results. 4925static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4926 // Assume it is a primitive operation. 4927 Base = Ptr; Offset = 0; 4928 4929 // If it's an adding a simple constant then integrate the offset. 4930 if (Base.getOpcode() == ISD::ADD) { 4931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4932 Base = Base.getOperand(0); 4933 Offset += C->getValue(); 4934 } 4935 } 4936 4937 // If it's any of the following then it can't alias with anything but itself. 4938 return isa<FrameIndexSDNode>(Base) || 4939 isa<ConstantPoolSDNode>(Base) || 4940 isa<GlobalAddressSDNode>(Base); 4941} 4942 4943/// isAlias - Return true if there is any possibility that the two addresses 4944/// overlap. 4945bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4946 const Value *SrcValue1, int SrcValueOffset1, 4947 SDOperand Ptr2, int64_t Size2, 4948 const Value *SrcValue2, int SrcValueOffset2) 4949{ 4950 // If they are the same then they must be aliases. 4951 if (Ptr1 == Ptr2) return true; 4952 4953 // Gather base node and offset information. 4954 SDOperand Base1, Base2; 4955 int64_t Offset1, Offset2; 4956 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4957 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4958 4959 // If they have a same base address then... 4960 if (Base1 == Base2) { 4961 // Check to see if the addresses overlap. 4962 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4963 } 4964 4965 // If we know both bases then they can't alias. 4966 if (KnownBase1 && KnownBase2) return false; 4967 4968 if (CombinerGlobalAA) { 4969 // Use alias analysis information. 4970 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 4971 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 4972 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 4973 AliasAnalysis::AliasResult AAResult = 4974 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4975 if (AAResult == AliasAnalysis::NoAlias) 4976 return false; 4977 } 4978 4979 // Otherwise we have to assume they alias. 4980 return true; 4981} 4982 4983/// FindAliasInfo - Extracts the relevant alias information from the memory 4984/// node. Returns true if the operand was a load. 4985bool DAGCombiner::FindAliasInfo(SDNode *N, 4986 SDOperand &Ptr, int64_t &Size, 4987 const Value *&SrcValue, int &SrcValueOffset) { 4988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4989 Ptr = LD->getBasePtr(); 4990 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4991 SrcValue = LD->getSrcValue(); 4992 SrcValueOffset = LD->getSrcValueOffset(); 4993 return true; 4994 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4995 Ptr = ST->getBasePtr(); 4996 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4997 SrcValue = ST->getSrcValue(); 4998 SrcValueOffset = ST->getSrcValueOffset(); 4999 } else { 5000 assert(0 && "FindAliasInfo expected a memory operand"); 5001 } 5002 5003 return false; 5004} 5005 5006/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5007/// looking for aliasing nodes and adding them to the Aliases vector. 5008void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5009 SmallVector<SDOperand, 8> &Aliases) { 5010 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5011 std::set<SDNode *> Visited; // Visited node set. 5012 5013 // Get alias information for node. 5014 SDOperand Ptr; 5015 int64_t Size; 5016 const Value *SrcValue; 5017 int SrcValueOffset; 5018 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5019 5020 // Starting off. 5021 Chains.push_back(OriginalChain); 5022 5023 // Look at each chain and determine if it is an alias. If so, add it to the 5024 // aliases list. If not, then continue up the chain looking for the next 5025 // candidate. 5026 while (!Chains.empty()) { 5027 SDOperand Chain = Chains.back(); 5028 Chains.pop_back(); 5029 5030 // Don't bother if we've been before. 5031 if (Visited.find(Chain.Val) != Visited.end()) continue; 5032 Visited.insert(Chain.Val); 5033 5034 switch (Chain.getOpcode()) { 5035 case ISD::EntryToken: 5036 // Entry token is ideal chain operand, but handled in FindBetterChain. 5037 break; 5038 5039 case ISD::LOAD: 5040 case ISD::STORE: { 5041 // Get alias information for Chain. 5042 SDOperand OpPtr; 5043 int64_t OpSize; 5044 const Value *OpSrcValue; 5045 int OpSrcValueOffset; 5046 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5047 OpSrcValue, OpSrcValueOffset); 5048 5049 // If chain is alias then stop here. 5050 if (!(IsLoad && IsOpLoad) && 5051 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5052 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5053 Aliases.push_back(Chain); 5054 } else { 5055 // Look further up the chain. 5056 Chains.push_back(Chain.getOperand(0)); 5057 // Clean up old chain. 5058 AddToWorkList(Chain.Val); 5059 } 5060 break; 5061 } 5062 5063 case ISD::TokenFactor: 5064 // We have to check each of the operands of the token factor, so we queue 5065 // then up. Adding the operands to the queue (stack) in reverse order 5066 // maintains the original order and increases the likelihood that getNode 5067 // will find a matching token factor (CSE.) 5068 for (unsigned n = Chain.getNumOperands(); n;) 5069 Chains.push_back(Chain.getOperand(--n)); 5070 // Eliminate the token factor if we can. 5071 AddToWorkList(Chain.Val); 5072 break; 5073 5074 default: 5075 // For all other instructions we will just have to take what we can get. 5076 Aliases.push_back(Chain); 5077 break; 5078 } 5079 } 5080} 5081 5082/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5083/// for a better chain (aliasing node.) 5084SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5085 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5086 5087 // Accumulate all the aliases to this node. 5088 GatherAllAliases(N, OldChain, Aliases); 5089 5090 if (Aliases.size() == 0) { 5091 // If no operands then chain to entry token. 5092 return DAG.getEntryNode(); 5093 } else if (Aliases.size() == 1) { 5094 // If a single operand then chain to it. We don't need to revisit it. 5095 return Aliases[0]; 5096 } 5097 5098 // Construct a custom tailored token factor. 5099 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5100 &Aliases[0], Aliases.size()); 5101 5102 // Make sure the old chain gets cleaned up. 5103 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5104 5105 return NewChain; 5106} 5107 5108// SelectionDAG::Combine - This is the entry point for the file. 5109// 5110void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5111 if (!RunningAfterLegalize && ViewDAGCombine1) 5112 viewGraph(); 5113 if (RunningAfterLegalize && ViewDAGCombine2) 5114 viewGraph(); 5115 /// run - This is the main entry point to this class. 5116 /// 5117 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5118} 5119