DAGCombiner.cpp revision efc96dd38c285c1a01aa6f613f533d1205e4acb2
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBITCAST(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 239 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 240 241 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 242 /// looking for aliasing nodes and adding them to the Aliases vector. 243 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 244 SmallVector<SDValue, 8> &Aliases); 245 246 /// isAlias - Return true if there is any possibility that the two addresses 247 /// overlap. 248 bool isAlias(SDValue Ptr1, int64_t Size1, 249 const Value *SrcValue1, int SrcValueOffset1, 250 unsigned SrcValueAlign1, 251 const MDNode *TBAAInfo1, 252 SDValue Ptr2, int64_t Size2, 253 const Value *SrcValue2, int SrcValueOffset2, 254 unsigned SrcValueAlign2, 255 const MDNode *TBAAInfo2) const; 256 257 /// FindAliasInfo - Extracts the relevant alias information from the memory 258 /// node. Returns true if the operand was a load. 259 bool FindAliasInfo(SDNode *N, 260 SDValue &Ptr, int64_t &Size, 261 const Value *&SrcValue, int &SrcValueOffset, 262 unsigned &SrcValueAlignment, 263 const MDNode *&TBAAInfo) const; 264 265 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 266 /// looking for a better chain (aliasing node.) 267 SDValue FindBetterChain(SDNode *N, SDValue Chain); 268 269 public: 270 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 271 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 272 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 273 274 /// Run - runs the dag combiner on all nodes in the work list 275 void Run(CombineLevel AtLevel); 276 277 SelectionDAG &getDAG() const { return DAG; } 278 279 /// getShiftAmountTy - Returns a type large enough to hold any valid 280 /// shift amount - before type legalization these can be huge. 281 EVT getShiftAmountTy() { 282 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 283 } 284 285 /// isTypeLegal - This method returns true if we are running before type 286 /// legalization or if the specified VT is legal. 287 bool isTypeLegal(const EVT &VT) { 288 if (!LegalTypes) return true; 289 return TLI.isTypeLegal(VT); 290 } 291 }; 292} 293 294 295namespace { 296/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 297/// nodes from the worklist. 298class WorkListRemover : public SelectionDAG::DAGUpdateListener { 299 DAGCombiner &DC; 300public: 301 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 302 303 virtual void NodeDeleted(SDNode *N, SDNode *E) { 304 DC.removeFromWorkList(N); 305 } 306 307 virtual void NodeUpdated(SDNode *N) { 308 // Ignore updates. 309 } 310}; 311} 312 313//===----------------------------------------------------------------------===// 314// TargetLowering::DAGCombinerInfo implementation 315//===----------------------------------------------------------------------===// 316 317void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 318 ((DAGCombiner*)DC)->AddToWorkList(N); 319} 320 321SDValue TargetLowering::DAGCombinerInfo:: 322CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 323 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 324} 325 326SDValue TargetLowering::DAGCombinerInfo:: 327CombineTo(SDNode *N, SDValue Res, bool AddTo) { 328 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 329} 330 331 332SDValue TargetLowering::DAGCombinerInfo:: 333CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 334 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 335} 336 337void TargetLowering::DAGCombinerInfo:: 338CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 339 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 340} 341 342//===----------------------------------------------------------------------===// 343// Helper Functions 344//===----------------------------------------------------------------------===// 345 346/// isNegatibleForFree - Return 1 if we can compute the negated form of the 347/// specified expression for the same cost as the expression itself, or 2 if we 348/// can compute the negated form more cheaply than the expression itself. 349static char isNegatibleForFree(SDValue Op, bool LegalOperations, 350 unsigned Depth = 0) { 351 // No compile time optimizations on this type. 352 if (Op.getValueType() == MVT::ppcf128) 353 return 0; 354 355 // fneg is removable even if it has multiple uses. 356 if (Op.getOpcode() == ISD::FNEG) return 2; 357 358 // Don't allow anything with multiple uses. 359 if (!Op.hasOneUse()) return 0; 360 361 // Don't recurse exponentially. 362 if (Depth > 6) return 0; 363 364 switch (Op.getOpcode()) { 365 default: return false; 366 case ISD::ConstantFP: 367 // Don't invert constant FP values after legalize. The negated constant 368 // isn't necessarily legal. 369 return LegalOperations ? 0 : 1; 370 case ISD::FADD: 371 // FIXME: determine better conditions for this xform. 372 if (!UnsafeFPMath) return 0; 373 374 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 375 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 376 return V; 377 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 378 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 379 case ISD::FSUB: 380 // We can't turn -(A-B) into B-A when we honor signed zeros. 381 if (!UnsafeFPMath) return 0; 382 383 // fold (fneg (fsub A, B)) -> (fsub B, A) 384 return 1; 385 386 case ISD::FMUL: 387 case ISD::FDIV: 388 if (HonorSignDependentRoundingFPMath()) return 0; 389 390 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 391 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 392 return V; 393 394 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 395 396 case ISD::FP_EXTEND: 397 case ISD::FP_ROUND: 398 case ISD::FSIN: 399 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 400 } 401} 402 403/// GetNegatedExpression - If isNegatibleForFree returns true, this function 404/// returns the newly negated expression. 405static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 406 bool LegalOperations, unsigned Depth = 0) { 407 // fneg is removable even if it has multiple uses. 408 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 409 410 // Don't allow anything with multiple uses. 411 assert(Op.hasOneUse() && "Unknown reuse!"); 412 413 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 414 switch (Op.getOpcode()) { 415 default: llvm_unreachable("Unknown code"); 416 case ISD::ConstantFP: { 417 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 418 V.changeSign(); 419 return DAG.getConstantFP(V, Op.getValueType()); 420 } 421 case ISD::FADD: 422 // FIXME: determine better conditions for this xform. 423 assert(UnsafeFPMath); 424 425 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 426 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 427 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 428 GetNegatedExpression(Op.getOperand(0), DAG, 429 LegalOperations, Depth+1), 430 Op.getOperand(1)); 431 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(1), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(0)); 436 case ISD::FSUB: 437 // We can't turn -(A-B) into B-A when we honor signed zeros. 438 assert(UnsafeFPMath); 439 440 // fold (fneg (fsub 0, B)) -> B 441 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 442 if (N0CFP->getValueAPF().isZero()) 443 return Op.getOperand(1); 444 445 // fold (fneg (fsub A, B)) -> (fsub B, A) 446 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 447 Op.getOperand(1), Op.getOperand(0)); 448 449 case ISD::FMUL: 450 case ISD::FDIV: 451 assert(!HonorSignDependentRoundingFPMath()); 452 453 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 454 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 455 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 456 GetNegatedExpression(Op.getOperand(0), DAG, 457 LegalOperations, Depth+1), 458 Op.getOperand(1)); 459 460 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 461 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 462 Op.getOperand(0), 463 GetNegatedExpression(Op.getOperand(1), DAG, 464 LegalOperations, Depth+1)); 465 466 case ISD::FP_EXTEND: 467 case ISD::FSIN: 468 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 469 GetNegatedExpression(Op.getOperand(0), DAG, 470 LegalOperations, Depth+1)); 471 case ISD::FP_ROUND: 472 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 473 GetNegatedExpression(Op.getOperand(0), DAG, 474 LegalOperations, Depth+1), 475 Op.getOperand(1)); 476 } 477} 478 479 480// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 481// that selects between the values 1 and 0, making it equivalent to a setcc. 482// Also, set the incoming LHS, RHS, and CC references to the appropriate 483// nodes based on the type of node we are checking. This simplifies life a 484// bit for the callers. 485static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 486 SDValue &CC) { 487 if (N.getOpcode() == ISD::SETCC) { 488 LHS = N.getOperand(0); 489 RHS = N.getOperand(1); 490 CC = N.getOperand(2); 491 return true; 492 } 493 if (N.getOpcode() == ISD::SELECT_CC && 494 N.getOperand(2).getOpcode() == ISD::Constant && 495 N.getOperand(3).getOpcode() == ISD::Constant && 496 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 497 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 498 LHS = N.getOperand(0); 499 RHS = N.getOperand(1); 500 CC = N.getOperand(4); 501 return true; 502 } 503 return false; 504} 505 506// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 507// one use. If this is true, it allows the users to invert the operation for 508// free when it is profitable to do so. 509static bool isOneUseSetCC(SDValue N) { 510 SDValue N0, N1, N2; 511 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 512 return true; 513 return false; 514} 515 516SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 517 SDValue N0, SDValue N1) { 518 EVT VT = N0.getValueType(); 519 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 520 if (isa<ConstantSDNode>(N1)) { 521 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 522 SDValue OpNode = 523 DAG.FoldConstantArithmetic(Opc, VT, 524 cast<ConstantSDNode>(N0.getOperand(1)), 525 cast<ConstantSDNode>(N1)); 526 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 527 } else if (N0.hasOneUse()) { 528 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 529 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 530 N0.getOperand(0), N1); 531 AddToWorkList(OpNode.getNode()); 532 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 533 } 534 } 535 536 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 537 if (isa<ConstantSDNode>(N0)) { 538 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 539 SDValue OpNode = 540 DAG.FoldConstantArithmetic(Opc, VT, 541 cast<ConstantSDNode>(N1.getOperand(1)), 542 cast<ConstantSDNode>(N0)); 543 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 544 } else if (N1.hasOneUse()) { 545 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 546 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 547 N1.getOperand(0), N0); 548 AddToWorkList(OpNode.getNode()); 549 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 550 } 551 } 552 553 return SDValue(); 554} 555 556SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 557 bool AddTo) { 558 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 559 ++NodesCombined; 560 DEBUG(dbgs() << "\nReplacing.1 "; 561 N->dump(&DAG); 562 dbgs() << "\nWith: "; 563 To[0].getNode()->dump(&DAG); 564 dbgs() << " and " << NumTo-1 << " other values\n"; 565 for (unsigned i = 0, e = NumTo; i != e; ++i) 566 assert((!To[i].getNode() || 567 N->getValueType(i) == To[i].getValueType()) && 568 "Cannot combine value to value of different type!")); 569 WorkListRemover DeadNodes(*this); 570 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 571 572 if (AddTo) { 573 // Push the new nodes and any users onto the worklist 574 for (unsigned i = 0, e = NumTo; i != e; ++i) { 575 if (To[i].getNode()) { 576 AddToWorkList(To[i].getNode()); 577 AddUsersToWorkList(To[i].getNode()); 578 } 579 } 580 } 581 582 // Finally, if the node is now dead, remove it from the graph. The node 583 // may not be dead if the replacement process recursively simplified to 584 // something else needing this node. 585 if (N->use_empty()) { 586 // Nodes can be reintroduced into the worklist. Make sure we do not 587 // process a node that has been replaced. 588 removeFromWorkList(N); 589 590 // Finally, since the node is now dead, remove it from the graph. 591 DAG.DeleteNode(N); 592 } 593 return SDValue(N, 0); 594} 595 596void DAGCombiner:: 597CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 598 // Replace all uses. If any nodes become isomorphic to other nodes and 599 // are deleted, make sure to remove them from our worklist. 600 WorkListRemover DeadNodes(*this); 601 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 602 603 // Push the new node and any (possibly new) users onto the worklist. 604 AddToWorkList(TLO.New.getNode()); 605 AddUsersToWorkList(TLO.New.getNode()); 606 607 // Finally, if the node is now dead, remove it from the graph. The node 608 // may not be dead if the replacement process recursively simplified to 609 // something else needing this node. 610 if (TLO.Old.getNode()->use_empty()) { 611 removeFromWorkList(TLO.Old.getNode()); 612 613 // If the operands of this node are only used by the node, they will now 614 // be dead. Make sure to visit them first to delete dead nodes early. 615 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 616 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 617 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 618 619 DAG.DeleteNode(TLO.Old.getNode()); 620 } 621} 622 623/// SimplifyDemandedBits - Check the specified integer node value to see if 624/// it can be simplified or if things it uses can be simplified by bit 625/// propagation. If so, return true. 626bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 627 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 628 APInt KnownZero, KnownOne; 629 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 630 return false; 631 632 // Revisit the node. 633 AddToWorkList(Op.getNode()); 634 635 // Replace the old value with the new one. 636 ++NodesCombined; 637 DEBUG(dbgs() << "\nReplacing.2 "; 638 TLO.Old.getNode()->dump(&DAG); 639 dbgs() << "\nWith: "; 640 TLO.New.getNode()->dump(&DAG); 641 dbgs() << '\n'); 642 643 CommitTargetLoweringOpt(TLO); 644 return true; 645} 646 647void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 648 DebugLoc dl = Load->getDebugLoc(); 649 EVT VT = Load->getValueType(0); 650 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 651 652 DEBUG(dbgs() << "\nReplacing.9 "; 653 Load->dump(&DAG); 654 dbgs() << "\nWith: "; 655 Trunc.getNode()->dump(&DAG); 656 dbgs() << '\n'); 657 WorkListRemover DeadNodes(*this); 658 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 659 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 660 &DeadNodes); 661 removeFromWorkList(Load); 662 DAG.DeleteNode(Load); 663 AddToWorkList(Trunc.getNode()); 664} 665 666SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 667 Replace = false; 668 DebugLoc dl = Op.getDebugLoc(); 669 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 670 EVT MemVT = LD->getMemoryVT(); 671 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 672 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 673 : ISD::EXTLOAD) 674 : LD->getExtensionType(); 675 Replace = true; 676 return DAG.getExtLoad(ExtType, PVT, dl, 677 LD->getChain(), LD->getBasePtr(), 678 LD->getPointerInfo(), 679 MemVT, LD->isVolatile(), 680 LD->isNonTemporal(), LD->getAlignment()); 681 } 682 683 unsigned Opc = Op.getOpcode(); 684 switch (Opc) { 685 default: break; 686 case ISD::AssertSext: 687 return DAG.getNode(ISD::AssertSext, dl, PVT, 688 SExtPromoteOperand(Op.getOperand(0), PVT), 689 Op.getOperand(1)); 690 case ISD::AssertZext: 691 return DAG.getNode(ISD::AssertZext, dl, PVT, 692 ZExtPromoteOperand(Op.getOperand(0), PVT), 693 Op.getOperand(1)); 694 case ISD::Constant: { 695 unsigned ExtOpc = 696 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 697 return DAG.getNode(ExtOpc, dl, PVT, Op); 698 } 699 } 700 701 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 702 return SDValue(); 703 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 704} 705 706SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 707 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 708 return SDValue(); 709 EVT OldVT = Op.getValueType(); 710 DebugLoc dl = Op.getDebugLoc(); 711 bool Replace = false; 712 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 713 if (NewOp.getNode() == 0) 714 return SDValue(); 715 AddToWorkList(NewOp.getNode()); 716 717 if (Replace) 718 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 720 DAG.getValueType(OldVT)); 721} 722 723SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 724 EVT OldVT = Op.getValueType(); 725 DebugLoc dl = Op.getDebugLoc(); 726 bool Replace = false; 727 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 728 if (NewOp.getNode() == 0) 729 return SDValue(); 730 AddToWorkList(NewOp.getNode()); 731 732 if (Replace) 733 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 734 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 735} 736 737/// PromoteIntBinOp - Promote the specified integer binary operation if the 738/// target indicates it is beneficial. e.g. On x86, it's usually better to 739/// promote i16 operations to i32 since i16 instructions are longer. 740SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 741 if (!LegalOperations) 742 return SDValue(); 743 744 EVT VT = Op.getValueType(); 745 if (VT.isVector() || !VT.isInteger()) 746 return SDValue(); 747 748 // If operation type is 'undesirable', e.g. i16 on x86, consider 749 // promoting it. 750 unsigned Opc = Op.getOpcode(); 751 if (TLI.isTypeDesirableForOp(Opc, VT)) 752 return SDValue(); 753 754 EVT PVT = VT; 755 // Consult target whether it is a good idea to promote this operation and 756 // what's the right type to promote it to. 757 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 758 assert(PVT != VT && "Don't know what type to promote to!"); 759 760 bool Replace0 = false; 761 SDValue N0 = Op.getOperand(0); 762 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 763 if (NN0.getNode() == 0) 764 return SDValue(); 765 766 bool Replace1 = false; 767 SDValue N1 = Op.getOperand(1); 768 SDValue NN1; 769 if (N0 == N1) 770 NN1 = NN0; 771 else { 772 NN1 = PromoteOperand(N1, PVT, Replace1); 773 if (NN1.getNode() == 0) 774 return SDValue(); 775 } 776 777 AddToWorkList(NN0.getNode()); 778 if (NN1.getNode()) 779 AddToWorkList(NN1.getNode()); 780 781 if (Replace0) 782 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 783 if (Replace1) 784 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 785 786 DEBUG(dbgs() << "\nPromoting "; 787 Op.getNode()->dump(&DAG)); 788 DebugLoc dl = Op.getDebugLoc(); 789 return DAG.getNode(ISD::TRUNCATE, dl, VT, 790 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 791 } 792 return SDValue(); 793} 794 795/// PromoteIntShiftOp - Promote the specified integer shift operation if the 796/// target indicates it is beneficial. e.g. On x86, it's usually better to 797/// promote i16 operations to i32 since i16 instructions are longer. 798SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 799 if (!LegalOperations) 800 return SDValue(); 801 802 EVT VT = Op.getValueType(); 803 if (VT.isVector() || !VT.isInteger()) 804 return SDValue(); 805 806 // If operation type is 'undesirable', e.g. i16 on x86, consider 807 // promoting it. 808 unsigned Opc = Op.getOpcode(); 809 if (TLI.isTypeDesirableForOp(Opc, VT)) 810 return SDValue(); 811 812 EVT PVT = VT; 813 // Consult target whether it is a good idea to promote this operation and 814 // what's the right type to promote it to. 815 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 816 assert(PVT != VT && "Don't know what type to promote to!"); 817 818 bool Replace = false; 819 SDValue N0 = Op.getOperand(0); 820 if (Opc == ISD::SRA) 821 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 822 else if (Opc == ISD::SRL) 823 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 824 else 825 N0 = PromoteOperand(N0, PVT, Replace); 826 if (N0.getNode() == 0) 827 return SDValue(); 828 829 AddToWorkList(N0.getNode()); 830 if (Replace) 831 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 832 833 DEBUG(dbgs() << "\nPromoting "; 834 Op.getNode()->dump(&DAG)); 835 DebugLoc dl = Op.getDebugLoc(); 836 return DAG.getNode(ISD::TRUNCATE, dl, VT, 837 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 838 } 839 return SDValue(); 840} 841 842SDValue DAGCombiner::PromoteExtend(SDValue Op) { 843 if (!LegalOperations) 844 return SDValue(); 845 846 EVT VT = Op.getValueType(); 847 if (VT.isVector() || !VT.isInteger()) 848 return SDValue(); 849 850 // If operation type is 'undesirable', e.g. i16 on x86, consider 851 // promoting it. 852 unsigned Opc = Op.getOpcode(); 853 if (TLI.isTypeDesirableForOp(Opc, VT)) 854 return SDValue(); 855 856 EVT PVT = VT; 857 // Consult target whether it is a good idea to promote this operation and 858 // what's the right type to promote it to. 859 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 860 assert(PVT != VT && "Don't know what type to promote to!"); 861 // fold (aext (aext x)) -> (aext x) 862 // fold (aext (zext x)) -> (zext x) 863 // fold (aext (sext x)) -> (sext x) 864 DEBUG(dbgs() << "\nPromoting "; 865 Op.getNode()->dump(&DAG)); 866 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 867 } 868 return SDValue(); 869} 870 871bool DAGCombiner::PromoteLoad(SDValue Op) { 872 if (!LegalOperations) 873 return false; 874 875 EVT VT = Op.getValueType(); 876 if (VT.isVector() || !VT.isInteger()) 877 return false; 878 879 // If operation type is 'undesirable', e.g. i16 on x86, consider 880 // promoting it. 881 unsigned Opc = Op.getOpcode(); 882 if (TLI.isTypeDesirableForOp(Opc, VT)) 883 return false; 884 885 EVT PVT = VT; 886 // Consult target whether it is a good idea to promote this operation and 887 // what's the right type to promote it to. 888 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 889 assert(PVT != VT && "Don't know what type to promote to!"); 890 891 DebugLoc dl = Op.getDebugLoc(); 892 SDNode *N = Op.getNode(); 893 LoadSDNode *LD = cast<LoadSDNode>(N); 894 EVT MemVT = LD->getMemoryVT(); 895 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 896 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 897 : ISD::EXTLOAD) 898 : LD->getExtensionType(); 899 SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl, 900 LD->getChain(), LD->getBasePtr(), 901 LD->getPointerInfo(), 902 MemVT, LD->isVolatile(), 903 LD->isNonTemporal(), LD->getAlignment()); 904 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 905 906 DEBUG(dbgs() << "\nPromoting "; 907 N->dump(&DAG); 908 dbgs() << "\nTo: "; 909 Result.getNode()->dump(&DAG); 910 dbgs() << '\n'); 911 WorkListRemover DeadNodes(*this); 912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 913 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 914 removeFromWorkList(N); 915 DAG.DeleteNode(N); 916 AddToWorkList(Result.getNode()); 917 return true; 918 } 919 return false; 920} 921 922 923//===----------------------------------------------------------------------===// 924// Main DAG Combiner implementation 925//===----------------------------------------------------------------------===// 926 927void DAGCombiner::Run(CombineLevel AtLevel) { 928 // set the instance variables, so that the various visit routines may use it. 929 Level = AtLevel; 930 LegalOperations = Level >= NoIllegalOperations; 931 LegalTypes = Level >= NoIllegalTypes; 932 933 // Add all the dag nodes to the worklist. 934 WorkList.reserve(DAG.allnodes_size()); 935 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 936 E = DAG.allnodes_end(); I != E; ++I) 937 WorkList.push_back(I); 938 939 // Create a dummy node (which is not added to allnodes), that adds a reference 940 // to the root node, preventing it from being deleted, and tracking any 941 // changes of the root. 942 HandleSDNode Dummy(DAG.getRoot()); 943 944 // The root of the dag may dangle to deleted nodes until the dag combiner is 945 // done. Set it to null to avoid confusion. 946 DAG.setRoot(SDValue()); 947 948 // while the worklist isn't empty, inspect the node on the end of it and 949 // try and combine it. 950 while (!WorkList.empty()) { 951 SDNode *N = WorkList.back(); 952 WorkList.pop_back(); 953 954 // If N has no uses, it is dead. Make sure to revisit all N's operands once 955 // N is deleted from the DAG, since they too may now be dead or may have a 956 // reduced number of uses, allowing other xforms. 957 if (N->use_empty() && N != &Dummy) { 958 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 959 AddToWorkList(N->getOperand(i).getNode()); 960 961 DAG.DeleteNode(N); 962 continue; 963 } 964 965 SDValue RV = combine(N); 966 967 if (RV.getNode() == 0) 968 continue; 969 970 ++NodesCombined; 971 972 // If we get back the same node we passed in, rather than a new node or 973 // zero, we know that the node must have defined multiple values and 974 // CombineTo was used. Since CombineTo takes care of the worklist 975 // mechanics for us, we have no work to do in this case. 976 if (RV.getNode() == N) 977 continue; 978 979 assert(N->getOpcode() != ISD::DELETED_NODE && 980 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 981 "Node was deleted but visit returned new node!"); 982 983 DEBUG(dbgs() << "\nReplacing.3 "; 984 N->dump(&DAG); 985 dbgs() << "\nWith: "; 986 RV.getNode()->dump(&DAG); 987 dbgs() << '\n'); 988 WorkListRemover DeadNodes(*this); 989 if (N->getNumValues() == RV.getNode()->getNumValues()) 990 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 991 else { 992 assert(N->getValueType(0) == RV.getValueType() && 993 N->getNumValues() == 1 && "Type mismatch"); 994 SDValue OpV = RV; 995 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 996 } 997 998 // Push the new node and any users onto the worklist 999 AddToWorkList(RV.getNode()); 1000 AddUsersToWorkList(RV.getNode()); 1001 1002 // Add any uses of the old node to the worklist in case this node is the 1003 // last one that uses them. They may become dead after this node is 1004 // deleted. 1005 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1006 AddToWorkList(N->getOperand(i).getNode()); 1007 1008 // Finally, if the node is now dead, remove it from the graph. The node 1009 // may not be dead if the replacement process recursively simplified to 1010 // something else needing this node. 1011 if (N->use_empty()) { 1012 // Nodes can be reintroduced into the worklist. Make sure we do not 1013 // process a node that has been replaced. 1014 removeFromWorkList(N); 1015 1016 // Finally, since the node is now dead, remove it from the graph. 1017 DAG.DeleteNode(N); 1018 } 1019 } 1020 1021 // If the root changed (e.g. it was a dead load, update the root). 1022 DAG.setRoot(Dummy.getValue()); 1023} 1024 1025SDValue DAGCombiner::visit(SDNode *N) { 1026 switch (N->getOpcode()) { 1027 default: break; 1028 case ISD::TokenFactor: return visitTokenFactor(N); 1029 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1030 case ISD::ADD: return visitADD(N); 1031 case ISD::SUB: return visitSUB(N); 1032 case ISD::ADDC: return visitADDC(N); 1033 case ISD::ADDE: return visitADDE(N); 1034 case ISD::MUL: return visitMUL(N); 1035 case ISD::SDIV: return visitSDIV(N); 1036 case ISD::UDIV: return visitUDIV(N); 1037 case ISD::SREM: return visitSREM(N); 1038 case ISD::UREM: return visitUREM(N); 1039 case ISD::MULHU: return visitMULHU(N); 1040 case ISD::MULHS: return visitMULHS(N); 1041 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1042 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1043 case ISD::SDIVREM: return visitSDIVREM(N); 1044 case ISD::UDIVREM: return visitUDIVREM(N); 1045 case ISD::AND: return visitAND(N); 1046 case ISD::OR: return visitOR(N); 1047 case ISD::XOR: return visitXOR(N); 1048 case ISD::SHL: return visitSHL(N); 1049 case ISD::SRA: return visitSRA(N); 1050 case ISD::SRL: return visitSRL(N); 1051 case ISD::CTLZ: return visitCTLZ(N); 1052 case ISD::CTTZ: return visitCTTZ(N); 1053 case ISD::CTPOP: return visitCTPOP(N); 1054 case ISD::SELECT: return visitSELECT(N); 1055 case ISD::SELECT_CC: return visitSELECT_CC(N); 1056 case ISD::SETCC: return visitSETCC(N); 1057 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1058 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1059 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1060 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1061 case ISD::TRUNCATE: return visitTRUNCATE(N); 1062 case ISD::BITCAST: return visitBITCAST(N); 1063 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1064 case ISD::FADD: return visitFADD(N); 1065 case ISD::FSUB: return visitFSUB(N); 1066 case ISD::FMUL: return visitFMUL(N); 1067 case ISD::FDIV: return visitFDIV(N); 1068 case ISD::FREM: return visitFREM(N); 1069 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1070 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1071 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1072 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1073 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1074 case ISD::FP_ROUND: return visitFP_ROUND(N); 1075 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1076 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1077 case ISD::FNEG: return visitFNEG(N); 1078 case ISD::FABS: return visitFABS(N); 1079 case ISD::BRCOND: return visitBRCOND(N); 1080 case ISD::BR_CC: return visitBR_CC(N); 1081 case ISD::LOAD: return visitLOAD(N); 1082 case ISD::STORE: return visitSTORE(N); 1083 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1084 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1085 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1086 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1087 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1088 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1089 } 1090 return SDValue(); 1091} 1092 1093SDValue DAGCombiner::combine(SDNode *N) { 1094 SDValue RV = visit(N); 1095 1096 // If nothing happened, try a target-specific DAG combine. 1097 if (RV.getNode() == 0) { 1098 assert(N->getOpcode() != ISD::DELETED_NODE && 1099 "Node was deleted but visit returned NULL!"); 1100 1101 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1102 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1103 1104 // Expose the DAG combiner to the target combiner impls. 1105 TargetLowering::DAGCombinerInfo 1106 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1107 1108 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1109 } 1110 } 1111 1112 // If nothing happened still, try promoting the operation. 1113 if (RV.getNode() == 0) { 1114 switch (N->getOpcode()) { 1115 default: break; 1116 case ISD::ADD: 1117 case ISD::SUB: 1118 case ISD::MUL: 1119 case ISD::AND: 1120 case ISD::OR: 1121 case ISD::XOR: 1122 RV = PromoteIntBinOp(SDValue(N, 0)); 1123 break; 1124 case ISD::SHL: 1125 case ISD::SRA: 1126 case ISD::SRL: 1127 RV = PromoteIntShiftOp(SDValue(N, 0)); 1128 break; 1129 case ISD::SIGN_EXTEND: 1130 case ISD::ZERO_EXTEND: 1131 case ISD::ANY_EXTEND: 1132 RV = PromoteExtend(SDValue(N, 0)); 1133 break; 1134 case ISD::LOAD: 1135 if (PromoteLoad(SDValue(N, 0))) 1136 RV = SDValue(N, 0); 1137 break; 1138 } 1139 } 1140 1141 // If N is a commutative binary node, try commuting it to enable more 1142 // sdisel CSE. 1143 if (RV.getNode() == 0 && 1144 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1145 N->getNumValues() == 1) { 1146 SDValue N0 = N->getOperand(0); 1147 SDValue N1 = N->getOperand(1); 1148 1149 // Constant operands are canonicalized to RHS. 1150 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1151 SDValue Ops[] = { N1, N0 }; 1152 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1153 Ops, 2); 1154 if (CSENode) 1155 return SDValue(CSENode, 0); 1156 } 1157 } 1158 1159 return RV; 1160} 1161 1162/// getInputChainForNode - Given a node, return its input chain if it has one, 1163/// otherwise return a null sd operand. 1164static SDValue getInputChainForNode(SDNode *N) { 1165 if (unsigned NumOps = N->getNumOperands()) { 1166 if (N->getOperand(0).getValueType() == MVT::Other) 1167 return N->getOperand(0); 1168 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1169 return N->getOperand(NumOps-1); 1170 for (unsigned i = 1; i < NumOps-1; ++i) 1171 if (N->getOperand(i).getValueType() == MVT::Other) 1172 return N->getOperand(i); 1173 } 1174 return SDValue(); 1175} 1176 1177SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1178 // If N has two operands, where one has an input chain equal to the other, 1179 // the 'other' chain is redundant. 1180 if (N->getNumOperands() == 2) { 1181 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1182 return N->getOperand(0); 1183 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1184 return N->getOperand(1); 1185 } 1186 1187 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1188 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1189 SmallPtrSet<SDNode*, 16> SeenOps; 1190 bool Changed = false; // If we should replace this token factor. 1191 1192 // Start out with this token factor. 1193 TFs.push_back(N); 1194 1195 // Iterate through token factors. The TFs grows when new token factors are 1196 // encountered. 1197 for (unsigned i = 0; i < TFs.size(); ++i) { 1198 SDNode *TF = TFs[i]; 1199 1200 // Check each of the operands. 1201 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1202 SDValue Op = TF->getOperand(i); 1203 1204 switch (Op.getOpcode()) { 1205 case ISD::EntryToken: 1206 // Entry tokens don't need to be added to the list. They are 1207 // rededundant. 1208 Changed = true; 1209 break; 1210 1211 case ISD::TokenFactor: 1212 if (Op.hasOneUse() && 1213 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1214 // Queue up for processing. 1215 TFs.push_back(Op.getNode()); 1216 // Clean up in case the token factor is removed. 1217 AddToWorkList(Op.getNode()); 1218 Changed = true; 1219 break; 1220 } 1221 // Fall thru 1222 1223 default: 1224 // Only add if it isn't already in the list. 1225 if (SeenOps.insert(Op.getNode())) 1226 Ops.push_back(Op); 1227 else 1228 Changed = true; 1229 break; 1230 } 1231 } 1232 } 1233 1234 SDValue Result; 1235 1236 // If we've change things around then replace token factor. 1237 if (Changed) { 1238 if (Ops.empty()) { 1239 // The entry token is the only possible outcome. 1240 Result = DAG.getEntryNode(); 1241 } else { 1242 // New and improved token factor. 1243 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1244 MVT::Other, &Ops[0], Ops.size()); 1245 } 1246 1247 // Don't add users to work list. 1248 return CombineTo(N, Result, false); 1249 } 1250 1251 return Result; 1252} 1253 1254/// MERGE_VALUES can always be eliminated. 1255SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1256 WorkListRemover DeadNodes(*this); 1257 // Replacing results may cause a different MERGE_VALUES to suddenly 1258 // be CSE'd with N, and carry its uses with it. Iterate until no 1259 // uses remain, to ensure that the node can be safely deleted. 1260 do { 1261 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1262 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1263 &DeadNodes); 1264 } while (!N->use_empty()); 1265 removeFromWorkList(N); 1266 DAG.DeleteNode(N); 1267 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1268} 1269 1270static 1271SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1272 SelectionDAG &DAG) { 1273 EVT VT = N0.getValueType(); 1274 SDValue N00 = N0.getOperand(0); 1275 SDValue N01 = N0.getOperand(1); 1276 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1277 1278 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1279 isa<ConstantSDNode>(N00.getOperand(1))) { 1280 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1281 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1282 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1283 N00.getOperand(0), N01), 1284 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1285 N00.getOperand(1), N01)); 1286 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1287 } 1288 1289 return SDValue(); 1290} 1291 1292SDValue DAGCombiner::visitADD(SDNode *N) { 1293 SDValue N0 = N->getOperand(0); 1294 SDValue N1 = N->getOperand(1); 1295 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1296 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1297 EVT VT = N0.getValueType(); 1298 1299 // fold vector ops 1300 if (VT.isVector()) { 1301 SDValue FoldedVOp = SimplifyVBinOp(N); 1302 if (FoldedVOp.getNode()) return FoldedVOp; 1303 } 1304 1305 // fold (add x, undef) -> undef 1306 if (N0.getOpcode() == ISD::UNDEF) 1307 return N0; 1308 if (N1.getOpcode() == ISD::UNDEF) 1309 return N1; 1310 // fold (add c1, c2) -> c1+c2 1311 if (N0C && N1C) 1312 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1313 // canonicalize constant to RHS 1314 if (N0C && !N1C) 1315 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1316 // fold (add x, 0) -> x 1317 if (N1C && N1C->isNullValue()) 1318 return N0; 1319 // fold (add Sym, c) -> Sym+c 1320 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1321 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1322 GA->getOpcode() == ISD::GlobalAddress) 1323 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1324 GA->getOffset() + 1325 (uint64_t)N1C->getSExtValue()); 1326 // fold ((c1-A)+c2) -> (c1+c2)-A 1327 if (N1C && N0.getOpcode() == ISD::SUB) 1328 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1330 DAG.getConstant(N1C->getAPIntValue()+ 1331 N0C->getAPIntValue(), VT), 1332 N0.getOperand(1)); 1333 // reassociate add 1334 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1335 if (RADD.getNode() != 0) 1336 return RADD; 1337 // fold ((0-A) + B) -> B-A 1338 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1339 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1340 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1341 // fold (A + (0-B)) -> A-B 1342 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1343 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1345 // fold (A+(B-A)) -> B 1346 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1347 return N1.getOperand(0); 1348 // fold ((B-A)+A) -> B 1349 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1350 return N0.getOperand(0); 1351 // fold (A+(B-(A+C))) to (B-C) 1352 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1353 N0 == N1.getOperand(1).getOperand(0)) 1354 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1355 N1.getOperand(1).getOperand(1)); 1356 // fold (A+(B-(C+A))) to (B-C) 1357 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1358 N0 == N1.getOperand(1).getOperand(1)) 1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1360 N1.getOperand(1).getOperand(0)); 1361 // fold (A+((B-A)+or-C)) to (B+or-C) 1362 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1363 N1.getOperand(0).getOpcode() == ISD::SUB && 1364 N0 == N1.getOperand(0).getOperand(1)) 1365 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1366 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1367 1368 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1369 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1370 SDValue N00 = N0.getOperand(0); 1371 SDValue N01 = N0.getOperand(1); 1372 SDValue N10 = N1.getOperand(0); 1373 SDValue N11 = N1.getOperand(1); 1374 1375 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1376 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1377 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1378 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1379 } 1380 1381 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1382 return SDValue(N, 0); 1383 1384 // fold (a+b) -> (a|b) iff a and b share no bits. 1385 if (VT.isInteger() && !VT.isVector()) { 1386 APInt LHSZero, LHSOne; 1387 APInt RHSZero, RHSOne; 1388 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1389 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1390 1391 if (LHSZero.getBoolValue()) { 1392 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1393 1394 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1395 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1396 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1397 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1398 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1399 } 1400 } 1401 1402 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1403 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1404 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1405 if (Result.getNode()) return Result; 1406 } 1407 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1408 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1409 if (Result.getNode()) return Result; 1410 } 1411 1412 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1413 if (N1.getOpcode() == ISD::SHL && 1414 N1.getOperand(0).getOpcode() == ISD::SUB) 1415 if (ConstantSDNode *C = 1416 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1417 if (C->getAPIntValue() == 0) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1419 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1420 N1.getOperand(0).getOperand(1), 1421 N1.getOperand(1))); 1422 if (N0.getOpcode() == ISD::SHL && 1423 N0.getOperand(0).getOpcode() == ISD::SUB) 1424 if (ConstantSDNode *C = 1425 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1426 if (C->getAPIntValue() == 0) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1428 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1429 N0.getOperand(0).getOperand(1), 1430 N0.getOperand(1))); 1431 1432 if (N1.getOpcode() == ISD::AND) { 1433 SDValue AndOp0 = N1.getOperand(0); 1434 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1435 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1436 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1437 1438 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1439 // and similar xforms where the inner op is either ~0 or 0. 1440 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1441 DebugLoc DL = N->getDebugLoc(); 1442 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1443 } 1444 } 1445 1446 return SDValue(); 1447} 1448 1449SDValue DAGCombiner::visitADDC(SDNode *N) { 1450 SDValue N0 = N->getOperand(0); 1451 SDValue N1 = N->getOperand(1); 1452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1454 EVT VT = N0.getValueType(); 1455 1456 // If the flag result is dead, turn this into an ADD. 1457 if (N->hasNUsesOfValue(0, 1)) 1458 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1459 DAG.getNode(ISD::CARRY_FALSE, 1460 N->getDebugLoc(), MVT::Glue)); 1461 1462 // canonicalize constant to RHS. 1463 if (N0C && !N1C) 1464 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1465 1466 // fold (addc x, 0) -> x + no carry out 1467 if (N1C && N1C->isNullValue()) 1468 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1469 N->getDebugLoc(), MVT::Glue)); 1470 1471 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1472 APInt LHSZero, LHSOne; 1473 APInt RHSZero, RHSOne; 1474 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1475 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1476 1477 if (LHSZero.getBoolValue()) { 1478 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1479 1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1482 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1483 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1484 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1485 DAG.getNode(ISD::CARRY_FALSE, 1486 N->getDebugLoc(), MVT::Glue)); 1487 } 1488 1489 return SDValue(); 1490} 1491 1492SDValue DAGCombiner::visitADDE(SDNode *N) { 1493 SDValue N0 = N->getOperand(0); 1494 SDValue N1 = N->getOperand(1); 1495 SDValue CarryIn = N->getOperand(2); 1496 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1497 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1498 1499 // canonicalize constant to RHS 1500 if (N0C && !N1C) 1501 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1502 N1, N0, CarryIn); 1503 1504 // fold (adde x, y, false) -> (addc x, y) 1505 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1506 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1507 1508 return SDValue(); 1509} 1510 1511SDValue DAGCombiner::visitSUB(SDNode *N) { 1512 SDValue N0 = N->getOperand(0); 1513 SDValue N1 = N->getOperand(1); 1514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1515 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1516 EVT VT = N0.getValueType(); 1517 1518 // fold vector ops 1519 if (VT.isVector()) { 1520 SDValue FoldedVOp = SimplifyVBinOp(N); 1521 if (FoldedVOp.getNode()) return FoldedVOp; 1522 } 1523 1524 // fold (sub x, x) -> 0 1525 if (N0 == N1) 1526 return DAG.getConstant(0, N->getValueType(0)); 1527 // fold (sub c1, c2) -> c1-c2 1528 if (N0C && N1C) 1529 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1530 // fold (sub x, c) -> (add x, -c) 1531 if (N1C) 1532 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1533 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1534 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1535 if (N0C && N0C->isAllOnesValue()) 1536 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1537 // fold (A+B)-A -> B 1538 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1539 return N0.getOperand(1); 1540 // fold (A+B)-B -> A 1541 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1542 return N0.getOperand(0); 1543 // fold ((A+(B+or-C))-B) -> A+or-C 1544 if (N0.getOpcode() == ISD::ADD && 1545 (N0.getOperand(1).getOpcode() == ISD::SUB || 1546 N0.getOperand(1).getOpcode() == ISD::ADD) && 1547 N0.getOperand(1).getOperand(0) == N1) 1548 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1549 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1550 // fold ((A+(C+B))-B) -> A+C 1551 if (N0.getOpcode() == ISD::ADD && 1552 N0.getOperand(1).getOpcode() == ISD::ADD && 1553 N0.getOperand(1).getOperand(1) == N1) 1554 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1555 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1556 // fold ((A-(B-C))-C) -> A-B 1557 if (N0.getOpcode() == ISD::SUB && 1558 N0.getOperand(1).getOpcode() == ISD::SUB && 1559 N0.getOperand(1).getOperand(1) == N1) 1560 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1561 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1562 1563 // If either operand of a sub is undef, the result is undef 1564 if (N0.getOpcode() == ISD::UNDEF) 1565 return N0; 1566 if (N1.getOpcode() == ISD::UNDEF) 1567 return N1; 1568 1569 // If the relocation model supports it, consider symbol offsets. 1570 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1571 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1572 // fold (sub Sym, c) -> Sym-c 1573 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1574 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1575 GA->getOffset() - 1576 (uint64_t)N1C->getSExtValue()); 1577 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1578 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1579 if (GA->getGlobal() == GB->getGlobal()) 1580 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1581 VT); 1582 } 1583 1584 return SDValue(); 1585} 1586 1587SDValue DAGCombiner::visitMUL(SDNode *N) { 1588 SDValue N0 = N->getOperand(0); 1589 SDValue N1 = N->getOperand(1); 1590 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1591 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1592 EVT VT = N0.getValueType(); 1593 1594 // fold vector ops 1595 if (VT.isVector()) { 1596 SDValue FoldedVOp = SimplifyVBinOp(N); 1597 if (FoldedVOp.getNode()) return FoldedVOp; 1598 } 1599 1600 // fold (mul x, undef) -> 0 1601 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1602 return DAG.getConstant(0, VT); 1603 // fold (mul c1, c2) -> c1*c2 1604 if (N0C && N1C) 1605 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1606 // canonicalize constant to RHS 1607 if (N0C && !N1C) 1608 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1609 // fold (mul x, 0) -> 0 1610 if (N1C && N1C->isNullValue()) 1611 return N1; 1612 // fold (mul x, -1) -> 0-x 1613 if (N1C && N1C->isAllOnesValue()) 1614 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1615 DAG.getConstant(0, VT), N0); 1616 // fold (mul x, (1 << c)) -> x << c 1617 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1618 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1619 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1620 getShiftAmountTy())); 1621 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1622 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1623 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1624 // FIXME: If the input is something that is easily negated (e.g. a 1625 // single-use add), we should put the negate there. 1626 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1627 DAG.getConstant(0, VT), 1628 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1629 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1630 } 1631 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1632 if (N1C && N0.getOpcode() == ISD::SHL && 1633 isa<ConstantSDNode>(N0.getOperand(1))) { 1634 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1635 N1, N0.getOperand(1)); 1636 AddToWorkList(C3.getNode()); 1637 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1638 N0.getOperand(0), C3); 1639 } 1640 1641 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1642 // use. 1643 { 1644 SDValue Sh(0,0), Y(0,0); 1645 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1646 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1647 N0.getNode()->hasOneUse()) { 1648 Sh = N0; Y = N1; 1649 } else if (N1.getOpcode() == ISD::SHL && 1650 isa<ConstantSDNode>(N1.getOperand(1)) && 1651 N1.getNode()->hasOneUse()) { 1652 Sh = N1; Y = N0; 1653 } 1654 1655 if (Sh.getNode()) { 1656 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1657 Sh.getOperand(0), Y); 1658 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1659 Mul, Sh.getOperand(1)); 1660 } 1661 } 1662 1663 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1664 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1665 isa<ConstantSDNode>(N0.getOperand(1))) 1666 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1667 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1668 N0.getOperand(0), N1), 1669 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1670 N0.getOperand(1), N1)); 1671 1672 // reassociate mul 1673 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1674 if (RMUL.getNode() != 0) 1675 return RMUL; 1676 1677 return SDValue(); 1678} 1679 1680SDValue DAGCombiner::visitSDIV(SDNode *N) { 1681 SDValue N0 = N->getOperand(0); 1682 SDValue N1 = N->getOperand(1); 1683 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1685 EVT VT = N->getValueType(0); 1686 1687 // fold vector ops 1688 if (VT.isVector()) { 1689 SDValue FoldedVOp = SimplifyVBinOp(N); 1690 if (FoldedVOp.getNode()) return FoldedVOp; 1691 } 1692 1693 // fold (sdiv c1, c2) -> c1/c2 1694 if (N0C && N1C && !N1C->isNullValue()) 1695 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1696 // fold (sdiv X, 1) -> X 1697 if (N1C && N1C->getSExtValue() == 1LL) 1698 return N0; 1699 // fold (sdiv X, -1) -> 0-X 1700 if (N1C && N1C->isAllOnesValue()) 1701 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1702 DAG.getConstant(0, VT), N0); 1703 // If we know the sign bits of both operands are zero, strength reduce to a 1704 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1705 if (!VT.isVector()) { 1706 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1707 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1708 N0, N1); 1709 } 1710 // fold (sdiv X, pow2) -> simple ops after legalize 1711 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1712 (isPowerOf2_64(N1C->getSExtValue()) || 1713 isPowerOf2_64(-N1C->getSExtValue()))) { 1714 // If dividing by powers of two is cheap, then don't perform the following 1715 // fold. 1716 if (TLI.isPow2DivCheap()) 1717 return SDValue(); 1718 1719 int64_t pow2 = N1C->getSExtValue(); 1720 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1721 unsigned lg2 = Log2_64(abs2); 1722 1723 // Splat the sign bit into the register 1724 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1725 DAG.getConstant(VT.getSizeInBits()-1, 1726 getShiftAmountTy())); 1727 AddToWorkList(SGN.getNode()); 1728 1729 // Add (N0 < 0) ? abs2 - 1 : 0; 1730 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1731 DAG.getConstant(VT.getSizeInBits() - lg2, 1732 getShiftAmountTy())); 1733 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1734 AddToWorkList(SRL.getNode()); 1735 AddToWorkList(ADD.getNode()); // Divide by pow2 1736 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1737 DAG.getConstant(lg2, getShiftAmountTy())); 1738 1739 // If we're dividing by a positive value, we're done. Otherwise, we must 1740 // negate the result. 1741 if (pow2 > 0) 1742 return SRA; 1743 1744 AddToWorkList(SRA.getNode()); 1745 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1746 DAG.getConstant(0, VT), SRA); 1747 } 1748 1749 // if integer divide is expensive and we satisfy the requirements, emit an 1750 // alternate sequence. 1751 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1752 !TLI.isIntDivCheap()) { 1753 SDValue Op = BuildSDIV(N); 1754 if (Op.getNode()) return Op; 1755 } 1756 1757 // undef / X -> 0 1758 if (N0.getOpcode() == ISD::UNDEF) 1759 return DAG.getConstant(0, VT); 1760 // X / undef -> undef 1761 if (N1.getOpcode() == ISD::UNDEF) 1762 return N1; 1763 1764 return SDValue(); 1765} 1766 1767SDValue DAGCombiner::visitUDIV(SDNode *N) { 1768 SDValue N0 = N->getOperand(0); 1769 SDValue N1 = N->getOperand(1); 1770 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1772 EVT VT = N->getValueType(0); 1773 1774 // fold vector ops 1775 if (VT.isVector()) { 1776 SDValue FoldedVOp = SimplifyVBinOp(N); 1777 if (FoldedVOp.getNode()) return FoldedVOp; 1778 } 1779 1780 // fold (udiv c1, c2) -> c1/c2 1781 if (N0C && N1C && !N1C->isNullValue()) 1782 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1783 // fold (udiv x, (1 << c)) -> x >>u c 1784 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1785 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1786 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1787 getShiftAmountTy())); 1788 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1789 if (N1.getOpcode() == ISD::SHL) { 1790 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1791 if (SHC->getAPIntValue().isPowerOf2()) { 1792 EVT ADDVT = N1.getOperand(1).getValueType(); 1793 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1794 N1.getOperand(1), 1795 DAG.getConstant(SHC->getAPIntValue() 1796 .logBase2(), 1797 ADDVT)); 1798 AddToWorkList(Add.getNode()); 1799 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1800 } 1801 } 1802 } 1803 // fold (udiv x, c) -> alternate 1804 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1805 SDValue Op = BuildUDIV(N); 1806 if (Op.getNode()) return Op; 1807 } 1808 1809 // undef / X -> 0 1810 if (N0.getOpcode() == ISD::UNDEF) 1811 return DAG.getConstant(0, VT); 1812 // X / undef -> undef 1813 if (N1.getOpcode() == ISD::UNDEF) 1814 return N1; 1815 1816 return SDValue(); 1817} 1818 1819SDValue DAGCombiner::visitSREM(SDNode *N) { 1820 SDValue N0 = N->getOperand(0); 1821 SDValue N1 = N->getOperand(1); 1822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1824 EVT VT = N->getValueType(0); 1825 1826 // fold (srem c1, c2) -> c1%c2 1827 if (N0C && N1C && !N1C->isNullValue()) 1828 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1829 // If we know the sign bits of both operands are zero, strength reduce to a 1830 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1831 if (!VT.isVector()) { 1832 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1833 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1834 } 1835 1836 // If X/C can be simplified by the division-by-constant logic, lower 1837 // X%C to the equivalent of X-X/C*C. 1838 if (N1C && !N1C->isNullValue()) { 1839 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1840 AddToWorkList(Div.getNode()); 1841 SDValue OptimizedDiv = combine(Div.getNode()); 1842 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1843 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1844 OptimizedDiv, N1); 1845 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1846 AddToWorkList(Mul.getNode()); 1847 return Sub; 1848 } 1849 } 1850 1851 // undef % X -> 0 1852 if (N0.getOpcode() == ISD::UNDEF) 1853 return DAG.getConstant(0, VT); 1854 // X % undef -> undef 1855 if (N1.getOpcode() == ISD::UNDEF) 1856 return N1; 1857 1858 return SDValue(); 1859} 1860 1861SDValue DAGCombiner::visitUREM(SDNode *N) { 1862 SDValue N0 = N->getOperand(0); 1863 SDValue N1 = N->getOperand(1); 1864 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1865 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1866 EVT VT = N->getValueType(0); 1867 1868 // fold (urem c1, c2) -> c1%c2 1869 if (N0C && N1C && !N1C->isNullValue()) 1870 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1871 // fold (urem x, pow2) -> (and x, pow2-1) 1872 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1873 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1874 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1875 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1876 if (N1.getOpcode() == ISD::SHL) { 1877 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1878 if (SHC->getAPIntValue().isPowerOf2()) { 1879 SDValue Add = 1880 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1881 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1882 VT)); 1883 AddToWorkList(Add.getNode()); 1884 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1885 } 1886 } 1887 } 1888 1889 // If X/C can be simplified by the division-by-constant logic, lower 1890 // X%C to the equivalent of X-X/C*C. 1891 if (N1C && !N1C->isNullValue()) { 1892 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1893 AddToWorkList(Div.getNode()); 1894 SDValue OptimizedDiv = combine(Div.getNode()); 1895 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1896 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1897 OptimizedDiv, N1); 1898 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1899 AddToWorkList(Mul.getNode()); 1900 return Sub; 1901 } 1902 } 1903 1904 // undef % X -> 0 1905 if (N0.getOpcode() == ISD::UNDEF) 1906 return DAG.getConstant(0, VT); 1907 // X % undef -> undef 1908 if (N1.getOpcode() == ISD::UNDEF) 1909 return N1; 1910 1911 return SDValue(); 1912} 1913 1914SDValue DAGCombiner::visitMULHS(SDNode *N) { 1915 SDValue N0 = N->getOperand(0); 1916 SDValue N1 = N->getOperand(1); 1917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1918 EVT VT = N->getValueType(0); 1919 DebugLoc DL = N->getDebugLoc(); 1920 1921 // fold (mulhs x, 0) -> 0 1922 if (N1C && N1C->isNullValue()) 1923 return N1; 1924 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1925 if (N1C && N1C->getAPIntValue() == 1) 1926 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1927 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1928 getShiftAmountTy())); 1929 // fold (mulhs x, undef) -> 0 1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1931 return DAG.getConstant(0, VT); 1932 1933 // If the type twice as wide is legal, transform the mulhs to a wider multiply 1934 // plus a shift. 1935 if (VT.isSimple() && !VT.isVector()) { 1936 MVT Simple = VT.getSimpleVT(); 1937 unsigned SimpleSize = Simple.getSizeInBits(); 1938 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1939 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1940 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 1941 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 1942 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 1943 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 1944 DAG.getConstant(SimpleSize, getShiftAmountTy())); 1945 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 1946 } 1947 } 1948 1949 return SDValue(); 1950} 1951 1952SDValue DAGCombiner::visitMULHU(SDNode *N) { 1953 SDValue N0 = N->getOperand(0); 1954 SDValue N1 = N->getOperand(1); 1955 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1956 EVT VT = N->getValueType(0); 1957 DebugLoc DL = N->getDebugLoc(); 1958 1959 // fold (mulhu x, 0) -> 0 1960 if (N1C && N1C->isNullValue()) 1961 return N1; 1962 // fold (mulhu x, 1) -> 0 1963 if (N1C && N1C->getAPIntValue() == 1) 1964 return DAG.getConstant(0, N0.getValueType()); 1965 // fold (mulhu x, undef) -> 0 1966 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1967 return DAG.getConstant(0, VT); 1968 1969 // If the type twice as wide is legal, transform the mulhu to a wider multiply 1970 // plus a shift. 1971 if (VT.isSimple() && !VT.isVector()) { 1972 MVT Simple = VT.getSimpleVT(); 1973 unsigned SimpleSize = Simple.getSizeInBits(); 1974 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 1975 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 1976 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 1977 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 1978 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 1979 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 1980 DAG.getConstant(SimpleSize, getShiftAmountTy())); 1981 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 1982 } 1983 } 1984 1985 return SDValue(); 1986} 1987 1988/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1989/// compute two values. LoOp and HiOp give the opcodes for the two computations 1990/// that are being performed. Return true if a simplification was made. 1991/// 1992SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1993 unsigned HiOp) { 1994 // If the high half is not needed, just compute the low half. 1995 bool HiExists = N->hasAnyUseOfValue(1); 1996 if (!HiExists && 1997 (!LegalOperations || 1998 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1999 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2000 N->op_begin(), N->getNumOperands()); 2001 return CombineTo(N, Res, Res); 2002 } 2003 2004 // If the low half is not needed, just compute the high half. 2005 bool LoExists = N->hasAnyUseOfValue(0); 2006 if (!LoExists && 2007 (!LegalOperations || 2008 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2009 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2010 N->op_begin(), N->getNumOperands()); 2011 return CombineTo(N, Res, Res); 2012 } 2013 2014 // If both halves are used, return as it is. 2015 if (LoExists && HiExists) 2016 return SDValue(); 2017 2018 // If the two computed results can be simplified separately, separate them. 2019 if (LoExists) { 2020 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2021 N->op_begin(), N->getNumOperands()); 2022 AddToWorkList(Lo.getNode()); 2023 SDValue LoOpt = combine(Lo.getNode()); 2024 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2025 (!LegalOperations || 2026 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2027 return CombineTo(N, LoOpt, LoOpt); 2028 } 2029 2030 if (HiExists) { 2031 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2032 N->op_begin(), N->getNumOperands()); 2033 AddToWorkList(Hi.getNode()); 2034 SDValue HiOpt = combine(Hi.getNode()); 2035 if (HiOpt.getNode() && HiOpt != Hi && 2036 (!LegalOperations || 2037 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2038 return CombineTo(N, HiOpt, HiOpt); 2039 } 2040 2041 return SDValue(); 2042} 2043 2044SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2045 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2046 if (Res.getNode()) return Res; 2047 2048 EVT VT = N->getValueType(0); 2049 DebugLoc DL = N->getDebugLoc(); 2050 2051 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2052 // plus a shift. 2053 if (VT.isSimple() && !VT.isVector()) { 2054 MVT Simple = VT.getSimpleVT(); 2055 unsigned SimpleSize = Simple.getSizeInBits(); 2056 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2057 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2058 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2059 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2060 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2061 // Compute the high part as N1. 2062 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2063 DAG.getConstant(SimpleSize, getShiftAmountTy())); 2064 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2065 // Compute the low part as N0. 2066 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2067 return CombineTo(N, Lo, Hi); 2068 } 2069 } 2070 2071 return SDValue(); 2072} 2073 2074SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2075 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2076 if (Res.getNode()) return Res; 2077 2078 EVT VT = N->getValueType(0); 2079 DebugLoc DL = N->getDebugLoc(); 2080 2081 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2082 // plus a shift. 2083 if (VT.isSimple() && !VT.isVector()) { 2084 MVT Simple = VT.getSimpleVT(); 2085 unsigned SimpleSize = Simple.getSizeInBits(); 2086 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2087 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2088 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2089 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2090 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2091 // Compute the high part as N1. 2092 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2093 DAG.getConstant(SimpleSize, getShiftAmountTy())); 2094 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2095 // Compute the low part as N0. 2096 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2097 return CombineTo(N, Lo, Hi); 2098 } 2099 } 2100 2101 return SDValue(); 2102} 2103 2104SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2105 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2106 if (Res.getNode()) return Res; 2107 2108 return SDValue(); 2109} 2110 2111SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2112 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2113 if (Res.getNode()) return Res; 2114 2115 return SDValue(); 2116} 2117 2118/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2119/// two operands of the same opcode, try to simplify it. 2120SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2121 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2122 EVT VT = N0.getValueType(); 2123 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2124 2125 // Bail early if none of these transforms apply. 2126 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2127 2128 // For each of OP in AND/OR/XOR: 2129 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2130 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2131 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2132 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2133 // 2134 // do not sink logical op inside of a vector extend, since it may combine 2135 // into a vsetcc. 2136 EVT Op0VT = N0.getOperand(0).getValueType(); 2137 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2138 N0.getOpcode() == ISD::SIGN_EXTEND || 2139 // Avoid infinite looping with PromoteIntBinOp. 2140 (N0.getOpcode() == ISD::ANY_EXTEND && 2141 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2142 (N0.getOpcode() == ISD::TRUNCATE && 2143 (!TLI.isZExtFree(VT, Op0VT) || 2144 !TLI.isTruncateFree(Op0VT, VT)) && 2145 TLI.isTypeLegal(Op0VT))) && 2146 !VT.isVector() && 2147 Op0VT == N1.getOperand(0).getValueType() && 2148 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2149 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2150 N0.getOperand(0).getValueType(), 2151 N0.getOperand(0), N1.getOperand(0)); 2152 AddToWorkList(ORNode.getNode()); 2153 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2154 } 2155 2156 // For each of OP in SHL/SRL/SRA/AND... 2157 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2158 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2159 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2160 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2161 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2162 N0.getOperand(1) == N1.getOperand(1)) { 2163 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2164 N0.getOperand(0).getValueType(), 2165 N0.getOperand(0), N1.getOperand(0)); 2166 AddToWorkList(ORNode.getNode()); 2167 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2168 ORNode, N0.getOperand(1)); 2169 } 2170 2171 return SDValue(); 2172} 2173 2174SDValue DAGCombiner::visitAND(SDNode *N) { 2175 SDValue N0 = N->getOperand(0); 2176 SDValue N1 = N->getOperand(1); 2177 SDValue LL, LR, RL, RR, CC0, CC1; 2178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2180 EVT VT = N1.getValueType(); 2181 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2182 2183 // fold vector ops 2184 if (VT.isVector()) { 2185 SDValue FoldedVOp = SimplifyVBinOp(N); 2186 if (FoldedVOp.getNode()) return FoldedVOp; 2187 } 2188 2189 // fold (and x, undef) -> 0 2190 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2191 return DAG.getConstant(0, VT); 2192 // fold (and c1, c2) -> c1&c2 2193 if (N0C && N1C) 2194 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2195 // canonicalize constant to RHS 2196 if (N0C && !N1C) 2197 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2198 // fold (and x, -1) -> x 2199 if (N1C && N1C->isAllOnesValue()) 2200 return N0; 2201 // if (and x, c) is known to be zero, return 0 2202 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2203 APInt::getAllOnesValue(BitWidth))) 2204 return DAG.getConstant(0, VT); 2205 // reassociate and 2206 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2207 if (RAND.getNode() != 0) 2208 return RAND; 2209 // fold (and (or x, C), D) -> D if (C & D) == D 2210 if (N1C && N0.getOpcode() == ISD::OR) 2211 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2212 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2213 return N1; 2214 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2215 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2216 SDValue N0Op0 = N0.getOperand(0); 2217 APInt Mask = ~N1C->getAPIntValue(); 2218 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2219 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2220 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2221 N0.getValueType(), N0Op0); 2222 2223 // Replace uses of the AND with uses of the Zero extend node. 2224 CombineTo(N, Zext); 2225 2226 // We actually want to replace all uses of the any_extend with the 2227 // zero_extend, to avoid duplicating things. This will later cause this 2228 // AND to be folded. 2229 CombineTo(N0.getNode(), Zext); 2230 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2231 } 2232 } 2233 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2234 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2235 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2236 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2237 2238 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2239 LL.getValueType().isInteger()) { 2240 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2241 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2242 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2243 LR.getValueType(), LL, RL); 2244 AddToWorkList(ORNode.getNode()); 2245 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2246 } 2247 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2248 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2249 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2250 LR.getValueType(), LL, RL); 2251 AddToWorkList(ANDNode.getNode()); 2252 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2253 } 2254 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2255 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2256 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2257 LR.getValueType(), LL, RL); 2258 AddToWorkList(ORNode.getNode()); 2259 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2260 } 2261 } 2262 // canonicalize equivalent to ll == rl 2263 if (LL == RR && LR == RL) { 2264 Op1 = ISD::getSetCCSwappedOperands(Op1); 2265 std::swap(RL, RR); 2266 } 2267 if (LL == RL && LR == RR) { 2268 bool isInteger = LL.getValueType().isInteger(); 2269 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2270 if (Result != ISD::SETCC_INVALID && 2271 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2272 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2273 LL, LR, Result); 2274 } 2275 } 2276 2277 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2278 if (N0.getOpcode() == N1.getOpcode()) { 2279 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2280 if (Tmp.getNode()) return Tmp; 2281 } 2282 2283 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2284 // fold (and (sra)) -> (and (srl)) when possible. 2285 if (!VT.isVector() && 2286 SimplifyDemandedBits(SDValue(N, 0))) 2287 return SDValue(N, 0); 2288 2289 // fold (zext_inreg (extload x)) -> (zextload x) 2290 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2291 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2292 EVT MemVT = LN0->getMemoryVT(); 2293 // If we zero all the possible extended bits, then we can turn this into 2294 // a zextload if we are running before legalize or the operation is legal. 2295 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2296 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2297 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2298 ((!LegalOperations && !LN0->isVolatile()) || 2299 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2300 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2301 LN0->getChain(), LN0->getBasePtr(), 2302 LN0->getPointerInfo(), MemVT, 2303 LN0->isVolatile(), LN0->isNonTemporal(), 2304 LN0->getAlignment()); 2305 AddToWorkList(N); 2306 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2307 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2308 } 2309 } 2310 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2311 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2312 N0.hasOneUse()) { 2313 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2314 EVT MemVT = LN0->getMemoryVT(); 2315 // If we zero all the possible extended bits, then we can turn this into 2316 // a zextload if we are running before legalize or the operation is legal. 2317 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2318 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2319 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2320 ((!LegalOperations && !LN0->isVolatile()) || 2321 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2322 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getDebugLoc(), 2323 LN0->getChain(), 2324 LN0->getBasePtr(), LN0->getPointerInfo(), 2325 MemVT, 2326 LN0->isVolatile(), LN0->isNonTemporal(), 2327 LN0->getAlignment()); 2328 AddToWorkList(N); 2329 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2330 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2331 } 2332 } 2333 2334 // fold (and (load x), 255) -> (zextload x, i8) 2335 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2336 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2337 if (N1C && (N0.getOpcode() == ISD::LOAD || 2338 (N0.getOpcode() == ISD::ANY_EXTEND && 2339 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2340 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2341 LoadSDNode *LN0 = HasAnyExt 2342 ? cast<LoadSDNode>(N0.getOperand(0)) 2343 : cast<LoadSDNode>(N0); 2344 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2345 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2346 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2347 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2348 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2349 EVT LoadedVT = LN0->getMemoryVT(); 2350 2351 if (ExtVT == LoadedVT && 2352 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2353 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2354 2355 SDValue NewLoad = 2356 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2357 LN0->getChain(), LN0->getBasePtr(), 2358 LN0->getPointerInfo(), 2359 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2360 LN0->getAlignment()); 2361 AddToWorkList(N); 2362 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2363 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2364 } 2365 2366 // Do not change the width of a volatile load. 2367 // Do not generate loads of non-round integer types since these can 2368 // be expensive (and would be wrong if the type is not byte sized). 2369 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2370 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2371 EVT PtrType = LN0->getOperand(1).getValueType(); 2372 2373 unsigned Alignment = LN0->getAlignment(); 2374 SDValue NewPtr = LN0->getBasePtr(); 2375 2376 // For big endian targets, we need to add an offset to the pointer 2377 // to load the correct bytes. For little endian systems, we merely 2378 // need to read fewer bytes from the same pointer. 2379 if (TLI.isBigEndian()) { 2380 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2381 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2382 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2383 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2384 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2385 Alignment = MinAlign(Alignment, PtrOff); 2386 } 2387 2388 AddToWorkList(NewPtr.getNode()); 2389 2390 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2391 SDValue Load = 2392 DAG.getExtLoad(ISD::ZEXTLOAD, LoadResultTy, LN0->getDebugLoc(), 2393 LN0->getChain(), NewPtr, 2394 LN0->getPointerInfo(), 2395 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2396 Alignment); 2397 AddToWorkList(N); 2398 CombineTo(LN0, Load, Load.getValue(1)); 2399 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2400 } 2401 } 2402 } 2403 } 2404 2405 return SDValue(); 2406} 2407 2408SDValue DAGCombiner::visitOR(SDNode *N) { 2409 SDValue N0 = N->getOperand(0); 2410 SDValue N1 = N->getOperand(1); 2411 SDValue LL, LR, RL, RR, CC0, CC1; 2412 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2414 EVT VT = N1.getValueType(); 2415 2416 // fold vector ops 2417 if (VT.isVector()) { 2418 SDValue FoldedVOp = SimplifyVBinOp(N); 2419 if (FoldedVOp.getNode()) return FoldedVOp; 2420 } 2421 2422 // fold (or x, undef) -> -1 2423 if (!LegalOperations && 2424 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2425 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2426 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2427 } 2428 // fold (or c1, c2) -> c1|c2 2429 if (N0C && N1C) 2430 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2431 // canonicalize constant to RHS 2432 if (N0C && !N1C) 2433 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2434 // fold (or x, 0) -> x 2435 if (N1C && N1C->isNullValue()) 2436 return N0; 2437 // fold (or x, -1) -> -1 2438 if (N1C && N1C->isAllOnesValue()) 2439 return N1; 2440 // fold (or x, c) -> c iff (x & ~c) == 0 2441 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2442 return N1; 2443 // reassociate or 2444 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2445 if (ROR.getNode() != 0) 2446 return ROR; 2447 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2448 // iff (c1 & c2) == 0. 2449 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2450 isa<ConstantSDNode>(N0.getOperand(1))) { 2451 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2452 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2453 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2454 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2455 N0.getOperand(0), N1), 2456 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2457 } 2458 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2459 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2460 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2461 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2462 2463 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2464 LL.getValueType().isInteger()) { 2465 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2466 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2467 if (cast<ConstantSDNode>(LR)->isNullValue() && 2468 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2469 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2470 LR.getValueType(), LL, RL); 2471 AddToWorkList(ORNode.getNode()); 2472 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2473 } 2474 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2475 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2476 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2477 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2478 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2479 LR.getValueType(), LL, RL); 2480 AddToWorkList(ANDNode.getNode()); 2481 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2482 } 2483 } 2484 // canonicalize equivalent to ll == rl 2485 if (LL == RR && LR == RL) { 2486 Op1 = ISD::getSetCCSwappedOperands(Op1); 2487 std::swap(RL, RR); 2488 } 2489 if (LL == RL && LR == RR) { 2490 bool isInteger = LL.getValueType().isInteger(); 2491 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2492 if (Result != ISD::SETCC_INVALID && 2493 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2494 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2495 LL, LR, Result); 2496 } 2497 } 2498 2499 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2500 if (N0.getOpcode() == N1.getOpcode()) { 2501 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2502 if (Tmp.getNode()) return Tmp; 2503 } 2504 2505 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2506 if (N0.getOpcode() == ISD::AND && 2507 N1.getOpcode() == ISD::AND && 2508 N0.getOperand(1).getOpcode() == ISD::Constant && 2509 N1.getOperand(1).getOpcode() == ISD::Constant && 2510 // Don't increase # computations. 2511 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2512 // We can only do this xform if we know that bits from X that are set in C2 2513 // but not in C1 are already zero. Likewise for Y. 2514 const APInt &LHSMask = 2515 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2516 const APInt &RHSMask = 2517 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2518 2519 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2520 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2521 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2522 N0.getOperand(0), N1.getOperand(0)); 2523 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2524 DAG.getConstant(LHSMask | RHSMask, VT)); 2525 } 2526 } 2527 2528 // See if this is some rotate idiom. 2529 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2530 return SDValue(Rot, 0); 2531 2532 // Simplify the operands using demanded-bits information. 2533 if (!VT.isVector() && 2534 SimplifyDemandedBits(SDValue(N, 0))) 2535 return SDValue(N, 0); 2536 2537 return SDValue(); 2538} 2539 2540/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2541static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2542 if (Op.getOpcode() == ISD::AND) { 2543 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2544 Mask = Op.getOperand(1); 2545 Op = Op.getOperand(0); 2546 } else { 2547 return false; 2548 } 2549 } 2550 2551 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2552 Shift = Op; 2553 return true; 2554 } 2555 2556 return false; 2557} 2558 2559// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2560// idioms for rotate, and if the target supports rotation instructions, generate 2561// a rot[lr]. 2562SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2563 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2564 EVT VT = LHS.getValueType(); 2565 if (!TLI.isTypeLegal(VT)) return 0; 2566 2567 // The target must have at least one rotate flavor. 2568 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2569 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2570 if (!HasROTL && !HasROTR) return 0; 2571 2572 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2573 SDValue LHSShift; // The shift. 2574 SDValue LHSMask; // AND value if any. 2575 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2576 return 0; // Not part of a rotate. 2577 2578 SDValue RHSShift; // The shift. 2579 SDValue RHSMask; // AND value if any. 2580 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2581 return 0; // Not part of a rotate. 2582 2583 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2584 return 0; // Not shifting the same value. 2585 2586 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2587 return 0; // Shifts must disagree. 2588 2589 // Canonicalize shl to left side in a shl/srl pair. 2590 if (RHSShift.getOpcode() == ISD::SHL) { 2591 std::swap(LHS, RHS); 2592 std::swap(LHSShift, RHSShift); 2593 std::swap(LHSMask , RHSMask ); 2594 } 2595 2596 unsigned OpSizeInBits = VT.getSizeInBits(); 2597 SDValue LHSShiftArg = LHSShift.getOperand(0); 2598 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2599 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2600 2601 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2602 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2603 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2604 RHSShiftAmt.getOpcode() == ISD::Constant) { 2605 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2606 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2607 if ((LShVal + RShVal) != OpSizeInBits) 2608 return 0; 2609 2610 SDValue Rot; 2611 if (HasROTL) 2612 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2613 else 2614 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2615 2616 // If there is an AND of either shifted operand, apply it to the result. 2617 if (LHSMask.getNode() || RHSMask.getNode()) { 2618 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2619 2620 if (LHSMask.getNode()) { 2621 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2622 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2623 } 2624 if (RHSMask.getNode()) { 2625 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2626 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2627 } 2628 2629 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2630 } 2631 2632 return Rot.getNode(); 2633 } 2634 2635 // If there is a mask here, and we have a variable shift, we can't be sure 2636 // that we're masking out the right stuff. 2637 if (LHSMask.getNode() || RHSMask.getNode()) 2638 return 0; 2639 2640 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2641 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2642 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2643 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2644 if (ConstantSDNode *SUBC = 2645 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2646 if (SUBC->getAPIntValue() == OpSizeInBits) { 2647 if (HasROTL) 2648 return DAG.getNode(ISD::ROTL, DL, VT, 2649 LHSShiftArg, LHSShiftAmt).getNode(); 2650 else 2651 return DAG.getNode(ISD::ROTR, DL, VT, 2652 LHSShiftArg, RHSShiftAmt).getNode(); 2653 } 2654 } 2655 } 2656 2657 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2658 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2659 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2660 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2661 if (ConstantSDNode *SUBC = 2662 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2663 if (SUBC->getAPIntValue() == OpSizeInBits) { 2664 if (HasROTR) 2665 return DAG.getNode(ISD::ROTR, DL, VT, 2666 LHSShiftArg, RHSShiftAmt).getNode(); 2667 else 2668 return DAG.getNode(ISD::ROTL, DL, VT, 2669 LHSShiftArg, LHSShiftAmt).getNode(); 2670 } 2671 } 2672 } 2673 2674 // Look for sign/zext/any-extended or truncate cases: 2675 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2676 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2677 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2678 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2679 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2680 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2681 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2682 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2683 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2684 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2685 if (RExtOp0.getOpcode() == ISD::SUB && 2686 RExtOp0.getOperand(1) == LExtOp0) { 2687 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2688 // (rotl x, y) 2689 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2690 // (rotr x, (sub 32, y)) 2691 if (ConstantSDNode *SUBC = 2692 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2693 if (SUBC->getAPIntValue() == OpSizeInBits) { 2694 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2695 LHSShiftArg, 2696 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2697 } 2698 } 2699 } else if (LExtOp0.getOpcode() == ISD::SUB && 2700 RExtOp0 == LExtOp0.getOperand(1)) { 2701 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2702 // (rotr x, y) 2703 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2704 // (rotl x, (sub 32, y)) 2705 if (ConstantSDNode *SUBC = 2706 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2707 if (SUBC->getAPIntValue() == OpSizeInBits) { 2708 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2709 LHSShiftArg, 2710 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2711 } 2712 } 2713 } 2714 } 2715 2716 return 0; 2717} 2718 2719SDValue DAGCombiner::visitXOR(SDNode *N) { 2720 SDValue N0 = N->getOperand(0); 2721 SDValue N1 = N->getOperand(1); 2722 SDValue LHS, RHS, CC; 2723 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2725 EVT VT = N0.getValueType(); 2726 2727 // fold vector ops 2728 if (VT.isVector()) { 2729 SDValue FoldedVOp = SimplifyVBinOp(N); 2730 if (FoldedVOp.getNode()) return FoldedVOp; 2731 } 2732 2733 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2734 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2735 return DAG.getConstant(0, VT); 2736 // fold (xor x, undef) -> undef 2737 if (N0.getOpcode() == ISD::UNDEF) 2738 return N0; 2739 if (N1.getOpcode() == ISD::UNDEF) 2740 return N1; 2741 // fold (xor c1, c2) -> c1^c2 2742 if (N0C && N1C) 2743 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2744 // canonicalize constant to RHS 2745 if (N0C && !N1C) 2746 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2747 // fold (xor x, 0) -> x 2748 if (N1C && N1C->isNullValue()) 2749 return N0; 2750 // reassociate xor 2751 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2752 if (RXOR.getNode() != 0) 2753 return RXOR; 2754 2755 // fold !(x cc y) -> (x !cc y) 2756 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2757 bool isInt = LHS.getValueType().isInteger(); 2758 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2759 isInt); 2760 2761 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2762 switch (N0.getOpcode()) { 2763 default: 2764 llvm_unreachable("Unhandled SetCC Equivalent!"); 2765 case ISD::SETCC: 2766 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2767 case ISD::SELECT_CC: 2768 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2769 N0.getOperand(3), NotCC); 2770 } 2771 } 2772 } 2773 2774 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2775 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2776 N0.getNode()->hasOneUse() && 2777 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2778 SDValue V = N0.getOperand(0); 2779 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2780 DAG.getConstant(1, V.getValueType())); 2781 AddToWorkList(V.getNode()); 2782 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2783 } 2784 2785 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2786 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2787 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2788 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2789 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2790 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2791 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2792 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2793 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2794 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2795 } 2796 } 2797 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2798 if (N1C && N1C->isAllOnesValue() && 2799 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2800 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2801 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2802 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2803 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2804 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2805 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2806 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2807 } 2808 } 2809 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2810 if (N1C && N0.getOpcode() == ISD::XOR) { 2811 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2812 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2813 if (N00C) 2814 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2815 DAG.getConstant(N1C->getAPIntValue() ^ 2816 N00C->getAPIntValue(), VT)); 2817 if (N01C) 2818 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2819 DAG.getConstant(N1C->getAPIntValue() ^ 2820 N01C->getAPIntValue(), VT)); 2821 } 2822 // fold (xor x, x) -> 0 2823 if (N0 == N1) { 2824 if (!VT.isVector()) { 2825 return DAG.getConstant(0, VT); 2826 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2827 // Produce a vector of zeros. 2828 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2829 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2830 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2831 &Ops[0], Ops.size()); 2832 } 2833 } 2834 2835 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2836 if (N0.getOpcode() == N1.getOpcode()) { 2837 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2838 if (Tmp.getNode()) return Tmp; 2839 } 2840 2841 // Simplify the expression using non-local knowledge. 2842 if (!VT.isVector() && 2843 SimplifyDemandedBits(SDValue(N, 0))) 2844 return SDValue(N, 0); 2845 2846 return SDValue(); 2847} 2848 2849/// visitShiftByConstant - Handle transforms common to the three shifts, when 2850/// the shift amount is a constant. 2851SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2852 SDNode *LHS = N->getOperand(0).getNode(); 2853 if (!LHS->hasOneUse()) return SDValue(); 2854 2855 // We want to pull some binops through shifts, so that we have (and (shift)) 2856 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2857 // thing happens with address calculations, so it's important to canonicalize 2858 // it. 2859 bool HighBitSet = false; // Can we transform this if the high bit is set? 2860 2861 switch (LHS->getOpcode()) { 2862 default: return SDValue(); 2863 case ISD::OR: 2864 case ISD::XOR: 2865 HighBitSet = false; // We can only transform sra if the high bit is clear. 2866 break; 2867 case ISD::AND: 2868 HighBitSet = true; // We can only transform sra if the high bit is set. 2869 break; 2870 case ISD::ADD: 2871 if (N->getOpcode() != ISD::SHL) 2872 return SDValue(); // only shl(add) not sr[al](add). 2873 HighBitSet = false; // We can only transform sra if the high bit is clear. 2874 break; 2875 } 2876 2877 // We require the RHS of the binop to be a constant as well. 2878 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2879 if (!BinOpCst) return SDValue(); 2880 2881 // FIXME: disable this unless the input to the binop is a shift by a constant. 2882 // If it is not a shift, it pessimizes some common cases like: 2883 // 2884 // void foo(int *X, int i) { X[i & 1235] = 1; } 2885 // int bar(int *X, int i) { return X[i & 255]; } 2886 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2887 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2888 BinOpLHSVal->getOpcode() != ISD::SRA && 2889 BinOpLHSVal->getOpcode() != ISD::SRL) || 2890 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2891 return SDValue(); 2892 2893 EVT VT = N->getValueType(0); 2894 2895 // If this is a signed shift right, and the high bit is modified by the 2896 // logical operation, do not perform the transformation. The highBitSet 2897 // boolean indicates the value of the high bit of the constant which would 2898 // cause it to be modified for this operation. 2899 if (N->getOpcode() == ISD::SRA) { 2900 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2901 if (BinOpRHSSignSet != HighBitSet) 2902 return SDValue(); 2903 } 2904 2905 // Fold the constants, shifting the binop RHS by the shift amount. 2906 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2907 N->getValueType(0), 2908 LHS->getOperand(1), N->getOperand(1)); 2909 2910 // Create the new shift. 2911 SDValue NewShift = DAG.getNode(N->getOpcode(), 2912 LHS->getOperand(0).getDebugLoc(), 2913 VT, LHS->getOperand(0), N->getOperand(1)); 2914 2915 // Create the new binop. 2916 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2917} 2918 2919SDValue DAGCombiner::visitSHL(SDNode *N) { 2920 SDValue N0 = N->getOperand(0); 2921 SDValue N1 = N->getOperand(1); 2922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2924 EVT VT = N0.getValueType(); 2925 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2926 2927 // fold (shl c1, c2) -> c1<<c2 2928 if (N0C && N1C) 2929 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2930 // fold (shl 0, x) -> 0 2931 if (N0C && N0C->isNullValue()) 2932 return N0; 2933 // fold (shl x, c >= size(x)) -> undef 2934 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2935 return DAG.getUNDEF(VT); 2936 // fold (shl x, 0) -> x 2937 if (N1C && N1C->isNullValue()) 2938 return N0; 2939 // if (shl x, c) is known to be zero, return 0 2940 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2941 APInt::getAllOnesValue(OpSizeInBits))) 2942 return DAG.getConstant(0, VT); 2943 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2944 if (N1.getOpcode() == ISD::TRUNCATE && 2945 N1.getOperand(0).getOpcode() == ISD::AND && 2946 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2947 SDValue N101 = N1.getOperand(0).getOperand(1); 2948 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2949 EVT TruncVT = N1.getValueType(); 2950 SDValue N100 = N1.getOperand(0).getOperand(0); 2951 APInt TruncC = N101C->getAPIntValue(); 2952 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 2953 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2954 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2955 DAG.getNode(ISD::TRUNCATE, 2956 N->getDebugLoc(), 2957 TruncVT, N100), 2958 DAG.getConstant(TruncC, TruncVT))); 2959 } 2960 } 2961 2962 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2963 return SDValue(N, 0); 2964 2965 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2966 if (N1C && N0.getOpcode() == ISD::SHL && 2967 N0.getOperand(1).getOpcode() == ISD::Constant) { 2968 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2969 uint64_t c2 = N1C->getZExtValue(); 2970 if (c1 + c2 >= OpSizeInBits) 2971 return DAG.getConstant(0, VT); 2972 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2973 DAG.getConstant(c1 + c2, N1.getValueType())); 2974 } 2975 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2976 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2977 if (N1C && N0.getOpcode() == ISD::SRL && 2978 N0.getOperand(1).getOpcode() == ISD::Constant) { 2979 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2980 if (c1 < VT.getSizeInBits()) { 2981 uint64_t c2 = N1C->getZExtValue(); 2982 SDValue HiBitsMask = 2983 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2984 VT.getSizeInBits() - c1), 2985 VT); 2986 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2987 N0.getOperand(0), 2988 HiBitsMask); 2989 if (c2 > c1) 2990 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2991 DAG.getConstant(c2-c1, N1.getValueType())); 2992 else 2993 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2994 DAG.getConstant(c1-c2, N1.getValueType())); 2995 } 2996 } 2997 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2998 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2999 SDValue HiBitsMask = 3000 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3001 VT.getSizeInBits() - 3002 N1C->getZExtValue()), 3003 VT); 3004 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3005 HiBitsMask); 3006 } 3007 3008 if (N1C) { 3009 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3010 if (NewSHL.getNode()) 3011 return NewSHL; 3012 } 3013 3014 return SDValue(); 3015} 3016 3017SDValue DAGCombiner::visitSRA(SDNode *N) { 3018 SDValue N0 = N->getOperand(0); 3019 SDValue N1 = N->getOperand(1); 3020 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3021 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3022 EVT VT = N0.getValueType(); 3023 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3024 3025 // fold (sra c1, c2) -> (sra c1, c2) 3026 if (N0C && N1C) 3027 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3028 // fold (sra 0, x) -> 0 3029 if (N0C && N0C->isNullValue()) 3030 return N0; 3031 // fold (sra -1, x) -> -1 3032 if (N0C && N0C->isAllOnesValue()) 3033 return N0; 3034 // fold (sra x, (setge c, size(x))) -> undef 3035 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3036 return DAG.getUNDEF(VT); 3037 // fold (sra x, 0) -> x 3038 if (N1C && N1C->isNullValue()) 3039 return N0; 3040 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3041 // sext_inreg. 3042 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3043 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3044 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3045 if (VT.isVector()) 3046 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3047 ExtVT, VT.getVectorNumElements()); 3048 if ((!LegalOperations || 3049 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3050 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3051 N0.getOperand(0), DAG.getValueType(ExtVT)); 3052 } 3053 3054 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3055 if (N1C && N0.getOpcode() == ISD::SRA) { 3056 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3057 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3058 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3059 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3060 DAG.getConstant(Sum, N1C->getValueType(0))); 3061 } 3062 } 3063 3064 // fold (sra (shl X, m), (sub result_size, n)) 3065 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3066 // result_size - n != m. 3067 // If truncate is free for the target sext(shl) is likely to result in better 3068 // code. 3069 if (N0.getOpcode() == ISD::SHL) { 3070 // Get the two constanst of the shifts, CN0 = m, CN = n. 3071 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3072 if (N01C && N1C) { 3073 // Determine what the truncate's result bitsize and type would be. 3074 EVT TruncVT = 3075 EVT::getIntegerVT(*DAG.getContext(), 3076 OpSizeInBits - N1C->getZExtValue()); 3077 // Determine the residual right-shift amount. 3078 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3079 3080 // If the shift is not a no-op (in which case this should be just a sign 3081 // extend already), the truncated to type is legal, sign_extend is legal 3082 // on that type, and the truncate to that type is both legal and free, 3083 // perform the transform. 3084 if ((ShiftAmt > 0) && 3085 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3086 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3087 TLI.isTruncateFree(VT, TruncVT)) { 3088 3089 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 3090 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3091 N0.getOperand(0), Amt); 3092 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3093 Shift); 3094 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3095 N->getValueType(0), Trunc); 3096 } 3097 } 3098 } 3099 3100 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3101 if (N1.getOpcode() == ISD::TRUNCATE && 3102 N1.getOperand(0).getOpcode() == ISD::AND && 3103 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3104 SDValue N101 = N1.getOperand(0).getOperand(1); 3105 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3106 EVT TruncVT = N1.getValueType(); 3107 SDValue N100 = N1.getOperand(0).getOperand(0); 3108 APInt TruncC = N101C->getAPIntValue(); 3109 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3110 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3111 DAG.getNode(ISD::AND, N->getDebugLoc(), 3112 TruncVT, 3113 DAG.getNode(ISD::TRUNCATE, 3114 N->getDebugLoc(), 3115 TruncVT, N100), 3116 DAG.getConstant(TruncC, TruncVT))); 3117 } 3118 } 3119 3120 // Simplify, based on bits shifted out of the LHS. 3121 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3122 return SDValue(N, 0); 3123 3124 3125 // If the sign bit is known to be zero, switch this to a SRL. 3126 if (DAG.SignBitIsZero(N0)) 3127 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3128 3129 if (N1C) { 3130 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3131 if (NewSRA.getNode()) 3132 return NewSRA; 3133 } 3134 3135 return SDValue(); 3136} 3137 3138SDValue DAGCombiner::visitSRL(SDNode *N) { 3139 SDValue N0 = N->getOperand(0); 3140 SDValue N1 = N->getOperand(1); 3141 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3142 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3143 EVT VT = N0.getValueType(); 3144 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3145 3146 // fold (srl c1, c2) -> c1 >>u c2 3147 if (N0C && N1C) 3148 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3149 // fold (srl 0, x) -> 0 3150 if (N0C && N0C->isNullValue()) 3151 return N0; 3152 // fold (srl x, c >= size(x)) -> undef 3153 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3154 return DAG.getUNDEF(VT); 3155 // fold (srl x, 0) -> x 3156 if (N1C && N1C->isNullValue()) 3157 return N0; 3158 // if (srl x, c) is known to be zero, return 0 3159 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3160 APInt::getAllOnesValue(OpSizeInBits))) 3161 return DAG.getConstant(0, VT); 3162 3163 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3164 if (N1C && N0.getOpcode() == ISD::SRL && 3165 N0.getOperand(1).getOpcode() == ISD::Constant) { 3166 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3167 uint64_t c2 = N1C->getZExtValue(); 3168 if (c1 + c2 >= OpSizeInBits) 3169 return DAG.getConstant(0, VT); 3170 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3171 DAG.getConstant(c1 + c2, N1.getValueType())); 3172 } 3173 3174 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3175 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3176 N0.getOperand(0).getOpcode() == ISD::SRL && 3177 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3178 uint64_t c1 = 3179 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3180 uint64_t c2 = N1C->getZExtValue(); 3181 EVT InnerShiftVT = N0.getOperand(0)->getOperand(1).getValueType(); 3182 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3183 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3184 if (c1 + OpSizeInBits == InnerShiftSize) { 3185 if (c1 + c2 >= InnerShiftSize) 3186 return DAG.getConstant(0, VT); 3187 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3188 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3189 N0.getOperand(0)->getOperand(0), 3190 DAG.getConstant(c1 + c2, InnerShiftVT))); 3191 } 3192 } 3193 3194 // fold (srl (shl x, c), c) -> (and x, cst2) 3195 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3196 N0.getValueSizeInBits() <= 64) { 3197 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3198 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3199 DAG.getConstant(~0ULL >> ShAmt, VT)); 3200 } 3201 3202 3203 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3204 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3205 // Shifting in all undef bits? 3206 EVT SmallVT = N0.getOperand(0).getValueType(); 3207 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3208 return DAG.getUNDEF(VT); 3209 3210 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3211 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3212 N0.getOperand(0), N1); 3213 AddToWorkList(SmallShift.getNode()); 3214 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3215 } 3216 } 3217 3218 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3219 // bit, which is unmodified by sra. 3220 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3221 if (N0.getOpcode() == ISD::SRA) 3222 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3223 } 3224 3225 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3226 if (N1C && N0.getOpcode() == ISD::CTLZ && 3227 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3228 APInt KnownZero, KnownOne; 3229 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3230 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3231 3232 // If any of the input bits are KnownOne, then the input couldn't be all 3233 // zeros, thus the result of the srl will always be zero. 3234 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3235 3236 // If all of the bits input the to ctlz node are known to be zero, then 3237 // the result of the ctlz is "32" and the result of the shift is one. 3238 APInt UnknownBits = ~KnownZero & Mask; 3239 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3240 3241 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3242 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3243 // Okay, we know that only that the single bit specified by UnknownBits 3244 // could be set on input to the CTLZ node. If this bit is set, the SRL 3245 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3246 // to an SRL/XOR pair, which is likely to simplify more. 3247 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3248 SDValue Op = N0.getOperand(0); 3249 3250 if (ShAmt) { 3251 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3252 DAG.getConstant(ShAmt, getShiftAmountTy())); 3253 AddToWorkList(Op.getNode()); 3254 } 3255 3256 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3257 Op, DAG.getConstant(1, VT)); 3258 } 3259 } 3260 3261 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3262 if (N1.getOpcode() == ISD::TRUNCATE && 3263 N1.getOperand(0).getOpcode() == ISD::AND && 3264 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3265 SDValue N101 = N1.getOperand(0).getOperand(1); 3266 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3267 EVT TruncVT = N1.getValueType(); 3268 SDValue N100 = N1.getOperand(0).getOperand(0); 3269 APInt TruncC = N101C->getAPIntValue(); 3270 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3271 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3272 DAG.getNode(ISD::AND, N->getDebugLoc(), 3273 TruncVT, 3274 DAG.getNode(ISD::TRUNCATE, 3275 N->getDebugLoc(), 3276 TruncVT, N100), 3277 DAG.getConstant(TruncC, TruncVT))); 3278 } 3279 } 3280 3281 // fold operands of srl based on knowledge that the low bits are not 3282 // demanded. 3283 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3284 return SDValue(N, 0); 3285 3286 if (N1C) { 3287 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3288 if (NewSRL.getNode()) 3289 return NewSRL; 3290 } 3291 3292 // Attempt to convert a srl of a load into a narrower zero-extending load. 3293 SDValue NarrowLoad = ReduceLoadWidth(N); 3294 if (NarrowLoad.getNode()) 3295 return NarrowLoad; 3296 3297 // Here is a common situation. We want to optimize: 3298 // 3299 // %a = ... 3300 // %b = and i32 %a, 2 3301 // %c = srl i32 %b, 1 3302 // brcond i32 %c ... 3303 // 3304 // into 3305 // 3306 // %a = ... 3307 // %b = and %a, 2 3308 // %c = setcc eq %b, 0 3309 // brcond %c ... 3310 // 3311 // However when after the source operand of SRL is optimized into AND, the SRL 3312 // itself may not be optimized further. Look for it and add the BRCOND into 3313 // the worklist. 3314 if (N->hasOneUse()) { 3315 SDNode *Use = *N->use_begin(); 3316 if (Use->getOpcode() == ISD::BRCOND) 3317 AddToWorkList(Use); 3318 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3319 // Also look pass the truncate. 3320 Use = *Use->use_begin(); 3321 if (Use->getOpcode() == ISD::BRCOND) 3322 AddToWorkList(Use); 3323 } 3324 } 3325 3326 return SDValue(); 3327} 3328 3329SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3330 SDValue N0 = N->getOperand(0); 3331 EVT VT = N->getValueType(0); 3332 3333 // fold (ctlz c1) -> c2 3334 if (isa<ConstantSDNode>(N0)) 3335 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3336 return SDValue(); 3337} 3338 3339SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3340 SDValue N0 = N->getOperand(0); 3341 EVT VT = N->getValueType(0); 3342 3343 // fold (cttz c1) -> c2 3344 if (isa<ConstantSDNode>(N0)) 3345 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3346 return SDValue(); 3347} 3348 3349SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3350 SDValue N0 = N->getOperand(0); 3351 EVT VT = N->getValueType(0); 3352 3353 // fold (ctpop c1) -> c2 3354 if (isa<ConstantSDNode>(N0)) 3355 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3356 return SDValue(); 3357} 3358 3359SDValue DAGCombiner::visitSELECT(SDNode *N) { 3360 SDValue N0 = N->getOperand(0); 3361 SDValue N1 = N->getOperand(1); 3362 SDValue N2 = N->getOperand(2); 3363 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3364 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3365 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3366 EVT VT = N->getValueType(0); 3367 EVT VT0 = N0.getValueType(); 3368 3369 // fold (select C, X, X) -> X 3370 if (N1 == N2) 3371 return N1; 3372 // fold (select true, X, Y) -> X 3373 if (N0C && !N0C->isNullValue()) 3374 return N1; 3375 // fold (select false, X, Y) -> Y 3376 if (N0C && N0C->isNullValue()) 3377 return N2; 3378 // fold (select C, 1, X) -> (or C, X) 3379 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3380 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3381 // fold (select C, 0, 1) -> (xor C, 1) 3382 if (VT.isInteger() && 3383 (VT0 == MVT::i1 || 3384 (VT0.isInteger() && 3385 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3386 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3387 SDValue XORNode; 3388 if (VT == VT0) 3389 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3390 N0, DAG.getConstant(1, VT0)); 3391 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3392 N0, DAG.getConstant(1, VT0)); 3393 AddToWorkList(XORNode.getNode()); 3394 if (VT.bitsGT(VT0)) 3395 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3396 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3397 } 3398 // fold (select C, 0, X) -> (and (not C), X) 3399 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3400 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3401 AddToWorkList(NOTNode.getNode()); 3402 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3403 } 3404 // fold (select C, X, 1) -> (or (not C), X) 3405 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3406 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3407 AddToWorkList(NOTNode.getNode()); 3408 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3409 } 3410 // fold (select C, X, 0) -> (and C, X) 3411 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3412 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3413 // fold (select X, X, Y) -> (or X, Y) 3414 // fold (select X, 1, Y) -> (or X, Y) 3415 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3416 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3417 // fold (select X, Y, X) -> (and X, Y) 3418 // fold (select X, Y, 0) -> (and X, Y) 3419 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3420 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3421 3422 // If we can fold this based on the true/false value, do so. 3423 if (SimplifySelectOps(N, N1, N2)) 3424 return SDValue(N, 0); // Don't revisit N. 3425 3426 // fold selects based on a setcc into other things, such as min/max/abs 3427 if (N0.getOpcode() == ISD::SETCC) { 3428 // FIXME: 3429 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3430 // having to say they don't support SELECT_CC on every type the DAG knows 3431 // about, since there is no way to mark an opcode illegal at all value types 3432 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3433 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3434 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3435 N0.getOperand(0), N0.getOperand(1), 3436 N1, N2, N0.getOperand(2)); 3437 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3438 } 3439 3440 return SDValue(); 3441} 3442 3443SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3444 SDValue N0 = N->getOperand(0); 3445 SDValue N1 = N->getOperand(1); 3446 SDValue N2 = N->getOperand(2); 3447 SDValue N3 = N->getOperand(3); 3448 SDValue N4 = N->getOperand(4); 3449 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3450 3451 // fold select_cc lhs, rhs, x, x, cc -> x 3452 if (N2 == N3) 3453 return N2; 3454 3455 // Determine if the condition we're dealing with is constant 3456 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3457 N0, N1, CC, N->getDebugLoc(), false); 3458 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3459 3460 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3461 if (!SCCC->isNullValue()) 3462 return N2; // cond always true -> true val 3463 else 3464 return N3; // cond always false -> false val 3465 } 3466 3467 // Fold to a simpler select_cc 3468 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3469 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3470 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3471 SCC.getOperand(2)); 3472 3473 // If we can fold this based on the true/false value, do so. 3474 if (SimplifySelectOps(N, N2, N3)) 3475 return SDValue(N, 0); // Don't revisit N. 3476 3477 // fold select_cc into other things, such as min/max/abs 3478 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3479} 3480 3481SDValue DAGCombiner::visitSETCC(SDNode *N) { 3482 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3483 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3484 N->getDebugLoc()); 3485} 3486 3487// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3488// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3489// transformation. Returns true if extension are possible and the above 3490// mentioned transformation is profitable. 3491static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3492 unsigned ExtOpc, 3493 SmallVector<SDNode*, 4> &ExtendNodes, 3494 const TargetLowering &TLI) { 3495 bool HasCopyToRegUses = false; 3496 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3497 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3498 UE = N0.getNode()->use_end(); 3499 UI != UE; ++UI) { 3500 SDNode *User = *UI; 3501 if (User == N) 3502 continue; 3503 if (UI.getUse().getResNo() != N0.getResNo()) 3504 continue; 3505 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3506 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3507 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3508 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3509 // Sign bits will be lost after a zext. 3510 return false; 3511 bool Add = false; 3512 for (unsigned i = 0; i != 2; ++i) { 3513 SDValue UseOp = User->getOperand(i); 3514 if (UseOp == N0) 3515 continue; 3516 if (!isa<ConstantSDNode>(UseOp)) 3517 return false; 3518 Add = true; 3519 } 3520 if (Add) 3521 ExtendNodes.push_back(User); 3522 continue; 3523 } 3524 // If truncates aren't free and there are users we can't 3525 // extend, it isn't worthwhile. 3526 if (!isTruncFree) 3527 return false; 3528 // Remember if this value is live-out. 3529 if (User->getOpcode() == ISD::CopyToReg) 3530 HasCopyToRegUses = true; 3531 } 3532 3533 if (HasCopyToRegUses) { 3534 bool BothLiveOut = false; 3535 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3536 UI != UE; ++UI) { 3537 SDUse &Use = UI.getUse(); 3538 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3539 BothLiveOut = true; 3540 break; 3541 } 3542 } 3543 if (BothLiveOut) 3544 // Both unextended and extended values are live out. There had better be 3545 // a good reason for the transformation. 3546 return ExtendNodes.size(); 3547 } 3548 return true; 3549} 3550 3551SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3552 SDValue N0 = N->getOperand(0); 3553 EVT VT = N->getValueType(0); 3554 3555 // fold (sext c1) -> c1 3556 if (isa<ConstantSDNode>(N0)) 3557 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3558 3559 // fold (sext (sext x)) -> (sext x) 3560 // fold (sext (aext x)) -> (sext x) 3561 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3562 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3563 N0.getOperand(0)); 3564 3565 if (N0.getOpcode() == ISD::TRUNCATE) { 3566 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3567 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3568 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3569 if (NarrowLoad.getNode()) { 3570 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3571 if (NarrowLoad.getNode() != N0.getNode()) { 3572 CombineTo(N0.getNode(), NarrowLoad); 3573 // CombineTo deleted the truncate, if needed, but not what's under it. 3574 AddToWorkList(oye); 3575 } 3576 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3577 } 3578 3579 // See if the value being truncated is already sign extended. If so, just 3580 // eliminate the trunc/sext pair. 3581 SDValue Op = N0.getOperand(0); 3582 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3583 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3584 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3585 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3586 3587 if (OpBits == DestBits) { 3588 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3589 // bits, it is already ready. 3590 if (NumSignBits > DestBits-MidBits) 3591 return Op; 3592 } else if (OpBits < DestBits) { 3593 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3594 // bits, just sext from i32. 3595 if (NumSignBits > OpBits-MidBits) 3596 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3597 } else { 3598 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3599 // bits, just truncate to i32. 3600 if (NumSignBits > OpBits-MidBits) 3601 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3602 } 3603 3604 // fold (sext (truncate x)) -> (sextinreg x). 3605 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3606 N0.getValueType())) { 3607 if (OpBits < DestBits) 3608 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3609 else if (OpBits > DestBits) 3610 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3611 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3612 DAG.getValueType(N0.getValueType())); 3613 } 3614 } 3615 3616 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3617 if (ISD::isNON_EXTLoad(N0.getNode()) && 3618 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3619 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3620 bool DoXform = true; 3621 SmallVector<SDNode*, 4> SetCCs; 3622 if (!N0.hasOneUse()) 3623 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3624 if (DoXform) { 3625 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3626 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3627 LN0->getChain(), 3628 LN0->getBasePtr(), LN0->getPointerInfo(), 3629 N0.getValueType(), 3630 LN0->isVolatile(), LN0->isNonTemporal(), 3631 LN0->getAlignment()); 3632 CombineTo(N, ExtLoad); 3633 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3634 N0.getValueType(), ExtLoad); 3635 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3636 3637 // Extend SetCC uses if necessary. 3638 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3639 SDNode *SetCC = SetCCs[i]; 3640 SmallVector<SDValue, 4> Ops; 3641 3642 for (unsigned j = 0; j != 2; ++j) { 3643 SDValue SOp = SetCC->getOperand(j); 3644 if (SOp == Trunc) 3645 Ops.push_back(ExtLoad); 3646 else 3647 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3648 N->getDebugLoc(), VT, SOp)); 3649 } 3650 3651 Ops.push_back(SetCC->getOperand(2)); 3652 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3653 SetCC->getValueType(0), 3654 &Ops[0], Ops.size())); 3655 } 3656 3657 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3658 } 3659 } 3660 3661 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3662 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3663 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3664 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3665 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3666 EVT MemVT = LN0->getMemoryVT(); 3667 if ((!LegalOperations && !LN0->isVolatile()) || 3668 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3669 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 3670 LN0->getChain(), 3671 LN0->getBasePtr(), LN0->getPointerInfo(), 3672 MemVT, 3673 LN0->isVolatile(), LN0->isNonTemporal(), 3674 LN0->getAlignment()); 3675 CombineTo(N, ExtLoad); 3676 CombineTo(N0.getNode(), 3677 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3678 N0.getValueType(), ExtLoad), 3679 ExtLoad.getValue(1)); 3680 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3681 } 3682 } 3683 3684 if (N0.getOpcode() == ISD::SETCC) { 3685 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3686 // Only do this before legalize for now. 3687 if (VT.isVector() && !LegalOperations) { 3688 EVT N0VT = N0.getOperand(0).getValueType(); 3689 // We know that the # elements of the results is the same as the 3690 // # elements of the compare (and the # elements of the compare result 3691 // for that matter). Check to see that they are the same size. If so, 3692 // we know that the element size of the sext'd result matches the 3693 // element size of the compare operands. 3694 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3695 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3696 N0.getOperand(1), 3697 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3698 // If the desired elements are smaller or larger than the source 3699 // elements we can use a matching integer vector type and then 3700 // truncate/sign extend 3701 else { 3702 EVT MatchingElementType = 3703 EVT::getIntegerVT(*DAG.getContext(), 3704 N0VT.getScalarType().getSizeInBits()); 3705 EVT MatchingVectorType = 3706 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3707 N0VT.getVectorNumElements()); 3708 SDValue VsetCC = 3709 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3710 N0.getOperand(1), 3711 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3712 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3713 } 3714 } 3715 3716 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3717 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3718 SDValue NegOne = 3719 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3720 SDValue SCC = 3721 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3722 NegOne, DAG.getConstant(0, VT), 3723 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3724 if (SCC.getNode()) return SCC; 3725 if (!LegalOperations || 3726 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3727 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3728 DAG.getSetCC(N->getDebugLoc(), 3729 TLI.getSetCCResultType(VT), 3730 N0.getOperand(0), N0.getOperand(1), 3731 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3732 NegOne, DAG.getConstant(0, VT)); 3733 } 3734 3735 // fold (sext x) -> (zext x) if the sign bit is known zero. 3736 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3737 DAG.SignBitIsZero(N0)) 3738 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3739 3740 return SDValue(); 3741} 3742 3743SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3744 SDValue N0 = N->getOperand(0); 3745 EVT VT = N->getValueType(0); 3746 3747 // fold (zext c1) -> c1 3748 if (isa<ConstantSDNode>(N0)) 3749 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3750 // fold (zext (zext x)) -> (zext x) 3751 // fold (zext (aext x)) -> (zext x) 3752 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3753 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3754 N0.getOperand(0)); 3755 3756 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3757 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3758 if (N0.getOpcode() == ISD::TRUNCATE) { 3759 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3760 if (NarrowLoad.getNode()) { 3761 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3762 if (NarrowLoad.getNode() != N0.getNode()) { 3763 CombineTo(N0.getNode(), NarrowLoad); 3764 // CombineTo deleted the truncate, if needed, but not what's under it. 3765 AddToWorkList(oye); 3766 } 3767 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3768 } 3769 } 3770 3771 // fold (zext (truncate x)) -> (and x, mask) 3772 if (N0.getOpcode() == ISD::TRUNCATE && 3773 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3774 3775 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3776 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3777 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3778 if (NarrowLoad.getNode()) { 3779 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3780 if (NarrowLoad.getNode() != N0.getNode()) { 3781 CombineTo(N0.getNode(), NarrowLoad); 3782 // CombineTo deleted the truncate, if needed, but not what's under it. 3783 AddToWorkList(oye); 3784 } 3785 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3786 } 3787 3788 SDValue Op = N0.getOperand(0); 3789 if (Op.getValueType().bitsLT(VT)) { 3790 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3791 } else if (Op.getValueType().bitsGT(VT)) { 3792 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3793 } 3794 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3795 N0.getValueType().getScalarType()); 3796 } 3797 3798 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3799 // if either of the casts is not free. 3800 if (N0.getOpcode() == ISD::AND && 3801 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3802 N0.getOperand(1).getOpcode() == ISD::Constant && 3803 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3804 N0.getValueType()) || 3805 !TLI.isZExtFree(N0.getValueType(), VT))) { 3806 SDValue X = N0.getOperand(0).getOperand(0); 3807 if (X.getValueType().bitsLT(VT)) { 3808 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3809 } else if (X.getValueType().bitsGT(VT)) { 3810 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3811 } 3812 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3813 Mask = Mask.zext(VT.getSizeInBits()); 3814 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3815 X, DAG.getConstant(Mask, VT)); 3816 } 3817 3818 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3819 if (ISD::isNON_EXTLoad(N0.getNode()) && 3820 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3821 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3822 bool DoXform = true; 3823 SmallVector<SDNode*, 4> SetCCs; 3824 if (!N0.hasOneUse()) 3825 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3826 if (DoXform) { 3827 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3828 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3829 LN0->getChain(), 3830 LN0->getBasePtr(), LN0->getPointerInfo(), 3831 N0.getValueType(), 3832 LN0->isVolatile(), LN0->isNonTemporal(), 3833 LN0->getAlignment()); 3834 CombineTo(N, ExtLoad); 3835 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3836 N0.getValueType(), ExtLoad); 3837 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3838 3839 // Extend SetCC uses if necessary. 3840 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3841 SDNode *SetCC = SetCCs[i]; 3842 SmallVector<SDValue, 4> Ops; 3843 3844 for (unsigned j = 0; j != 2; ++j) { 3845 SDValue SOp = SetCC->getOperand(j); 3846 if (SOp == Trunc) 3847 Ops.push_back(ExtLoad); 3848 else 3849 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3850 N->getDebugLoc(), VT, SOp)); 3851 } 3852 3853 Ops.push_back(SetCC->getOperand(2)); 3854 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3855 SetCC->getValueType(0), 3856 &Ops[0], Ops.size())); 3857 } 3858 3859 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3860 } 3861 } 3862 3863 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3864 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3865 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3866 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3867 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3868 EVT MemVT = LN0->getMemoryVT(); 3869 if ((!LegalOperations && !LN0->isVolatile()) || 3870 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3871 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N->getDebugLoc(), 3872 LN0->getChain(), 3873 LN0->getBasePtr(), LN0->getPointerInfo(), 3874 MemVT, 3875 LN0->isVolatile(), LN0->isNonTemporal(), 3876 LN0->getAlignment()); 3877 CombineTo(N, ExtLoad); 3878 CombineTo(N0.getNode(), 3879 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3880 ExtLoad), 3881 ExtLoad.getValue(1)); 3882 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3883 } 3884 } 3885 3886 if (N0.getOpcode() == ISD::SETCC) { 3887 if (!LegalOperations && VT.isVector()) { 3888 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 3889 // Only do this before legalize for now. 3890 EVT N0VT = N0.getOperand(0).getValueType(); 3891 EVT EltVT = VT.getVectorElementType(); 3892 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 3893 DAG.getConstant(1, EltVT)); 3894 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 3895 // We know that the # elements of the results is the same as the 3896 // # elements of the compare (and the # elements of the compare result 3897 // for that matter). Check to see that they are the same size. If so, 3898 // we know that the element size of the sext'd result matches the 3899 // element size of the compare operands. 3900 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3901 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3902 N0.getOperand(1), 3903 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3904 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3905 &OneOps[0], OneOps.size())); 3906 } else { 3907 // If the desired elements are smaller or larger than the source 3908 // elements we can use a matching integer vector type and then 3909 // truncate/sign extend 3910 EVT MatchingElementType = 3911 EVT::getIntegerVT(*DAG.getContext(), 3912 N0VT.getScalarType().getSizeInBits()); 3913 EVT MatchingVectorType = 3914 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3915 N0VT.getVectorNumElements()); 3916 SDValue VsetCC = 3917 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3918 N0.getOperand(1), 3919 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3920 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3921 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 3922 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 3923 &OneOps[0], OneOps.size())); 3924 } 3925 } 3926 3927 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3928 SDValue SCC = 3929 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3930 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3931 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3932 if (SCC.getNode()) return SCC; 3933 } 3934 3935 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3936 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3937 isa<ConstantSDNode>(N0.getOperand(1)) && 3938 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3939 N0.hasOneUse()) { 3940 if (N0.getOpcode() == ISD::SHL) { 3941 // If the original shl may be shifting out bits, do not perform this 3942 // transformation. 3943 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3944 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3945 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3946 if (ShAmt > KnownZeroBits) 3947 return SDValue(); 3948 } 3949 DebugLoc dl = N->getDebugLoc(); 3950 return DAG.getNode(N0.getOpcode(), dl, VT, 3951 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3952 DAG.getNode(ISD::ZERO_EXTEND, dl, 3953 N0.getOperand(1).getValueType(), 3954 N0.getOperand(1))); 3955 } 3956 3957 return SDValue(); 3958} 3959 3960SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3961 SDValue N0 = N->getOperand(0); 3962 EVT VT = N->getValueType(0); 3963 3964 // fold (aext c1) -> c1 3965 if (isa<ConstantSDNode>(N0)) 3966 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3967 // fold (aext (aext x)) -> (aext x) 3968 // fold (aext (zext x)) -> (zext x) 3969 // fold (aext (sext x)) -> (sext x) 3970 if (N0.getOpcode() == ISD::ANY_EXTEND || 3971 N0.getOpcode() == ISD::ZERO_EXTEND || 3972 N0.getOpcode() == ISD::SIGN_EXTEND) 3973 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3974 3975 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3976 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3977 if (N0.getOpcode() == ISD::TRUNCATE) { 3978 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3979 if (NarrowLoad.getNode()) { 3980 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3981 if (NarrowLoad.getNode() != N0.getNode()) { 3982 CombineTo(N0.getNode(), NarrowLoad); 3983 // CombineTo deleted the truncate, if needed, but not what's under it. 3984 AddToWorkList(oye); 3985 } 3986 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3987 } 3988 } 3989 3990 // fold (aext (truncate x)) 3991 if (N0.getOpcode() == ISD::TRUNCATE) { 3992 SDValue TruncOp = N0.getOperand(0); 3993 if (TruncOp.getValueType() == VT) 3994 return TruncOp; // x iff x size == zext size. 3995 if (TruncOp.getValueType().bitsGT(VT)) 3996 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3997 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3998 } 3999 4000 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4001 // if the trunc is not free. 4002 if (N0.getOpcode() == ISD::AND && 4003 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4004 N0.getOperand(1).getOpcode() == ISD::Constant && 4005 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4006 N0.getValueType())) { 4007 SDValue X = N0.getOperand(0).getOperand(0); 4008 if (X.getValueType().bitsLT(VT)) { 4009 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4010 } else if (X.getValueType().bitsGT(VT)) { 4011 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4012 } 4013 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4014 Mask = Mask.zext(VT.getSizeInBits()); 4015 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4016 X, DAG.getConstant(Mask, VT)); 4017 } 4018 4019 // fold (aext (load x)) -> (aext (truncate (extload x))) 4020 if (ISD::isNON_EXTLoad(N0.getNode()) && 4021 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4022 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4023 bool DoXform = true; 4024 SmallVector<SDNode*, 4> SetCCs; 4025 if (!N0.hasOneUse()) 4026 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4027 if (DoXform) { 4028 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4029 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 4030 LN0->getChain(), 4031 LN0->getBasePtr(), LN0->getPointerInfo(), 4032 N0.getValueType(), 4033 LN0->isVolatile(), LN0->isNonTemporal(), 4034 LN0->getAlignment()); 4035 CombineTo(N, ExtLoad); 4036 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4037 N0.getValueType(), ExtLoad); 4038 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4039 4040 // Extend SetCC uses if necessary. 4041 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4042 SDNode *SetCC = SetCCs[i]; 4043 SmallVector<SDValue, 4> Ops; 4044 4045 for (unsigned j = 0; j != 2; ++j) { 4046 SDValue SOp = SetCC->getOperand(j); 4047 if (SOp == Trunc) 4048 Ops.push_back(ExtLoad); 4049 else 4050 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4051 N->getDebugLoc(), VT, SOp)); 4052 } 4053 4054 Ops.push_back(SetCC->getOperand(2)); 4055 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4056 SetCC->getValueType(0), 4057 &Ops[0], Ops.size())); 4058 } 4059 4060 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4061 } 4062 } 4063 4064 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4065 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4066 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4067 if (N0.getOpcode() == ISD::LOAD && 4068 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4069 N0.hasOneUse()) { 4070 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4071 EVT MemVT = LN0->getMemoryVT(); 4072 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 4073 N->getDebugLoc(), 4074 LN0->getChain(), LN0->getBasePtr(), 4075 LN0->getPointerInfo(), MemVT, 4076 LN0->isVolatile(), LN0->isNonTemporal(), 4077 LN0->getAlignment()); 4078 CombineTo(N, ExtLoad); 4079 CombineTo(N0.getNode(), 4080 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4081 N0.getValueType(), ExtLoad), 4082 ExtLoad.getValue(1)); 4083 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4084 } 4085 4086 if (N0.getOpcode() == ISD::SETCC) { 4087 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4088 // Only do this before legalize for now. 4089 if (VT.isVector() && !LegalOperations) { 4090 EVT N0VT = N0.getOperand(0).getValueType(); 4091 // We know that the # elements of the results is the same as the 4092 // # elements of the compare (and the # elements of the compare result 4093 // for that matter). Check to see that they are the same size. If so, 4094 // we know that the element size of the sext'd result matches the 4095 // element size of the compare operands. 4096 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4097 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4098 N0.getOperand(1), 4099 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4100 // If the desired elements are smaller or larger than the source 4101 // elements we can use a matching integer vector type and then 4102 // truncate/sign extend 4103 else { 4104 EVT MatchingElementType = 4105 EVT::getIntegerVT(*DAG.getContext(), 4106 N0VT.getScalarType().getSizeInBits()); 4107 EVT MatchingVectorType = 4108 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4109 N0VT.getVectorNumElements()); 4110 SDValue VsetCC = 4111 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4112 N0.getOperand(1), 4113 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4114 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4115 } 4116 } 4117 4118 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4119 SDValue SCC = 4120 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4121 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4122 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4123 if (SCC.getNode()) 4124 return SCC; 4125 } 4126 4127 return SDValue(); 4128} 4129 4130/// GetDemandedBits - See if the specified operand can be simplified with the 4131/// knowledge that only the bits specified by Mask are used. If so, return the 4132/// simpler operand, otherwise return a null SDValue. 4133SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4134 switch (V.getOpcode()) { 4135 default: break; 4136 case ISD::OR: 4137 case ISD::XOR: 4138 // If the LHS or RHS don't contribute bits to the or, drop them. 4139 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4140 return V.getOperand(1); 4141 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4142 return V.getOperand(0); 4143 break; 4144 case ISD::SRL: 4145 // Only look at single-use SRLs. 4146 if (!V.getNode()->hasOneUse()) 4147 break; 4148 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4149 // See if we can recursively simplify the LHS. 4150 unsigned Amt = RHSC->getZExtValue(); 4151 4152 // Watch out for shift count overflow though. 4153 if (Amt >= Mask.getBitWidth()) break; 4154 APInt NewMask = Mask << Amt; 4155 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4156 if (SimplifyLHS.getNode()) 4157 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4158 SimplifyLHS, V.getOperand(1)); 4159 } 4160 } 4161 return SDValue(); 4162} 4163 4164/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4165/// bits and then truncated to a narrower type and where N is a multiple 4166/// of number of bits of the narrower type, transform it to a narrower load 4167/// from address + N / num of bits of new type. If the result is to be 4168/// extended, also fold the extension to form a extending load. 4169SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4170 unsigned Opc = N->getOpcode(); 4171 4172 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4173 SDValue N0 = N->getOperand(0); 4174 EVT VT = N->getValueType(0); 4175 EVT ExtVT = VT; 4176 4177 // This transformation isn't valid for vector loads. 4178 if (VT.isVector()) 4179 return SDValue(); 4180 4181 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4182 // extended to VT. 4183 if (Opc == ISD::SIGN_EXTEND_INREG) { 4184 ExtType = ISD::SEXTLOAD; 4185 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4186 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 4187 return SDValue(); 4188 } else if (Opc == ISD::SRL) { 4189 // Another special-case: SRL is basically zero-extending a narrower value. 4190 ExtType = ISD::ZEXTLOAD; 4191 N0 = SDValue(N, 0); 4192 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4193 if (!N01) return SDValue(); 4194 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4195 VT.getSizeInBits() - N01->getZExtValue()); 4196 } 4197 4198 unsigned EVTBits = ExtVT.getSizeInBits(); 4199 unsigned ShAmt = 0; 4200 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 4201 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4202 ShAmt = N01->getZExtValue(); 4203 // Is the shift amount a multiple of size of VT? 4204 if ((ShAmt & (EVTBits-1)) == 0) { 4205 N0 = N0.getOperand(0); 4206 // Is the load width a multiple of size of VT? 4207 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4208 return SDValue(); 4209 } 4210 4211 // If the shift amount is larger than the input type then we're not 4212 // accessing any of the loaded bytes. If the load was a zextload/extload 4213 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4214 // If the load was a sextload then the result is a splat of the sign bit 4215 // of the extended byte. This is not worth optimizing for. 4216 if (ShAmt >= VT.getSizeInBits()) 4217 return SDValue(); 4218 4219 } 4220 } 4221 4222 // If the load is shifted left (and the result isn't shifted back right), 4223 // we can fold the truncate through the shift. 4224 unsigned ShLeftAmt = 0; 4225 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4226 ExtVT == VT && 4227 TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4228 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4229 ShLeftAmt = N01->getZExtValue(); 4230 N0 = N0.getOperand(0); 4231 } 4232 } 4233 4234 // Do not generate loads of non-round integer types since these can 4235 // be expensive (and would be wrong if the type is not byte sized). 4236 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 4237 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits && 4238 // Do not change the width of a volatile load. 4239 !cast<LoadSDNode>(N0)->isVolatile()) { 4240 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4241 EVT PtrType = N0.getOperand(1).getValueType(); 4242 4243 // For big endian targets, we need to adjust the offset to the pointer to 4244 // load the correct bytes. 4245 if (TLI.isBigEndian()) { 4246 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4247 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4248 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4249 } 4250 4251 uint64_t PtrOff = ShAmt / 8; 4252 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4253 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4254 PtrType, LN0->getBasePtr(), 4255 DAG.getConstant(PtrOff, PtrType)); 4256 AddToWorkList(NewPtr.getNode()); 4257 4258 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 4259 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4260 LN0->getPointerInfo().getWithOffset(PtrOff), 4261 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 4262 : DAG.getExtLoad(ExtType, VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4263 LN0->getPointerInfo().getWithOffset(PtrOff), 4264 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4265 NewAlign); 4266 4267 // Replace the old load's chain with the new load's chain. 4268 WorkListRemover DeadNodes(*this); 4269 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4270 &DeadNodes); 4271 4272 // Shift the result left, if we've swallowed a left shift. 4273 SDValue Result = Load; 4274 if (ShLeftAmt != 0) { 4275 EVT ShImmTy = getShiftAmountTy(); 4276 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4277 ShImmTy = VT; 4278 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4279 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4280 } 4281 4282 // Return the new loaded value. 4283 return Result; 4284 } 4285 4286 return SDValue(); 4287} 4288 4289SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4290 SDValue N0 = N->getOperand(0); 4291 SDValue N1 = N->getOperand(1); 4292 EVT VT = N->getValueType(0); 4293 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4294 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4295 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4296 4297 // fold (sext_in_reg c1) -> c1 4298 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4299 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4300 4301 // If the input is already sign extended, just drop the extension. 4302 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4303 return N0; 4304 4305 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4306 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4307 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4308 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4309 N0.getOperand(0), N1); 4310 } 4311 4312 // fold (sext_in_reg (sext x)) -> (sext x) 4313 // fold (sext_in_reg (aext x)) -> (sext x) 4314 // if x is small enough. 4315 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4316 SDValue N00 = N0.getOperand(0); 4317 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4318 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4319 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4320 } 4321 4322 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4323 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4324 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4325 4326 // fold operands of sext_in_reg based on knowledge that the top bits are not 4327 // demanded. 4328 if (SimplifyDemandedBits(SDValue(N, 0))) 4329 return SDValue(N, 0); 4330 4331 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4332 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4333 SDValue NarrowLoad = ReduceLoadWidth(N); 4334 if (NarrowLoad.getNode()) 4335 return NarrowLoad; 4336 4337 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4338 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4339 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4340 if (N0.getOpcode() == ISD::SRL) { 4341 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4342 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4343 // We can turn this into an SRA iff the input to the SRL is already sign 4344 // extended enough. 4345 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4346 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4347 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4348 N0.getOperand(0), N0.getOperand(1)); 4349 } 4350 } 4351 4352 // fold (sext_inreg (extload x)) -> (sextload x) 4353 if (ISD::isEXTLoad(N0.getNode()) && 4354 ISD::isUNINDEXEDLoad(N0.getNode()) && 4355 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4356 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4357 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4358 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4359 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4360 LN0->getChain(), 4361 LN0->getBasePtr(), LN0->getPointerInfo(), 4362 EVT, 4363 LN0->isVolatile(), LN0->isNonTemporal(), 4364 LN0->getAlignment()); 4365 CombineTo(N, ExtLoad); 4366 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4367 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4368 } 4369 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4370 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4371 N0.hasOneUse() && 4372 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4373 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4374 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4375 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4376 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N->getDebugLoc(), 4377 LN0->getChain(), 4378 LN0->getBasePtr(), LN0->getPointerInfo(), 4379 EVT, 4380 LN0->isVolatile(), LN0->isNonTemporal(), 4381 LN0->getAlignment()); 4382 CombineTo(N, ExtLoad); 4383 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4384 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4385 } 4386 return SDValue(); 4387} 4388 4389SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4390 SDValue N0 = N->getOperand(0); 4391 EVT VT = N->getValueType(0); 4392 4393 // noop truncate 4394 if (N0.getValueType() == N->getValueType(0)) 4395 return N0; 4396 // fold (truncate c1) -> c1 4397 if (isa<ConstantSDNode>(N0)) 4398 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4399 // fold (truncate (truncate x)) -> (truncate x) 4400 if (N0.getOpcode() == ISD::TRUNCATE) 4401 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4402 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4403 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4404 N0.getOpcode() == ISD::SIGN_EXTEND || 4405 N0.getOpcode() == ISD::ANY_EXTEND) { 4406 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4407 // if the source is smaller than the dest, we still need an extend 4408 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4409 N0.getOperand(0)); 4410 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4411 // if the source is larger than the dest, than we just need the truncate 4412 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4413 else 4414 // if the source and dest are the same type, we can drop both the extend 4415 // and the truncate. 4416 return N0.getOperand(0); 4417 } 4418 4419 // See if we can simplify the input to this truncate through knowledge that 4420 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 4421 // -> trunc y 4422 SDValue Shorter = 4423 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4424 VT.getSizeInBits())); 4425 if (Shorter.getNode()) 4426 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4427 4428 // fold (truncate (load x)) -> (smaller load x) 4429 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4430 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4431 SDValue Reduced = ReduceLoadWidth(N); 4432 if (Reduced.getNode()) 4433 return Reduced; 4434 } 4435 4436 // Simplify the operands using demanded-bits information. 4437 if (!VT.isVector() && 4438 SimplifyDemandedBits(SDValue(N, 0))) 4439 return SDValue(N, 0); 4440 4441 return SDValue(); 4442} 4443 4444static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4445 SDValue Elt = N->getOperand(i); 4446 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4447 return Elt.getNode(); 4448 return Elt.getOperand(Elt.getResNo()).getNode(); 4449} 4450 4451/// CombineConsecutiveLoads - build_pair (load, load) -> load 4452/// if load locations are consecutive. 4453SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4454 assert(N->getOpcode() == ISD::BUILD_PAIR); 4455 4456 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4457 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4458 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4459 LD1->getPointerInfo().getAddrSpace() != 4460 LD2->getPointerInfo().getAddrSpace()) 4461 return SDValue(); 4462 EVT LD1VT = LD1->getValueType(0); 4463 4464 if (ISD::isNON_EXTLoad(LD2) && 4465 LD2->hasOneUse() && 4466 // If both are volatile this would reduce the number of volatile loads. 4467 // If one is volatile it might be ok, but play conservative and bail out. 4468 !LD1->isVolatile() && 4469 !LD2->isVolatile() && 4470 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4471 unsigned Align = LD1->getAlignment(); 4472 unsigned NewAlign = TLI.getTargetData()-> 4473 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4474 4475 if (NewAlign <= Align && 4476 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4477 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4478 LD1->getBasePtr(), LD1->getPointerInfo(), 4479 false, false, Align); 4480 } 4481 4482 return SDValue(); 4483} 4484 4485SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4486 SDValue N0 = N->getOperand(0); 4487 EVT VT = N->getValueType(0); 4488 4489 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4490 // Only do this before legalize, since afterward the target may be depending 4491 // on the bitconvert. 4492 // First check to see if this is all constant. 4493 if (!LegalTypes && 4494 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4495 VT.isVector()) { 4496 bool isSimple = true; 4497 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4498 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4499 N0.getOperand(i).getOpcode() != ISD::Constant && 4500 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4501 isSimple = false; 4502 break; 4503 } 4504 4505 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4506 assert(!DestEltVT.isVector() && 4507 "Element type of vector ValueType must not be vector!"); 4508 if (isSimple) 4509 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4510 } 4511 4512 // If the input is a constant, let getNode fold it. 4513 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4514 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4515 if (Res.getNode() != N) { 4516 if (!LegalOperations || 4517 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4518 return Res; 4519 4520 // Folding it resulted in an illegal node, and it's too late to 4521 // do that. Clean up the old node and forego the transformation. 4522 // Ideally this won't happen very often, because instcombine 4523 // and the earlier dagcombine runs (where illegal nodes are 4524 // permitted) should have folded most of them already. 4525 DAG.DeleteNode(Res.getNode()); 4526 } 4527 } 4528 4529 // (conv (conv x, t1), t2) -> (conv x, t2) 4530 if (N0.getOpcode() == ISD::BITCAST) 4531 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4532 N0.getOperand(0)); 4533 4534 // fold (conv (load x)) -> (load (conv*)x) 4535 // If the resultant load doesn't need a higher alignment than the original! 4536 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4537 // Do not change the width of a volatile load. 4538 !cast<LoadSDNode>(N0)->isVolatile() && 4539 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4540 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4541 unsigned Align = TLI.getTargetData()-> 4542 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4543 unsigned OrigAlign = LN0->getAlignment(); 4544 4545 if (Align <= OrigAlign) { 4546 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4547 LN0->getBasePtr(), LN0->getPointerInfo(), 4548 LN0->isVolatile(), LN0->isNonTemporal(), 4549 OrigAlign); 4550 AddToWorkList(N); 4551 CombineTo(N0.getNode(), 4552 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4553 N0.getValueType(), Load), 4554 Load.getValue(1)); 4555 return Load; 4556 } 4557 } 4558 4559 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4560 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4561 // This often reduces constant pool loads. 4562 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4563 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4564 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4565 N0.getOperand(0)); 4566 AddToWorkList(NewConv.getNode()); 4567 4568 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4569 if (N0.getOpcode() == ISD::FNEG) 4570 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4571 NewConv, DAG.getConstant(SignBit, VT)); 4572 assert(N0.getOpcode() == ISD::FABS); 4573 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4574 NewConv, DAG.getConstant(~SignBit, VT)); 4575 } 4576 4577 // fold (bitconvert (fcopysign cst, x)) -> 4578 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4579 // Note that we don't handle (copysign x, cst) because this can always be 4580 // folded to an fneg or fabs. 4581 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4582 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4583 VT.isInteger() && !VT.isVector()) { 4584 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4585 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4586 if (isTypeLegal(IntXVT)) { 4587 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4588 IntXVT, N0.getOperand(1)); 4589 AddToWorkList(X.getNode()); 4590 4591 // If X has a different width than the result/lhs, sext it or truncate it. 4592 unsigned VTWidth = VT.getSizeInBits(); 4593 if (OrigXWidth < VTWidth) { 4594 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4595 AddToWorkList(X.getNode()); 4596 } else if (OrigXWidth > VTWidth) { 4597 // To get the sign bit in the right place, we have to shift it right 4598 // before truncating. 4599 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4600 X.getValueType(), X, 4601 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4602 AddToWorkList(X.getNode()); 4603 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4604 AddToWorkList(X.getNode()); 4605 } 4606 4607 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4608 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4609 X, DAG.getConstant(SignBit, VT)); 4610 AddToWorkList(X.getNode()); 4611 4612 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4613 VT, N0.getOperand(0)); 4614 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4615 Cst, DAG.getConstant(~SignBit, VT)); 4616 AddToWorkList(Cst.getNode()); 4617 4618 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4619 } 4620 } 4621 4622 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4623 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4624 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4625 if (CombineLD.getNode()) 4626 return CombineLD; 4627 } 4628 4629 return SDValue(); 4630} 4631 4632SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4633 EVT VT = N->getValueType(0); 4634 return CombineConsecutiveLoads(N, VT); 4635} 4636 4637/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4638/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4639/// destination element value type. 4640SDValue DAGCombiner:: 4641ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4642 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4643 4644 // If this is already the right type, we're done. 4645 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4646 4647 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4648 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4649 4650 // If this is a conversion of N elements of one type to N elements of another 4651 // type, convert each element. This handles FP<->INT cases. 4652 if (SrcBitSize == DstBitSize) { 4653 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4654 BV->getValueType(0).getVectorNumElements()); 4655 4656 // Due to the FP element handling below calling this routine recursively, 4657 // we can end up with a scalar-to-vector node here. 4658 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4659 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4660 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4661 DstEltVT, BV->getOperand(0))); 4662 4663 SmallVector<SDValue, 8> Ops; 4664 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4665 SDValue Op = BV->getOperand(i); 4666 // If the vector element type is not legal, the BUILD_VECTOR operands 4667 // are promoted and implicitly truncated. Make that explicit here. 4668 if (Op.getValueType() != SrcEltVT) 4669 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4670 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4671 DstEltVT, Op)); 4672 AddToWorkList(Ops.back().getNode()); 4673 } 4674 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4675 &Ops[0], Ops.size()); 4676 } 4677 4678 // Otherwise, we're growing or shrinking the elements. To avoid having to 4679 // handle annoying details of growing/shrinking FP values, we convert them to 4680 // int first. 4681 if (SrcEltVT.isFloatingPoint()) { 4682 // Convert the input float vector to a int vector where the elements are the 4683 // same sizes. 4684 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4685 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4686 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4687 SrcEltVT = IntVT; 4688 } 4689 4690 // Now we know the input is an integer vector. If the output is a FP type, 4691 // convert to integer first, then to FP of the right size. 4692 if (DstEltVT.isFloatingPoint()) { 4693 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4694 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4695 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4696 4697 // Next, convert to FP elements of the same size. 4698 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4699 } 4700 4701 // Okay, we know the src/dst types are both integers of differing types. 4702 // Handling growing first. 4703 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4704 if (SrcBitSize < DstBitSize) { 4705 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4706 4707 SmallVector<SDValue, 8> Ops; 4708 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4709 i += NumInputsPerOutput) { 4710 bool isLE = TLI.isLittleEndian(); 4711 APInt NewBits = APInt(DstBitSize, 0); 4712 bool EltIsUndef = true; 4713 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4714 // Shift the previously computed bits over. 4715 NewBits <<= SrcBitSize; 4716 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4717 if (Op.getOpcode() == ISD::UNDEF) continue; 4718 EltIsUndef = false; 4719 4720 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4721 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4722 } 4723 4724 if (EltIsUndef) 4725 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4726 else 4727 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4728 } 4729 4730 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4731 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4732 &Ops[0], Ops.size()); 4733 } 4734 4735 // Finally, this must be the case where we are shrinking elements: each input 4736 // turns into multiple outputs. 4737 bool isS2V = ISD::isScalarToVector(BV); 4738 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4739 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4740 NumOutputsPerInput*BV->getNumOperands()); 4741 SmallVector<SDValue, 8> Ops; 4742 4743 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4744 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4745 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4746 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4747 continue; 4748 } 4749 4750 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4751 getAPIntValue().zextOrTrunc(SrcBitSize); 4752 4753 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4754 APInt ThisVal = OpVal.trunc(DstBitSize); 4755 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4756 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4757 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4758 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4759 Ops[0]); 4760 OpVal = OpVal.lshr(DstBitSize); 4761 } 4762 4763 // For big endian targets, swap the order of the pieces of each element. 4764 if (TLI.isBigEndian()) 4765 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4766 } 4767 4768 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4769 &Ops[0], Ops.size()); 4770} 4771 4772SDValue DAGCombiner::visitFADD(SDNode *N) { 4773 SDValue N0 = N->getOperand(0); 4774 SDValue N1 = N->getOperand(1); 4775 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4776 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4777 EVT VT = N->getValueType(0); 4778 4779 // fold vector ops 4780 if (VT.isVector()) { 4781 SDValue FoldedVOp = SimplifyVBinOp(N); 4782 if (FoldedVOp.getNode()) return FoldedVOp; 4783 } 4784 4785 // fold (fadd c1, c2) -> (fadd c1, c2) 4786 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4787 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4788 // canonicalize constant to RHS 4789 if (N0CFP && !N1CFP) 4790 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4791 // fold (fadd A, 0) -> A 4792 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4793 return N0; 4794 // fold (fadd A, (fneg B)) -> (fsub A, B) 4795 if (isNegatibleForFree(N1, LegalOperations) == 2) 4796 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4797 GetNegatedExpression(N1, DAG, LegalOperations)); 4798 // fold (fadd (fneg A), B) -> (fsub B, A) 4799 if (isNegatibleForFree(N0, LegalOperations) == 2) 4800 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4801 GetNegatedExpression(N0, DAG, LegalOperations)); 4802 4803 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4804 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4805 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4806 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4807 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4808 N0.getOperand(1), N1)); 4809 4810 return SDValue(); 4811} 4812 4813SDValue DAGCombiner::visitFSUB(SDNode *N) { 4814 SDValue N0 = N->getOperand(0); 4815 SDValue N1 = N->getOperand(1); 4816 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4817 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4818 EVT VT = N->getValueType(0); 4819 4820 // fold vector ops 4821 if (VT.isVector()) { 4822 SDValue FoldedVOp = SimplifyVBinOp(N); 4823 if (FoldedVOp.getNode()) return FoldedVOp; 4824 } 4825 4826 // fold (fsub c1, c2) -> c1-c2 4827 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4828 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4829 // fold (fsub A, 0) -> A 4830 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4831 return N0; 4832 // fold (fsub 0, B) -> -B 4833 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4834 if (isNegatibleForFree(N1, LegalOperations)) 4835 return GetNegatedExpression(N1, DAG, LegalOperations); 4836 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4837 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4838 } 4839 // fold (fsub A, (fneg B)) -> (fadd A, B) 4840 if (isNegatibleForFree(N1, LegalOperations)) 4841 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4842 GetNegatedExpression(N1, DAG, LegalOperations)); 4843 4844 return SDValue(); 4845} 4846 4847SDValue DAGCombiner::visitFMUL(SDNode *N) { 4848 SDValue N0 = N->getOperand(0); 4849 SDValue N1 = N->getOperand(1); 4850 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4851 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4852 EVT VT = N->getValueType(0); 4853 4854 // fold vector ops 4855 if (VT.isVector()) { 4856 SDValue FoldedVOp = SimplifyVBinOp(N); 4857 if (FoldedVOp.getNode()) return FoldedVOp; 4858 } 4859 4860 // fold (fmul c1, c2) -> c1*c2 4861 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4862 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4863 // canonicalize constant to RHS 4864 if (N0CFP && !N1CFP) 4865 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4866 // fold (fmul A, 0) -> 0 4867 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4868 return N1; 4869 // fold (fmul A, 0) -> 0, vector edition. 4870 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4871 return N1; 4872 // fold (fmul X, 2.0) -> (fadd X, X) 4873 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4874 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4875 // fold (fmul X, -1.0) -> (fneg X) 4876 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4877 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4878 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4879 4880 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4881 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4882 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4883 // Both can be negated for free, check to see if at least one is cheaper 4884 // negated. 4885 if (LHSNeg == 2 || RHSNeg == 2) 4886 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4887 GetNegatedExpression(N0, DAG, LegalOperations), 4888 GetNegatedExpression(N1, DAG, LegalOperations)); 4889 } 4890 } 4891 4892 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4893 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4894 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4895 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4896 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4897 N0.getOperand(1), N1)); 4898 4899 return SDValue(); 4900} 4901 4902SDValue DAGCombiner::visitFDIV(SDNode *N) { 4903 SDValue N0 = N->getOperand(0); 4904 SDValue N1 = N->getOperand(1); 4905 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4906 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4907 EVT VT = N->getValueType(0); 4908 4909 // fold vector ops 4910 if (VT.isVector()) { 4911 SDValue FoldedVOp = SimplifyVBinOp(N); 4912 if (FoldedVOp.getNode()) return FoldedVOp; 4913 } 4914 4915 // fold (fdiv c1, c2) -> c1/c2 4916 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4917 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4918 4919 4920 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4921 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4922 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4923 // Both can be negated for free, check to see if at least one is cheaper 4924 // negated. 4925 if (LHSNeg == 2 || RHSNeg == 2) 4926 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4927 GetNegatedExpression(N0, DAG, LegalOperations), 4928 GetNegatedExpression(N1, DAG, LegalOperations)); 4929 } 4930 } 4931 4932 return SDValue(); 4933} 4934 4935SDValue DAGCombiner::visitFREM(SDNode *N) { 4936 SDValue N0 = N->getOperand(0); 4937 SDValue N1 = N->getOperand(1); 4938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4939 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4940 EVT VT = N->getValueType(0); 4941 4942 // fold (frem c1, c2) -> fmod(c1,c2) 4943 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4944 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4945 4946 return SDValue(); 4947} 4948 4949SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4950 SDValue N0 = N->getOperand(0); 4951 SDValue N1 = N->getOperand(1); 4952 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4953 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4954 EVT VT = N->getValueType(0); 4955 4956 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4957 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4958 4959 if (N1CFP) { 4960 const APFloat& V = N1CFP->getValueAPF(); 4961 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4962 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4963 if (!V.isNegative()) { 4964 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4965 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4966 } else { 4967 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4968 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4969 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4970 } 4971 } 4972 4973 // copysign(fabs(x), y) -> copysign(x, y) 4974 // copysign(fneg(x), y) -> copysign(x, y) 4975 // copysign(copysign(x,z), y) -> copysign(x, y) 4976 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4977 N0.getOpcode() == ISD::FCOPYSIGN) 4978 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4979 N0.getOperand(0), N1); 4980 4981 // copysign(x, abs(y)) -> abs(x) 4982 if (N1.getOpcode() == ISD::FABS) 4983 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4984 4985 // copysign(x, copysign(y,z)) -> copysign(x, z) 4986 if (N1.getOpcode() == ISD::FCOPYSIGN) 4987 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4988 N0, N1.getOperand(1)); 4989 4990 // copysign(x, fp_extend(y)) -> copysign(x, y) 4991 // copysign(x, fp_round(y)) -> copysign(x, y) 4992 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4993 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4994 N0, N1.getOperand(0)); 4995 4996 return SDValue(); 4997} 4998 4999SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5000 SDValue N0 = N->getOperand(0); 5001 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5002 EVT VT = N->getValueType(0); 5003 EVT OpVT = N0.getValueType(); 5004 5005 // fold (sint_to_fp c1) -> c1fp 5006 if (N0C && OpVT != MVT::ppcf128) 5007 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5008 5009 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5010 // but UINT_TO_FP is legal on this target, try to convert. 5011 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5012 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5013 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5014 if (DAG.SignBitIsZero(N0)) 5015 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5016 } 5017 5018 return SDValue(); 5019} 5020 5021SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5022 SDValue N0 = N->getOperand(0); 5023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5024 EVT VT = N->getValueType(0); 5025 EVT OpVT = N0.getValueType(); 5026 5027 // fold (uint_to_fp c1) -> c1fp 5028 if (N0C && OpVT != MVT::ppcf128) 5029 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5030 5031 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5032 // but SINT_TO_FP is legal on this target, try to convert. 5033 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5034 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5035 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5036 if (DAG.SignBitIsZero(N0)) 5037 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5038 } 5039 5040 return SDValue(); 5041} 5042 5043SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5044 SDValue N0 = N->getOperand(0); 5045 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5046 EVT VT = N->getValueType(0); 5047 5048 // fold (fp_to_sint c1fp) -> c1 5049 if (N0CFP) 5050 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5051 5052 return SDValue(); 5053} 5054 5055SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5056 SDValue N0 = N->getOperand(0); 5057 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5058 EVT VT = N->getValueType(0); 5059 5060 // fold (fp_to_uint c1fp) -> c1 5061 if (N0CFP && VT != MVT::ppcf128) 5062 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5063 5064 return SDValue(); 5065} 5066 5067SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5068 SDValue N0 = N->getOperand(0); 5069 SDValue N1 = N->getOperand(1); 5070 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5071 EVT VT = N->getValueType(0); 5072 5073 // fold (fp_round c1fp) -> c1fp 5074 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5075 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5076 5077 // fold (fp_round (fp_extend x)) -> x 5078 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5079 return N0.getOperand(0); 5080 5081 // fold (fp_round (fp_round x)) -> (fp_round x) 5082 if (N0.getOpcode() == ISD::FP_ROUND) { 5083 // This is a value preserving truncation if both round's are. 5084 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5085 N0.getNode()->getConstantOperandVal(1) == 1; 5086 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5087 DAG.getIntPtrConstant(IsTrunc)); 5088 } 5089 5090 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5091 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5092 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5093 N0.getOperand(0), N1); 5094 AddToWorkList(Tmp.getNode()); 5095 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5096 Tmp, N0.getOperand(1)); 5097 } 5098 5099 return SDValue(); 5100} 5101 5102SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5103 SDValue N0 = N->getOperand(0); 5104 EVT VT = N->getValueType(0); 5105 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5106 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5107 5108 // fold (fp_round_inreg c1fp) -> c1fp 5109 if (N0CFP && isTypeLegal(EVT)) { 5110 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5111 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5112 } 5113 5114 return SDValue(); 5115} 5116 5117SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5118 SDValue N0 = N->getOperand(0); 5119 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5120 EVT VT = N->getValueType(0); 5121 5122 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5123 if (N->hasOneUse() && 5124 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5125 return SDValue(); 5126 5127 // fold (fp_extend c1fp) -> c1fp 5128 if (N0CFP && VT != MVT::ppcf128) 5129 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5130 5131 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5132 // value of X. 5133 if (N0.getOpcode() == ISD::FP_ROUND 5134 && N0.getNode()->getConstantOperandVal(1) == 1) { 5135 SDValue In = N0.getOperand(0); 5136 if (In.getValueType() == VT) return In; 5137 if (VT.bitsLT(In.getValueType())) 5138 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5139 In, N0.getOperand(1)); 5140 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5141 } 5142 5143 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5144 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5145 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5146 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5147 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5148 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N->getDebugLoc(), 5149 LN0->getChain(), 5150 LN0->getBasePtr(), LN0->getPointerInfo(), 5151 N0.getValueType(), 5152 LN0->isVolatile(), LN0->isNonTemporal(), 5153 LN0->getAlignment()); 5154 CombineTo(N, ExtLoad); 5155 CombineTo(N0.getNode(), 5156 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5157 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5158 ExtLoad.getValue(1)); 5159 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5160 } 5161 5162 return SDValue(); 5163} 5164 5165SDValue DAGCombiner::visitFNEG(SDNode *N) { 5166 SDValue N0 = N->getOperand(0); 5167 EVT VT = N->getValueType(0); 5168 5169 if (isNegatibleForFree(N0, LegalOperations)) 5170 return GetNegatedExpression(N0, DAG, LegalOperations); 5171 5172 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5173 // constant pool values. 5174 if (N0.getOpcode() == ISD::BITCAST && 5175 !VT.isVector() && 5176 N0.getNode()->hasOneUse() && 5177 N0.getOperand(0).getValueType().isInteger()) { 5178 SDValue Int = N0.getOperand(0); 5179 EVT IntVT = Int.getValueType(); 5180 if (IntVT.isInteger() && !IntVT.isVector()) { 5181 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5182 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5183 AddToWorkList(Int.getNode()); 5184 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5185 VT, Int); 5186 } 5187 } 5188 5189 return SDValue(); 5190} 5191 5192SDValue DAGCombiner::visitFABS(SDNode *N) { 5193 SDValue N0 = N->getOperand(0); 5194 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5195 EVT VT = N->getValueType(0); 5196 5197 // fold (fabs c1) -> fabs(c1) 5198 if (N0CFP && VT != MVT::ppcf128) 5199 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5200 // fold (fabs (fabs x)) -> (fabs x) 5201 if (N0.getOpcode() == ISD::FABS) 5202 return N->getOperand(0); 5203 // fold (fabs (fneg x)) -> (fabs x) 5204 // fold (fabs (fcopysign x, y)) -> (fabs x) 5205 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5206 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5207 5208 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5209 // constant pool values. 5210 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5211 N0.getOperand(0).getValueType().isInteger() && 5212 !N0.getOperand(0).getValueType().isVector()) { 5213 SDValue Int = N0.getOperand(0); 5214 EVT IntVT = Int.getValueType(); 5215 if (IntVT.isInteger() && !IntVT.isVector()) { 5216 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5217 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5218 AddToWorkList(Int.getNode()); 5219 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5220 N->getValueType(0), Int); 5221 } 5222 } 5223 5224 return SDValue(); 5225} 5226 5227SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5228 SDValue Chain = N->getOperand(0); 5229 SDValue N1 = N->getOperand(1); 5230 SDValue N2 = N->getOperand(2); 5231 5232 // If N is a constant we could fold this into a fallthrough or unconditional 5233 // branch. However that doesn't happen very often in normal code, because 5234 // Instcombine/SimplifyCFG should have handled the available opportunities. 5235 // If we did this folding here, it would be necessary to update the 5236 // MachineBasicBlock CFG, which is awkward. 5237 5238 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5239 // on the target. 5240 if (N1.getOpcode() == ISD::SETCC && 5241 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5242 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5243 Chain, N1.getOperand(2), 5244 N1.getOperand(0), N1.getOperand(1), N2); 5245 } 5246 5247 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5248 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5249 (N1.getOperand(0).hasOneUse() && 5250 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5251 SDNode *Trunc = 0; 5252 if (N1.getOpcode() == ISD::TRUNCATE) { 5253 // Look pass the truncate. 5254 Trunc = N1.getNode(); 5255 N1 = N1.getOperand(0); 5256 } 5257 5258 // Match this pattern so that we can generate simpler code: 5259 // 5260 // %a = ... 5261 // %b = and i32 %a, 2 5262 // %c = srl i32 %b, 1 5263 // brcond i32 %c ... 5264 // 5265 // into 5266 // 5267 // %a = ... 5268 // %b = and i32 %a, 2 5269 // %c = setcc eq %b, 0 5270 // brcond %c ... 5271 // 5272 // This applies only when the AND constant value has one bit set and the 5273 // SRL constant is equal to the log2 of the AND constant. The back-end is 5274 // smart enough to convert the result into a TEST/JMP sequence. 5275 SDValue Op0 = N1.getOperand(0); 5276 SDValue Op1 = N1.getOperand(1); 5277 5278 if (Op0.getOpcode() == ISD::AND && 5279 Op1.getOpcode() == ISD::Constant) { 5280 SDValue AndOp1 = Op0.getOperand(1); 5281 5282 if (AndOp1.getOpcode() == ISD::Constant) { 5283 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5284 5285 if (AndConst.isPowerOf2() && 5286 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5287 SDValue SetCC = 5288 DAG.getSetCC(N->getDebugLoc(), 5289 TLI.getSetCCResultType(Op0.getValueType()), 5290 Op0, DAG.getConstant(0, Op0.getValueType()), 5291 ISD::SETNE); 5292 5293 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5294 MVT::Other, Chain, SetCC, N2); 5295 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5296 // will convert it back to (X & C1) >> C2. 5297 CombineTo(N, NewBRCond, false); 5298 // Truncate is dead. 5299 if (Trunc) { 5300 removeFromWorkList(Trunc); 5301 DAG.DeleteNode(Trunc); 5302 } 5303 // Replace the uses of SRL with SETCC 5304 WorkListRemover DeadNodes(*this); 5305 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5306 removeFromWorkList(N1.getNode()); 5307 DAG.DeleteNode(N1.getNode()); 5308 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5309 } 5310 } 5311 } 5312 5313 if (Trunc) 5314 // Restore N1 if the above transformation doesn't match. 5315 N1 = N->getOperand(1); 5316 } 5317 5318 // Transform br(xor(x, y)) -> br(x != y) 5319 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5320 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5321 SDNode *TheXor = N1.getNode(); 5322 SDValue Op0 = TheXor->getOperand(0); 5323 SDValue Op1 = TheXor->getOperand(1); 5324 if (Op0.getOpcode() == Op1.getOpcode()) { 5325 // Avoid missing important xor optimizations. 5326 SDValue Tmp = visitXOR(TheXor); 5327 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5328 DEBUG(dbgs() << "\nReplacing.8 "; 5329 TheXor->dump(&DAG); 5330 dbgs() << "\nWith: "; 5331 Tmp.getNode()->dump(&DAG); 5332 dbgs() << '\n'); 5333 WorkListRemover DeadNodes(*this); 5334 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5335 removeFromWorkList(TheXor); 5336 DAG.DeleteNode(TheXor); 5337 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5338 MVT::Other, Chain, Tmp, N2); 5339 } 5340 } 5341 5342 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5343 bool Equal = false; 5344 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5345 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5346 Op0.getOpcode() == ISD::XOR) { 5347 TheXor = Op0.getNode(); 5348 Equal = true; 5349 } 5350 5351 EVT SetCCVT = N1.getValueType(); 5352 if (LegalTypes) 5353 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5354 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5355 SetCCVT, 5356 Op0, Op1, 5357 Equal ? ISD::SETEQ : ISD::SETNE); 5358 // Replace the uses of XOR with SETCC 5359 WorkListRemover DeadNodes(*this); 5360 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5361 removeFromWorkList(N1.getNode()); 5362 DAG.DeleteNode(N1.getNode()); 5363 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5364 MVT::Other, Chain, SetCC, N2); 5365 } 5366 } 5367 5368 return SDValue(); 5369} 5370 5371// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5372// 5373SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5374 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5375 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5376 5377 // If N is a constant we could fold this into a fallthrough or unconditional 5378 // branch. However that doesn't happen very often in normal code, because 5379 // Instcombine/SimplifyCFG should have handled the available opportunities. 5380 // If we did this folding here, it would be necessary to update the 5381 // MachineBasicBlock CFG, which is awkward. 5382 5383 // Use SimplifySetCC to simplify SETCC's. 5384 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5385 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5386 false); 5387 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5388 5389 // fold to a simpler setcc 5390 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5391 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5392 N->getOperand(0), Simp.getOperand(2), 5393 Simp.getOperand(0), Simp.getOperand(1), 5394 N->getOperand(4)); 5395 5396 return SDValue(); 5397} 5398 5399/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5400/// pre-indexed load / store when the base pointer is an add or subtract 5401/// and it has other uses besides the load / store. After the 5402/// transformation, the new indexed load / store has effectively folded 5403/// the add / subtract in and all of its other uses are redirected to the 5404/// new load / store. 5405bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5406 if (!LegalOperations) 5407 return false; 5408 5409 bool isLoad = true; 5410 SDValue Ptr; 5411 EVT VT; 5412 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5413 if (LD->isIndexed()) 5414 return false; 5415 VT = LD->getMemoryVT(); 5416 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5417 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5418 return false; 5419 Ptr = LD->getBasePtr(); 5420 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5421 if (ST->isIndexed()) 5422 return false; 5423 VT = ST->getMemoryVT(); 5424 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5425 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5426 return false; 5427 Ptr = ST->getBasePtr(); 5428 isLoad = false; 5429 } else { 5430 return false; 5431 } 5432 5433 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5434 // out. There is no reason to make this a preinc/predec. 5435 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5436 Ptr.getNode()->hasOneUse()) 5437 return false; 5438 5439 // Ask the target to do addressing mode selection. 5440 SDValue BasePtr; 5441 SDValue Offset; 5442 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5443 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5444 return false; 5445 // Don't create a indexed load / store with zero offset. 5446 if (isa<ConstantSDNode>(Offset) && 5447 cast<ConstantSDNode>(Offset)->isNullValue()) 5448 return false; 5449 5450 // Try turning it into a pre-indexed load / store except when: 5451 // 1) The new base ptr is a frame index. 5452 // 2) If N is a store and the new base ptr is either the same as or is a 5453 // predecessor of the value being stored. 5454 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5455 // that would create a cycle. 5456 // 4) All uses are load / store ops that use it as old base ptr. 5457 5458 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5459 // (plus the implicit offset) to a register to preinc anyway. 5460 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5461 return false; 5462 5463 // Check #2. 5464 if (!isLoad) { 5465 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5466 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5467 return false; 5468 } 5469 5470 // Now check for #3 and #4. 5471 bool RealUse = false; 5472 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5473 E = Ptr.getNode()->use_end(); I != E; ++I) { 5474 SDNode *Use = *I; 5475 if (Use == N) 5476 continue; 5477 if (Use->isPredecessorOf(N)) 5478 return false; 5479 5480 if (!((Use->getOpcode() == ISD::LOAD && 5481 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5482 (Use->getOpcode() == ISD::STORE && 5483 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5484 RealUse = true; 5485 } 5486 5487 if (!RealUse) 5488 return false; 5489 5490 SDValue Result; 5491 if (isLoad) 5492 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5493 BasePtr, Offset, AM); 5494 else 5495 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5496 BasePtr, Offset, AM); 5497 ++PreIndexedNodes; 5498 ++NodesCombined; 5499 DEBUG(dbgs() << "\nReplacing.4 "; 5500 N->dump(&DAG); 5501 dbgs() << "\nWith: "; 5502 Result.getNode()->dump(&DAG); 5503 dbgs() << '\n'); 5504 WorkListRemover DeadNodes(*this); 5505 if (isLoad) { 5506 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5507 &DeadNodes); 5508 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5509 &DeadNodes); 5510 } else { 5511 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5512 &DeadNodes); 5513 } 5514 5515 // Finally, since the node is now dead, remove it from the graph. 5516 DAG.DeleteNode(N); 5517 5518 // Replace the uses of Ptr with uses of the updated base value. 5519 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5520 &DeadNodes); 5521 removeFromWorkList(Ptr.getNode()); 5522 DAG.DeleteNode(Ptr.getNode()); 5523 5524 return true; 5525} 5526 5527/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5528/// add / sub of the base pointer node into a post-indexed load / store. 5529/// The transformation folded the add / subtract into the new indexed 5530/// load / store effectively and all of its uses are redirected to the 5531/// new load / store. 5532bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5533 if (!LegalOperations) 5534 return false; 5535 5536 bool isLoad = true; 5537 SDValue Ptr; 5538 EVT VT; 5539 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5540 if (LD->isIndexed()) 5541 return false; 5542 VT = LD->getMemoryVT(); 5543 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5544 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5545 return false; 5546 Ptr = LD->getBasePtr(); 5547 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5548 if (ST->isIndexed()) 5549 return false; 5550 VT = ST->getMemoryVT(); 5551 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5552 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5553 return false; 5554 Ptr = ST->getBasePtr(); 5555 isLoad = false; 5556 } else { 5557 return false; 5558 } 5559 5560 if (Ptr.getNode()->hasOneUse()) 5561 return false; 5562 5563 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5564 E = Ptr.getNode()->use_end(); I != E; ++I) { 5565 SDNode *Op = *I; 5566 if (Op == N || 5567 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5568 continue; 5569 5570 SDValue BasePtr; 5571 SDValue Offset; 5572 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5573 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5574 // Don't create a indexed load / store with zero offset. 5575 if (isa<ConstantSDNode>(Offset) && 5576 cast<ConstantSDNode>(Offset)->isNullValue()) 5577 continue; 5578 5579 // Try turning it into a post-indexed load / store except when 5580 // 1) All uses are load / store ops that use it as base ptr. 5581 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5582 // nor a successor of N. Otherwise, if Op is folded that would 5583 // create a cycle. 5584 5585 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5586 continue; 5587 5588 // Check for #1. 5589 bool TryNext = false; 5590 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5591 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5592 SDNode *Use = *II; 5593 if (Use == Ptr.getNode()) 5594 continue; 5595 5596 // If all the uses are load / store addresses, then don't do the 5597 // transformation. 5598 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5599 bool RealUse = false; 5600 for (SDNode::use_iterator III = Use->use_begin(), 5601 EEE = Use->use_end(); III != EEE; ++III) { 5602 SDNode *UseUse = *III; 5603 if (!((UseUse->getOpcode() == ISD::LOAD && 5604 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5605 (UseUse->getOpcode() == ISD::STORE && 5606 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5607 RealUse = true; 5608 } 5609 5610 if (!RealUse) { 5611 TryNext = true; 5612 break; 5613 } 5614 } 5615 } 5616 5617 if (TryNext) 5618 continue; 5619 5620 // Check for #2 5621 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5622 SDValue Result = isLoad 5623 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5624 BasePtr, Offset, AM) 5625 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5626 BasePtr, Offset, AM); 5627 ++PostIndexedNodes; 5628 ++NodesCombined; 5629 DEBUG(dbgs() << "\nReplacing.5 "; 5630 N->dump(&DAG); 5631 dbgs() << "\nWith: "; 5632 Result.getNode()->dump(&DAG); 5633 dbgs() << '\n'); 5634 WorkListRemover DeadNodes(*this); 5635 if (isLoad) { 5636 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5637 &DeadNodes); 5638 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5639 &DeadNodes); 5640 } else { 5641 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5642 &DeadNodes); 5643 } 5644 5645 // Finally, since the node is now dead, remove it from the graph. 5646 DAG.DeleteNode(N); 5647 5648 // Replace the uses of Use with uses of the updated base value. 5649 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5650 Result.getValue(isLoad ? 1 : 0), 5651 &DeadNodes); 5652 removeFromWorkList(Op); 5653 DAG.DeleteNode(Op); 5654 return true; 5655 } 5656 } 5657 } 5658 5659 return false; 5660} 5661 5662SDValue DAGCombiner::visitLOAD(SDNode *N) { 5663 LoadSDNode *LD = cast<LoadSDNode>(N); 5664 SDValue Chain = LD->getChain(); 5665 SDValue Ptr = LD->getBasePtr(); 5666 5667 // If load is not volatile and there are no uses of the loaded value (and 5668 // the updated indexed value in case of indexed loads), change uses of the 5669 // chain value into uses of the chain input (i.e. delete the dead load). 5670 if (!LD->isVolatile()) { 5671 if (N->getValueType(1) == MVT::Other) { 5672 // Unindexed loads. 5673 if (N->hasNUsesOfValue(0, 0)) { 5674 // It's not safe to use the two value CombineTo variant here. e.g. 5675 // v1, chain2 = load chain1, loc 5676 // v2, chain3 = load chain2, loc 5677 // v3 = add v2, c 5678 // Now we replace use of chain2 with chain1. This makes the second load 5679 // isomorphic to the one we are deleting, and thus makes this load live. 5680 DEBUG(dbgs() << "\nReplacing.6 "; 5681 N->dump(&DAG); 5682 dbgs() << "\nWith chain: "; 5683 Chain.getNode()->dump(&DAG); 5684 dbgs() << "\n"); 5685 WorkListRemover DeadNodes(*this); 5686 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5687 5688 if (N->use_empty()) { 5689 removeFromWorkList(N); 5690 DAG.DeleteNode(N); 5691 } 5692 5693 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5694 } 5695 } else { 5696 // Indexed loads. 5697 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5698 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5699 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5700 DEBUG(dbgs() << "\nReplacing.7 "; 5701 N->dump(&DAG); 5702 dbgs() << "\nWith: "; 5703 Undef.getNode()->dump(&DAG); 5704 dbgs() << " and 2 other values\n"); 5705 WorkListRemover DeadNodes(*this); 5706 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5707 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5708 DAG.getUNDEF(N->getValueType(1)), 5709 &DeadNodes); 5710 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5711 removeFromWorkList(N); 5712 DAG.DeleteNode(N); 5713 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5714 } 5715 } 5716 } 5717 5718 // If this load is directly stored, replace the load value with the stored 5719 // value. 5720 // TODO: Handle store large -> read small portion. 5721 // TODO: Handle TRUNCSTORE/LOADEXT 5722 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5723 !LD->isVolatile()) { 5724 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5725 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5726 if (PrevST->getBasePtr() == Ptr && 5727 PrevST->getValue().getValueType() == N->getValueType(0)) 5728 return CombineTo(N, Chain.getOperand(1), Chain); 5729 } 5730 } 5731 5732 // Try to infer better alignment information than the load already has. 5733 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5734 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5735 if (Align > LD->getAlignment()) 5736 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5737 N->getDebugLoc(), 5738 Chain, Ptr, LD->getPointerInfo(), 5739 LD->getMemoryVT(), 5740 LD->isVolatile(), LD->isNonTemporal(), Align); 5741 } 5742 } 5743 5744 if (CombinerAA) { 5745 // Walk up chain skipping non-aliasing memory nodes. 5746 SDValue BetterChain = FindBetterChain(N, Chain); 5747 5748 // If there is a better chain. 5749 if (Chain != BetterChain) { 5750 SDValue ReplLoad; 5751 5752 // Replace the chain to void dependency. 5753 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5754 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5755 BetterChain, Ptr, LD->getPointerInfo(), 5756 LD->isVolatile(), LD->isNonTemporal(), 5757 LD->getAlignment()); 5758 } else { 5759 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 5760 LD->getDebugLoc(), 5761 BetterChain, Ptr, LD->getPointerInfo(), 5762 LD->getMemoryVT(), 5763 LD->isVolatile(), 5764 LD->isNonTemporal(), 5765 LD->getAlignment()); 5766 } 5767 5768 // Create token factor to keep old chain connected. 5769 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5770 MVT::Other, Chain, ReplLoad.getValue(1)); 5771 5772 // Make sure the new and old chains are cleaned up. 5773 AddToWorkList(Token.getNode()); 5774 5775 // Replace uses with load result and token factor. Don't add users 5776 // to work list. 5777 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5778 } 5779 } 5780 5781 // Try transforming N to an indexed load. 5782 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5783 return SDValue(N, 0); 5784 5785 return SDValue(); 5786} 5787 5788/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5789/// load is having specific bytes cleared out. If so, return the byte size 5790/// being masked out and the shift amount. 5791static std::pair<unsigned, unsigned> 5792CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5793 std::pair<unsigned, unsigned> Result(0, 0); 5794 5795 // Check for the structure we're looking for. 5796 if (V->getOpcode() != ISD::AND || 5797 !isa<ConstantSDNode>(V->getOperand(1)) || 5798 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5799 return Result; 5800 5801 // Check the chain and pointer. 5802 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5803 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5804 5805 // The store should be chained directly to the load or be an operand of a 5806 // tokenfactor. 5807 if (LD == Chain.getNode()) 5808 ; // ok. 5809 else if (Chain->getOpcode() != ISD::TokenFactor) 5810 return Result; // Fail. 5811 else { 5812 bool isOk = false; 5813 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5814 if (Chain->getOperand(i).getNode() == LD) { 5815 isOk = true; 5816 break; 5817 } 5818 if (!isOk) return Result; 5819 } 5820 5821 // This only handles simple types. 5822 if (V.getValueType() != MVT::i16 && 5823 V.getValueType() != MVT::i32 && 5824 V.getValueType() != MVT::i64) 5825 return Result; 5826 5827 // Check the constant mask. Invert it so that the bits being masked out are 5828 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5829 // follow the sign bit for uniformity. 5830 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5831 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5832 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5833 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5834 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5835 if (NotMaskLZ == 64) return Result; // All zero mask. 5836 5837 // See if we have a continuous run of bits. If so, we have 0*1+0* 5838 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5839 return Result; 5840 5841 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5842 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5843 NotMaskLZ -= 64-V.getValueSizeInBits(); 5844 5845 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5846 switch (MaskedBytes) { 5847 case 1: 5848 case 2: 5849 case 4: break; 5850 default: return Result; // All one mask, or 5-byte mask. 5851 } 5852 5853 // Verify that the first bit starts at a multiple of mask so that the access 5854 // is aligned the same as the access width. 5855 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5856 5857 Result.first = MaskedBytes; 5858 Result.second = NotMaskTZ/8; 5859 return Result; 5860} 5861 5862 5863/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5864/// provides a value as specified by MaskInfo. If so, replace the specified 5865/// store with a narrower store of truncated IVal. 5866static SDNode * 5867ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5868 SDValue IVal, StoreSDNode *St, 5869 DAGCombiner *DC) { 5870 unsigned NumBytes = MaskInfo.first; 5871 unsigned ByteShift = MaskInfo.second; 5872 SelectionDAG &DAG = DC->getDAG(); 5873 5874 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5875 // that uses this. If not, this is not a replacement. 5876 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5877 ByteShift*8, (ByteShift+NumBytes)*8); 5878 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5879 5880 // Check that it is legal on the target to do this. It is legal if the new 5881 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5882 // legalization. 5883 MVT VT = MVT::getIntegerVT(NumBytes*8); 5884 if (!DC->isTypeLegal(VT)) 5885 return 0; 5886 5887 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5888 // shifted by ByteShift and truncated down to NumBytes. 5889 if (ByteShift) 5890 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5891 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5892 5893 // Figure out the offset for the store and the alignment of the access. 5894 unsigned StOffset; 5895 unsigned NewAlign = St->getAlignment(); 5896 5897 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5898 StOffset = ByteShift; 5899 else 5900 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5901 5902 SDValue Ptr = St->getBasePtr(); 5903 if (StOffset) { 5904 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5905 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5906 NewAlign = MinAlign(NewAlign, StOffset); 5907 } 5908 5909 // Truncate down to the new size. 5910 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5911 5912 ++OpsNarrowed; 5913 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5914 St->getPointerInfo().getWithOffset(StOffset), 5915 false, false, NewAlign).getNode(); 5916} 5917 5918 5919/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5920/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5921/// of the loaded bits, try narrowing the load and store if it would end up 5922/// being a win for performance or code size. 5923SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5924 StoreSDNode *ST = cast<StoreSDNode>(N); 5925 if (ST->isVolatile()) 5926 return SDValue(); 5927 5928 SDValue Chain = ST->getChain(); 5929 SDValue Value = ST->getValue(); 5930 SDValue Ptr = ST->getBasePtr(); 5931 EVT VT = Value.getValueType(); 5932 5933 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5934 return SDValue(); 5935 5936 unsigned Opc = Value.getOpcode(); 5937 5938 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5939 // is a byte mask indicating a consecutive number of bytes, check to see if 5940 // Y is known to provide just those bytes. If so, we try to replace the 5941 // load + replace + store sequence with a single (narrower) store, which makes 5942 // the load dead. 5943 if (Opc == ISD::OR) { 5944 std::pair<unsigned, unsigned> MaskedLoad; 5945 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5946 if (MaskedLoad.first) 5947 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5948 Value.getOperand(1), ST,this)) 5949 return SDValue(NewST, 0); 5950 5951 // Or is commutative, so try swapping X and Y. 5952 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5953 if (MaskedLoad.first) 5954 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5955 Value.getOperand(0), ST,this)) 5956 return SDValue(NewST, 0); 5957 } 5958 5959 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5960 Value.getOperand(1).getOpcode() != ISD::Constant) 5961 return SDValue(); 5962 5963 SDValue N0 = Value.getOperand(0); 5964 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5965 Chain == SDValue(N0.getNode(), 1)) { 5966 LoadSDNode *LD = cast<LoadSDNode>(N0); 5967 if (LD->getBasePtr() != Ptr || 5968 LD->getPointerInfo().getAddrSpace() != 5969 ST->getPointerInfo().getAddrSpace()) 5970 return SDValue(); 5971 5972 // Find the type to narrow it the load / op / store to. 5973 SDValue N1 = Value.getOperand(1); 5974 unsigned BitWidth = N1.getValueSizeInBits(); 5975 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5976 if (Opc == ISD::AND) 5977 Imm ^= APInt::getAllOnesValue(BitWidth); 5978 if (Imm == 0 || Imm.isAllOnesValue()) 5979 return SDValue(); 5980 unsigned ShAmt = Imm.countTrailingZeros(); 5981 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5982 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5983 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5984 while (NewBW < BitWidth && 5985 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5986 TLI.isNarrowingProfitable(VT, NewVT))) { 5987 NewBW = NextPowerOf2(NewBW); 5988 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5989 } 5990 if (NewBW >= BitWidth) 5991 return SDValue(); 5992 5993 // If the lsb changed does not start at the type bitwidth boundary, 5994 // start at the previous one. 5995 if (ShAmt % NewBW) 5996 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5997 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5998 if ((Imm & Mask) == Imm) { 5999 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6000 if (Opc == ISD::AND) 6001 NewImm ^= APInt::getAllOnesValue(NewBW); 6002 uint64_t PtrOff = ShAmt / 8; 6003 // For big endian targets, we need to adjust the offset to the pointer to 6004 // load the correct bytes. 6005 if (TLI.isBigEndian()) 6006 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6007 6008 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6009 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6010 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6011 return SDValue(); 6012 6013 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6014 Ptr.getValueType(), Ptr, 6015 DAG.getConstant(PtrOff, Ptr.getValueType())); 6016 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6017 LD->getChain(), NewPtr, 6018 LD->getPointerInfo().getWithOffset(PtrOff), 6019 LD->isVolatile(), LD->isNonTemporal(), 6020 NewAlign); 6021 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6022 DAG.getConstant(NewImm, NewVT)); 6023 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6024 NewVal, NewPtr, 6025 ST->getPointerInfo().getWithOffset(PtrOff), 6026 false, false, NewAlign); 6027 6028 AddToWorkList(NewPtr.getNode()); 6029 AddToWorkList(NewLD.getNode()); 6030 AddToWorkList(NewVal.getNode()); 6031 WorkListRemover DeadNodes(*this); 6032 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6033 &DeadNodes); 6034 ++OpsNarrowed; 6035 return NewST; 6036 } 6037 } 6038 6039 return SDValue(); 6040} 6041 6042SDValue DAGCombiner::visitSTORE(SDNode *N) { 6043 StoreSDNode *ST = cast<StoreSDNode>(N); 6044 SDValue Chain = ST->getChain(); 6045 SDValue Value = ST->getValue(); 6046 SDValue Ptr = ST->getBasePtr(); 6047 6048 // If this is a store of a bit convert, store the input value if the 6049 // resultant store does not need a higher alignment than the original. 6050 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6051 ST->isUnindexed()) { 6052 unsigned OrigAlign = ST->getAlignment(); 6053 EVT SVT = Value.getOperand(0).getValueType(); 6054 unsigned Align = TLI.getTargetData()-> 6055 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6056 if (Align <= OrigAlign && 6057 ((!LegalOperations && !ST->isVolatile()) || 6058 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6059 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6060 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6061 ST->isNonTemporal(), OrigAlign); 6062 } 6063 6064 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6065 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6066 // NOTE: If the original store is volatile, this transform must not increase 6067 // the number of stores. For example, on x86-32 an f64 can be stored in one 6068 // processor operation but an i64 (which is not legal) requires two. So the 6069 // transform should not be done in this case. 6070 if (Value.getOpcode() != ISD::TargetConstantFP) { 6071 SDValue Tmp; 6072 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6073 default: llvm_unreachable("Unknown FP type"); 6074 case MVT::f80: // We don't do this for these yet. 6075 case MVT::f128: 6076 case MVT::ppcf128: 6077 break; 6078 case MVT::f32: 6079 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6080 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6081 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6082 bitcastToAPInt().getZExtValue(), MVT::i32); 6083 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6084 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6085 ST->isNonTemporal(), ST->getAlignment()); 6086 } 6087 break; 6088 case MVT::f64: 6089 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6090 !ST->isVolatile()) || 6091 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6092 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6093 getZExtValue(), MVT::i64); 6094 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6095 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6096 ST->isNonTemporal(), ST->getAlignment()); 6097 } else if (!ST->isVolatile() && 6098 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6099 // Many FP stores are not made apparent until after legalize, e.g. for 6100 // argument passing. Since this is so common, custom legalize the 6101 // 64-bit integer store into two 32-bit stores. 6102 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6103 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6104 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6105 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6106 6107 unsigned Alignment = ST->getAlignment(); 6108 bool isVolatile = ST->isVolatile(); 6109 bool isNonTemporal = ST->isNonTemporal(); 6110 6111 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6112 Ptr, ST->getPointerInfo(), 6113 isVolatile, isNonTemporal, 6114 ST->getAlignment()); 6115 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6116 DAG.getConstant(4, Ptr.getValueType())); 6117 Alignment = MinAlign(Alignment, 4U); 6118 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6119 Ptr, ST->getPointerInfo().getWithOffset(4), 6120 isVolatile, isNonTemporal, 6121 Alignment); 6122 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6123 St0, St1); 6124 } 6125 6126 break; 6127 } 6128 } 6129 } 6130 6131 // Try to infer better alignment information than the store already has. 6132 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6133 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6134 if (Align > ST->getAlignment()) 6135 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6136 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6137 ST->isVolatile(), ST->isNonTemporal(), Align); 6138 } 6139 } 6140 6141 if (CombinerAA) { 6142 // Walk up chain skipping non-aliasing memory nodes. 6143 SDValue BetterChain = FindBetterChain(N, Chain); 6144 6145 // If there is a better chain. 6146 if (Chain != BetterChain) { 6147 SDValue ReplStore; 6148 6149 // Replace the chain to avoid dependency. 6150 if (ST->isTruncatingStore()) { 6151 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6152 ST->getPointerInfo(), 6153 ST->getMemoryVT(), ST->isVolatile(), 6154 ST->isNonTemporal(), ST->getAlignment()); 6155 } else { 6156 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6157 ST->getPointerInfo(), 6158 ST->isVolatile(), ST->isNonTemporal(), 6159 ST->getAlignment()); 6160 } 6161 6162 // Create token to keep both nodes around. 6163 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6164 MVT::Other, Chain, ReplStore); 6165 6166 // Make sure the new and old chains are cleaned up. 6167 AddToWorkList(Token.getNode()); 6168 6169 // Don't add users to work list. 6170 return CombineTo(N, Token, false); 6171 } 6172 } 6173 6174 // Try transforming N to an indexed store. 6175 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6176 return SDValue(N, 0); 6177 6178 // FIXME: is there such a thing as a truncating indexed store? 6179 if (ST->isTruncatingStore() && ST->isUnindexed() && 6180 Value.getValueType().isInteger()) { 6181 // See if we can simplify the input to this truncstore with knowledge that 6182 // only the low bits are being used. For example: 6183 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6184 SDValue Shorter = 6185 GetDemandedBits(Value, 6186 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6187 ST->getMemoryVT().getSizeInBits())); 6188 AddToWorkList(Value.getNode()); 6189 if (Shorter.getNode()) 6190 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6191 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6192 ST->isVolatile(), ST->isNonTemporal(), 6193 ST->getAlignment()); 6194 6195 // Otherwise, see if we can simplify the operation with 6196 // SimplifyDemandedBits, which only works if the value has a single use. 6197 if (SimplifyDemandedBits(Value, 6198 APInt::getLowBitsSet( 6199 Value.getValueType().getScalarType().getSizeInBits(), 6200 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6201 return SDValue(N, 0); 6202 } 6203 6204 // If this is a load followed by a store to the same location, then the store 6205 // is dead/noop. 6206 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6207 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6208 ST->isUnindexed() && !ST->isVolatile() && 6209 // There can't be any side effects between the load and store, such as 6210 // a call or store. 6211 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6212 // The store is dead, remove it. 6213 return Chain; 6214 } 6215 } 6216 6217 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6218 // truncating store. We can do this even if this is already a truncstore. 6219 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6220 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6221 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6222 ST->getMemoryVT())) { 6223 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6224 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6225 ST->isVolatile(), ST->isNonTemporal(), 6226 ST->getAlignment()); 6227 } 6228 6229 return ReduceLoadOpStoreWidth(N); 6230} 6231 6232SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6233 SDValue InVec = N->getOperand(0); 6234 SDValue InVal = N->getOperand(1); 6235 SDValue EltNo = N->getOperand(2); 6236 6237 // If the inserted element is an UNDEF, just use the input vector. 6238 if (InVal.getOpcode() == ISD::UNDEF) 6239 return InVec; 6240 6241 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6242 // vector with the inserted element. 6243 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6244 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6245 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6246 InVec.getNode()->op_end()); 6247 if (Elt < Ops.size()) 6248 Ops[Elt] = InVal; 6249 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6250 InVec.getValueType(), &Ops[0], Ops.size()); 6251 } 6252 // If the invec is an UNDEF and if EltNo is a constant, create a new 6253 // BUILD_VECTOR with undef elements and the inserted element. 6254 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 6255 isa<ConstantSDNode>(EltNo)) { 6256 EVT VT = InVec.getValueType(); 6257 EVT EltVT = VT.getVectorElementType(); 6258 unsigned NElts = VT.getVectorNumElements(); 6259 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6260 6261 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6262 if (Elt < Ops.size()) 6263 Ops[Elt] = InVal; 6264 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6265 InVec.getValueType(), &Ops[0], Ops.size()); 6266 } 6267 return SDValue(); 6268} 6269 6270SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6271 // (vextract (scalar_to_vector val, 0) -> val 6272 SDValue InVec = N->getOperand(0); 6273 6274 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6275 // Check if the result type doesn't match the inserted element type. A 6276 // SCALAR_TO_VECTOR may truncate the inserted element and the 6277 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6278 SDValue InOp = InVec.getOperand(0); 6279 EVT NVT = N->getValueType(0); 6280 if (InOp.getValueType() != NVT) { 6281 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6282 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6283 } 6284 return InOp; 6285 } 6286 6287 // Perform only after legalization to ensure build_vector / vector_shuffle 6288 // optimizations have already been done. 6289 if (!LegalOperations) return SDValue(); 6290 6291 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6292 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6293 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6294 SDValue EltNo = N->getOperand(1); 6295 6296 if (isa<ConstantSDNode>(EltNo)) { 6297 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6298 bool NewLoad = false; 6299 bool BCNumEltsChanged = false; 6300 EVT VT = InVec.getValueType(); 6301 EVT ExtVT = VT.getVectorElementType(); 6302 EVT LVT = ExtVT; 6303 6304 if (InVec.getOpcode() == ISD::BITCAST) { 6305 EVT BCVT = InVec.getOperand(0).getValueType(); 6306 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6307 return SDValue(); 6308 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6309 BCNumEltsChanged = true; 6310 InVec = InVec.getOperand(0); 6311 ExtVT = BCVT.getVectorElementType(); 6312 NewLoad = true; 6313 } 6314 6315 LoadSDNode *LN0 = NULL; 6316 const ShuffleVectorSDNode *SVN = NULL; 6317 if (ISD::isNormalLoad(InVec.getNode())) { 6318 LN0 = cast<LoadSDNode>(InVec); 6319 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6320 InVec.getOperand(0).getValueType() == ExtVT && 6321 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6322 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6323 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6324 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6325 // => 6326 // (load $addr+1*size) 6327 6328 // If the bit convert changed the number of elements, it is unsafe 6329 // to examine the mask. 6330 if (BCNumEltsChanged) 6331 return SDValue(); 6332 6333 // Select the input vector, guarding against out of range extract vector. 6334 unsigned NumElems = VT.getVectorNumElements(); 6335 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6336 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6337 6338 if (InVec.getOpcode() == ISD::BITCAST) 6339 InVec = InVec.getOperand(0); 6340 if (ISD::isNormalLoad(InVec.getNode())) { 6341 LN0 = cast<LoadSDNode>(InVec); 6342 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6343 } 6344 } 6345 6346 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6347 return SDValue(); 6348 6349 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6350 if (Elt == -1) 6351 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6352 6353 unsigned Align = LN0->getAlignment(); 6354 if (NewLoad) { 6355 // Check the resultant load doesn't need a higher alignment than the 6356 // original load. 6357 unsigned NewAlign = 6358 TLI.getTargetData() 6359 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6360 6361 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6362 return SDValue(); 6363 6364 Align = NewAlign; 6365 } 6366 6367 SDValue NewPtr = LN0->getBasePtr(); 6368 unsigned PtrOff = 0; 6369 6370 if (Elt) { 6371 PtrOff = LVT.getSizeInBits() * Elt / 8; 6372 EVT PtrType = NewPtr.getValueType(); 6373 if (TLI.isBigEndian()) 6374 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6375 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6376 DAG.getConstant(PtrOff, PtrType)); 6377 } 6378 6379 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6380 LN0->getPointerInfo().getWithOffset(PtrOff), 6381 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6382 } 6383 6384 return SDValue(); 6385} 6386 6387SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6388 unsigned NumInScalars = N->getNumOperands(); 6389 EVT VT = N->getValueType(0); 6390 6391 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6392 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6393 // at most two distinct vectors, turn this into a shuffle node. 6394 SDValue VecIn1, VecIn2; 6395 for (unsigned i = 0; i != NumInScalars; ++i) { 6396 // Ignore undef inputs. 6397 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6398 6399 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6400 // constant index, bail out. 6401 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6402 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6403 VecIn1 = VecIn2 = SDValue(0, 0); 6404 break; 6405 } 6406 6407 // If the input vector type disagrees with the result of the build_vector, 6408 // we can't make a shuffle. 6409 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6410 if (ExtractedFromVec.getValueType() != VT) { 6411 VecIn1 = VecIn2 = SDValue(0, 0); 6412 break; 6413 } 6414 6415 // Otherwise, remember this. We allow up to two distinct input vectors. 6416 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6417 continue; 6418 6419 if (VecIn1.getNode() == 0) { 6420 VecIn1 = ExtractedFromVec; 6421 } else if (VecIn2.getNode() == 0) { 6422 VecIn2 = ExtractedFromVec; 6423 } else { 6424 // Too many inputs. 6425 VecIn1 = VecIn2 = SDValue(0, 0); 6426 break; 6427 } 6428 } 6429 6430 // If everything is good, we can make a shuffle operation. 6431 if (VecIn1.getNode()) { 6432 SmallVector<int, 8> Mask; 6433 for (unsigned i = 0; i != NumInScalars; ++i) { 6434 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6435 Mask.push_back(-1); 6436 continue; 6437 } 6438 6439 // If extracting from the first vector, just use the index directly. 6440 SDValue Extract = N->getOperand(i); 6441 SDValue ExtVal = Extract.getOperand(1); 6442 if (Extract.getOperand(0) == VecIn1) { 6443 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6444 if (ExtIndex > VT.getVectorNumElements()) 6445 return SDValue(); 6446 6447 Mask.push_back(ExtIndex); 6448 continue; 6449 } 6450 6451 // Otherwise, use InIdx + VecSize 6452 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6453 Mask.push_back(Idx+NumInScalars); 6454 } 6455 6456 // Add count and size info. 6457 if (!isTypeLegal(VT)) 6458 return SDValue(); 6459 6460 // Return the new VECTOR_SHUFFLE node. 6461 SDValue Ops[2]; 6462 Ops[0] = VecIn1; 6463 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6464 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6465 } 6466 6467 return SDValue(); 6468} 6469 6470SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6471 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6472 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6473 // inputs come from at most two distinct vectors, turn this into a shuffle 6474 // node. 6475 6476 // If we only have one input vector, we don't need to do any concatenation. 6477 if (N->getNumOperands() == 1) 6478 return N->getOperand(0); 6479 6480 return SDValue(); 6481} 6482 6483SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6484 EVT VT = N->getValueType(0); 6485 unsigned NumElts = VT.getVectorNumElements(); 6486 6487 SDValue N0 = N->getOperand(0); 6488 6489 assert(N0.getValueType().getVectorNumElements() == NumElts && 6490 "Vector shuffle must be normalized in DAG"); 6491 6492 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6493 6494 // If it is a splat, check if the argument vector is another splat or a 6495 // build_vector with all scalar elements the same. 6496 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6497 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6498 SDNode *V = N0.getNode(); 6499 6500 // If this is a bit convert that changes the element type of the vector but 6501 // not the number of vector elements, look through it. Be careful not to 6502 // look though conversions that change things like v4f32 to v2f64. 6503 if (V->getOpcode() == ISD::BITCAST) { 6504 SDValue ConvInput = V->getOperand(0); 6505 if (ConvInput.getValueType().isVector() && 6506 ConvInput.getValueType().getVectorNumElements() == NumElts) 6507 V = ConvInput.getNode(); 6508 } 6509 6510 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6511 assert(V->getNumOperands() == NumElts && 6512 "BUILD_VECTOR has wrong number of operands"); 6513 SDValue Base; 6514 bool AllSame = true; 6515 for (unsigned i = 0; i != NumElts; ++i) { 6516 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6517 Base = V->getOperand(i); 6518 break; 6519 } 6520 } 6521 // Splat of <u, u, u, u>, return <u, u, u, u> 6522 if (!Base.getNode()) 6523 return N0; 6524 for (unsigned i = 0; i != NumElts; ++i) { 6525 if (V->getOperand(i) != Base) { 6526 AllSame = false; 6527 break; 6528 } 6529 } 6530 // Splat of <x, x, x, x>, return <x, x, x, x> 6531 if (AllSame) 6532 return N0; 6533 } 6534 } 6535 return SDValue(); 6536} 6537 6538SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6539 if (!TLI.getShouldFoldAtomicFences()) 6540 return SDValue(); 6541 6542 SDValue atomic = N->getOperand(0); 6543 switch (atomic.getOpcode()) { 6544 case ISD::ATOMIC_CMP_SWAP: 6545 case ISD::ATOMIC_SWAP: 6546 case ISD::ATOMIC_LOAD_ADD: 6547 case ISD::ATOMIC_LOAD_SUB: 6548 case ISD::ATOMIC_LOAD_AND: 6549 case ISD::ATOMIC_LOAD_OR: 6550 case ISD::ATOMIC_LOAD_XOR: 6551 case ISD::ATOMIC_LOAD_NAND: 6552 case ISD::ATOMIC_LOAD_MIN: 6553 case ISD::ATOMIC_LOAD_MAX: 6554 case ISD::ATOMIC_LOAD_UMIN: 6555 case ISD::ATOMIC_LOAD_UMAX: 6556 break; 6557 default: 6558 return SDValue(); 6559 } 6560 6561 SDValue fence = atomic.getOperand(0); 6562 if (fence.getOpcode() != ISD::MEMBARRIER) 6563 return SDValue(); 6564 6565 switch (atomic.getOpcode()) { 6566 case ISD::ATOMIC_CMP_SWAP: 6567 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6568 fence.getOperand(0), 6569 atomic.getOperand(1), atomic.getOperand(2), 6570 atomic.getOperand(3)), atomic.getResNo()); 6571 case ISD::ATOMIC_SWAP: 6572 case ISD::ATOMIC_LOAD_ADD: 6573 case ISD::ATOMIC_LOAD_SUB: 6574 case ISD::ATOMIC_LOAD_AND: 6575 case ISD::ATOMIC_LOAD_OR: 6576 case ISD::ATOMIC_LOAD_XOR: 6577 case ISD::ATOMIC_LOAD_NAND: 6578 case ISD::ATOMIC_LOAD_MIN: 6579 case ISD::ATOMIC_LOAD_MAX: 6580 case ISD::ATOMIC_LOAD_UMIN: 6581 case ISD::ATOMIC_LOAD_UMAX: 6582 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6583 fence.getOperand(0), 6584 atomic.getOperand(1), atomic.getOperand(2)), 6585 atomic.getResNo()); 6586 default: 6587 return SDValue(); 6588 } 6589} 6590 6591/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6592/// an AND to a vector_shuffle with the destination vector and a zero vector. 6593/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6594/// vector_shuffle V, Zero, <0, 4, 2, 4> 6595SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6596 EVT VT = N->getValueType(0); 6597 DebugLoc dl = N->getDebugLoc(); 6598 SDValue LHS = N->getOperand(0); 6599 SDValue RHS = N->getOperand(1); 6600 if (N->getOpcode() == ISD::AND) { 6601 if (RHS.getOpcode() == ISD::BITCAST) 6602 RHS = RHS.getOperand(0); 6603 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6604 SmallVector<int, 8> Indices; 6605 unsigned NumElts = RHS.getNumOperands(); 6606 for (unsigned i = 0; i != NumElts; ++i) { 6607 SDValue Elt = RHS.getOperand(i); 6608 if (!isa<ConstantSDNode>(Elt)) 6609 return SDValue(); 6610 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6611 Indices.push_back(i); 6612 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6613 Indices.push_back(NumElts); 6614 else 6615 return SDValue(); 6616 } 6617 6618 // Let's see if the target supports this vector_shuffle. 6619 EVT RVT = RHS.getValueType(); 6620 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6621 return SDValue(); 6622 6623 // Return the new VECTOR_SHUFFLE node. 6624 EVT EltVT = RVT.getVectorElementType(); 6625 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6626 DAG.getConstant(0, EltVT)); 6627 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6628 RVT, &ZeroOps[0], ZeroOps.size()); 6629 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6630 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6631 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6632 } 6633 } 6634 6635 return SDValue(); 6636} 6637 6638/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6639SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6640 // After legalize, the target may be depending on adds and other 6641 // binary ops to provide legal ways to construct constants or other 6642 // things. Simplifying them may result in a loss of legality. 6643 if (LegalOperations) return SDValue(); 6644 6645 assert(N->getValueType(0).isVector() && 6646 "SimplifyVBinOp only works on vectors!"); 6647 6648 SDValue LHS = N->getOperand(0); 6649 SDValue RHS = N->getOperand(1); 6650 SDValue Shuffle = XformToShuffleWithZero(N); 6651 if (Shuffle.getNode()) return Shuffle; 6652 6653 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6654 // this operation. 6655 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6656 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6657 SmallVector<SDValue, 8> Ops; 6658 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6659 SDValue LHSOp = LHS.getOperand(i); 6660 SDValue RHSOp = RHS.getOperand(i); 6661 // If these two elements can't be folded, bail out. 6662 if ((LHSOp.getOpcode() != ISD::UNDEF && 6663 LHSOp.getOpcode() != ISD::Constant && 6664 LHSOp.getOpcode() != ISD::ConstantFP) || 6665 (RHSOp.getOpcode() != ISD::UNDEF && 6666 RHSOp.getOpcode() != ISD::Constant && 6667 RHSOp.getOpcode() != ISD::ConstantFP)) 6668 break; 6669 6670 // Can't fold divide by zero. 6671 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6672 N->getOpcode() == ISD::FDIV) { 6673 if ((RHSOp.getOpcode() == ISD::Constant && 6674 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6675 (RHSOp.getOpcode() == ISD::ConstantFP && 6676 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6677 break; 6678 } 6679 6680 EVT VT = LHSOp.getValueType(); 6681 assert(RHSOp.getValueType() == VT && 6682 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6683 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6684 LHSOp, RHSOp); 6685 if (FoldOp.getOpcode() != ISD::UNDEF && 6686 FoldOp.getOpcode() != ISD::Constant && 6687 FoldOp.getOpcode() != ISD::ConstantFP) 6688 break; 6689 Ops.push_back(FoldOp); 6690 AddToWorkList(FoldOp.getNode()); 6691 } 6692 6693 if (Ops.size() == LHS.getNumOperands()) 6694 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6695 LHS.getValueType(), &Ops[0], Ops.size()); 6696 } 6697 6698 return SDValue(); 6699} 6700 6701SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6702 SDValue N1, SDValue N2){ 6703 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6704 6705 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6706 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6707 6708 // If we got a simplified select_cc node back from SimplifySelectCC, then 6709 // break it down into a new SETCC node, and a new SELECT node, and then return 6710 // the SELECT node, since we were called with a SELECT node. 6711 if (SCC.getNode()) { 6712 // Check to see if we got a select_cc back (to turn into setcc/select). 6713 // Otherwise, just return whatever node we got back, like fabs. 6714 if (SCC.getOpcode() == ISD::SELECT_CC) { 6715 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6716 N0.getValueType(), 6717 SCC.getOperand(0), SCC.getOperand(1), 6718 SCC.getOperand(4)); 6719 AddToWorkList(SETCC.getNode()); 6720 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6721 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6722 } 6723 6724 return SCC; 6725 } 6726 return SDValue(); 6727} 6728 6729/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6730/// are the two values being selected between, see if we can simplify the 6731/// select. Callers of this should assume that TheSelect is deleted if this 6732/// returns true. As such, they should return the appropriate thing (e.g. the 6733/// node) back to the top-level of the DAG combiner loop to avoid it being 6734/// looked at. 6735bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6736 SDValue RHS) { 6737 6738 // If this is a select from two identical things, try to pull the operation 6739 // through the select. 6740 if (LHS.getOpcode() != RHS.getOpcode() || 6741 !LHS.hasOneUse() || !RHS.hasOneUse()) 6742 return false; 6743 6744 // If this is a load and the token chain is identical, replace the select 6745 // of two loads with a load through a select of the address to load from. 6746 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6747 // constants have been dropped into the constant pool. 6748 if (LHS.getOpcode() == ISD::LOAD) { 6749 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6750 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6751 6752 // Token chains must be identical. 6753 if (LHS.getOperand(0) != RHS.getOperand(0) || 6754 // Do not let this transformation reduce the number of volatile loads. 6755 LLD->isVolatile() || RLD->isVolatile() || 6756 // If this is an EXTLOAD, the VT's must match. 6757 LLD->getMemoryVT() != RLD->getMemoryVT() || 6758 // If this is an EXTLOAD, the kind of extension must match. 6759 (LLD->getExtensionType() != RLD->getExtensionType() && 6760 // The only exception is if one of the extensions is anyext. 6761 LLD->getExtensionType() != ISD::EXTLOAD && 6762 RLD->getExtensionType() != ISD::EXTLOAD) || 6763 // FIXME: this discards src value information. This is 6764 // over-conservative. It would be beneficial to be able to remember 6765 // both potential memory locations. Since we are discarding 6766 // src value info, don't do the transformation if the memory 6767 // locations are not in the default address space. 6768 LLD->getPointerInfo().getAddrSpace() != 0 || 6769 RLD->getPointerInfo().getAddrSpace() != 0) 6770 return false; 6771 6772 // Check that the select condition doesn't reach either load. If so, 6773 // folding this will induce a cycle into the DAG. If not, this is safe to 6774 // xform, so create a select of the addresses. 6775 SDValue Addr; 6776 if (TheSelect->getOpcode() == ISD::SELECT) { 6777 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 6778 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 6779 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 6780 return false; 6781 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6782 LLD->getBasePtr().getValueType(), 6783 TheSelect->getOperand(0), LLD->getBasePtr(), 6784 RLD->getBasePtr()); 6785 } else { // Otherwise SELECT_CC 6786 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 6787 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 6788 6789 if ((LLD->hasAnyUseOfValue(1) && 6790 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 6791 (LLD->hasAnyUseOfValue(1) && 6792 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 6793 return false; 6794 6795 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6796 LLD->getBasePtr().getValueType(), 6797 TheSelect->getOperand(0), 6798 TheSelect->getOperand(1), 6799 LLD->getBasePtr(), RLD->getBasePtr(), 6800 TheSelect->getOperand(4)); 6801 } 6802 6803 SDValue Load; 6804 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6805 Load = DAG.getLoad(TheSelect->getValueType(0), 6806 TheSelect->getDebugLoc(), 6807 // FIXME: Discards pointer info. 6808 LLD->getChain(), Addr, MachinePointerInfo(), 6809 LLD->isVolatile(), LLD->isNonTemporal(), 6810 LLD->getAlignment()); 6811 } else { 6812 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 6813 RLD->getExtensionType() : LLD->getExtensionType(), 6814 TheSelect->getValueType(0), 6815 TheSelect->getDebugLoc(), 6816 // FIXME: Discards pointer info. 6817 LLD->getChain(), Addr, MachinePointerInfo(), 6818 LLD->getMemoryVT(), LLD->isVolatile(), 6819 LLD->isNonTemporal(), LLD->getAlignment()); 6820 } 6821 6822 // Users of the select now use the result of the load. 6823 CombineTo(TheSelect, Load); 6824 6825 // Users of the old loads now use the new load's chain. We know the 6826 // old-load value is dead now. 6827 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6828 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6829 return true; 6830 } 6831 6832 return false; 6833} 6834 6835/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6836/// where 'cond' is the comparison specified by CC. 6837SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6838 SDValue N2, SDValue N3, 6839 ISD::CondCode CC, bool NotExtCompare) { 6840 // (x ? y : y) -> y. 6841 if (N2 == N3) return N2; 6842 6843 EVT VT = N2.getValueType(); 6844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6845 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6846 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6847 6848 // Determine if the condition we're dealing with is constant 6849 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6850 N0, N1, CC, DL, false); 6851 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6852 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6853 6854 // fold select_cc true, x, y -> x 6855 if (SCCC && !SCCC->isNullValue()) 6856 return N2; 6857 // fold select_cc false, x, y -> y 6858 if (SCCC && SCCC->isNullValue()) 6859 return N3; 6860 6861 // Check to see if we can simplify the select into an fabs node 6862 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6863 // Allow either -0.0 or 0.0 6864 if (CFP->getValueAPF().isZero()) { 6865 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6866 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6867 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6868 N2 == N3.getOperand(0)) 6869 return DAG.getNode(ISD::FABS, DL, VT, N0); 6870 6871 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6872 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6873 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6874 N2.getOperand(0) == N3) 6875 return DAG.getNode(ISD::FABS, DL, VT, N3); 6876 } 6877 } 6878 6879 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6880 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6881 // in it. This is a win when the constant is not otherwise available because 6882 // it replaces two constant pool loads with one. We only do this if the FP 6883 // type is known to be legal, because if it isn't, then we are before legalize 6884 // types an we want the other legalization to happen first (e.g. to avoid 6885 // messing with soft float) and if the ConstantFP is not legal, because if 6886 // it is legal, we may not need to store the FP constant in a constant pool. 6887 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6888 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6889 if (TLI.isTypeLegal(N2.getValueType()) && 6890 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6891 TargetLowering::Legal) && 6892 // If both constants have multiple uses, then we won't need to do an 6893 // extra load, they are likely around in registers for other users. 6894 (TV->hasOneUse() || FV->hasOneUse())) { 6895 Constant *Elts[] = { 6896 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6897 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6898 }; 6899 const Type *FPTy = Elts[0]->getType(); 6900 const TargetData &TD = *TLI.getTargetData(); 6901 6902 // Create a ConstantArray of the two constants. 6903 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6904 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6905 TD.getPrefTypeAlignment(FPTy)); 6906 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6907 6908 // Get the offsets to the 0 and 1 element of the array so that we can 6909 // select between them. 6910 SDValue Zero = DAG.getIntPtrConstant(0); 6911 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6912 SDValue One = DAG.getIntPtrConstant(EltSize); 6913 6914 SDValue Cond = DAG.getSetCC(DL, 6915 TLI.getSetCCResultType(N0.getValueType()), 6916 N0, N1, CC); 6917 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6918 Cond, One, Zero); 6919 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6920 CstOffset); 6921 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6922 MachinePointerInfo::getConstantPool(), false, 6923 false, Alignment); 6924 6925 } 6926 } 6927 6928 // Check to see if we can perform the "gzip trick", transforming 6929 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6930 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6931 N0.getValueType().isInteger() && 6932 N2.getValueType().isInteger() && 6933 (N1C->isNullValue() || // (a < 0) ? b : 0 6934 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6935 EVT XType = N0.getValueType(); 6936 EVT AType = N2.getValueType(); 6937 if (XType.bitsGE(AType)) { 6938 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6939 // single-bit constant. 6940 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6941 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6942 ShCtV = XType.getSizeInBits()-ShCtV-1; 6943 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6944 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6945 XType, N0, ShCt); 6946 AddToWorkList(Shift.getNode()); 6947 6948 if (XType.bitsGT(AType)) { 6949 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6950 AddToWorkList(Shift.getNode()); 6951 } 6952 6953 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6954 } 6955 6956 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6957 XType, N0, 6958 DAG.getConstant(XType.getSizeInBits()-1, 6959 getShiftAmountTy())); 6960 AddToWorkList(Shift.getNode()); 6961 6962 if (XType.bitsGT(AType)) { 6963 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6964 AddToWorkList(Shift.getNode()); 6965 } 6966 6967 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6968 } 6969 } 6970 6971 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 6972 // where y is has a single bit set. 6973 // A plaintext description would be, we can turn the SELECT_CC into an AND 6974 // when the condition can be materialized as an all-ones register. Any 6975 // single bit-test can be materialized as an all-ones register with 6976 // shift-left and shift-right-arith. 6977 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 6978 N0->getValueType(0) == VT && 6979 N1C && N1C->isNullValue() && 6980 N2C && N2C->isNullValue()) { 6981 SDValue AndLHS = N0->getOperand(0); 6982 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 6983 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 6984 // Shift the tested bit over the sign bit. 6985 APInt AndMask = ConstAndRHS->getAPIntValue(); 6986 SDValue ShlAmt = 6987 DAG.getConstant(AndMask.countLeadingZeros(), getShiftAmountTy()); 6988 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 6989 6990 // Now arithmetic right shift it all the way over, so the result is either 6991 // all-ones, or zero. 6992 SDValue ShrAmt = 6993 DAG.getConstant(AndMask.getBitWidth()-1, getShiftAmountTy()); 6994 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 6995 6996 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 6997 } 6998 } 6999 7000 // fold select C, 16, 0 -> shl C, 4 7001 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7002 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7003 7004 // If the caller doesn't want us to simplify this into a zext of a compare, 7005 // don't do it. 7006 if (NotExtCompare && N2C->getAPIntValue() == 1) 7007 return SDValue(); 7008 7009 // Get a SetCC of the condition 7010 // FIXME: Should probably make sure that setcc is legal if we ever have a 7011 // target where it isn't. 7012 SDValue Temp, SCC; 7013 // cast from setcc result type to select result type 7014 if (LegalTypes) { 7015 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7016 N0, N1, CC); 7017 if (N2.getValueType().bitsLT(SCC.getValueType())) 7018 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7019 else 7020 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7021 N2.getValueType(), SCC); 7022 } else { 7023 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7024 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7025 N2.getValueType(), SCC); 7026 } 7027 7028 AddToWorkList(SCC.getNode()); 7029 AddToWorkList(Temp.getNode()); 7030 7031 if (N2C->getAPIntValue() == 1) 7032 return Temp; 7033 7034 // shl setcc result by log2 n2c 7035 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7036 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7037 getShiftAmountTy())); 7038 } 7039 7040 // Check to see if this is the equivalent of setcc 7041 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7042 // otherwise, go ahead with the folds. 7043 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7044 EVT XType = N0.getValueType(); 7045 if (!LegalOperations || 7046 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7047 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7048 if (Res.getValueType() != VT) 7049 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7050 return Res; 7051 } 7052 7053 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7054 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7055 (!LegalOperations || 7056 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7057 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7058 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7059 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7060 getShiftAmountTy())); 7061 } 7062 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7063 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7064 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7065 XType, DAG.getConstant(0, XType), N0); 7066 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7067 return DAG.getNode(ISD::SRL, DL, XType, 7068 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7069 DAG.getConstant(XType.getSizeInBits()-1, 7070 getShiftAmountTy())); 7071 } 7072 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7073 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7074 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7075 DAG.getConstant(XType.getSizeInBits()-1, 7076 getShiftAmountTy())); 7077 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7078 } 7079 } 7080 7081 // Check to see if this is an integer abs. 7082 // select_cc setg[te] X, 0, X, -X -> 7083 // select_cc setgt X, -1, X, -X -> 7084 // select_cc setl[te] X, 0, -X, X -> 7085 // select_cc setlt X, 1, -X, X -> 7086 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7087 if (N1C) { 7088 ConstantSDNode *SubC = NULL; 7089 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7090 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7091 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7092 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7093 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7094 (N1C->isOne() && CC == ISD::SETLT)) && 7095 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7096 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7097 7098 EVT XType = N0.getValueType(); 7099 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7100 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7101 N0, 7102 DAG.getConstant(XType.getSizeInBits()-1, 7103 getShiftAmountTy())); 7104 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7105 XType, N0, Shift); 7106 AddToWorkList(Shift.getNode()); 7107 AddToWorkList(Add.getNode()); 7108 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7109 } 7110 } 7111 7112 return SDValue(); 7113} 7114 7115/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7116SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7117 SDValue N1, ISD::CondCode Cond, 7118 DebugLoc DL, bool foldBooleans) { 7119 TargetLowering::DAGCombinerInfo 7120 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7121 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7122} 7123 7124/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7125/// return a DAG expression to select that will generate the same value by 7126/// multiplying by a magic number. See: 7127/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7128SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7129 std::vector<SDNode*> Built; 7130 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7131 7132 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7133 ii != ee; ++ii) 7134 AddToWorkList(*ii); 7135 return S; 7136} 7137 7138/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7139/// return a DAG expression to select that will generate the same value by 7140/// multiplying by a magic number. See: 7141/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7142SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7143 std::vector<SDNode*> Built; 7144 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7145 7146 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7147 ii != ee; ++ii) 7148 AddToWorkList(*ii); 7149 return S; 7150} 7151 7152/// FindBaseOffset - Return true if base is a frame index, which is known not 7153// to alias with anything but itself. Provides base object and offset as 7154// results. 7155static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7156 const GlobalValue *&GV, void *&CV) { 7157 // Assume it is a primitive operation. 7158 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7159 7160 // If it's an adding a simple constant then integrate the offset. 7161 if (Base.getOpcode() == ISD::ADD) { 7162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7163 Base = Base.getOperand(0); 7164 Offset += C->getZExtValue(); 7165 } 7166 } 7167 7168 // Return the underlying GlobalValue, and update the Offset. Return false 7169 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7170 // by multiple nodes with different offsets. 7171 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7172 GV = G->getGlobal(); 7173 Offset += G->getOffset(); 7174 return false; 7175 } 7176 7177 // Return the underlying Constant value, and update the Offset. Return false 7178 // for ConstantSDNodes since the same constant pool entry may be represented 7179 // by multiple nodes with different offsets. 7180 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7181 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7182 : (void *)C->getConstVal(); 7183 Offset += C->getOffset(); 7184 return false; 7185 } 7186 // If it's any of the following then it can't alias with anything but itself. 7187 return isa<FrameIndexSDNode>(Base); 7188} 7189 7190/// isAlias - Return true if there is any possibility that the two addresses 7191/// overlap. 7192bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7193 const Value *SrcValue1, int SrcValueOffset1, 7194 unsigned SrcValueAlign1, 7195 const MDNode *TBAAInfo1, 7196 SDValue Ptr2, int64_t Size2, 7197 const Value *SrcValue2, int SrcValueOffset2, 7198 unsigned SrcValueAlign2, 7199 const MDNode *TBAAInfo2) const { 7200 // If they are the same then they must be aliases. 7201 if (Ptr1 == Ptr2) return true; 7202 7203 // Gather base node and offset information. 7204 SDValue Base1, Base2; 7205 int64_t Offset1, Offset2; 7206 const GlobalValue *GV1, *GV2; 7207 void *CV1, *CV2; 7208 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7209 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7210 7211 // If they have a same base address then check to see if they overlap. 7212 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7213 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7214 7215 // It is possible for different frame indices to alias each other, mostly 7216 // when tail call optimization reuses return address slots for arguments. 7217 // To catch this case, look up the actual index of frame indices to compute 7218 // the real alias relationship. 7219 if (isFrameIndex1 && isFrameIndex2) { 7220 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7221 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7222 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7223 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7224 } 7225 7226 // Otherwise, if we know what the bases are, and they aren't identical, then 7227 // we know they cannot alias. 7228 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7229 return false; 7230 7231 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7232 // compared to the size and offset of the access, we may be able to prove they 7233 // do not alias. This check is conservative for now to catch cases created by 7234 // splitting vector types. 7235 if ((SrcValueAlign1 == SrcValueAlign2) && 7236 (SrcValueOffset1 != SrcValueOffset2) && 7237 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7238 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7239 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7240 7241 // There is no overlap between these relatively aligned accesses of similar 7242 // size, return no alias. 7243 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7244 return false; 7245 } 7246 7247 if (CombinerGlobalAA) { 7248 // Use alias analysis information. 7249 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7250 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7251 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7252 AliasAnalysis::AliasResult AAResult = 7253 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7254 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7255 if (AAResult == AliasAnalysis::NoAlias) 7256 return false; 7257 } 7258 7259 // Otherwise we have to assume they alias. 7260 return true; 7261} 7262 7263/// FindAliasInfo - Extracts the relevant alias information from the memory 7264/// node. Returns true if the operand was a load. 7265bool DAGCombiner::FindAliasInfo(SDNode *N, 7266 SDValue &Ptr, int64_t &Size, 7267 const Value *&SrcValue, 7268 int &SrcValueOffset, 7269 unsigned &SrcValueAlign, 7270 const MDNode *&TBAAInfo) const { 7271 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7272 Ptr = LD->getBasePtr(); 7273 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7274 SrcValue = LD->getSrcValue(); 7275 SrcValueOffset = LD->getSrcValueOffset(); 7276 SrcValueAlign = LD->getOriginalAlignment(); 7277 TBAAInfo = LD->getTBAAInfo(); 7278 return true; 7279 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7280 Ptr = ST->getBasePtr(); 7281 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7282 SrcValue = ST->getSrcValue(); 7283 SrcValueOffset = ST->getSrcValueOffset(); 7284 SrcValueAlign = ST->getOriginalAlignment(); 7285 TBAAInfo = ST->getTBAAInfo(); 7286 } else { 7287 llvm_unreachable("FindAliasInfo expected a memory operand"); 7288 } 7289 7290 return false; 7291} 7292 7293/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7294/// looking for aliasing nodes and adding them to the Aliases vector. 7295void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7296 SmallVector<SDValue, 8> &Aliases) { 7297 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7298 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7299 7300 // Get alias information for node. 7301 SDValue Ptr; 7302 int64_t Size; 7303 const Value *SrcValue; 7304 int SrcValueOffset; 7305 unsigned SrcValueAlign; 7306 const MDNode *SrcTBAAInfo; 7307 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7308 SrcValueAlign, SrcTBAAInfo); 7309 7310 // Starting off. 7311 Chains.push_back(OriginalChain); 7312 unsigned Depth = 0; 7313 7314 // Look at each chain and determine if it is an alias. If so, add it to the 7315 // aliases list. If not, then continue up the chain looking for the next 7316 // candidate. 7317 while (!Chains.empty()) { 7318 SDValue Chain = Chains.back(); 7319 Chains.pop_back(); 7320 7321 // For TokenFactor nodes, look at each operand and only continue up the 7322 // chain until we find two aliases. If we've seen two aliases, assume we'll 7323 // find more and revert to original chain since the xform is unlikely to be 7324 // profitable. 7325 // 7326 // FIXME: The depth check could be made to return the last non-aliasing 7327 // chain we found before we hit a tokenfactor rather than the original 7328 // chain. 7329 if (Depth > 6 || Aliases.size() == 2) { 7330 Aliases.clear(); 7331 Aliases.push_back(OriginalChain); 7332 break; 7333 } 7334 7335 // Don't bother if we've been before. 7336 if (!Visited.insert(Chain.getNode())) 7337 continue; 7338 7339 switch (Chain.getOpcode()) { 7340 case ISD::EntryToken: 7341 // Entry token is ideal chain operand, but handled in FindBetterChain. 7342 break; 7343 7344 case ISD::LOAD: 7345 case ISD::STORE: { 7346 // Get alias information for Chain. 7347 SDValue OpPtr; 7348 int64_t OpSize; 7349 const Value *OpSrcValue; 7350 int OpSrcValueOffset; 7351 unsigned OpSrcValueAlign; 7352 const MDNode *OpSrcTBAAInfo; 7353 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7354 OpSrcValue, OpSrcValueOffset, 7355 OpSrcValueAlign, 7356 OpSrcTBAAInfo); 7357 7358 // If chain is alias then stop here. 7359 if (!(IsLoad && IsOpLoad) && 7360 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7361 SrcTBAAInfo, 7362 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7363 OpSrcValueAlign, OpSrcTBAAInfo)) { 7364 Aliases.push_back(Chain); 7365 } else { 7366 // Look further up the chain. 7367 Chains.push_back(Chain.getOperand(0)); 7368 ++Depth; 7369 } 7370 break; 7371 } 7372 7373 case ISD::TokenFactor: 7374 // We have to check each of the operands of the token factor for "small" 7375 // token factors, so we queue them up. Adding the operands to the queue 7376 // (stack) in reverse order maintains the original order and increases the 7377 // likelihood that getNode will find a matching token factor (CSE.) 7378 if (Chain.getNumOperands() > 16) { 7379 Aliases.push_back(Chain); 7380 break; 7381 } 7382 for (unsigned n = Chain.getNumOperands(); n;) 7383 Chains.push_back(Chain.getOperand(--n)); 7384 ++Depth; 7385 break; 7386 7387 default: 7388 // For all other instructions we will just have to take what we can get. 7389 Aliases.push_back(Chain); 7390 break; 7391 } 7392 } 7393} 7394 7395/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7396/// for a better chain (aliasing node.) 7397SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7398 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7399 7400 // Accumulate all the aliases to this node. 7401 GatherAllAliases(N, OldChain, Aliases); 7402 7403 if (Aliases.size() == 0) { 7404 // If no operands then chain to entry token. 7405 return DAG.getEntryNode(); 7406 } else if (Aliases.size() == 1) { 7407 // If a single operand then chain to it. We don't need to revisit it. 7408 return Aliases[0]; 7409 } 7410 7411 // Construct a custom tailored token factor. 7412 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7413 &Aliases[0], Aliases.size()); 7414} 7415 7416// SelectionDAG::Combine - This is the entry point for the file. 7417// 7418void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7419 CodeGenOpt::Level OptLevel) { 7420 /// run - This is the main entry point to this class. 7421 /// 7422 DAGCombiner(*this, AA, OptLevel).Run(Level); 7423} 7424