DAGCombiner.cpp revision f3cbca279db891403659208a99f8e1cceb8c9ea6
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.getNode() == 0 - No change was made 129 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 194 SDValue XformToShuffleWithZero(SDNode *N); 195 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 196 197 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 198 199 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 200 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 201 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 202 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 203 SDValue N3, ISD::CondCode CC, 204 bool NotExtCompare = false); 205 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 206 ISD::CondCode Cond, bool foldBooleans = true); 207 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 208 unsigned HiOp); 209 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 210 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 211 SDValue BuildSDIV(SDNode *N); 212 SDValue BuildUDIV(SDNode *N); 213 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 214 SDValue ReduceLoadWidth(SDNode *N); 215 216 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 217 218 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 219 /// looking for aliasing nodes and adding them to the Aliases vector. 220 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 221 SmallVector<SDValue, 8> &Aliases); 222 223 /// isAlias - Return true if there is any possibility that the two addresses 224 /// overlap. 225 bool isAlias(SDValue Ptr1, int64_t Size1, 226 const Value *SrcValue1, int SrcValueOffset1, 227 SDValue Ptr2, int64_t Size2, 228 const Value *SrcValue2, int SrcValueOffset2); 229 230 /// FindAliasInfo - Extracts the relevant alias information from the memory 231 /// node. Returns true if the operand was a load. 232 bool FindAliasInfo(SDNode *N, 233 SDValue &Ptr, int64_t &Size, 234 const Value *&SrcValue, int &SrcValueOffset); 235 236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 237 /// looking for a better chain (aliasing node.) 238 SDValue FindBetterChain(SDNode *N, SDValue Chain); 239 240public: 241 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 242 : DAG(D), 243 TLI(D.getTargetLoweringInfo()), 244 AfterLegalize(false), 245 Fast(fast), 246 AA(A) {} 247 248 /// Run - runs the dag combiner on all nodes in the work list 249 void Run(bool RunningAfterLegalize); 250 }; 251} 252 253 254namespace { 255/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 256/// nodes from the worklist. 257class VISIBILITY_HIDDEN WorkListRemover : 258 public SelectionDAG::DAGUpdateListener { 259 DAGCombiner &DC; 260public: 261 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 262 263 virtual void NodeDeleted(SDNode *N, SDNode *E) { 264 DC.removeFromWorkList(N); 265 } 266 267 virtual void NodeUpdated(SDNode *N) { 268 // Ignore updates. 269 } 270}; 271} 272 273//===----------------------------------------------------------------------===// 274// TargetLowering::DAGCombinerInfo implementation 275//===----------------------------------------------------------------------===// 276 277void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 278 ((DAGCombiner*)DC)->AddToWorkList(N); 279} 280 281SDValue TargetLowering::DAGCombinerInfo:: 282CombineTo(SDNode *N, const std::vector<SDValue> &To) { 283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 284} 285 286SDValue TargetLowering::DAGCombinerInfo:: 287CombineTo(SDNode *N, SDValue Res) { 288 return ((DAGCombiner*)DC)->CombineTo(N, Res); 289} 290 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 295} 296 297 298//===----------------------------------------------------------------------===// 299// Helper Functions 300//===----------------------------------------------------------------------===// 301 302/// isNegatibleForFree - Return 1 if we can compute the negated form of the 303/// specified expression for the same cost as the expression itself, or 2 if we 304/// can compute the negated form more cheaply than the expression itself. 305static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 306 unsigned Depth = 0) { 307 // No compile time optimizations on this type. 308 if (Op.getValueType() == MVT::ppcf128) 309 return 0; 310 311 // fneg is removable even if it has multiple uses. 312 if (Op.getOpcode() == ISD::FNEG) return 2; 313 314 // Don't allow anything with multiple uses. 315 if (!Op.hasOneUse()) return 0; 316 317 // Don't recurse exponentially. 318 if (Depth > 6) return 0; 319 320 switch (Op.getOpcode()) { 321 default: return false; 322 case ISD::ConstantFP: 323 // Don't invert constant FP values after legalize. The negated constant 324 // isn't necessarily legal. 325 return AfterLegalize ? 0 : 1; 326 case ISD::FADD: 327 // FIXME: determine better conditions for this xform. 328 if (!UnsafeFPMath) return 0; 329 330 // -(A+B) -> -A - B 331 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 332 return V; 333 // -(A+B) -> -B - A 334 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 335 case ISD::FSUB: 336 // We can't turn -(A-B) into B-A when we honor signed zeros. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A-B) -> B-A 340 return 1; 341 342 case ISD::FMUL: 343 case ISD::FDIV: 344 if (HonorSignDependentRoundingFPMath()) return 0; 345 346 // -(X*Y) -> (-X * Y) or (X*-Y) 347 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 348 return V; 349 350 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 351 352 case ISD::FP_EXTEND: 353 case ISD::FP_ROUND: 354 case ISD::FSIN: 355 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 356 } 357} 358 359/// GetNegatedExpression - If isNegatibleForFree returns true, this function 360/// returns the newly negated expression. 361static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 362 bool AfterLegalize, unsigned Depth = 0) { 363 // fneg is removable even if it has multiple uses. 364 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 365 366 // Don't allow anything with multiple uses. 367 assert(Op.hasOneUse() && "Unknown reuse!"); 368 369 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 370 switch (Op.getOpcode()) { 371 default: assert(0 && "Unknown code"); 372 case ISD::ConstantFP: { 373 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 374 V.changeSign(); 375 return DAG.getConstantFP(V, Op.getValueType()); 376 } 377 case ISD::FADD: 378 // FIXME: determine better conditions for this xform. 379 assert(UnsafeFPMath); 380 381 // -(A+B) -> -A - B 382 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 383 return DAG.getNode(ISD::FSUB, Op.getValueType(), 384 GetNegatedExpression(Op.getOperand(0), DAG, 385 AfterLegalize, Depth+1), 386 Op.getOperand(1)); 387 // -(A+B) -> -B - A 388 return DAG.getNode(ISD::FSUB, Op.getValueType(), 389 GetNegatedExpression(Op.getOperand(1), DAG, 390 AfterLegalize, Depth+1), 391 Op.getOperand(0)); 392 case ISD::FSUB: 393 // We can't turn -(A-B) into B-A when we honor signed zeros. 394 assert(UnsafeFPMath); 395 396 // -(0-B) -> B 397 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 398 if (N0CFP->getValueAPF().isZero()) 399 return Op.getOperand(1); 400 401 // -(A-B) -> B-A 402 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 403 Op.getOperand(0)); 404 405 case ISD::FMUL: 406 case ISD::FDIV: 407 assert(!HonorSignDependentRoundingFPMath()); 408 409 // -(X*Y) -> -X * Y 410 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 411 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 AfterLegalize, Depth+1), 414 Op.getOperand(1)); 415 416 // -(X*Y) -> X * -Y 417 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 418 Op.getOperand(0), 419 GetNegatedExpression(Op.getOperand(1), DAG, 420 AfterLegalize, Depth+1)); 421 422 case ISD::FP_EXTEND: 423 case ISD::FSIN: 424 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 AfterLegalize, Depth+1)); 427 case ISD::FP_ROUND: 428 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 AfterLegalize, Depth+1), 431 Op.getOperand(1)); 432 } 433} 434 435 436// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 437// that selects between the values 1 and 0, making it equivalent to a setcc. 438// Also, set the incoming LHS, RHS, and CC references to the appropriate 439// nodes based on the type of node we are checking. This simplifies life a 440// bit for the callers. 441static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 442 SDValue &CC) { 443 if (N.getOpcode() == ISD::SETCC) { 444 LHS = N.getOperand(0); 445 RHS = N.getOperand(1); 446 CC = N.getOperand(2); 447 return true; 448 } 449 if (N.getOpcode() == ISD::SELECT_CC && 450 N.getOperand(2).getOpcode() == ISD::Constant && 451 N.getOperand(3).getOpcode() == ISD::Constant && 452 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(4); 457 return true; 458 } 459 return false; 460} 461 462// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 463// one use. If this is true, it allows the users to invert the operation for 464// free when it is profitable to do so. 465static bool isOneUseSetCC(SDValue N) { 466 SDValue N0, N1, N2; 467 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 468 return true; 469 return false; 470} 471 472SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 473 MVT VT = N0.getValueType(); 474 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 475 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 476 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 477 if (isa<ConstantSDNode>(N1)) { 478 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 479 AddToWorkList(OpNode.getNode()); 480 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 481 } else if (N0.hasOneUse()) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 485 } 486 } 487 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 488 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 489 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 490 if (isa<ConstantSDNode>(N0)) { 491 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 492 AddToWorkList(OpNode.getNode()); 493 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 494 } else if (N1.hasOneUse()) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 498 } 499 } 500 return SDValue(); 501} 502 503SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 504 bool AddTo) { 505 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 506 ++NodesCombined; 507 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 508 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 509 DOUT << " and " << NumTo-1 << " other values\n"; 510 WorkListRemover DeadNodes(*this); 511 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 512 513 if (AddTo) { 514 // Push the new nodes and any users onto the worklist 515 for (unsigned i = 0, e = NumTo; i != e; ++i) { 516 AddToWorkList(To[i].getNode()); 517 AddUsersToWorkList(To[i].getNode()); 518 } 519 } 520 521 // Nodes can be reintroduced into the worklist. Make sure we do not 522 // process a node that has been replaced. 523 removeFromWorkList(N); 524 525 // Finally, since the node is now dead, remove it from the graph. 526 DAG.DeleteNode(N); 527 return SDValue(N, 0); 528} 529 530/// SimplifyDemandedBits - Check the specified integer node value to see if 531/// it can be simplified or if things it uses can be simplified by bit 532/// propagation. If so, return true. 533bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 534 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 535 APInt KnownZero, KnownOne; 536 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 537 return false; 538 539 // Revisit the node. 540 AddToWorkList(Op.getNode()); 541 542 // Replace the old value with the new one. 543 ++NodesCombined; 544 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 545 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 546 DOUT << '\n'; 547 548 // Replace all uses. If any nodes become isomorphic to other nodes and 549 // are deleted, make sure to remove them from our worklist. 550 WorkListRemover DeadNodes(*this); 551 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 552 553 // Push the new node and any (possibly new) users onto the worklist. 554 AddToWorkList(TLO.New.getNode()); 555 AddUsersToWorkList(TLO.New.getNode()); 556 557 // Finally, if the node is now dead, remove it from the graph. The node 558 // may not be dead if the replacement process recursively simplified to 559 // something else needing this node. 560 if (TLO.Old.getNode()->use_empty()) { 561 removeFromWorkList(TLO.Old.getNode()); 562 563 // If the operands of this node are only used by the node, they will now 564 // be dead. Make sure to visit them first to delete dead nodes early. 565 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 566 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 567 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 568 569 DAG.DeleteNode(TLO.Old.getNode()); 570 } 571 return true; 572} 573 574//===----------------------------------------------------------------------===// 575// Main DAG Combiner implementation 576//===----------------------------------------------------------------------===// 577 578void DAGCombiner::Run(bool RunningAfterLegalize) { 579 // set the instance variable, so that the various visit routines may use it. 580 AfterLegalize = RunningAfterLegalize; 581 582 // Add all the dag nodes to the worklist. 583 WorkList.reserve(DAG.allnodes_size()); 584 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 585 E = DAG.allnodes_end(); I != E; ++I) 586 WorkList.push_back(I); 587 588 // Create a dummy node (which is not added to allnodes), that adds a reference 589 // to the root node, preventing it from being deleted, and tracking any 590 // changes of the root. 591 HandleSDNode Dummy(DAG.getRoot()); 592 593 // The root of the dag may dangle to deleted nodes until the dag combiner is 594 // done. Set it to null to avoid confusion. 595 DAG.setRoot(SDValue()); 596 597 // while the worklist isn't empty, inspect the node on the end of it and 598 // try and combine it. 599 while (!WorkList.empty()) { 600 SDNode *N = WorkList.back(); 601 WorkList.pop_back(); 602 603 // If N has no uses, it is dead. Make sure to revisit all N's operands once 604 // N is deleted from the DAG, since they too may now be dead or may have a 605 // reduced number of uses, allowing other xforms. 606 if (N->use_empty() && N != &Dummy) { 607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 608 AddToWorkList(N->getOperand(i).getNode()); 609 610 DAG.DeleteNode(N); 611 continue; 612 } 613 614 SDValue RV = combine(N); 615 616 if (RV.getNode() == 0) 617 continue; 618 619 ++NodesCombined; 620 621 // If we get back the same node we passed in, rather than a new node or 622 // zero, we know that the node must have defined multiple values and 623 // CombineTo was used. Since CombineTo takes care of the worklist 624 // mechanics for us, we have no work to do in this case. 625 if (RV.getNode() == N) 626 continue; 627 628 assert(N->getOpcode() != ISD::DELETED_NODE && 629 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 630 "Node was deleted but visit returned new node!"); 631 632 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 633 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 634 DOUT << '\n'; 635 WorkListRemover DeadNodes(*this); 636 if (N->getNumValues() == RV.getNode()->getNumValues()) 637 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 638 else { 639 assert(N->getValueType(0) == RV.getValueType() && 640 N->getNumValues() == 1 && "Type mismatch"); 641 SDValue OpV = RV; 642 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 643 } 644 645 // Push the new node and any users onto the worklist 646 AddToWorkList(RV.getNode()); 647 AddUsersToWorkList(RV.getNode()); 648 649 // Add any uses of the old node to the worklist in case this node is the 650 // last one that uses them. They may become dead after this node is 651 // deleted. 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).getNode()); 654 655 // Nodes can be reintroduced into the worklist. Make sure we do not 656 // process a node that has been replaced. 657 removeFromWorkList(N); 658 659 // Finally, since the node is now dead, remove it from the graph. 660 DAG.DeleteNode(N); 661 } 662 663 // If the root changed (e.g. it was a dead load, update the root). 664 DAG.setRoot(Dummy.getValue()); 665} 666 667SDValue DAGCombiner::visit(SDNode *N) { 668 switch(N->getOpcode()) { 669 default: break; 670 case ISD::TokenFactor: return visitTokenFactor(N); 671 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 672 case ISD::ADD: return visitADD(N); 673 case ISD::SUB: return visitSUB(N); 674 case ISD::ADDC: return visitADDC(N); 675 case ISD::ADDE: return visitADDE(N); 676 case ISD::MUL: return visitMUL(N); 677 case ISD::SDIV: return visitSDIV(N); 678 case ISD::UDIV: return visitUDIV(N); 679 case ISD::SREM: return visitSREM(N); 680 case ISD::UREM: return visitUREM(N); 681 case ISD::MULHU: return visitMULHU(N); 682 case ISD::MULHS: return visitMULHS(N); 683 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 684 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 685 case ISD::SDIVREM: return visitSDIVREM(N); 686 case ISD::UDIVREM: return visitUDIVREM(N); 687 case ISD::AND: return visitAND(N); 688 case ISD::OR: return visitOR(N); 689 case ISD::XOR: return visitXOR(N); 690 case ISD::SHL: return visitSHL(N); 691 case ISD::SRA: return visitSRA(N); 692 case ISD::SRL: return visitSRL(N); 693 case ISD::CTLZ: return visitCTLZ(N); 694 case ISD::CTTZ: return visitCTTZ(N); 695 case ISD::CTPOP: return visitCTPOP(N); 696 case ISD::SELECT: return visitSELECT(N); 697 case ISD::SELECT_CC: return visitSELECT_CC(N); 698 case ISD::SETCC: return visitSETCC(N); 699 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 700 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 701 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 702 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 703 case ISD::TRUNCATE: return visitTRUNCATE(N); 704 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 705 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 706 case ISD::FADD: return visitFADD(N); 707 case ISD::FSUB: return visitFSUB(N); 708 case ISD::FMUL: return visitFMUL(N); 709 case ISD::FDIV: return visitFDIV(N); 710 case ISD::FREM: return visitFREM(N); 711 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 712 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 713 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 714 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 715 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 716 case ISD::FP_ROUND: return visitFP_ROUND(N); 717 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 718 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 719 case ISD::FNEG: return visitFNEG(N); 720 case ISD::FABS: return visitFABS(N); 721 case ISD::BRCOND: return visitBRCOND(N); 722 case ISD::BR_CC: return visitBR_CC(N); 723 case ISD::LOAD: return visitLOAD(N); 724 case ISD::STORE: return visitSTORE(N); 725 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 726 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 727 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 728 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 729 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 730 } 731 return SDValue(); 732} 733 734SDValue DAGCombiner::combine(SDNode *N) { 735 736 SDValue RV = visit(N); 737 738 // If nothing happened, try a target-specific DAG combine. 739 if (RV.getNode() == 0) { 740 assert(N->getOpcode() != ISD::DELETED_NODE && 741 "Node was deleted but visit returned NULL!"); 742 743 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 744 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 745 746 // Expose the DAG combiner to the target combiner impls. 747 TargetLowering::DAGCombinerInfo 748 DagCombineInfo(DAG, !AfterLegalize, false, this); 749 750 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 751 } 752 } 753 754 // If N is a commutative binary node, try commuting it to enable more 755 // sdisel CSE. 756 if (RV.getNode() == 0 && 757 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 758 N->getNumValues() == 1) { 759 SDValue N0 = N->getOperand(0); 760 SDValue N1 = N->getOperand(1); 761 // Constant operands are canonicalized to RHS. 762 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 763 SDValue Ops[] = { N1, N0 }; 764 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 765 Ops, 2); 766 if (CSENode) 767 return SDValue(CSENode, 0); 768 } 769 } 770 771 return RV; 772} 773 774/// getInputChainForNode - Given a node, return its input chain if it has one, 775/// otherwise return a null sd operand. 776static SDValue getInputChainForNode(SDNode *N) { 777 if (unsigned NumOps = N->getNumOperands()) { 778 if (N->getOperand(0).getValueType() == MVT::Other) 779 return N->getOperand(0); 780 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 781 return N->getOperand(NumOps-1); 782 for (unsigned i = 1; i < NumOps-1; ++i) 783 if (N->getOperand(i).getValueType() == MVT::Other) 784 return N->getOperand(i); 785 } 786 return SDValue(0, 0); 787} 788 789SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 790 // If N has two operands, where one has an input chain equal to the other, 791 // the 'other' chain is redundant. 792 if (N->getNumOperands() == 2) { 793 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 794 return N->getOperand(0); 795 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 796 return N->getOperand(1); 797 } 798 799 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 800 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 801 SmallPtrSet<SDNode*, 16> SeenOps; 802 bool Changed = false; // If we should replace this token factor. 803 804 // Start out with this token factor. 805 TFs.push_back(N); 806 807 // Iterate through token factors. The TFs grows when new token factors are 808 // encountered. 809 for (unsigned i = 0; i < TFs.size(); ++i) { 810 SDNode *TF = TFs[i]; 811 812 // Check each of the operands. 813 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 814 SDValue Op = TF->getOperand(i); 815 816 switch (Op.getOpcode()) { 817 case ISD::EntryToken: 818 // Entry tokens don't need to be added to the list. They are 819 // rededundant. 820 Changed = true; 821 break; 822 823 case ISD::TokenFactor: 824 if ((CombinerAA || Op.hasOneUse()) && 825 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 826 // Queue up for processing. 827 TFs.push_back(Op.getNode()); 828 // Clean up in case the token factor is removed. 829 AddToWorkList(Op.getNode()); 830 Changed = true; 831 break; 832 } 833 // Fall thru 834 835 default: 836 // Only add if it isn't already in the list. 837 if (SeenOps.insert(Op.getNode())) 838 Ops.push_back(Op); 839 else 840 Changed = true; 841 break; 842 } 843 } 844 } 845 846 SDValue Result; 847 848 // If we've change things around then replace token factor. 849 if (Changed) { 850 if (Ops.empty()) { 851 // The entry token is the only possible outcome. 852 Result = DAG.getEntryNode(); 853 } else { 854 // New and improved token factor. 855 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 856 } 857 858 // Don't add users to work list. 859 return CombineTo(N, Result, false); 860 } 861 862 return Result; 863} 864 865/// MERGE_VALUES can always be eliminated. 866SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 867 WorkListRemover DeadNodes(*this); 868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 869 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 870 &DeadNodes); 871 removeFromWorkList(N); 872 DAG.DeleteNode(N); 873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 874} 875 876 877static 878SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 879 MVT VT = N0.getValueType(); 880 SDValue N00 = N0.getOperand(0); 881 SDValue N01 = N0.getOperand(1); 882 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 883 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 884 isa<ConstantSDNode>(N00.getOperand(1))) { 885 N0 = DAG.getNode(ISD::ADD, VT, 886 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 887 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 888 return DAG.getNode(ISD::ADD, VT, N0, N1); 889 } 890 return SDValue(); 891} 892 893static 894SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 895 SelectionDAG &DAG) { 896 MVT VT = N->getValueType(0); 897 unsigned Opc = N->getOpcode(); 898 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 899 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 900 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 901 ISD::CondCode CC = ISD::SETCC_INVALID; 902 if (isSlctCC) 903 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 904 else { 905 SDValue CCOp = Slct.getOperand(0); 906 if (CCOp.getOpcode() == ISD::SETCC) 907 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 908 } 909 910 bool DoXform = false; 911 bool InvCC = false; 912 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 913 "Bad input!"); 914 if (LHS.getOpcode() == ISD::Constant && 915 cast<ConstantSDNode>(LHS)->isNullValue()) 916 DoXform = true; 917 else if (CC != ISD::SETCC_INVALID && 918 RHS.getOpcode() == ISD::Constant && 919 cast<ConstantSDNode>(RHS)->isNullValue()) { 920 std::swap(LHS, RHS); 921 SDValue Op0 = Slct.getOperand(0); 922 bool isInt = (isSlctCC ? Op0.getValueType() : 923 Op0.getOperand(0).getValueType()).isInteger(); 924 CC = ISD::getSetCCInverse(CC, isInt); 925 DoXform = true; 926 InvCC = true; 927 } 928 929 if (DoXform) { 930 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 931 if (isSlctCC) 932 return DAG.getSelectCC(OtherOp, Result, 933 Slct.getOperand(0), Slct.getOperand(1), CC); 934 SDValue CCOp = Slct.getOperand(0); 935 if (InvCC) 936 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 937 CCOp.getOperand(1), CC); 938 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 939 } 940 return SDValue(); 941} 942 943SDValue DAGCombiner::visitADD(SDNode *N) { 944 SDValue N0 = N->getOperand(0); 945 SDValue N1 = N->getOperand(1); 946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 948 MVT VT = N0.getValueType(); 949 950 // fold vector ops 951 if (VT.isVector()) { 952 SDValue FoldedVOp = SimplifyVBinOp(N); 953 if (FoldedVOp.getNode()) return FoldedVOp; 954 } 955 956 // fold (add x, undef) -> undef 957 if (N0.getOpcode() == ISD::UNDEF) 958 return N0; 959 if (N1.getOpcode() == ISD::UNDEF) 960 return N1; 961 // fold (add c1, c2) -> c1+c2 962 if (N0C && N1C) 963 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 964 // canonicalize constant to RHS 965 if (N0C && !N1C) 966 return DAG.getNode(ISD::ADD, VT, N1, N0); 967 // fold (add x, 0) -> x 968 if (N1C && N1C->isNullValue()) 969 return N0; 970 // fold ((c1-A)+c2) -> (c1+c2)-A 971 if (N1C && N0.getOpcode() == ISD::SUB) 972 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 973 return DAG.getNode(ISD::SUB, VT, 974 DAG.getConstant(N1C->getAPIntValue()+ 975 N0C->getAPIntValue(), VT), 976 N0.getOperand(1)); 977 // reassociate add 978 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 979 if (RADD.getNode() != 0) 980 return RADD; 981 // fold ((0-A) + B) -> B-A 982 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 983 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 984 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 985 // fold (A + (0-B)) -> A-B 986 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 987 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 988 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 989 // fold (A+(B-A)) -> B 990 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 991 return N1.getOperand(0); 992 993 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 994 return SDValue(N, 0); 995 996 // fold (a+b) -> (a|b) iff a and b share no bits. 997 if (VT.isInteger() && !VT.isVector()) { 998 APInt LHSZero, LHSOne; 999 APInt RHSZero, RHSOne; 1000 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1001 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1002 if (LHSZero.getBoolValue()) { 1003 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1004 1005 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1006 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1007 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1008 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1009 return DAG.getNode(ISD::OR, VT, N0, N1); 1010 } 1011 } 1012 1013 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1014 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1015 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1016 if (Result.getNode()) return Result; 1017 } 1018 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1019 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1020 if (Result.getNode()) return Result; 1021 } 1022 1023 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1024 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1025 SDValue Result = combineSelectAndUse(N, N0, N1, DAG); 1026 if (Result.getNode()) return Result; 1027 } 1028 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1029 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1030 if (Result.getNode()) return Result; 1031 } 1032 1033 return SDValue(); 1034} 1035 1036SDValue DAGCombiner::visitADDC(SDNode *N) { 1037 SDValue N0 = N->getOperand(0); 1038 SDValue N1 = N->getOperand(1); 1039 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1040 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1041 MVT VT = N0.getValueType(); 1042 1043 // If the flag result is dead, turn this into an ADD. 1044 if (N->hasNUsesOfValue(0, 1)) 1045 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1046 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1047 1048 // canonicalize constant to RHS. 1049 if (N0C && !N1C) 1050 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1051 1052 // fold (addc x, 0) -> x + no carry out 1053 if (N1C && N1C->isNullValue()) 1054 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1055 1056 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1057 APInt LHSZero, LHSOne; 1058 APInt RHSZero, RHSOne; 1059 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1060 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1061 if (LHSZero.getBoolValue()) { 1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1063 1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1068 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1069 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1070 } 1071 1072 return SDValue(); 1073} 1074 1075SDValue DAGCombiner::visitADDE(SDNode *N) { 1076 SDValue N0 = N->getOperand(0); 1077 SDValue N1 = N->getOperand(1); 1078 SDValue CarryIn = N->getOperand(2); 1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1081 //MVT VT = N0.getValueType(); 1082 1083 // canonicalize constant to RHS 1084 if (N0C && !N1C) 1085 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1086 1087 // fold (adde x, y, false) -> (addc x, y) 1088 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1089 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1090 1091 return SDValue(); 1092} 1093 1094 1095 1096SDValue DAGCombiner::visitSUB(SDNode *N) { 1097 SDValue N0 = N->getOperand(0); 1098 SDValue N1 = N->getOperand(1); 1099 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1101 MVT VT = N0.getValueType(); 1102 1103 // fold vector ops 1104 if (VT.isVector()) { 1105 SDValue FoldedVOp = SimplifyVBinOp(N); 1106 if (FoldedVOp.getNode()) return FoldedVOp; 1107 } 1108 1109 // fold (sub x, x) -> 0 1110 if (N0 == N1) 1111 return DAG.getConstant(0, N->getValueType(0)); 1112 // fold (sub c1, c2) -> c1-c2 1113 if (N0C && N1C) 1114 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1115 // fold (sub x, c) -> (add x, -c) 1116 if (N1C) 1117 return DAG.getNode(ISD::ADD, VT, N0, 1118 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1119 // fold (A+B)-A -> B 1120 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1121 return N0.getOperand(1); 1122 // fold (A+B)-B -> A 1123 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1124 return N0.getOperand(0); 1125 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1126 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1127 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1128 if (Result.getNode()) return Result; 1129 } 1130 // If either operand of a sub is undef, the result is undef 1131 if (N0.getOpcode() == ISD::UNDEF) 1132 return N0; 1133 if (N1.getOpcode() == ISD::UNDEF) 1134 return N1; 1135 1136 return SDValue(); 1137} 1138 1139SDValue DAGCombiner::visitMUL(SDNode *N) { 1140 SDValue N0 = N->getOperand(0); 1141 SDValue N1 = N->getOperand(1); 1142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1144 MVT VT = N0.getValueType(); 1145 1146 // fold vector ops 1147 if (VT.isVector()) { 1148 SDValue FoldedVOp = SimplifyVBinOp(N); 1149 if (FoldedVOp.getNode()) return FoldedVOp; 1150 } 1151 1152 // fold (mul x, undef) -> 0 1153 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1154 return DAG.getConstant(0, VT); 1155 // fold (mul c1, c2) -> c1*c2 1156 if (N0C && N1C) 1157 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1158 // canonicalize constant to RHS 1159 if (N0C && !N1C) 1160 return DAG.getNode(ISD::MUL, VT, N1, N0); 1161 // fold (mul x, 0) -> 0 1162 if (N1C && N1C->isNullValue()) 1163 return N1; 1164 // fold (mul x, -1) -> 0-x 1165 if (N1C && N1C->isAllOnesValue()) 1166 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1167 // fold (mul x, (1 << c)) -> x << c 1168 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1169 return DAG.getNode(ISD::SHL, VT, N0, 1170 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1171 TLI.getShiftAmountTy())); 1172 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1173 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1174 // FIXME: If the input is something that is easily negated (e.g. a 1175 // single-use add), we should put the negate there. 1176 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1177 DAG.getNode(ISD::SHL, VT, N0, 1178 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1179 TLI.getShiftAmountTy()))); 1180 } 1181 1182 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1183 if (N1C && N0.getOpcode() == ISD::SHL && 1184 isa<ConstantSDNode>(N0.getOperand(1))) { 1185 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1186 AddToWorkList(C3.getNode()); 1187 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1188 } 1189 1190 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1191 // use. 1192 { 1193 SDValue Sh(0,0), Y(0,0); 1194 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1195 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1196 N0.getNode()->hasOneUse()) { 1197 Sh = N0; Y = N1; 1198 } else if (N1.getOpcode() == ISD::SHL && 1199 isa<ConstantSDNode>(N1.getOperand(1)) && 1200 N1.getNode()->hasOneUse()) { 1201 Sh = N1; Y = N0; 1202 } 1203 if (Sh.getNode()) { 1204 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1205 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1206 } 1207 } 1208 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1209 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1210 isa<ConstantSDNode>(N0.getOperand(1))) { 1211 return DAG.getNode(ISD::ADD, VT, 1212 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1213 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1214 } 1215 1216 // reassociate mul 1217 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1218 if (RMUL.getNode() != 0) 1219 return RMUL; 1220 1221 return SDValue(); 1222} 1223 1224SDValue DAGCombiner::visitSDIV(SDNode *N) { 1225 SDValue N0 = N->getOperand(0); 1226 SDValue N1 = N->getOperand(1); 1227 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1229 MVT VT = N->getValueType(0); 1230 1231 // fold vector ops 1232 if (VT.isVector()) { 1233 SDValue FoldedVOp = SimplifyVBinOp(N); 1234 if (FoldedVOp.getNode()) return FoldedVOp; 1235 } 1236 1237 // fold (sdiv c1, c2) -> c1/c2 1238 if (N0C && N1C && !N1C->isNullValue()) 1239 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1240 // fold (sdiv X, 1) -> X 1241 if (N1C && N1C->getSignExtended() == 1LL) 1242 return N0; 1243 // fold (sdiv X, -1) -> 0-X 1244 if (N1C && N1C->isAllOnesValue()) 1245 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1246 // If we know the sign bits of both operands are zero, strength reduce to a 1247 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1248 if (!VT.isVector()) { 1249 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1250 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1251 } 1252 // fold (sdiv X, pow2) -> simple ops after legalize 1253 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1254 (isPowerOf2_64(N1C->getSignExtended()) || 1255 isPowerOf2_64(-N1C->getSignExtended()))) { 1256 // If dividing by powers of two is cheap, then don't perform the following 1257 // fold. 1258 if (TLI.isPow2DivCheap()) 1259 return SDValue(); 1260 int64_t pow2 = N1C->getSignExtended(); 1261 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1262 unsigned lg2 = Log2_64(abs2); 1263 // Splat the sign bit into the register 1264 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1265 DAG.getConstant(VT.getSizeInBits()-1, 1266 TLI.getShiftAmountTy())); 1267 AddToWorkList(SGN.getNode()); 1268 // Add (N0 < 0) ? abs2 - 1 : 0; 1269 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1270 DAG.getConstant(VT.getSizeInBits()-lg2, 1271 TLI.getShiftAmountTy())); 1272 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1273 AddToWorkList(SRL.getNode()); 1274 AddToWorkList(ADD.getNode()); // Divide by pow2 1275 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1276 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1277 // If we're dividing by a positive value, we're done. Otherwise, we must 1278 // negate the result. 1279 if (pow2 > 0) 1280 return SRA; 1281 AddToWorkList(SRA.getNode()); 1282 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1283 } 1284 // if integer divide is expensive and we satisfy the requirements, emit an 1285 // alternate sequence. 1286 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1287 !TLI.isIntDivCheap()) { 1288 SDValue Op = BuildSDIV(N); 1289 if (Op.getNode()) return Op; 1290 } 1291 1292 // undef / X -> 0 1293 if (N0.getOpcode() == ISD::UNDEF) 1294 return DAG.getConstant(0, VT); 1295 // X / undef -> undef 1296 if (N1.getOpcode() == ISD::UNDEF) 1297 return N1; 1298 1299 return SDValue(); 1300} 1301 1302SDValue DAGCombiner::visitUDIV(SDNode *N) { 1303 SDValue N0 = N->getOperand(0); 1304 SDValue N1 = N->getOperand(1); 1305 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1306 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1307 MVT VT = N->getValueType(0); 1308 1309 // fold vector ops 1310 if (VT.isVector()) { 1311 SDValue FoldedVOp = SimplifyVBinOp(N); 1312 if (FoldedVOp.getNode()) return FoldedVOp; 1313 } 1314 1315 // fold (udiv c1, c2) -> c1/c2 1316 if (N0C && N1C && !N1C->isNullValue()) 1317 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1318 // fold (udiv x, (1 << c)) -> x >>u c 1319 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1320 return DAG.getNode(ISD::SRL, VT, N0, 1321 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1322 TLI.getShiftAmountTy())); 1323 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1324 if (N1.getOpcode() == ISD::SHL) { 1325 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1326 if (SHC->getAPIntValue().isPowerOf2()) { 1327 MVT ADDVT = N1.getOperand(1).getValueType(); 1328 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1329 DAG.getConstant(SHC->getAPIntValue() 1330 .logBase2(), 1331 ADDVT)); 1332 AddToWorkList(Add.getNode()); 1333 return DAG.getNode(ISD::SRL, VT, N0, Add); 1334 } 1335 } 1336 } 1337 // fold (udiv x, c) -> alternate 1338 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1339 SDValue Op = BuildUDIV(N); 1340 if (Op.getNode()) return Op; 1341 } 1342 1343 // undef / X -> 0 1344 if (N0.getOpcode() == ISD::UNDEF) 1345 return DAG.getConstant(0, VT); 1346 // X / undef -> undef 1347 if (N1.getOpcode() == ISD::UNDEF) 1348 return N1; 1349 1350 return SDValue(); 1351} 1352 1353SDValue DAGCombiner::visitSREM(SDNode *N) { 1354 SDValue N0 = N->getOperand(0); 1355 SDValue N1 = N->getOperand(1); 1356 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1357 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1358 MVT VT = N->getValueType(0); 1359 1360 // fold (srem c1, c2) -> c1%c2 1361 if (N0C && N1C && !N1C->isNullValue()) 1362 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1363 // If we know the sign bits of both operands are zero, strength reduce to a 1364 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1365 if (!VT.isVector()) { 1366 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1367 return DAG.getNode(ISD::UREM, VT, N0, N1); 1368 } 1369 1370 // If X/C can be simplified by the division-by-constant logic, lower 1371 // X%C to the equivalent of X-X/C*C. 1372 if (N1C && !N1C->isNullValue()) { 1373 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1374 AddToWorkList(Div.getNode()); 1375 SDValue OptimizedDiv = combine(Div.getNode()); 1376 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1377 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1378 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1379 AddToWorkList(Mul.getNode()); 1380 return Sub; 1381 } 1382 } 1383 1384 // undef % X -> 0 1385 if (N0.getOpcode() == ISD::UNDEF) 1386 return DAG.getConstant(0, VT); 1387 // X % undef -> undef 1388 if (N1.getOpcode() == ISD::UNDEF) 1389 return N1; 1390 1391 return SDValue(); 1392} 1393 1394SDValue DAGCombiner::visitUREM(SDNode *N) { 1395 SDValue N0 = N->getOperand(0); 1396 SDValue N1 = N->getOperand(1); 1397 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1398 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1399 MVT VT = N->getValueType(0); 1400 1401 // fold (urem c1, c2) -> c1%c2 1402 if (N0C && N1C && !N1C->isNullValue()) 1403 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1404 // fold (urem x, pow2) -> (and x, pow2-1) 1405 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1406 return DAG.getNode(ISD::AND, VT, N0, 1407 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1408 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1409 if (N1.getOpcode() == ISD::SHL) { 1410 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1411 if (SHC->getAPIntValue().isPowerOf2()) { 1412 SDValue Add = 1413 DAG.getNode(ISD::ADD, VT, N1, 1414 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1415 VT)); 1416 AddToWorkList(Add.getNode()); 1417 return DAG.getNode(ISD::AND, VT, N0, Add); 1418 } 1419 } 1420 } 1421 1422 // If X/C can be simplified by the division-by-constant logic, lower 1423 // X%C to the equivalent of X-X/C*C. 1424 if (N1C && !N1C->isNullValue()) { 1425 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1426 AddToWorkList(Div.getNode()); 1427 SDValue OptimizedDiv = combine(Div.getNode()); 1428 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1429 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1430 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1431 AddToWorkList(Mul.getNode()); 1432 return Sub; 1433 } 1434 } 1435 1436 // undef % X -> 0 1437 if (N0.getOpcode() == ISD::UNDEF) 1438 return DAG.getConstant(0, VT); 1439 // X % undef -> undef 1440 if (N1.getOpcode() == ISD::UNDEF) 1441 return N1; 1442 1443 return SDValue(); 1444} 1445 1446SDValue DAGCombiner::visitMULHS(SDNode *N) { 1447 SDValue N0 = N->getOperand(0); 1448 SDValue N1 = N->getOperand(1); 1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450 MVT VT = N->getValueType(0); 1451 1452 // fold (mulhs x, 0) -> 0 1453 if (N1C && N1C->isNullValue()) 1454 return N1; 1455 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1456 if (N1C && N1C->getAPIntValue() == 1) 1457 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1458 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1459 TLI.getShiftAmountTy())); 1460 // fold (mulhs x, undef) -> 0 1461 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1462 return DAG.getConstant(0, VT); 1463 1464 return SDValue(); 1465} 1466 1467SDValue DAGCombiner::visitMULHU(SDNode *N) { 1468 SDValue N0 = N->getOperand(0); 1469 SDValue N1 = N->getOperand(1); 1470 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1471 MVT VT = N->getValueType(0); 1472 1473 // fold (mulhu x, 0) -> 0 1474 if (N1C && N1C->isNullValue()) 1475 return N1; 1476 // fold (mulhu x, 1) -> 0 1477 if (N1C && N1C->getAPIntValue() == 1) 1478 return DAG.getConstant(0, N0.getValueType()); 1479 // fold (mulhu x, undef) -> 0 1480 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1481 return DAG.getConstant(0, VT); 1482 1483 return SDValue(); 1484} 1485 1486/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1487/// compute two values. LoOp and HiOp give the opcodes for the two computations 1488/// that are being performed. Return true if a simplification was made. 1489/// 1490SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1491 unsigned HiOp) { 1492 // If the high half is not needed, just compute the low half. 1493 bool HiExists = N->hasAnyUseOfValue(1); 1494 if (!HiExists && 1495 (!AfterLegalize || 1496 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1497 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1498 N->getNumOperands()); 1499 return CombineTo(N, Res, Res); 1500 } 1501 1502 // If the low half is not needed, just compute the high half. 1503 bool LoExists = N->hasAnyUseOfValue(0); 1504 if (!LoExists && 1505 (!AfterLegalize || 1506 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1507 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1508 N->getNumOperands()); 1509 return CombineTo(N, Res, Res); 1510 } 1511 1512 // If both halves are used, return as it is. 1513 if (LoExists && HiExists) 1514 return SDValue(); 1515 1516 // If the two computed results can be simplified separately, separate them. 1517 if (LoExists) { 1518 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1519 N->op_begin(), N->getNumOperands()); 1520 AddToWorkList(Lo.getNode()); 1521 SDValue LoOpt = combine(Lo.getNode()); 1522 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1523 (!AfterLegalize || 1524 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1525 return CombineTo(N, LoOpt, LoOpt); 1526 } 1527 1528 if (HiExists) { 1529 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1530 N->op_begin(), N->getNumOperands()); 1531 AddToWorkList(Hi.getNode()); 1532 SDValue HiOpt = combine(Hi.getNode()); 1533 if (HiOpt.getNode() && HiOpt != Hi && 1534 (!AfterLegalize || 1535 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1536 return CombineTo(N, HiOpt, HiOpt); 1537 } 1538 return SDValue(); 1539} 1540 1541SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1542 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1543 if (Res.getNode()) return Res; 1544 1545 return SDValue(); 1546} 1547 1548SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1549 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1550 if (Res.getNode()) return Res; 1551 1552 return SDValue(); 1553} 1554 1555SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1556 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1557 if (Res.getNode()) return Res; 1558 1559 return SDValue(); 1560} 1561 1562SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1563 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1564 if (Res.getNode()) return Res; 1565 1566 return SDValue(); 1567} 1568 1569/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1570/// two operands of the same opcode, try to simplify it. 1571SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1572 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1573 MVT VT = N0.getValueType(); 1574 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1575 1576 // For each of OP in AND/OR/XOR: 1577 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1578 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1579 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1580 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1581 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1582 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1583 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1584 SDValue ORNode = DAG.getNode(N->getOpcode(), 1585 N0.getOperand(0).getValueType(), 1586 N0.getOperand(0), N1.getOperand(0)); 1587 AddToWorkList(ORNode.getNode()); 1588 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1589 } 1590 1591 // For each of OP in SHL/SRL/SRA/AND... 1592 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1593 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1594 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1595 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1596 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1597 N0.getOperand(1) == N1.getOperand(1)) { 1598 SDValue ORNode = DAG.getNode(N->getOpcode(), 1599 N0.getOperand(0).getValueType(), 1600 N0.getOperand(0), N1.getOperand(0)); 1601 AddToWorkList(ORNode.getNode()); 1602 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1603 } 1604 1605 return SDValue(); 1606} 1607 1608SDValue DAGCombiner::visitAND(SDNode *N) { 1609 SDValue N0 = N->getOperand(0); 1610 SDValue N1 = N->getOperand(1); 1611 SDValue LL, LR, RL, RR, CC0, CC1; 1612 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1614 MVT VT = N1.getValueType(); 1615 unsigned BitWidth = VT.getSizeInBits(); 1616 1617 // fold vector ops 1618 if (VT.isVector()) { 1619 SDValue FoldedVOp = SimplifyVBinOp(N); 1620 if (FoldedVOp.getNode()) return FoldedVOp; 1621 } 1622 1623 // fold (and x, undef) -> 0 1624 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1625 return DAG.getConstant(0, VT); 1626 // fold (and c1, c2) -> c1&c2 1627 if (N0C && N1C) 1628 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1629 // canonicalize constant to RHS 1630 if (N0C && !N1C) 1631 return DAG.getNode(ISD::AND, VT, N1, N0); 1632 // fold (and x, -1) -> x 1633 if (N1C && N1C->isAllOnesValue()) 1634 return N0; 1635 // if (and x, c) is known to be zero, return 0 1636 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1637 APInt::getAllOnesValue(BitWidth))) 1638 return DAG.getConstant(0, VT); 1639 // reassociate and 1640 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1641 if (RAND.getNode() != 0) 1642 return RAND; 1643 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1644 if (N1C && N0.getOpcode() == ISD::OR) 1645 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1646 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1647 return N1; 1648 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1649 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1650 SDValue N0Op0 = N0.getOperand(0); 1651 APInt Mask = ~N1C->getAPIntValue(); 1652 Mask.trunc(N0Op0.getValueSizeInBits()); 1653 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1654 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1655 N0Op0); 1656 1657 // Replace uses of the AND with uses of the Zero extend node. 1658 CombineTo(N, Zext); 1659 1660 // We actually want to replace all uses of the any_extend with the 1661 // zero_extend, to avoid duplicating things. This will later cause this 1662 // AND to be folded. 1663 CombineTo(N0.getNode(), Zext); 1664 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1665 } 1666 } 1667 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1668 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1669 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1670 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1671 1672 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1673 LL.getValueType().isInteger()) { 1674 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1675 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1676 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1677 AddToWorkList(ORNode.getNode()); 1678 return DAG.getSetCC(VT, ORNode, LR, Op1); 1679 } 1680 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1681 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1682 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1683 AddToWorkList(ANDNode.getNode()); 1684 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1685 } 1686 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1687 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1688 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1689 AddToWorkList(ORNode.getNode()); 1690 return DAG.getSetCC(VT, ORNode, LR, Op1); 1691 } 1692 } 1693 // canonicalize equivalent to ll == rl 1694 if (LL == RR && LR == RL) { 1695 Op1 = ISD::getSetCCSwappedOperands(Op1); 1696 std::swap(RL, RR); 1697 } 1698 if (LL == RL && LR == RR) { 1699 bool isInteger = LL.getValueType().isInteger(); 1700 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1701 if (Result != ISD::SETCC_INVALID) 1702 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1703 } 1704 } 1705 1706 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1707 if (N0.getOpcode() == N1.getOpcode()) { 1708 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1709 if (Tmp.getNode()) return Tmp; 1710 } 1711 1712 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1713 // fold (and (sra)) -> (and (srl)) when possible. 1714 if (!VT.isVector() && 1715 SimplifyDemandedBits(SDValue(N, 0))) 1716 return SDValue(N, 0); 1717 // fold (zext_inreg (extload x)) -> (zextload x) 1718 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1719 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1720 MVT EVT = LN0->getMemoryVT(); 1721 // If we zero all the possible extended bits, then we can turn this into 1722 // a zextload if we are running before legalize or the operation is legal. 1723 unsigned BitWidth = N1.getValueSizeInBits(); 1724 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1725 BitWidth - EVT.getSizeInBits())) && 1726 ((!AfterLegalize && !LN0->isVolatile()) || 1727 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1728 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1729 LN0->getBasePtr(), LN0->getSrcValue(), 1730 LN0->getSrcValueOffset(), EVT, 1731 LN0->isVolatile(), 1732 LN0->getAlignment()); 1733 AddToWorkList(N); 1734 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1735 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1736 } 1737 } 1738 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1739 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1740 N0.hasOneUse()) { 1741 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1742 MVT EVT = LN0->getMemoryVT(); 1743 // If we zero all the possible extended bits, then we can turn this into 1744 // a zextload if we are running before legalize or the operation is legal. 1745 unsigned BitWidth = N1.getValueSizeInBits(); 1746 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1747 BitWidth - EVT.getSizeInBits())) && 1748 ((!AfterLegalize && !LN0->isVolatile()) || 1749 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1750 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1751 LN0->getBasePtr(), LN0->getSrcValue(), 1752 LN0->getSrcValueOffset(), EVT, 1753 LN0->isVolatile(), 1754 LN0->getAlignment()); 1755 AddToWorkList(N); 1756 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1757 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1758 } 1759 } 1760 1761 // fold (and (load x), 255) -> (zextload x, i8) 1762 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1763 if (N1C && N0.getOpcode() == ISD::LOAD) { 1764 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1765 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1766 LN0->isUnindexed() && N0.hasOneUse() && 1767 // Do not change the width of a volatile load. 1768 !LN0->isVolatile()) { 1769 MVT EVT = MVT::Other; 1770 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1771 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1772 EVT = MVT::getIntegerVT(ActiveBits); 1773 1774 MVT LoadedVT = LN0->getMemoryVT(); 1775 // Do not generate loads of non-round integer types since these can 1776 // be expensive (and would be wrong if the type is not byte sized). 1777 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1778 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1779 MVT PtrType = N0.getOperand(1).getValueType(); 1780 // For big endian targets, we need to add an offset to the pointer to 1781 // load the correct bytes. For little endian systems, we merely need to 1782 // read fewer bytes from the same pointer. 1783 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1784 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1785 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1786 unsigned Alignment = LN0->getAlignment(); 1787 SDValue NewPtr = LN0->getBasePtr(); 1788 if (TLI.isBigEndian()) { 1789 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1790 DAG.getConstant(PtrOff, PtrType)); 1791 Alignment = MinAlign(Alignment, PtrOff); 1792 } 1793 AddToWorkList(NewPtr.getNode()); 1794 SDValue Load = 1795 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1796 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1797 LN0->isVolatile(), Alignment); 1798 AddToWorkList(N); 1799 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1800 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1801 } 1802 } 1803 } 1804 1805 return SDValue(); 1806} 1807 1808SDValue DAGCombiner::visitOR(SDNode *N) { 1809 SDValue N0 = N->getOperand(0); 1810 SDValue N1 = N->getOperand(1); 1811 SDValue LL, LR, RL, RR, CC0, CC1; 1812 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1814 MVT VT = N1.getValueType(); 1815 1816 // fold vector ops 1817 if (VT.isVector()) { 1818 SDValue FoldedVOp = SimplifyVBinOp(N); 1819 if (FoldedVOp.getNode()) return FoldedVOp; 1820 } 1821 1822 // fold (or x, undef) -> -1 1823 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1824 return DAG.getConstant(~0ULL, VT); 1825 // fold (or c1, c2) -> c1|c2 1826 if (N0C && N1C) 1827 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1828 // canonicalize constant to RHS 1829 if (N0C && !N1C) 1830 return DAG.getNode(ISD::OR, VT, N1, N0); 1831 // fold (or x, 0) -> x 1832 if (N1C && N1C->isNullValue()) 1833 return N0; 1834 // fold (or x, -1) -> -1 1835 if (N1C && N1C->isAllOnesValue()) 1836 return N1; 1837 // fold (or x, c) -> c iff (x & ~c) == 0 1838 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1839 return N1; 1840 // reassociate or 1841 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1842 if (ROR.getNode() != 0) 1843 return ROR; 1844 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1845 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1846 isa<ConstantSDNode>(N0.getOperand(1))) { 1847 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1848 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1849 N1), 1850 DAG.getConstant(N1C->getAPIntValue() | 1851 C1->getAPIntValue(), VT)); 1852 } 1853 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1854 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1855 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1856 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1857 1858 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1859 LL.getValueType().isInteger()) { 1860 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1861 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1862 if (cast<ConstantSDNode>(LR)->isNullValue() && 1863 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1864 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1865 AddToWorkList(ORNode.getNode()); 1866 return DAG.getSetCC(VT, ORNode, LR, Op1); 1867 } 1868 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1869 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1870 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1871 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1872 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1873 AddToWorkList(ANDNode.getNode()); 1874 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1875 } 1876 } 1877 // canonicalize equivalent to ll == rl 1878 if (LL == RR && LR == RL) { 1879 Op1 = ISD::getSetCCSwappedOperands(Op1); 1880 std::swap(RL, RR); 1881 } 1882 if (LL == RL && LR == RR) { 1883 bool isInteger = LL.getValueType().isInteger(); 1884 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1885 if (Result != ISD::SETCC_INVALID) 1886 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1887 } 1888 } 1889 1890 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1891 if (N0.getOpcode() == N1.getOpcode()) { 1892 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1893 if (Tmp.getNode()) return Tmp; 1894 } 1895 1896 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1897 if (N0.getOpcode() == ISD::AND && 1898 N1.getOpcode() == ISD::AND && 1899 N0.getOperand(1).getOpcode() == ISD::Constant && 1900 N1.getOperand(1).getOpcode() == ISD::Constant && 1901 // Don't increase # computations. 1902 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1903 // We can only do this xform if we know that bits from X that are set in C2 1904 // but not in C1 are already zero. Likewise for Y. 1905 const APInt &LHSMask = 1906 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1907 const APInt &RHSMask = 1908 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1909 1910 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1911 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1912 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1913 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1914 } 1915 } 1916 1917 1918 // See if this is some rotate idiom. 1919 if (SDNode *Rot = MatchRotate(N0, N1)) 1920 return SDValue(Rot, 0); 1921 1922 return SDValue(); 1923} 1924 1925 1926/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1927static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1928 if (Op.getOpcode() == ISD::AND) { 1929 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1930 Mask = Op.getOperand(1); 1931 Op = Op.getOperand(0); 1932 } else { 1933 return false; 1934 } 1935 } 1936 1937 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1938 Shift = Op; 1939 return true; 1940 } 1941 return false; 1942} 1943 1944 1945// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1946// idioms for rotate, and if the target supports rotation instructions, generate 1947// a rot[lr]. 1948SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1949 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1950 MVT VT = LHS.getValueType(); 1951 if (!TLI.isTypeLegal(VT)) return 0; 1952 1953 // The target must have at least one rotate flavor. 1954 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1955 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1956 if (!HasROTL && !HasROTR) return 0; 1957 1958 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1959 SDValue LHSShift; // The shift. 1960 SDValue LHSMask; // AND value if any. 1961 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1962 return 0; // Not part of a rotate. 1963 1964 SDValue RHSShift; // The shift. 1965 SDValue RHSMask; // AND value if any. 1966 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1967 return 0; // Not part of a rotate. 1968 1969 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1970 return 0; // Not shifting the same value. 1971 1972 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1973 return 0; // Shifts must disagree. 1974 1975 // Canonicalize shl to left side in a shl/srl pair. 1976 if (RHSShift.getOpcode() == ISD::SHL) { 1977 std::swap(LHS, RHS); 1978 std::swap(LHSShift, RHSShift); 1979 std::swap(LHSMask , RHSMask ); 1980 } 1981 1982 unsigned OpSizeInBits = VT.getSizeInBits(); 1983 SDValue LHSShiftArg = LHSShift.getOperand(0); 1984 SDValue LHSShiftAmt = LHSShift.getOperand(1); 1985 SDValue RHSShiftAmt = RHSShift.getOperand(1); 1986 1987 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1988 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1989 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1990 RHSShiftAmt.getOpcode() == ISD::Constant) { 1991 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 1992 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 1993 if ((LShVal + RShVal) != OpSizeInBits) 1994 return 0; 1995 1996 SDValue Rot; 1997 if (HasROTL) 1998 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1999 else 2000 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2001 2002 // If there is an AND of either shifted operand, apply it to the result. 2003 if (LHSMask.getNode() || RHSMask.getNode()) { 2004 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2005 2006 if (LHSMask.getNode()) { 2007 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2008 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2009 } 2010 if (RHSMask.getNode()) { 2011 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2012 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2013 } 2014 2015 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2016 } 2017 2018 return Rot.getNode(); 2019 } 2020 2021 // If there is a mask here, and we have a variable shift, we can't be sure 2022 // that we're masking out the right stuff. 2023 if (LHSMask.getNode() || RHSMask.getNode()) 2024 return 0; 2025 2026 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2027 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2028 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2029 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2030 if (ConstantSDNode *SUBC = 2031 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2032 if (SUBC->getAPIntValue() == OpSizeInBits) { 2033 if (HasROTL) 2034 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2035 else 2036 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2037 } 2038 } 2039 } 2040 2041 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2042 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2043 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2044 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2045 if (ConstantSDNode *SUBC = 2046 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2047 if (SUBC->getAPIntValue() == OpSizeInBits) { 2048 if (HasROTR) 2049 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2050 else 2051 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2052 } 2053 } 2054 } 2055 2056 // Look for sign/zext/any-extended cases: 2057 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2058 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2059 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2060 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2061 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2062 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2063 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2064 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2065 if (RExtOp0.getOpcode() == ISD::SUB && 2066 RExtOp0.getOperand(1) == LExtOp0) { 2067 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2068 // (rotl x, y) 2069 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2070 // (rotr x, (sub 32, y)) 2071 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2072 if (SUBC->getAPIntValue() == OpSizeInBits) { 2073 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2074 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2075 } 2076 } 2077 } else if (LExtOp0.getOpcode() == ISD::SUB && 2078 RExtOp0 == LExtOp0.getOperand(1)) { 2079 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2080 // (rotr x, y) 2081 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2082 // (rotl x, (sub 32, y)) 2083 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2084 if (SUBC->getAPIntValue() == OpSizeInBits) { 2085 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2086 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2087 } 2088 } 2089 } 2090 } 2091 2092 return 0; 2093} 2094 2095 2096SDValue DAGCombiner::visitXOR(SDNode *N) { 2097 SDValue N0 = N->getOperand(0); 2098 SDValue N1 = N->getOperand(1); 2099 SDValue LHS, RHS, CC; 2100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2102 MVT VT = N0.getValueType(); 2103 2104 // fold vector ops 2105 if (VT.isVector()) { 2106 SDValue FoldedVOp = SimplifyVBinOp(N); 2107 if (FoldedVOp.getNode()) return FoldedVOp; 2108 } 2109 2110 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2111 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2112 return DAG.getConstant(0, VT); 2113 // fold (xor x, undef) -> undef 2114 if (N0.getOpcode() == ISD::UNDEF) 2115 return N0; 2116 if (N1.getOpcode() == ISD::UNDEF) 2117 return N1; 2118 // fold (xor c1, c2) -> c1^c2 2119 if (N0C && N1C) 2120 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2121 // canonicalize constant to RHS 2122 if (N0C && !N1C) 2123 return DAG.getNode(ISD::XOR, VT, N1, N0); 2124 // fold (xor x, 0) -> x 2125 if (N1C && N1C->isNullValue()) 2126 return N0; 2127 // reassociate xor 2128 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2129 if (RXOR.getNode() != 0) 2130 return RXOR; 2131 // fold !(x cc y) -> (x !cc y) 2132 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2133 bool isInt = LHS.getValueType().isInteger(); 2134 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2135 isInt); 2136 if (N0.getOpcode() == ISD::SETCC) 2137 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2138 if (N0.getOpcode() == ISD::SELECT_CC) 2139 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2140 assert(0 && "Unhandled SetCC Equivalent!"); 2141 abort(); 2142 } 2143 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2144 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2145 N0.getNode()->hasOneUse() && 2146 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2147 SDValue V = N0.getOperand(0); 2148 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2149 DAG.getConstant(1, V.getValueType())); 2150 AddToWorkList(V.getNode()); 2151 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2152 } 2153 2154 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2155 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2156 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2157 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2158 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2159 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2160 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2161 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2162 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2163 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2164 } 2165 } 2166 // fold !(x or y) -> (!x and !y) iff x or y are constants 2167 if (N1C && N1C->isAllOnesValue() && 2168 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2169 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2170 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2171 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2172 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2173 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2174 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2175 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2176 } 2177 } 2178 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2179 if (N1C && N0.getOpcode() == ISD::XOR) { 2180 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2181 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2182 if (N00C) 2183 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2184 DAG.getConstant(N1C->getAPIntValue()^ 2185 N00C->getAPIntValue(), VT)); 2186 if (N01C) 2187 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2188 DAG.getConstant(N1C->getAPIntValue()^ 2189 N01C->getAPIntValue(), VT)); 2190 } 2191 // fold (xor x, x) -> 0 2192 if (N0 == N1) { 2193 if (!VT.isVector()) { 2194 return DAG.getConstant(0, VT); 2195 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2196 // Produce a vector of zeros. 2197 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2198 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2199 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2200 } 2201 } 2202 2203 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2204 if (N0.getOpcode() == N1.getOpcode()) { 2205 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2206 if (Tmp.getNode()) return Tmp; 2207 } 2208 2209 // Simplify the expression using non-local knowledge. 2210 if (!VT.isVector() && 2211 SimplifyDemandedBits(SDValue(N, 0))) 2212 return SDValue(N, 0); 2213 2214 return SDValue(); 2215} 2216 2217/// visitShiftByConstant - Handle transforms common to the three shifts, when 2218/// the shift amount is a constant. 2219SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2220 SDNode *LHS = N->getOperand(0).getNode(); 2221 if (!LHS->hasOneUse()) return SDValue(); 2222 2223 // We want to pull some binops through shifts, so that we have (and (shift)) 2224 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2225 // thing happens with address calculations, so it's important to canonicalize 2226 // it. 2227 bool HighBitSet = false; // Can we transform this if the high bit is set? 2228 2229 switch (LHS->getOpcode()) { 2230 default: return SDValue(); 2231 case ISD::OR: 2232 case ISD::XOR: 2233 HighBitSet = false; // We can only transform sra if the high bit is clear. 2234 break; 2235 case ISD::AND: 2236 HighBitSet = true; // We can only transform sra if the high bit is set. 2237 break; 2238 case ISD::ADD: 2239 if (N->getOpcode() != ISD::SHL) 2240 return SDValue(); // only shl(add) not sr[al](add). 2241 HighBitSet = false; // We can only transform sra if the high bit is clear. 2242 break; 2243 } 2244 2245 // We require the RHS of the binop to be a constant as well. 2246 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2247 if (!BinOpCst) return SDValue(); 2248 2249 2250 // FIXME: disable this for unless the input to the binop is a shift by a 2251 // constant. If it is not a shift, it pessimizes some common cases like: 2252 // 2253 //void foo(int *X, int i) { X[i & 1235] = 1; } 2254 //int bar(int *X, int i) { return X[i & 255]; } 2255 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2256 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2257 BinOpLHSVal->getOpcode() != ISD::SRA && 2258 BinOpLHSVal->getOpcode() != ISD::SRL) || 2259 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2260 return SDValue(); 2261 2262 MVT VT = N->getValueType(0); 2263 2264 // If this is a signed shift right, and the high bit is modified 2265 // by the logical operation, do not perform the transformation. 2266 // The highBitSet boolean indicates the value of the high bit of 2267 // the constant which would cause it to be modified for this 2268 // operation. 2269 if (N->getOpcode() == ISD::SRA) { 2270 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2271 if (BinOpRHSSignSet != HighBitSet) 2272 return SDValue(); 2273 } 2274 2275 // Fold the constants, shifting the binop RHS by the shift amount. 2276 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2277 LHS->getOperand(1), N->getOperand(1)); 2278 2279 // Create the new shift. 2280 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2281 N->getOperand(1)); 2282 2283 // Create the new binop. 2284 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2285} 2286 2287 2288SDValue DAGCombiner::visitSHL(SDNode *N) { 2289 SDValue N0 = N->getOperand(0); 2290 SDValue N1 = N->getOperand(1); 2291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2293 MVT VT = N0.getValueType(); 2294 unsigned OpSizeInBits = VT.getSizeInBits(); 2295 2296 // fold (shl c1, c2) -> c1<<c2 2297 if (N0C && N1C) 2298 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2299 // fold (shl 0, x) -> 0 2300 if (N0C && N0C->isNullValue()) 2301 return N0; 2302 // fold (shl x, c >= size(x)) -> undef 2303 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2304 return DAG.getNode(ISD::UNDEF, VT); 2305 // fold (shl x, 0) -> x 2306 if (N1C && N1C->isNullValue()) 2307 return N0; 2308 // if (shl x, c) is known to be zero, return 0 2309 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2310 APInt::getAllOnesValue(VT.getSizeInBits()))) 2311 return DAG.getConstant(0, VT); 2312 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2313 // iff (trunc c) == c 2314 if (N1.getOpcode() == ISD::TRUNCATE && 2315 N1.getOperand(0).getOpcode() == ISD::AND && 2316 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2317 SDValue N101 = N1.getOperand(0).getOperand(1); 2318 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2319 MVT TruncVT = N1.getValueType(); 2320 SDValue N100 = N1.getOperand(0).getOperand(0); 2321 return DAG.getNode(ISD::SHL, VT, N0, 2322 DAG.getNode(ISD::AND, TruncVT, 2323 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2324 DAG.getConstant(N101C->getZExtValue(), 2325 TruncVT))); 2326 } 2327 } 2328 2329 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2330 return SDValue(N, 0); 2331 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2332 if (N1C && N0.getOpcode() == ISD::SHL && 2333 N0.getOperand(1).getOpcode() == ISD::Constant) { 2334 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2335 uint64_t c2 = N1C->getZExtValue(); 2336 if (c1 + c2 > OpSizeInBits) 2337 return DAG.getConstant(0, VT); 2338 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2339 DAG.getConstant(c1 + c2, N1.getValueType())); 2340 } 2341 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2342 // (srl (and x, -1 << c1), c1-c2) 2343 if (N1C && N0.getOpcode() == ISD::SRL && 2344 N0.getOperand(1).getOpcode() == ISD::Constant) { 2345 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2346 uint64_t c2 = N1C->getZExtValue(); 2347 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2348 DAG.getConstant(~0ULL << c1, VT)); 2349 if (c2 > c1) 2350 return DAG.getNode(ISD::SHL, VT, Mask, 2351 DAG.getConstant(c2-c1, N1.getValueType())); 2352 else 2353 return DAG.getNode(ISD::SRL, VT, Mask, 2354 DAG.getConstant(c1-c2, N1.getValueType())); 2355 } 2356 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2357 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2358 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2359 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2360 2361 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2362} 2363 2364SDValue DAGCombiner::visitSRA(SDNode *N) { 2365 SDValue N0 = N->getOperand(0); 2366 SDValue N1 = N->getOperand(1); 2367 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2369 MVT VT = N0.getValueType(); 2370 2371 // fold (sra c1, c2) -> c1>>c2 2372 if (N0C && N1C) 2373 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2374 // fold (sra 0, x) -> 0 2375 if (N0C && N0C->isNullValue()) 2376 return N0; 2377 // fold (sra -1, x) -> -1 2378 if (N0C && N0C->isAllOnesValue()) 2379 return N0; 2380 // fold (sra x, c >= size(x)) -> undef 2381 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2382 return DAG.getNode(ISD::UNDEF, VT); 2383 // fold (sra x, 0) -> x 2384 if (N1C && N1C->isNullValue()) 2385 return N0; 2386 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2387 // sext_inreg. 2388 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2389 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2390 MVT EVT = MVT::getIntegerVT(LowBits); 2391 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2392 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2393 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2394 DAG.getValueType(EVT)); 2395 } 2396 2397 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2398 if (N1C && N0.getOpcode() == ISD::SRA) { 2399 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2400 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2401 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2402 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2403 DAG.getConstant(Sum, N1C->getValueType(0))); 2404 } 2405 } 2406 2407 // fold sra (shl X, m), result_size - n 2408 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2409 // result_size - n != m. 2410 // If truncate is free for the target sext(shl) is likely to result in better 2411 // code. 2412 if (N0.getOpcode() == ISD::SHL) { 2413 // Get the two constanst of the shifts, CN0 = m, CN = n. 2414 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2415 if (N01C && N1C) { 2416 // Determine what the truncate's result bitsize and type would be. 2417 unsigned VTValSize = VT.getSizeInBits(); 2418 MVT TruncVT = 2419 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2420 // Determine the residual right-shift amount. 2421 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2422 2423 // If the shift is not a no-op (in which case this should be just a sign 2424 // extend already), the truncated to type is legal, sign_extend is legal 2425 // on that type, and the the truncate to that type is both legal and free, 2426 // perform the transform. 2427 if (ShiftAmt && 2428 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2429 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2430 TLI.isTruncateFree(VT, TruncVT)) { 2431 2432 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2433 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2434 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2435 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2436 } 2437 } 2438 } 2439 2440 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2441 // iff (trunc c) == c 2442 if (N1.getOpcode() == ISD::TRUNCATE && 2443 N1.getOperand(0).getOpcode() == ISD::AND && 2444 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2445 SDValue N101 = N1.getOperand(0).getOperand(1); 2446 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2447 MVT TruncVT = N1.getValueType(); 2448 SDValue N100 = N1.getOperand(0).getOperand(0); 2449 return DAG.getNode(ISD::SRA, VT, N0, 2450 DAG.getNode(ISD::AND, TruncVT, 2451 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2452 DAG.getConstant(N101C->getZExtValue(), 2453 TruncVT))); 2454 } 2455 } 2456 2457 // Simplify, based on bits shifted out of the LHS. 2458 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2459 return SDValue(N, 0); 2460 2461 2462 // If the sign bit is known to be zero, switch this to a SRL. 2463 if (DAG.SignBitIsZero(N0)) 2464 return DAG.getNode(ISD::SRL, VT, N0, N1); 2465 2466 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2467} 2468 2469SDValue DAGCombiner::visitSRL(SDNode *N) { 2470 SDValue N0 = N->getOperand(0); 2471 SDValue N1 = N->getOperand(1); 2472 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2473 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2474 MVT VT = N0.getValueType(); 2475 unsigned OpSizeInBits = VT.getSizeInBits(); 2476 2477 // fold (srl c1, c2) -> c1 >>u c2 2478 if (N0C && N1C) 2479 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2480 // fold (srl 0, x) -> 0 2481 if (N0C && N0C->isNullValue()) 2482 return N0; 2483 // fold (srl x, c >= size(x)) -> undef 2484 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2485 return DAG.getNode(ISD::UNDEF, VT); 2486 // fold (srl x, 0) -> x 2487 if (N1C && N1C->isNullValue()) 2488 return N0; 2489 // if (srl x, c) is known to be zero, return 0 2490 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2491 APInt::getAllOnesValue(OpSizeInBits))) 2492 return DAG.getConstant(0, VT); 2493 2494 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2495 if (N1C && N0.getOpcode() == ISD::SRL && 2496 N0.getOperand(1).getOpcode() == ISD::Constant) { 2497 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2498 uint64_t c2 = N1C->getZExtValue(); 2499 if (c1 + c2 > OpSizeInBits) 2500 return DAG.getConstant(0, VT); 2501 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2502 DAG.getConstant(c1 + c2, N1.getValueType())); 2503 } 2504 2505 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2506 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2507 // Shifting in all undef bits? 2508 MVT SmallVT = N0.getOperand(0).getValueType(); 2509 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2510 return DAG.getNode(ISD::UNDEF, VT); 2511 2512 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2513 AddToWorkList(SmallShift.getNode()); 2514 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2515 } 2516 2517 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2518 // bit, which is unmodified by sra. 2519 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2520 if (N0.getOpcode() == ISD::SRA) 2521 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2522 } 2523 2524 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2525 if (N1C && N0.getOpcode() == ISD::CTLZ && 2526 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2527 APInt KnownZero, KnownOne; 2528 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2529 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2530 2531 // If any of the input bits are KnownOne, then the input couldn't be all 2532 // zeros, thus the result of the srl will always be zero. 2533 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2534 2535 // If all of the bits input the to ctlz node are known to be zero, then 2536 // the result of the ctlz is "32" and the result of the shift is one. 2537 APInt UnknownBits = ~KnownZero & Mask; 2538 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2539 2540 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2541 if ((UnknownBits & (UnknownBits-1)) == 0) { 2542 // Okay, we know that only that the single bit specified by UnknownBits 2543 // could be set on input to the CTLZ node. If this bit is set, the SRL 2544 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2545 // to an SRL,XOR pair, which is likely to simplify more. 2546 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2547 SDValue Op = N0.getOperand(0); 2548 if (ShAmt) { 2549 Op = DAG.getNode(ISD::SRL, VT, Op, 2550 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2551 AddToWorkList(Op.getNode()); 2552 } 2553 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2554 } 2555 } 2556 2557 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2558 // iff (trunc c) == c 2559 if (N1.getOpcode() == ISD::TRUNCATE && 2560 N1.getOperand(0).getOpcode() == ISD::AND && 2561 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2562 SDValue N101 = N1.getOperand(0).getOperand(1); 2563 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2564 MVT TruncVT = N1.getValueType(); 2565 SDValue N100 = N1.getOperand(0).getOperand(0); 2566 return DAG.getNode(ISD::SRL, VT, N0, 2567 DAG.getNode(ISD::AND, TruncVT, 2568 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2569 DAG.getConstant(N101C->getZExtValue(), 2570 TruncVT))); 2571 } 2572 } 2573 2574 // fold operands of srl based on knowledge that the low bits are not 2575 // demanded. 2576 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2577 return SDValue(N, 0); 2578 2579 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2580} 2581 2582SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2583 SDValue N0 = N->getOperand(0); 2584 MVT VT = N->getValueType(0); 2585 2586 // fold (ctlz c1) -> c2 2587 if (isa<ConstantSDNode>(N0)) 2588 return DAG.getNode(ISD::CTLZ, VT, N0); 2589 return SDValue(); 2590} 2591 2592SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2593 SDValue N0 = N->getOperand(0); 2594 MVT VT = N->getValueType(0); 2595 2596 // fold (cttz c1) -> c2 2597 if (isa<ConstantSDNode>(N0)) 2598 return DAG.getNode(ISD::CTTZ, VT, N0); 2599 return SDValue(); 2600} 2601 2602SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2603 SDValue N0 = N->getOperand(0); 2604 MVT VT = N->getValueType(0); 2605 2606 // fold (ctpop c1) -> c2 2607 if (isa<ConstantSDNode>(N0)) 2608 return DAG.getNode(ISD::CTPOP, VT, N0); 2609 return SDValue(); 2610} 2611 2612SDValue DAGCombiner::visitSELECT(SDNode *N) { 2613 SDValue N0 = N->getOperand(0); 2614 SDValue N1 = N->getOperand(1); 2615 SDValue N2 = N->getOperand(2); 2616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2617 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2618 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2619 MVT VT = N->getValueType(0); 2620 MVT VT0 = N0.getValueType(); 2621 2622 // fold select C, X, X -> X 2623 if (N1 == N2) 2624 return N1; 2625 // fold select true, X, Y -> X 2626 if (N0C && !N0C->isNullValue()) 2627 return N1; 2628 // fold select false, X, Y -> Y 2629 if (N0C && N0C->isNullValue()) 2630 return N2; 2631 // fold select C, 1, X -> C | X 2632 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2633 return DAG.getNode(ISD::OR, VT, N0, N2); 2634 // fold select C, 0, 1 -> ~C 2635 if (VT.isInteger() && VT0.isInteger() && 2636 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2637 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2638 if (VT == VT0) 2639 return XORNode; 2640 AddToWorkList(XORNode.getNode()); 2641 if (VT.bitsGT(VT0)) 2642 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2643 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2644 } 2645 // fold select C, 0, X -> ~C & X 2646 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2647 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2648 AddToWorkList(XORNode.getNode()); 2649 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2650 } 2651 // fold select C, X, 1 -> ~C | X 2652 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2653 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2654 AddToWorkList(XORNode.getNode()); 2655 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2656 } 2657 // fold select C, X, 0 -> C & X 2658 // FIXME: this should check for C type == X type, not i1? 2659 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2660 return DAG.getNode(ISD::AND, VT, N0, N1); 2661 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2662 if (VT == MVT::i1 && N0 == N1) 2663 return DAG.getNode(ISD::OR, VT, N0, N2); 2664 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2665 if (VT == MVT::i1 && N0 == N2) 2666 return DAG.getNode(ISD::AND, VT, N0, N1); 2667 2668 // If we can fold this based on the true/false value, do so. 2669 if (SimplifySelectOps(N, N1, N2)) 2670 return SDValue(N, 0); // Don't revisit N. 2671 2672 // fold selects based on a setcc into other things, such as min/max/abs 2673 if (N0.getOpcode() == ISD::SETCC) { 2674 // FIXME: 2675 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2676 // having to say they don't support SELECT_CC on every type the DAG knows 2677 // about, since there is no way to mark an opcode illegal at all value types 2678 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2679 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2680 N1, N2, N0.getOperand(2)); 2681 else 2682 return SimplifySelect(N0, N1, N2); 2683 } 2684 return SDValue(); 2685} 2686 2687SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2688 SDValue N0 = N->getOperand(0); 2689 SDValue N1 = N->getOperand(1); 2690 SDValue N2 = N->getOperand(2); 2691 SDValue N3 = N->getOperand(3); 2692 SDValue N4 = N->getOperand(4); 2693 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2694 2695 // fold select_cc lhs, rhs, x, x, cc -> x 2696 if (N2 == N3) 2697 return N2; 2698 2699 // Determine if the condition we're dealing with is constant 2700 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2701 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2702 2703 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2704 if (!SCCC->isNullValue()) 2705 return N2; // cond always true -> true val 2706 else 2707 return N3; // cond always false -> false val 2708 } 2709 2710 // Fold to a simpler select_cc 2711 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2712 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2713 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2714 SCC.getOperand(2)); 2715 2716 // If we can fold this based on the true/false value, do so. 2717 if (SimplifySelectOps(N, N2, N3)) 2718 return SDValue(N, 0); // Don't revisit N. 2719 2720 // fold select_cc into other things, such as min/max/abs 2721 return SimplifySelectCC(N0, N1, N2, N3, CC); 2722} 2723 2724SDValue DAGCombiner::visitSETCC(SDNode *N) { 2725 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2726 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2727} 2728 2729// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2730// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2731// transformation. Returns true if extension are possible and the above 2732// mentioned transformation is profitable. 2733static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2734 unsigned ExtOpc, 2735 SmallVector<SDNode*, 4> &ExtendNodes, 2736 TargetLowering &TLI) { 2737 bool HasCopyToRegUses = false; 2738 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2739 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2740 UE = N0.getNode()->use_end(); 2741 UI != UE; ++UI) { 2742 SDNode *User = *UI; 2743 if (User == N) 2744 continue; 2745 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2746 if (User->getOpcode() == ISD::SETCC) { 2747 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2748 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2749 // Sign bits will be lost after a zext. 2750 return false; 2751 bool Add = false; 2752 for (unsigned i = 0; i != 2; ++i) { 2753 SDValue UseOp = User->getOperand(i); 2754 if (UseOp == N0) 2755 continue; 2756 if (!isa<ConstantSDNode>(UseOp)) 2757 return false; 2758 Add = true; 2759 } 2760 if (Add) 2761 ExtendNodes.push_back(User); 2762 } else { 2763 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2764 SDValue UseOp = User->getOperand(i); 2765 if (UseOp == N0) { 2766 // If truncate from extended type to original load type is free 2767 // on this target, then it's ok to extend a CopyToReg. 2768 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2769 HasCopyToRegUses = true; 2770 else 2771 return false; 2772 } 2773 } 2774 } 2775 } 2776 2777 if (HasCopyToRegUses) { 2778 bool BothLiveOut = false; 2779 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2780 UI != UE; ++UI) { 2781 SDNode *User = *UI; 2782 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2783 SDValue UseOp = User->getOperand(i); 2784 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2785 BothLiveOut = true; 2786 break; 2787 } 2788 } 2789 } 2790 if (BothLiveOut) 2791 // Both unextended and extended values are live out. There had better be 2792 // good a reason for the transformation. 2793 return ExtendNodes.size(); 2794 } 2795 return true; 2796} 2797 2798SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2799 SDValue N0 = N->getOperand(0); 2800 MVT VT = N->getValueType(0); 2801 2802 // fold (sext c1) -> c1 2803 if (isa<ConstantSDNode>(N0)) 2804 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2805 2806 // fold (sext (sext x)) -> (sext x) 2807 // fold (sext (aext x)) -> (sext x) 2808 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2809 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2810 2811 if (N0.getOpcode() == ISD::TRUNCATE) { 2812 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2813 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2814 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2815 if (NarrowLoad.getNode()) { 2816 if (NarrowLoad.getNode() != N0.getNode()) 2817 CombineTo(N0.getNode(), NarrowLoad); 2818 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2819 } 2820 2821 // See if the value being truncated is already sign extended. If so, just 2822 // eliminate the trunc/sext pair. 2823 SDValue Op = N0.getOperand(0); 2824 unsigned OpBits = Op.getValueType().getSizeInBits(); 2825 unsigned MidBits = N0.getValueType().getSizeInBits(); 2826 unsigned DestBits = VT.getSizeInBits(); 2827 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2828 2829 if (OpBits == DestBits) { 2830 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2831 // bits, it is already ready. 2832 if (NumSignBits > DestBits-MidBits) 2833 return Op; 2834 } else if (OpBits < DestBits) { 2835 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2836 // bits, just sext from i32. 2837 if (NumSignBits > OpBits-MidBits) 2838 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2839 } else { 2840 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2841 // bits, just truncate to i32. 2842 if (NumSignBits > OpBits-MidBits) 2843 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2844 } 2845 2846 // fold (sext (truncate x)) -> (sextinreg x). 2847 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2848 N0.getValueType())) { 2849 if (Op.getValueType().bitsLT(VT)) 2850 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2851 else if (Op.getValueType().bitsGT(VT)) 2852 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2853 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2854 DAG.getValueType(N0.getValueType())); 2855 } 2856 } 2857 2858 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2859 if (ISD::isNON_EXTLoad(N0.getNode()) && 2860 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2861 TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2862 bool DoXform = true; 2863 SmallVector<SDNode*, 4> SetCCs; 2864 if (!N0.hasOneUse()) 2865 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2866 if (DoXform) { 2867 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2868 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2869 LN0->getBasePtr(), LN0->getSrcValue(), 2870 LN0->getSrcValueOffset(), 2871 N0.getValueType(), 2872 LN0->isVolatile(), 2873 LN0->getAlignment()); 2874 CombineTo(N, ExtLoad); 2875 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2876 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2877 // Extend SetCC uses if necessary. 2878 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2879 SDNode *SetCC = SetCCs[i]; 2880 SmallVector<SDValue, 4> Ops; 2881 for (unsigned j = 0; j != 2; ++j) { 2882 SDValue SOp = SetCC->getOperand(j); 2883 if (SOp == Trunc) 2884 Ops.push_back(ExtLoad); 2885 else 2886 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2887 } 2888 Ops.push_back(SetCC->getOperand(2)); 2889 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2890 &Ops[0], Ops.size())); 2891 } 2892 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2893 } 2894 } 2895 2896 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2897 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2898 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2899 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2900 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2901 MVT EVT = LN0->getMemoryVT(); 2902 if ((!AfterLegalize && !LN0->isVolatile()) || 2903 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2904 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2905 LN0->getBasePtr(), LN0->getSrcValue(), 2906 LN0->getSrcValueOffset(), EVT, 2907 LN0->isVolatile(), 2908 LN0->getAlignment()); 2909 CombineTo(N, ExtLoad); 2910 CombineTo(N0.getNode(), 2911 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2912 ExtLoad.getValue(1)); 2913 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2914 } 2915 } 2916 2917 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2918 if (N0.getOpcode() == ISD::SETCC) { 2919 SDValue SCC = 2920 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2921 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2922 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2923 if (SCC.getNode()) return SCC; 2924 } 2925 2926 // fold (sext x) -> (zext x) if the sign bit is known zero. 2927 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2928 DAG.SignBitIsZero(N0)) 2929 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2930 2931 return SDValue(); 2932} 2933 2934SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2935 SDValue N0 = N->getOperand(0); 2936 MVT VT = N->getValueType(0); 2937 2938 // fold (zext c1) -> c1 2939 if (isa<ConstantSDNode>(N0)) 2940 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2941 // fold (zext (zext x)) -> (zext x) 2942 // fold (zext (aext x)) -> (zext x) 2943 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2944 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2945 2946 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2947 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2948 if (N0.getOpcode() == ISD::TRUNCATE) { 2949 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2950 if (NarrowLoad.getNode()) { 2951 if (NarrowLoad.getNode() != N0.getNode()) 2952 CombineTo(N0.getNode(), NarrowLoad); 2953 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2954 } 2955 } 2956 2957 // fold (zext (truncate x)) -> (and x, mask) 2958 if (N0.getOpcode() == ISD::TRUNCATE && 2959 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2960 SDValue Op = N0.getOperand(0); 2961 if (Op.getValueType().bitsLT(VT)) { 2962 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2963 } else if (Op.getValueType().bitsGT(VT)) { 2964 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2965 } 2966 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2967 } 2968 2969 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2970 if (N0.getOpcode() == ISD::AND && 2971 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2972 N0.getOperand(1).getOpcode() == ISD::Constant) { 2973 SDValue X = N0.getOperand(0).getOperand(0); 2974 if (X.getValueType().bitsLT(VT)) { 2975 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2976 } else if (X.getValueType().bitsGT(VT)) { 2977 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2978 } 2979 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2980 Mask.zext(VT.getSizeInBits()); 2981 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2982 } 2983 2984 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2985 if (ISD::isNON_EXTLoad(N0.getNode()) && 2986 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2987 TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2988 bool DoXform = true; 2989 SmallVector<SDNode*, 4> SetCCs; 2990 if (!N0.hasOneUse()) 2991 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2992 if (DoXform) { 2993 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2994 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2995 LN0->getBasePtr(), LN0->getSrcValue(), 2996 LN0->getSrcValueOffset(), 2997 N0.getValueType(), 2998 LN0->isVolatile(), 2999 LN0->getAlignment()); 3000 CombineTo(N, ExtLoad); 3001 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3002 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3003 // Extend SetCC uses if necessary. 3004 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3005 SDNode *SetCC = SetCCs[i]; 3006 SmallVector<SDValue, 4> Ops; 3007 for (unsigned j = 0; j != 2; ++j) { 3008 SDValue SOp = SetCC->getOperand(j); 3009 if (SOp == Trunc) 3010 Ops.push_back(ExtLoad); 3011 else 3012 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3013 } 3014 Ops.push_back(SetCC->getOperand(2)); 3015 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3016 &Ops[0], Ops.size())); 3017 } 3018 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3019 } 3020 } 3021 3022 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3023 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3024 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3025 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3026 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3027 MVT EVT = LN0->getMemoryVT(); 3028 if ((!AfterLegalize && !LN0->isVolatile()) || 3029 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) { 3030 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3031 LN0->getBasePtr(), LN0->getSrcValue(), 3032 LN0->getSrcValueOffset(), EVT, 3033 LN0->isVolatile(), 3034 LN0->getAlignment()); 3035 CombineTo(N, ExtLoad); 3036 CombineTo(N0.getNode(), 3037 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3038 ExtLoad.getValue(1)); 3039 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3040 } 3041 } 3042 3043 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3044 if (N0.getOpcode() == ISD::SETCC) { 3045 SDValue SCC = 3046 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3047 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3048 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3049 if (SCC.getNode()) return SCC; 3050 } 3051 3052 return SDValue(); 3053} 3054 3055SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3056 SDValue N0 = N->getOperand(0); 3057 MVT VT = N->getValueType(0); 3058 3059 // fold (aext c1) -> c1 3060 if (isa<ConstantSDNode>(N0)) 3061 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3062 // fold (aext (aext x)) -> (aext x) 3063 // fold (aext (zext x)) -> (zext x) 3064 // fold (aext (sext x)) -> (sext x) 3065 if (N0.getOpcode() == ISD::ANY_EXTEND || 3066 N0.getOpcode() == ISD::ZERO_EXTEND || 3067 N0.getOpcode() == ISD::SIGN_EXTEND) 3068 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3069 3070 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3071 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3072 if (N0.getOpcode() == ISD::TRUNCATE) { 3073 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3074 if (NarrowLoad.getNode()) { 3075 if (NarrowLoad.getNode() != N0.getNode()) 3076 CombineTo(N0.getNode(), NarrowLoad); 3077 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3078 } 3079 } 3080 3081 // fold (aext (truncate x)) 3082 if (N0.getOpcode() == ISD::TRUNCATE) { 3083 SDValue TruncOp = N0.getOperand(0); 3084 if (TruncOp.getValueType() == VT) 3085 return TruncOp; // x iff x size == zext size. 3086 if (TruncOp.getValueType().bitsGT(VT)) 3087 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3088 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3089 } 3090 3091 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3092 if (N0.getOpcode() == ISD::AND && 3093 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3094 N0.getOperand(1).getOpcode() == ISD::Constant) { 3095 SDValue X = N0.getOperand(0).getOperand(0); 3096 if (X.getValueType().bitsLT(VT)) { 3097 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3098 } else if (X.getValueType().bitsGT(VT)) { 3099 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3100 } 3101 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3102 Mask.zext(VT.getSizeInBits()); 3103 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3104 } 3105 3106 // fold (aext (load x)) -> (aext (truncate (extload x))) 3107 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3108 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3109 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3110 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3111 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3112 LN0->getBasePtr(), LN0->getSrcValue(), 3113 LN0->getSrcValueOffset(), 3114 N0.getValueType(), 3115 LN0->isVolatile(), 3116 LN0->getAlignment()); 3117 CombineTo(N, ExtLoad); 3118 // Redirect any chain users to the new load. 3119 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3120 SDValue(ExtLoad.getNode(), 1)); 3121 // If any node needs the original loaded value, recompute it. 3122 if (!LN0->use_empty()) 3123 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3124 ExtLoad.getValue(1)); 3125 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3126 } 3127 3128 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3129 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3130 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3131 if (N0.getOpcode() == ISD::LOAD && 3132 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3133 N0.hasOneUse()) { 3134 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3135 MVT EVT = LN0->getMemoryVT(); 3136 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3137 LN0->getChain(), LN0->getBasePtr(), 3138 LN0->getSrcValue(), 3139 LN0->getSrcValueOffset(), EVT, 3140 LN0->isVolatile(), 3141 LN0->getAlignment()); 3142 CombineTo(N, ExtLoad); 3143 CombineTo(N0.getNode(), 3144 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3145 ExtLoad.getValue(1)); 3146 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3147 } 3148 3149 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3150 if (N0.getOpcode() == ISD::SETCC) { 3151 SDValue SCC = 3152 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3153 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3154 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3155 if (SCC.getNode()) 3156 return SCC; 3157 } 3158 3159 return SDValue(); 3160} 3161 3162/// GetDemandedBits - See if the specified operand can be simplified with the 3163/// knowledge that only the bits specified by Mask are used. If so, return the 3164/// simpler operand, otherwise return a null SDValue. 3165SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3166 switch (V.getOpcode()) { 3167 default: break; 3168 case ISD::OR: 3169 case ISD::XOR: 3170 // If the LHS or RHS don't contribute bits to the or, drop them. 3171 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3172 return V.getOperand(1); 3173 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3174 return V.getOperand(0); 3175 break; 3176 case ISD::SRL: 3177 // Only look at single-use SRLs. 3178 if (!V.getNode()->hasOneUse()) 3179 break; 3180 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3181 // See if we can recursively simplify the LHS. 3182 unsigned Amt = RHSC->getZExtValue(); 3183 APInt NewMask = Mask << Amt; 3184 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3185 if (SimplifyLHS.getNode()) { 3186 return DAG.getNode(ISD::SRL, V.getValueType(), 3187 SimplifyLHS, V.getOperand(1)); 3188 } 3189 } 3190 } 3191 return SDValue(); 3192} 3193 3194/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3195/// bits and then truncated to a narrower type and where N is a multiple 3196/// of number of bits of the narrower type, transform it to a narrower load 3197/// from address + N / num of bits of new type. If the result is to be 3198/// extended, also fold the extension to form a extending load. 3199SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3200 unsigned Opc = N->getOpcode(); 3201 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3202 SDValue N0 = N->getOperand(0); 3203 MVT VT = N->getValueType(0); 3204 MVT EVT = N->getValueType(0); 3205 3206 // This transformation isn't valid for vector loads. 3207 if (VT.isVector()) 3208 return SDValue(); 3209 3210 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3211 // extended to VT. 3212 if (Opc == ISD::SIGN_EXTEND_INREG) { 3213 ExtType = ISD::SEXTLOAD; 3214 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3215 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3216 return SDValue(); 3217 } 3218 3219 unsigned EVTBits = EVT.getSizeInBits(); 3220 unsigned ShAmt = 0; 3221 bool CombineSRL = false; 3222 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3223 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3224 ShAmt = N01->getZExtValue(); 3225 // Is the shift amount a multiple of size of VT? 3226 if ((ShAmt & (EVTBits-1)) == 0) { 3227 N0 = N0.getOperand(0); 3228 if (N0.getValueType().getSizeInBits() <= EVTBits) 3229 return SDValue(); 3230 CombineSRL = true; 3231 } 3232 } 3233 } 3234 3235 // Do not generate loads of non-round integer types since these can 3236 // be expensive (and would be wrong if the type is not byte sized). 3237 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3238 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3239 // Do not change the width of a volatile load. 3240 !cast<LoadSDNode>(N0)->isVolatile()) { 3241 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3242 MVT PtrType = N0.getOperand(1).getValueType(); 3243 // For big endian targets, we need to adjust the offset to the pointer to 3244 // load the correct bytes. 3245 if (TLI.isBigEndian()) { 3246 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3247 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3248 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3249 } 3250 uint64_t PtrOff = ShAmt / 8; 3251 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3252 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3253 DAG.getConstant(PtrOff, PtrType)); 3254 AddToWorkList(NewPtr.getNode()); 3255 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3256 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3257 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3258 LN0->isVolatile(), NewAlign) 3259 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3260 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3261 EVT, LN0->isVolatile(), NewAlign); 3262 AddToWorkList(N); 3263 if (CombineSRL) { 3264 WorkListRemover DeadNodes(*this); 3265 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3266 &DeadNodes); 3267 CombineTo(N->getOperand(0).getNode(), Load); 3268 } else 3269 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3270 if (ShAmt) { 3271 if (Opc == ISD::SIGN_EXTEND_INREG) 3272 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3273 else 3274 return DAG.getNode(Opc, VT, Load); 3275 } 3276 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3277 } 3278 3279 return SDValue(); 3280} 3281 3282 3283SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3284 SDValue N0 = N->getOperand(0); 3285 SDValue N1 = N->getOperand(1); 3286 MVT VT = N->getValueType(0); 3287 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3288 unsigned VTBits = VT.getSizeInBits(); 3289 unsigned EVTBits = EVT.getSizeInBits(); 3290 3291 // fold (sext_in_reg c1) -> c1 3292 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3293 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3294 3295 // If the input is already sign extended, just drop the extension. 3296 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3297 return N0; 3298 3299 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3300 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3301 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3302 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3303 } 3304 3305 // fold (sext_in_reg (sext x)) -> (sext x) 3306 // fold (sext_in_reg (aext x)) -> (sext x) 3307 // if x is small enough. 3308 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3309 SDValue N00 = N0.getOperand(0); 3310 if (N00.getValueType().getSizeInBits() < EVTBits) 3311 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3312 } 3313 3314 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3315 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3316 return DAG.getZeroExtendInReg(N0, EVT); 3317 3318 // fold operands of sext_in_reg based on knowledge that the top bits are not 3319 // demanded. 3320 if (SimplifyDemandedBits(SDValue(N, 0))) 3321 return SDValue(N, 0); 3322 3323 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3324 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3325 SDValue NarrowLoad = ReduceLoadWidth(N); 3326 if (NarrowLoad.getNode()) 3327 return NarrowLoad; 3328 3329 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3330 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3331 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3332 if (N0.getOpcode() == ISD::SRL) { 3333 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3334 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3335 // We can turn this into an SRA iff the input to the SRL is already sign 3336 // extended enough. 3337 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3338 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3339 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3340 } 3341 } 3342 3343 // fold (sext_inreg (extload x)) -> (sextload x) 3344 if (ISD::isEXTLoad(N0.getNode()) && 3345 ISD::isUNINDEXEDLoad(N0.getNode()) && 3346 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3347 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3348 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3349 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3350 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3351 LN0->getBasePtr(), LN0->getSrcValue(), 3352 LN0->getSrcValueOffset(), EVT, 3353 LN0->isVolatile(), 3354 LN0->getAlignment()); 3355 CombineTo(N, ExtLoad); 3356 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3357 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3358 } 3359 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3360 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3361 N0.hasOneUse() && 3362 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3363 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3364 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3365 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3366 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3367 LN0->getBasePtr(), LN0->getSrcValue(), 3368 LN0->getSrcValueOffset(), EVT, 3369 LN0->isVolatile(), 3370 LN0->getAlignment()); 3371 CombineTo(N, ExtLoad); 3372 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3373 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3374 } 3375 return SDValue(); 3376} 3377 3378SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3379 SDValue N0 = N->getOperand(0); 3380 MVT VT = N->getValueType(0); 3381 3382 // noop truncate 3383 if (N0.getValueType() == N->getValueType(0)) 3384 return N0; 3385 // fold (truncate c1) -> c1 3386 if (isa<ConstantSDNode>(N0)) 3387 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3388 // fold (truncate (truncate x)) -> (truncate x) 3389 if (N0.getOpcode() == ISD::TRUNCATE) 3390 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3391 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3392 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3393 N0.getOpcode() == ISD::ANY_EXTEND) { 3394 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3395 // if the source is smaller than the dest, we still need an extend 3396 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3397 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3398 // if the source is larger than the dest, than we just need the truncate 3399 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3400 else 3401 // if the source and dest are the same type, we can drop both the extend 3402 // and the truncate 3403 return N0.getOperand(0); 3404 } 3405 3406 // See if we can simplify the input to this truncate through knowledge that 3407 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3408 // -> trunc y 3409 SDValue Shorter = 3410 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3411 VT.getSizeInBits())); 3412 if (Shorter.getNode()) 3413 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3414 3415 // fold (truncate (load x)) -> (smaller load x) 3416 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3417 return ReduceLoadWidth(N); 3418} 3419 3420static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3421 SDValue Elt = N->getOperand(i); 3422 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3423 return Elt.getNode(); 3424 return Elt.getOperand(Elt.getResNo()).getNode(); 3425} 3426 3427/// CombineConsecutiveLoads - build_pair (load, load) -> load 3428/// if load locations are consecutive. 3429SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3430 assert(N->getOpcode() == ISD::BUILD_PAIR); 3431 3432 SDNode *LD1 = getBuildPairElt(N, 0); 3433 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3434 return SDValue(); 3435 MVT LD1VT = LD1->getValueType(0); 3436 SDNode *LD2 = getBuildPairElt(N, 1); 3437 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3438 if (ISD::isNON_EXTLoad(LD2) && 3439 LD2->hasOneUse() && 3440 // If both are volatile this would reduce the number of volatile loads. 3441 // If one is volatile it might be ok, but play conservative and bail out. 3442 !cast<LoadSDNode>(LD1)->isVolatile() && 3443 !cast<LoadSDNode>(LD2)->isVolatile() && 3444 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3445 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3446 unsigned Align = LD->getAlignment(); 3447 unsigned NewAlign = TLI.getTargetData()-> 3448 getABITypeAlignment(VT.getTypeForMVT()); 3449 if (NewAlign <= Align && 3450 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3451 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3452 LD->getSrcValue(), LD->getSrcValueOffset(), 3453 false, Align); 3454 } 3455 return SDValue(); 3456} 3457 3458SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3459 SDValue N0 = N->getOperand(0); 3460 MVT VT = N->getValueType(0); 3461 3462 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3463 // Only do this before legalize, since afterward the target may be depending 3464 // on the bitconvert. 3465 // First check to see if this is all constant. 3466 if (!AfterLegalize && 3467 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3468 VT.isVector()) { 3469 bool isSimple = true; 3470 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3471 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3472 N0.getOperand(i).getOpcode() != ISD::Constant && 3473 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3474 isSimple = false; 3475 break; 3476 } 3477 3478 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3479 assert(!DestEltVT.isVector() && 3480 "Element type of vector ValueType must not be vector!"); 3481 if (isSimple) { 3482 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3483 } 3484 } 3485 3486 // If the input is a constant, let getNode fold it. 3487 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3488 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3489 if (Res.getNode() != N) return Res; 3490 } 3491 3492 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3493 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3494 3495 // fold (conv (load x)) -> (load (conv*)x) 3496 // If the resultant load doesn't need a higher alignment than the original! 3497 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3498 // Do not change the width of a volatile load. 3499 !cast<LoadSDNode>(N0)->isVolatile() && 3500 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3501 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3502 unsigned Align = TLI.getTargetData()-> 3503 getABITypeAlignment(VT.getTypeForMVT()); 3504 unsigned OrigAlign = LN0->getAlignment(); 3505 if (Align <= OrigAlign) { 3506 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3507 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3508 LN0->isVolatile(), OrigAlign); 3509 AddToWorkList(N); 3510 CombineTo(N0.getNode(), 3511 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3512 Load.getValue(1)); 3513 return Load; 3514 } 3515 } 3516 3517 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3518 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3519 // This often reduces constant pool loads. 3520 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3521 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3522 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3523 AddToWorkList(NewConv.getNode()); 3524 3525 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3526 if (N0.getOpcode() == ISD::FNEG) 3527 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3528 assert(N0.getOpcode() == ISD::FABS); 3529 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3530 } 3531 3532 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3533 // Note that we don't handle copysign(x,cst) because this can always be folded 3534 // to an fneg or fabs. 3535 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3536 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3537 VT.isInteger() && !VT.isVector()) { 3538 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3539 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3540 MVT::getIntegerVT(OrigXWidth), 3541 N0.getOperand(1)); 3542 AddToWorkList(X.getNode()); 3543 3544 // If X has a different width than the result/lhs, sext it or truncate it. 3545 unsigned VTWidth = VT.getSizeInBits(); 3546 if (OrigXWidth < VTWidth) { 3547 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3548 AddToWorkList(X.getNode()); 3549 } else if (OrigXWidth > VTWidth) { 3550 // To get the sign bit in the right place, we have to shift it right 3551 // before truncating. 3552 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3553 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3554 AddToWorkList(X.getNode()); 3555 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3556 AddToWorkList(X.getNode()); 3557 } 3558 3559 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3560 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3561 AddToWorkList(X.getNode()); 3562 3563 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3564 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3565 AddToWorkList(Cst.getNode()); 3566 3567 return DAG.getNode(ISD::OR, VT, X, Cst); 3568 } 3569 3570 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3571 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3572 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3573 if (CombineLD.getNode()) 3574 return CombineLD; 3575 } 3576 3577 return SDValue(); 3578} 3579 3580SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3581 MVT VT = N->getValueType(0); 3582 return CombineConsecutiveLoads(N, VT); 3583} 3584 3585/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3586/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3587/// destination element value type. 3588SDValue DAGCombiner:: 3589ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3590 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3591 3592 // If this is already the right type, we're done. 3593 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3594 3595 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3596 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3597 3598 // If this is a conversion of N elements of one type to N elements of another 3599 // type, convert each element. This handles FP<->INT cases. 3600 if (SrcBitSize == DstBitSize) { 3601 SmallVector<SDValue, 8> Ops; 3602 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3603 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3604 AddToWorkList(Ops.back().getNode()); 3605 } 3606 MVT VT = MVT::getVectorVT(DstEltVT, 3607 BV->getValueType(0).getVectorNumElements()); 3608 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3609 } 3610 3611 // Otherwise, we're growing or shrinking the elements. To avoid having to 3612 // handle annoying details of growing/shrinking FP values, we convert them to 3613 // int first. 3614 if (SrcEltVT.isFloatingPoint()) { 3615 // Convert the input float vector to a int vector where the elements are the 3616 // same sizes. 3617 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3618 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3619 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3620 SrcEltVT = IntVT; 3621 } 3622 3623 // Now we know the input is an integer vector. If the output is a FP type, 3624 // convert to integer first, then to FP of the right size. 3625 if (DstEltVT.isFloatingPoint()) { 3626 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3627 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3628 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3629 3630 // Next, convert to FP elements of the same size. 3631 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3632 } 3633 3634 // Okay, we know the src/dst types are both integers of differing types. 3635 // Handling growing first. 3636 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3637 if (SrcBitSize < DstBitSize) { 3638 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3639 3640 SmallVector<SDValue, 8> Ops; 3641 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3642 i += NumInputsPerOutput) { 3643 bool isLE = TLI.isLittleEndian(); 3644 APInt NewBits = APInt(DstBitSize, 0); 3645 bool EltIsUndef = true; 3646 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3647 // Shift the previously computed bits over. 3648 NewBits <<= SrcBitSize; 3649 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3650 if (Op.getOpcode() == ISD::UNDEF) continue; 3651 EltIsUndef = false; 3652 3653 NewBits |= 3654 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3655 } 3656 3657 if (EltIsUndef) 3658 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3659 else 3660 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3661 } 3662 3663 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3664 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3665 } 3666 3667 // Finally, this must be the case where we are shrinking elements: each input 3668 // turns into multiple outputs. 3669 bool isS2V = ISD::isScalarToVector(BV); 3670 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3671 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3672 SmallVector<SDValue, 8> Ops; 3673 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3674 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3675 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3676 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3677 continue; 3678 } 3679 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3680 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3681 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3682 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3683 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3684 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3685 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3686 OpVal = OpVal.lshr(DstBitSize); 3687 } 3688 3689 // For big endian targets, swap the order of the pieces of each element. 3690 if (TLI.isBigEndian()) 3691 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3692 } 3693 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3694} 3695 3696 3697 3698SDValue DAGCombiner::visitFADD(SDNode *N) { 3699 SDValue N0 = N->getOperand(0); 3700 SDValue N1 = N->getOperand(1); 3701 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3702 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3703 MVT VT = N->getValueType(0); 3704 3705 // fold vector ops 3706 if (VT.isVector()) { 3707 SDValue FoldedVOp = SimplifyVBinOp(N); 3708 if (FoldedVOp.getNode()) return FoldedVOp; 3709 } 3710 3711 // fold (fadd c1, c2) -> c1+c2 3712 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3713 return DAG.getNode(ISD::FADD, VT, N0, N1); 3714 // canonicalize constant to RHS 3715 if (N0CFP && !N1CFP) 3716 return DAG.getNode(ISD::FADD, VT, N1, N0); 3717 // fold (A + (-B)) -> A-B 3718 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3719 return DAG.getNode(ISD::FSUB, VT, N0, 3720 GetNegatedExpression(N1, DAG, AfterLegalize)); 3721 // fold ((-A) + B) -> B-A 3722 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3723 return DAG.getNode(ISD::FSUB, VT, N1, 3724 GetNegatedExpression(N0, DAG, AfterLegalize)); 3725 3726 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3727 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3728 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3729 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3730 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3731 3732 return SDValue(); 3733} 3734 3735SDValue DAGCombiner::visitFSUB(SDNode *N) { 3736 SDValue N0 = N->getOperand(0); 3737 SDValue N1 = N->getOperand(1); 3738 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3739 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3740 MVT VT = N->getValueType(0); 3741 3742 // fold vector ops 3743 if (VT.isVector()) { 3744 SDValue FoldedVOp = SimplifyVBinOp(N); 3745 if (FoldedVOp.getNode()) return FoldedVOp; 3746 } 3747 3748 // fold (fsub c1, c2) -> c1-c2 3749 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3750 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3751 // fold (0-B) -> -B 3752 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3753 if (isNegatibleForFree(N1, AfterLegalize)) 3754 return GetNegatedExpression(N1, DAG, AfterLegalize); 3755 return DAG.getNode(ISD::FNEG, VT, N1); 3756 } 3757 // fold (A-(-B)) -> A+B 3758 if (isNegatibleForFree(N1, AfterLegalize)) 3759 return DAG.getNode(ISD::FADD, VT, N0, 3760 GetNegatedExpression(N1, DAG, AfterLegalize)); 3761 3762 return SDValue(); 3763} 3764 3765SDValue DAGCombiner::visitFMUL(SDNode *N) { 3766 SDValue N0 = N->getOperand(0); 3767 SDValue N1 = N->getOperand(1); 3768 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3769 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3770 MVT VT = N->getValueType(0); 3771 3772 // fold vector ops 3773 if (VT.isVector()) { 3774 SDValue FoldedVOp = SimplifyVBinOp(N); 3775 if (FoldedVOp.getNode()) return FoldedVOp; 3776 } 3777 3778 // fold (fmul c1, c2) -> c1*c2 3779 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3780 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3781 // canonicalize constant to RHS 3782 if (N0CFP && !N1CFP) 3783 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3784 // fold (fmul X, 2.0) -> (fadd X, X) 3785 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3786 return DAG.getNode(ISD::FADD, VT, N0, N0); 3787 // fold (fmul X, -1.0) -> (fneg X) 3788 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3789 return DAG.getNode(ISD::FNEG, VT, N0); 3790 3791 // -X * -Y -> X*Y 3792 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3793 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3794 // Both can be negated for free, check to see if at least one is cheaper 3795 // negated. 3796 if (LHSNeg == 2 || RHSNeg == 2) 3797 return DAG.getNode(ISD::FMUL, VT, 3798 GetNegatedExpression(N0, DAG, AfterLegalize), 3799 GetNegatedExpression(N1, DAG, AfterLegalize)); 3800 } 3801 } 3802 3803 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3804 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3805 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3806 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3807 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3808 3809 return SDValue(); 3810} 3811 3812SDValue DAGCombiner::visitFDIV(SDNode *N) { 3813 SDValue N0 = N->getOperand(0); 3814 SDValue N1 = N->getOperand(1); 3815 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3816 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3817 MVT VT = N->getValueType(0); 3818 3819 // fold vector ops 3820 if (VT.isVector()) { 3821 SDValue FoldedVOp = SimplifyVBinOp(N); 3822 if (FoldedVOp.getNode()) return FoldedVOp; 3823 } 3824 3825 // fold (fdiv c1, c2) -> c1/c2 3826 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3827 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3828 3829 3830 // -X / -Y -> X*Y 3831 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3832 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3833 // Both can be negated for free, check to see if at least one is cheaper 3834 // negated. 3835 if (LHSNeg == 2 || RHSNeg == 2) 3836 return DAG.getNode(ISD::FDIV, VT, 3837 GetNegatedExpression(N0, DAG, AfterLegalize), 3838 GetNegatedExpression(N1, DAG, AfterLegalize)); 3839 } 3840 } 3841 3842 return SDValue(); 3843} 3844 3845SDValue DAGCombiner::visitFREM(SDNode *N) { 3846 SDValue N0 = N->getOperand(0); 3847 SDValue N1 = N->getOperand(1); 3848 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3849 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3850 MVT VT = N->getValueType(0); 3851 3852 // fold (frem c1, c2) -> fmod(c1,c2) 3853 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3854 return DAG.getNode(ISD::FREM, VT, N0, N1); 3855 3856 return SDValue(); 3857} 3858 3859SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3860 SDValue N0 = N->getOperand(0); 3861 SDValue N1 = N->getOperand(1); 3862 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3863 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3864 MVT VT = N->getValueType(0); 3865 3866 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3867 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3868 3869 if (N1CFP) { 3870 const APFloat& V = N1CFP->getValueAPF(); 3871 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3872 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3873 if (!V.isNegative()) 3874 return DAG.getNode(ISD::FABS, VT, N0); 3875 else 3876 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3877 } 3878 3879 // copysign(fabs(x), y) -> copysign(x, y) 3880 // copysign(fneg(x), y) -> copysign(x, y) 3881 // copysign(copysign(x,z), y) -> copysign(x, y) 3882 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3883 N0.getOpcode() == ISD::FCOPYSIGN) 3884 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3885 3886 // copysign(x, abs(y)) -> abs(x) 3887 if (N1.getOpcode() == ISD::FABS) 3888 return DAG.getNode(ISD::FABS, VT, N0); 3889 3890 // copysign(x, copysign(y,z)) -> copysign(x, z) 3891 if (N1.getOpcode() == ISD::FCOPYSIGN) 3892 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3893 3894 // copysign(x, fp_extend(y)) -> copysign(x, y) 3895 // copysign(x, fp_round(y)) -> copysign(x, y) 3896 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3897 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3898 3899 return SDValue(); 3900} 3901 3902 3903 3904SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3905 SDValue N0 = N->getOperand(0); 3906 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3907 MVT VT = N->getValueType(0); 3908 MVT OpVT = N0.getValueType(); 3909 3910 // fold (sint_to_fp c1) -> c1fp 3911 if (N0C && OpVT != MVT::ppcf128) 3912 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3913 3914 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3915 // but UINT_TO_FP is legal on this target, try to convert. 3916 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3917 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3918 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3919 if (DAG.SignBitIsZero(N0)) 3920 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3921 } 3922 3923 3924 return SDValue(); 3925} 3926 3927SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3928 SDValue N0 = N->getOperand(0); 3929 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3930 MVT VT = N->getValueType(0); 3931 MVT OpVT = N0.getValueType(); 3932 3933 // fold (uint_to_fp c1) -> c1fp 3934 if (N0C && OpVT != MVT::ppcf128) 3935 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3936 3937 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3938 // but SINT_TO_FP is legal on this target, try to convert. 3939 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3940 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3941 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3942 if (DAG.SignBitIsZero(N0)) 3943 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3944 } 3945 3946 return SDValue(); 3947} 3948 3949SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3950 SDValue N0 = N->getOperand(0); 3951 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3952 MVT VT = N->getValueType(0); 3953 3954 // fold (fp_to_sint c1fp) -> c1 3955 if (N0CFP) 3956 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3957 return SDValue(); 3958} 3959 3960SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3961 SDValue N0 = N->getOperand(0); 3962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3963 MVT VT = N->getValueType(0); 3964 3965 // fold (fp_to_uint c1fp) -> c1 3966 if (N0CFP && VT != MVT::ppcf128) 3967 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3968 return SDValue(); 3969} 3970 3971SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 3972 SDValue N0 = N->getOperand(0); 3973 SDValue N1 = N->getOperand(1); 3974 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3975 MVT VT = N->getValueType(0); 3976 3977 // fold (fp_round c1fp) -> c1fp 3978 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3979 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3980 3981 // fold (fp_round (fp_extend x)) -> x 3982 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3983 return N0.getOperand(0); 3984 3985 // fold (fp_round (fp_round x)) -> (fp_round x) 3986 if (N0.getOpcode() == ISD::FP_ROUND) { 3987 // This is a value preserving truncation if both round's are. 3988 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3989 N0.getNode()->getConstantOperandVal(1) == 1; 3990 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3991 DAG.getIntPtrConstant(IsTrunc)); 3992 } 3993 3994 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3995 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 3996 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3997 AddToWorkList(Tmp.getNode()); 3998 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3999 } 4000 4001 return SDValue(); 4002} 4003 4004SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4005 SDValue N0 = N->getOperand(0); 4006 MVT VT = N->getValueType(0); 4007 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4008 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4009 4010 // fold (fp_round_inreg c1fp) -> c1fp 4011 if (N0CFP) { 4012 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4013 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4014 } 4015 return SDValue(); 4016} 4017 4018SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4019 SDValue N0 = N->getOperand(0); 4020 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4021 MVT VT = N->getValueType(0); 4022 4023 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4024 if (N->hasOneUse() && 4025 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4026 return SDValue(); 4027 4028 // fold (fp_extend c1fp) -> c1fp 4029 if (N0CFP && VT != MVT::ppcf128) 4030 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4031 4032 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4033 // value of X. 4034 if (N0.getOpcode() == ISD::FP_ROUND 4035 && N0.getNode()->getConstantOperandVal(1) == 1) { 4036 SDValue In = N0.getOperand(0); 4037 if (In.getValueType() == VT) return In; 4038 if (VT.bitsLT(In.getValueType())) 4039 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4040 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4041 } 4042 4043 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4044 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4045 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 4046 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 4047 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4048 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4049 LN0->getBasePtr(), LN0->getSrcValue(), 4050 LN0->getSrcValueOffset(), 4051 N0.getValueType(), 4052 LN0->isVolatile(), 4053 LN0->getAlignment()); 4054 CombineTo(N, ExtLoad); 4055 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4056 ExtLoad, DAG.getIntPtrConstant(1)), 4057 ExtLoad.getValue(1)); 4058 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4059 } 4060 4061 return SDValue(); 4062} 4063 4064SDValue DAGCombiner::visitFNEG(SDNode *N) { 4065 SDValue N0 = N->getOperand(0); 4066 4067 if (isNegatibleForFree(N0, AfterLegalize)) 4068 return GetNegatedExpression(N0, DAG, AfterLegalize); 4069 4070 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4071 // constant pool values. 4072 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4073 N0.getOperand(0).getValueType().isInteger() && 4074 !N0.getOperand(0).getValueType().isVector()) { 4075 SDValue Int = N0.getOperand(0); 4076 MVT IntVT = Int.getValueType(); 4077 if (IntVT.isInteger() && !IntVT.isVector()) { 4078 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4079 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4080 AddToWorkList(Int.getNode()); 4081 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4082 } 4083 } 4084 4085 return SDValue(); 4086} 4087 4088SDValue DAGCombiner::visitFABS(SDNode *N) { 4089 SDValue N0 = N->getOperand(0); 4090 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4091 MVT VT = N->getValueType(0); 4092 4093 // fold (fabs c1) -> fabs(c1) 4094 if (N0CFP && VT != MVT::ppcf128) 4095 return DAG.getNode(ISD::FABS, VT, N0); 4096 // fold (fabs (fabs x)) -> (fabs x) 4097 if (N0.getOpcode() == ISD::FABS) 4098 return N->getOperand(0); 4099 // fold (fabs (fneg x)) -> (fabs x) 4100 // fold (fabs (fcopysign x, y)) -> (fabs x) 4101 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4102 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4103 4104 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4105 // constant pool values. 4106 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4107 N0.getOperand(0).getValueType().isInteger() && 4108 !N0.getOperand(0).getValueType().isVector()) { 4109 SDValue Int = N0.getOperand(0); 4110 MVT IntVT = Int.getValueType(); 4111 if (IntVT.isInteger() && !IntVT.isVector()) { 4112 Int = DAG.getNode(ISD::AND, IntVT, Int, 4113 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4114 AddToWorkList(Int.getNode()); 4115 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4116 } 4117 } 4118 4119 return SDValue(); 4120} 4121 4122SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4123 SDValue Chain = N->getOperand(0); 4124 SDValue N1 = N->getOperand(1); 4125 SDValue N2 = N->getOperand(2); 4126 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4127 4128 // never taken branch, fold to chain 4129 if (N1C && N1C->isNullValue()) 4130 return Chain; 4131 // unconditional branch 4132 if (N1C && N1C->getAPIntValue() == 1) 4133 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4134 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4135 // on the target. 4136 if (N1.getOpcode() == ISD::SETCC && 4137 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4138 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4139 N1.getOperand(0), N1.getOperand(1), N2); 4140 } 4141 return SDValue(); 4142} 4143 4144// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4145// 4146SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4147 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4148 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4149 4150 // Use SimplifySetCC to simplify SETCC's. 4151 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4152 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4153 4154 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4155 4156 // fold br_cc true, dest -> br dest (unconditional branch) 4157 if (SCCC && !SCCC->isNullValue()) 4158 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4159 N->getOperand(4)); 4160 // fold br_cc false, dest -> unconditional fall through 4161 if (SCCC && SCCC->isNullValue()) 4162 return N->getOperand(0); 4163 4164 // fold to a simpler setcc 4165 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4166 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4167 Simp.getOperand(2), Simp.getOperand(0), 4168 Simp.getOperand(1), N->getOperand(4)); 4169 return SDValue(); 4170} 4171 4172 4173/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4174/// pre-indexed load / store when the base pointer is an add or subtract 4175/// and it has other uses besides the load / store. After the 4176/// transformation, the new indexed load / store has effectively folded 4177/// the add / subtract in and all of its other uses are redirected to the 4178/// new load / store. 4179bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4180 if (!AfterLegalize) 4181 return false; 4182 4183 bool isLoad = true; 4184 SDValue Ptr; 4185 MVT VT; 4186 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4187 if (LD->isIndexed()) 4188 return false; 4189 VT = LD->getMemoryVT(); 4190 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4191 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4192 return false; 4193 Ptr = LD->getBasePtr(); 4194 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4195 if (ST->isIndexed()) 4196 return false; 4197 VT = ST->getMemoryVT(); 4198 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4199 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4200 return false; 4201 Ptr = ST->getBasePtr(); 4202 isLoad = false; 4203 } else 4204 return false; 4205 4206 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4207 // out. There is no reason to make this a preinc/predec. 4208 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4209 Ptr.getNode()->hasOneUse()) 4210 return false; 4211 4212 // Ask the target to do addressing mode selection. 4213 SDValue BasePtr; 4214 SDValue Offset; 4215 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4216 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4217 return false; 4218 // Don't create a indexed load / store with zero offset. 4219 if (isa<ConstantSDNode>(Offset) && 4220 cast<ConstantSDNode>(Offset)->isNullValue()) 4221 return false; 4222 4223 // Try turning it into a pre-indexed load / store except when: 4224 // 1) The new base ptr is a frame index. 4225 // 2) If N is a store and the new base ptr is either the same as or is a 4226 // predecessor of the value being stored. 4227 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4228 // that would create a cycle. 4229 // 4) All uses are load / store ops that use it as old base ptr. 4230 4231 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4232 // (plus the implicit offset) to a register to preinc anyway. 4233 if (isa<FrameIndexSDNode>(BasePtr)) 4234 return false; 4235 4236 // Check #2. 4237 if (!isLoad) { 4238 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4239 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4240 return false; 4241 } 4242 4243 // Now check for #3 and #4. 4244 bool RealUse = false; 4245 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4246 E = Ptr.getNode()->use_end(); I != E; ++I) { 4247 SDNode *Use = *I; 4248 if (Use == N) 4249 continue; 4250 if (Use->isPredecessorOf(N)) 4251 return false; 4252 4253 if (!((Use->getOpcode() == ISD::LOAD && 4254 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4255 (Use->getOpcode() == ISD::STORE && 4256 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4257 RealUse = true; 4258 } 4259 if (!RealUse) 4260 return false; 4261 4262 SDValue Result; 4263 if (isLoad) 4264 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4265 else 4266 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4267 ++PreIndexedNodes; 4268 ++NodesCombined; 4269 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4270 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4271 DOUT << '\n'; 4272 WorkListRemover DeadNodes(*this); 4273 if (isLoad) { 4274 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4275 &DeadNodes); 4276 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4277 &DeadNodes); 4278 } else { 4279 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4280 &DeadNodes); 4281 } 4282 4283 // Finally, since the node is now dead, remove it from the graph. 4284 DAG.DeleteNode(N); 4285 4286 // Replace the uses of Ptr with uses of the updated base value. 4287 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4288 &DeadNodes); 4289 removeFromWorkList(Ptr.getNode()); 4290 DAG.DeleteNode(Ptr.getNode()); 4291 4292 return true; 4293} 4294 4295/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4296/// add / sub of the base pointer node into a post-indexed load / store. 4297/// The transformation folded the add / subtract into the new indexed 4298/// load / store effectively and all of its uses are redirected to the 4299/// new load / store. 4300bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4301 if (!AfterLegalize) 4302 return false; 4303 4304 bool isLoad = true; 4305 SDValue Ptr; 4306 MVT VT; 4307 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4308 if (LD->isIndexed()) 4309 return false; 4310 VT = LD->getMemoryVT(); 4311 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4312 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4313 return false; 4314 Ptr = LD->getBasePtr(); 4315 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4316 if (ST->isIndexed()) 4317 return false; 4318 VT = ST->getMemoryVT(); 4319 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4320 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4321 return false; 4322 Ptr = ST->getBasePtr(); 4323 isLoad = false; 4324 } else 4325 return false; 4326 4327 if (Ptr.getNode()->hasOneUse()) 4328 return false; 4329 4330 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4331 E = Ptr.getNode()->use_end(); I != E; ++I) { 4332 SDNode *Op = *I; 4333 if (Op == N || 4334 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4335 continue; 4336 4337 SDValue BasePtr; 4338 SDValue Offset; 4339 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4340 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4341 if (Ptr == Offset) 4342 std::swap(BasePtr, Offset); 4343 if (Ptr != BasePtr) 4344 continue; 4345 // Don't create a indexed load / store with zero offset. 4346 if (isa<ConstantSDNode>(Offset) && 4347 cast<ConstantSDNode>(Offset)->isNullValue()) 4348 continue; 4349 4350 // Try turning it into a post-indexed load / store except when 4351 // 1) All uses are load / store ops that use it as base ptr. 4352 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4353 // nor a successor of N. Otherwise, if Op is folded that would 4354 // create a cycle. 4355 4356 // Check for #1. 4357 bool TryNext = false; 4358 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4359 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4360 SDNode *Use = *II; 4361 if (Use == Ptr.getNode()) 4362 continue; 4363 4364 // If all the uses are load / store addresses, then don't do the 4365 // transformation. 4366 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4367 bool RealUse = false; 4368 for (SDNode::use_iterator III = Use->use_begin(), 4369 EEE = Use->use_end(); III != EEE; ++III) { 4370 SDNode *UseUse = *III; 4371 if (!((UseUse->getOpcode() == ISD::LOAD && 4372 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4373 (UseUse->getOpcode() == ISD::STORE && 4374 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4375 RealUse = true; 4376 } 4377 4378 if (!RealUse) { 4379 TryNext = true; 4380 break; 4381 } 4382 } 4383 } 4384 if (TryNext) 4385 continue; 4386 4387 // Check for #2 4388 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4389 SDValue Result = isLoad 4390 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4391 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4392 ++PostIndexedNodes; 4393 ++NodesCombined; 4394 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4395 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4396 DOUT << '\n'; 4397 WorkListRemover DeadNodes(*this); 4398 if (isLoad) { 4399 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4400 &DeadNodes); 4401 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4402 &DeadNodes); 4403 } else { 4404 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4405 &DeadNodes); 4406 } 4407 4408 // Finally, since the node is now dead, remove it from the graph. 4409 DAG.DeleteNode(N); 4410 4411 // Replace the uses of Use with uses of the updated base value. 4412 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4413 Result.getValue(isLoad ? 1 : 0), 4414 &DeadNodes); 4415 removeFromWorkList(Op); 4416 DAG.DeleteNode(Op); 4417 return true; 4418 } 4419 } 4420 } 4421 return false; 4422} 4423 4424/// InferAlignment - If we can infer some alignment information from this 4425/// pointer, return it. 4426static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4427 // If this is a direct reference to a stack slot, use information about the 4428 // stack slot's alignment. 4429 int FrameIdx = 1 << 31; 4430 int64_t FrameOffset = 0; 4431 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4432 FrameIdx = FI->getIndex(); 4433 } else if (Ptr.getOpcode() == ISD::ADD && 4434 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4435 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4436 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4437 FrameOffset = Ptr.getConstantOperandVal(1); 4438 } 4439 4440 if (FrameIdx != (1 << 31)) { 4441 // FIXME: Handle FI+CST. 4442 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4443 if (MFI.isFixedObjectIndex(FrameIdx)) { 4444 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4445 4446 // The alignment of the frame index can be determined from its offset from 4447 // the incoming frame position. If the frame object is at offset 32 and 4448 // the stack is guaranteed to be 16-byte aligned, then we know that the 4449 // object is 16-byte aligned. 4450 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4451 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4452 4453 // Finally, the frame object itself may have a known alignment. Factor 4454 // the alignment + offset into a new alignment. For example, if we know 4455 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4456 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4457 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4458 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4459 FrameOffset); 4460 return std::max(Align, FIInfoAlign); 4461 } 4462 } 4463 4464 return 0; 4465} 4466 4467SDValue DAGCombiner::visitLOAD(SDNode *N) { 4468 LoadSDNode *LD = cast<LoadSDNode>(N); 4469 SDValue Chain = LD->getChain(); 4470 SDValue Ptr = LD->getBasePtr(); 4471 4472 // Try to infer better alignment information than the load already has. 4473 if (!Fast && LD->isUnindexed()) { 4474 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4475 if (Align > LD->getAlignment()) 4476 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4477 Chain, Ptr, LD->getSrcValue(), 4478 LD->getSrcValueOffset(), LD->getMemoryVT(), 4479 LD->isVolatile(), Align); 4480 } 4481 } 4482 4483 4484 // If load is not volatile and there are no uses of the loaded value (and 4485 // the updated indexed value in case of indexed loads), change uses of the 4486 // chain value into uses of the chain input (i.e. delete the dead load). 4487 if (!LD->isVolatile()) { 4488 if (N->getValueType(1) == MVT::Other) { 4489 // Unindexed loads. 4490 if (N->hasNUsesOfValue(0, 0)) { 4491 // It's not safe to use the two value CombineTo variant here. e.g. 4492 // v1, chain2 = load chain1, loc 4493 // v2, chain3 = load chain2, loc 4494 // v3 = add v2, c 4495 // Now we replace use of chain2 with chain1. This makes the second load 4496 // isomorphic to the one we are deleting, and thus makes this load live. 4497 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4498 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4499 DOUT << "\n"; 4500 WorkListRemover DeadNodes(*this); 4501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4502 if (N->use_empty()) { 4503 removeFromWorkList(N); 4504 DAG.DeleteNode(N); 4505 } 4506 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4507 } 4508 } else { 4509 // Indexed loads. 4510 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4511 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4512 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4513 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4514 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4515 DOUT << " and 2 other values\n"; 4516 WorkListRemover DeadNodes(*this); 4517 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4518 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4519 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4520 &DeadNodes); 4521 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4522 removeFromWorkList(N); 4523 DAG.DeleteNode(N); 4524 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4525 } 4526 } 4527 } 4528 4529 // If this load is directly stored, replace the load value with the stored 4530 // value. 4531 // TODO: Handle store large -> read small portion. 4532 // TODO: Handle TRUNCSTORE/LOADEXT 4533 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4534 !LD->isVolatile()) { 4535 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4536 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4537 if (PrevST->getBasePtr() == Ptr && 4538 PrevST->getValue().getValueType() == N->getValueType(0)) 4539 return CombineTo(N, Chain.getOperand(1), Chain); 4540 } 4541 } 4542 4543 if (CombinerAA) { 4544 // Walk up chain skipping non-aliasing memory nodes. 4545 SDValue BetterChain = FindBetterChain(N, Chain); 4546 4547 // If there is a better chain. 4548 if (Chain != BetterChain) { 4549 SDValue ReplLoad; 4550 4551 // Replace the chain to void dependency. 4552 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4553 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4554 LD->getSrcValue(), LD->getSrcValueOffset(), 4555 LD->isVolatile(), LD->getAlignment()); 4556 } else { 4557 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4558 LD->getValueType(0), 4559 BetterChain, Ptr, LD->getSrcValue(), 4560 LD->getSrcValueOffset(), 4561 LD->getMemoryVT(), 4562 LD->isVolatile(), 4563 LD->getAlignment()); 4564 } 4565 4566 // Create token factor to keep old chain connected. 4567 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4568 Chain, ReplLoad.getValue(1)); 4569 4570 // Replace uses with load result and token factor. Don't add users 4571 // to work list. 4572 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4573 } 4574 } 4575 4576 // Try transforming N to an indexed load. 4577 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4578 return SDValue(N, 0); 4579 4580 return SDValue(); 4581} 4582 4583 4584SDValue DAGCombiner::visitSTORE(SDNode *N) { 4585 StoreSDNode *ST = cast<StoreSDNode>(N); 4586 SDValue Chain = ST->getChain(); 4587 SDValue Value = ST->getValue(); 4588 SDValue Ptr = ST->getBasePtr(); 4589 4590 // Try to infer better alignment information than the store already has. 4591 if (!Fast && ST->isUnindexed()) { 4592 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4593 if (Align > ST->getAlignment()) 4594 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4595 ST->getSrcValueOffset(), ST->getMemoryVT(), 4596 ST->isVolatile(), Align); 4597 } 4598 } 4599 4600 // If this is a store of a bit convert, store the input value if the 4601 // resultant store does not need a higher alignment than the original. 4602 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4603 ST->isUnindexed()) { 4604 unsigned Align = ST->getAlignment(); 4605 MVT SVT = Value.getOperand(0).getValueType(); 4606 unsigned OrigAlign = TLI.getTargetData()-> 4607 getABITypeAlignment(SVT.getTypeForMVT()); 4608 if (Align <= OrigAlign && 4609 ((!AfterLegalize && !ST->isVolatile()) || 4610 TLI.isOperationLegal(ISD::STORE, SVT))) 4611 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4612 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4613 } 4614 4615 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4616 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4617 // NOTE: If the original store is volatile, this transform must not increase 4618 // the number of stores. For example, on x86-32 an f64 can be stored in one 4619 // processor operation but an i64 (which is not legal) requires two. So the 4620 // transform should not be done in this case. 4621 if (Value.getOpcode() != ISD::TargetConstantFP) { 4622 SDValue Tmp; 4623 switch (CFP->getValueType(0).getSimpleVT()) { 4624 default: assert(0 && "Unknown FP type"); 4625 case MVT::f80: // We don't do this for these yet. 4626 case MVT::f128: 4627 case MVT::ppcf128: 4628 break; 4629 case MVT::f32: 4630 if ((!AfterLegalize && !ST->isVolatile()) || 4631 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4632 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4633 convertToAPInt().getZExtValue(), MVT::i32); 4634 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4635 ST->getSrcValueOffset(), ST->isVolatile(), 4636 ST->getAlignment()); 4637 } 4638 break; 4639 case MVT::f64: 4640 if ((!AfterLegalize && !ST->isVolatile()) || 4641 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4642 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4643 getZExtValue(), MVT::i64); 4644 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4645 ST->getSrcValueOffset(), ST->isVolatile(), 4646 ST->getAlignment()); 4647 } else if (!ST->isVolatile() && 4648 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4649 // Many FP stores are not made apparent until after legalize, e.g. for 4650 // argument passing. Since this is so common, custom legalize the 4651 // 64-bit integer store into two 32-bit stores. 4652 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4653 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4654 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4655 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4656 4657 int SVOffset = ST->getSrcValueOffset(); 4658 unsigned Alignment = ST->getAlignment(); 4659 bool isVolatile = ST->isVolatile(); 4660 4661 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4662 ST->getSrcValueOffset(), 4663 isVolatile, ST->getAlignment()); 4664 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4665 DAG.getConstant(4, Ptr.getValueType())); 4666 SVOffset += 4; 4667 Alignment = MinAlign(Alignment, 4U); 4668 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4669 SVOffset, isVolatile, Alignment); 4670 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4671 } 4672 break; 4673 } 4674 } 4675 } 4676 4677 if (CombinerAA) { 4678 // Walk up chain skipping non-aliasing memory nodes. 4679 SDValue BetterChain = FindBetterChain(N, Chain); 4680 4681 // If there is a better chain. 4682 if (Chain != BetterChain) { 4683 // Replace the chain to avoid dependency. 4684 SDValue ReplStore; 4685 if (ST->isTruncatingStore()) { 4686 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4687 ST->getSrcValue(),ST->getSrcValueOffset(), 4688 ST->getMemoryVT(), 4689 ST->isVolatile(), ST->getAlignment()); 4690 } else { 4691 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4692 ST->getSrcValue(), ST->getSrcValueOffset(), 4693 ST->isVolatile(), ST->getAlignment()); 4694 } 4695 4696 // Create token to keep both nodes around. 4697 SDValue Token = 4698 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4699 4700 // Don't add users to work list. 4701 return CombineTo(N, Token, false); 4702 } 4703 } 4704 4705 // Try transforming N to an indexed store. 4706 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4707 return SDValue(N, 0); 4708 4709 // FIXME: is there such a thing as a truncating indexed store? 4710 if (ST->isTruncatingStore() && ST->isUnindexed() && 4711 Value.getValueType().isInteger()) { 4712 // See if we can simplify the input to this truncstore with knowledge that 4713 // only the low bits are being used. For example: 4714 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4715 SDValue Shorter = 4716 GetDemandedBits(Value, 4717 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4718 ST->getMemoryVT().getSizeInBits())); 4719 AddToWorkList(Value.getNode()); 4720 if (Shorter.getNode()) 4721 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4722 ST->getSrcValueOffset(), ST->getMemoryVT(), 4723 ST->isVolatile(), ST->getAlignment()); 4724 4725 // Otherwise, see if we can simplify the operation with 4726 // SimplifyDemandedBits, which only works if the value has a single use. 4727 if (SimplifyDemandedBits(Value, 4728 APInt::getLowBitsSet( 4729 Value.getValueSizeInBits(), 4730 ST->getMemoryVT().getSizeInBits()))) 4731 return SDValue(N, 0); 4732 } 4733 4734 // If this is a load followed by a store to the same location, then the store 4735 // is dead/noop. 4736 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4737 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4738 ST->isUnindexed() && !ST->isVolatile() && 4739 // There can't be any side effects between the load and store, such as 4740 // a call or store. 4741 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4742 // The store is dead, remove it. 4743 return Chain; 4744 } 4745 } 4746 4747 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4748 // truncating store. We can do this even if this is already a truncstore. 4749 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4750 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4751 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4752 ST->getMemoryVT())) { 4753 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4754 ST->getSrcValueOffset(), ST->getMemoryVT(), 4755 ST->isVolatile(), ST->getAlignment()); 4756 } 4757 4758 return SDValue(); 4759} 4760 4761SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4762 SDValue InVec = N->getOperand(0); 4763 SDValue InVal = N->getOperand(1); 4764 SDValue EltNo = N->getOperand(2); 4765 4766 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4767 // vector with the inserted element. 4768 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4769 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4770 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4771 InVec.getNode()->op_end()); 4772 if (Elt < Ops.size()) 4773 Ops[Elt] = InVal; 4774 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4775 &Ops[0], Ops.size()); 4776 } 4777 4778 return SDValue(); 4779} 4780 4781SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4782 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4783 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4784 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4785 4786 // Perform only after legalization to ensure build_vector / vector_shuffle 4787 // optimizations have already been done. 4788 if (!AfterLegalize) return SDValue(); 4789 4790 SDValue InVec = N->getOperand(0); 4791 SDValue EltNo = N->getOperand(1); 4792 4793 if (isa<ConstantSDNode>(EltNo)) { 4794 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4795 bool NewLoad = false; 4796 MVT VT = InVec.getValueType(); 4797 MVT EVT = VT.getVectorElementType(); 4798 MVT LVT = EVT; 4799 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4800 MVT BCVT = InVec.getOperand(0).getValueType(); 4801 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4802 return SDValue(); 4803 InVec = InVec.getOperand(0); 4804 EVT = BCVT.getVectorElementType(); 4805 NewLoad = true; 4806 } 4807 4808 LoadSDNode *LN0 = NULL; 4809 if (ISD::isNormalLoad(InVec.getNode())) 4810 LN0 = cast<LoadSDNode>(InVec); 4811 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4812 InVec.getOperand(0).getValueType() == EVT && 4813 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4814 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4815 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4816 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4817 // => 4818 // (load $addr+1*size) 4819 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4820 getOperand(Elt))->getZExtValue(); 4821 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4822 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4823 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4824 InVec = InVec.getOperand(0); 4825 if (ISD::isNormalLoad(InVec.getNode())) { 4826 LN0 = cast<LoadSDNode>(InVec); 4827 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4828 } 4829 } 4830 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4831 return SDValue(); 4832 4833 unsigned Align = LN0->getAlignment(); 4834 if (NewLoad) { 4835 // Check the resultant load doesn't need a higher alignment than the 4836 // original load. 4837 unsigned NewAlign = TLI.getTargetData()-> 4838 getABITypeAlignment(LVT.getTypeForMVT()); 4839 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4840 return SDValue(); 4841 Align = NewAlign; 4842 } 4843 4844 SDValue NewPtr = LN0->getBasePtr(); 4845 if (Elt) { 4846 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4847 MVT PtrType = NewPtr.getValueType(); 4848 if (TLI.isBigEndian()) 4849 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4850 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4851 DAG.getConstant(PtrOff, PtrType)); 4852 } 4853 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4854 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4855 LN0->isVolatile(), Align); 4856 } 4857 return SDValue(); 4858} 4859 4860 4861SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4862 unsigned NumInScalars = N->getNumOperands(); 4863 MVT VT = N->getValueType(0); 4864 unsigned NumElts = VT.getVectorNumElements(); 4865 MVT EltType = VT.getVectorElementType(); 4866 4867 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4868 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4869 // at most two distinct vectors, turn this into a shuffle node. 4870 SDValue VecIn1, VecIn2; 4871 for (unsigned i = 0; i != NumInScalars; ++i) { 4872 // Ignore undef inputs. 4873 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4874 4875 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4876 // constant index, bail out. 4877 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4878 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4879 VecIn1 = VecIn2 = SDValue(0, 0); 4880 break; 4881 } 4882 4883 // If the input vector type disagrees with the result of the build_vector, 4884 // we can't make a shuffle. 4885 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4886 if (ExtractedFromVec.getValueType() != VT) { 4887 VecIn1 = VecIn2 = SDValue(0, 0); 4888 break; 4889 } 4890 4891 // Otherwise, remember this. We allow up to two distinct input vectors. 4892 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4893 continue; 4894 4895 if (VecIn1.getNode() == 0) { 4896 VecIn1 = ExtractedFromVec; 4897 } else if (VecIn2.getNode() == 0) { 4898 VecIn2 = ExtractedFromVec; 4899 } else { 4900 // Too many inputs. 4901 VecIn1 = VecIn2 = SDValue(0, 0); 4902 break; 4903 } 4904 } 4905 4906 // If everything is good, we can make a shuffle operation. 4907 if (VecIn1.getNode()) { 4908 SmallVector<SDValue, 8> BuildVecIndices; 4909 for (unsigned i = 0; i != NumInScalars; ++i) { 4910 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4911 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4912 continue; 4913 } 4914 4915 SDValue Extract = N->getOperand(i); 4916 4917 // If extracting from the first vector, just use the index directly. 4918 if (Extract.getOperand(0) == VecIn1) { 4919 BuildVecIndices.push_back(Extract.getOperand(1)); 4920 continue; 4921 } 4922 4923 // Otherwise, use InIdx + VecSize 4924 unsigned Idx = 4925 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4926 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4927 } 4928 4929 // Add count and size info. 4930 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4931 4932 // Return the new VECTOR_SHUFFLE node. 4933 SDValue Ops[5]; 4934 Ops[0] = VecIn1; 4935 if (VecIn2.getNode()) { 4936 Ops[1] = VecIn2; 4937 } else { 4938 // Use an undef build_vector as input for the second operand. 4939 std::vector<SDValue> UnOps(NumInScalars, 4940 DAG.getNode(ISD::UNDEF, 4941 EltType)); 4942 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4943 &UnOps[0], UnOps.size()); 4944 AddToWorkList(Ops[1].getNode()); 4945 } 4946 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4947 &BuildVecIndices[0], BuildVecIndices.size()); 4948 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4949 } 4950 4951 return SDValue(); 4952} 4953 4954SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4955 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4956 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4957 // inputs come from at most two distinct vectors, turn this into a shuffle 4958 // node. 4959 4960 // If we only have one input vector, we don't need to do any concatenation. 4961 if (N->getNumOperands() == 1) { 4962 return N->getOperand(0); 4963 } 4964 4965 return SDValue(); 4966} 4967 4968SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4969 SDValue ShufMask = N->getOperand(2); 4970 unsigned NumElts = ShufMask.getNumOperands(); 4971 4972 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4973 bool isIdentity = true; 4974 for (unsigned i = 0; i != NumElts; ++i) { 4975 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4976 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 4977 isIdentity = false; 4978 break; 4979 } 4980 } 4981 if (isIdentity) return N->getOperand(0); 4982 4983 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4984 isIdentity = true; 4985 for (unsigned i = 0; i != NumElts; ++i) { 4986 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4987 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 4988 i+NumElts) { 4989 isIdentity = false; 4990 break; 4991 } 4992 } 4993 if (isIdentity) return N->getOperand(1); 4994 4995 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4996 // needed at all. 4997 bool isUnary = true; 4998 bool isSplat = true; 4999 int VecNum = -1; 5000 unsigned BaseIdx = 0; 5001 for (unsigned i = 0; i != NumElts; ++i) 5002 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5003 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5004 int V = (Idx < NumElts) ? 0 : 1; 5005 if (VecNum == -1) { 5006 VecNum = V; 5007 BaseIdx = Idx; 5008 } else { 5009 if (BaseIdx != Idx) 5010 isSplat = false; 5011 if (VecNum != V) { 5012 isUnary = false; 5013 break; 5014 } 5015 } 5016 } 5017 5018 SDValue N0 = N->getOperand(0); 5019 SDValue N1 = N->getOperand(1); 5020 // Normalize unary shuffle so the RHS is undef. 5021 if (isUnary && VecNum == 1) 5022 std::swap(N0, N1); 5023 5024 // If it is a splat, check if the argument vector is a build_vector with 5025 // all scalar elements the same. 5026 if (isSplat) { 5027 SDNode *V = N0.getNode(); 5028 5029 // If this is a bit convert that changes the element type of the vector but 5030 // not the number of vector elements, look through it. Be careful not to 5031 // look though conversions that change things like v4f32 to v2f64. 5032 if (V->getOpcode() == ISD::BIT_CONVERT) { 5033 SDValue ConvInput = V->getOperand(0); 5034 if (ConvInput.getValueType().isVector() && 5035 ConvInput.getValueType().getVectorNumElements() == NumElts) 5036 V = ConvInput.getNode(); 5037 } 5038 5039 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5040 unsigned NumElems = V->getNumOperands(); 5041 if (NumElems > BaseIdx) { 5042 SDValue Base; 5043 bool AllSame = true; 5044 for (unsigned i = 0; i != NumElems; ++i) { 5045 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5046 Base = V->getOperand(i); 5047 break; 5048 } 5049 } 5050 // Splat of <u, u, u, u>, return <u, u, u, u> 5051 if (!Base.getNode()) 5052 return N0; 5053 for (unsigned i = 0; i != NumElems; ++i) { 5054 if (V->getOperand(i) != Base) { 5055 AllSame = false; 5056 break; 5057 } 5058 } 5059 // Splat of <x, x, x, x>, return <x, x, x, x> 5060 if (AllSame) 5061 return N0; 5062 } 5063 } 5064 } 5065 5066 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5067 // into an undef. 5068 if (isUnary || N0 == N1) { 5069 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5070 // first operand. 5071 SmallVector<SDValue, 8> MappedOps; 5072 for (unsigned i = 0; i != NumElts; ++i) { 5073 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5074 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5075 NumElts) { 5076 MappedOps.push_back(ShufMask.getOperand(i)); 5077 } else { 5078 unsigned NewIdx = 5079 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5080 NumElts; 5081 MappedOps.push_back(DAG.getConstant(NewIdx, 5082 ShufMask.getOperand(i).getValueType())); 5083 } 5084 } 5085 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5086 &MappedOps[0], MappedOps.size()); 5087 AddToWorkList(ShufMask.getNode()); 5088 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5089 N0, 5090 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5091 ShufMask); 5092 } 5093 5094 return SDValue(); 5095} 5096 5097/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5098/// an AND to a vector_shuffle with the destination vector and a zero vector. 5099/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5100/// vector_shuffle V, Zero, <0, 4, 2, 4> 5101SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5102 SDValue LHS = N->getOperand(0); 5103 SDValue RHS = N->getOperand(1); 5104 if (N->getOpcode() == ISD::AND) { 5105 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5106 RHS = RHS.getOperand(0); 5107 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5108 std::vector<SDValue> IdxOps; 5109 unsigned NumOps = RHS.getNumOperands(); 5110 unsigned NumElts = NumOps; 5111 MVT EVT = RHS.getValueType().getVectorElementType(); 5112 for (unsigned i = 0; i != NumElts; ++i) { 5113 SDValue Elt = RHS.getOperand(i); 5114 if (!isa<ConstantSDNode>(Elt)) 5115 return SDValue(); 5116 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5117 IdxOps.push_back(DAG.getConstant(i, EVT)); 5118 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5119 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5120 else 5121 return SDValue(); 5122 } 5123 5124 // Let's see if the target supports this vector_shuffle. 5125 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5126 return SDValue(); 5127 5128 // Return the new VECTOR_SHUFFLE node. 5129 MVT VT = MVT::getVectorVT(EVT, NumElts); 5130 std::vector<SDValue> Ops; 5131 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5132 Ops.push_back(LHS); 5133 AddToWorkList(LHS.getNode()); 5134 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5135 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5136 &ZeroOps[0], ZeroOps.size())); 5137 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5138 &IdxOps[0], IdxOps.size())); 5139 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5140 &Ops[0], Ops.size()); 5141 if (VT != N->getValueType(0)) 5142 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5143 return Result; 5144 } 5145 } 5146 return SDValue(); 5147} 5148 5149/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5150SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5151 // After legalize, the target may be depending on adds and other 5152 // binary ops to provide legal ways to construct constants or other 5153 // things. Simplifying them may result in a loss of legality. 5154 if (AfterLegalize) return SDValue(); 5155 5156 MVT VT = N->getValueType(0); 5157 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5158 5159 MVT EltType = VT.getVectorElementType(); 5160 SDValue LHS = N->getOperand(0); 5161 SDValue RHS = N->getOperand(1); 5162 SDValue Shuffle = XformToShuffleWithZero(N); 5163 if (Shuffle.getNode()) return Shuffle; 5164 5165 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5166 // this operation. 5167 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5168 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5169 SmallVector<SDValue, 8> Ops; 5170 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5171 SDValue LHSOp = LHS.getOperand(i); 5172 SDValue RHSOp = RHS.getOperand(i); 5173 // If these two elements can't be folded, bail out. 5174 if ((LHSOp.getOpcode() != ISD::UNDEF && 5175 LHSOp.getOpcode() != ISD::Constant && 5176 LHSOp.getOpcode() != ISD::ConstantFP) || 5177 (RHSOp.getOpcode() != ISD::UNDEF && 5178 RHSOp.getOpcode() != ISD::Constant && 5179 RHSOp.getOpcode() != ISD::ConstantFP)) 5180 break; 5181 // Can't fold divide by zero. 5182 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5183 N->getOpcode() == ISD::FDIV) { 5184 if ((RHSOp.getOpcode() == ISD::Constant && 5185 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5186 (RHSOp.getOpcode() == ISD::ConstantFP && 5187 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5188 break; 5189 } 5190 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5191 AddToWorkList(Ops.back().getNode()); 5192 assert((Ops.back().getOpcode() == ISD::UNDEF || 5193 Ops.back().getOpcode() == ISD::Constant || 5194 Ops.back().getOpcode() == ISD::ConstantFP) && 5195 "Scalar binop didn't fold!"); 5196 } 5197 5198 if (Ops.size() == LHS.getNumOperands()) { 5199 MVT VT = LHS.getValueType(); 5200 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5201 } 5202 } 5203 5204 return SDValue(); 5205} 5206 5207SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5208 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5209 5210 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5211 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5212 // If we got a simplified select_cc node back from SimplifySelectCC, then 5213 // break it down into a new SETCC node, and a new SELECT node, and then return 5214 // the SELECT node, since we were called with a SELECT node. 5215 if (SCC.getNode()) { 5216 // Check to see if we got a select_cc back (to turn into setcc/select). 5217 // Otherwise, just return whatever node we got back, like fabs. 5218 if (SCC.getOpcode() == ISD::SELECT_CC) { 5219 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5220 SCC.getOperand(0), SCC.getOperand(1), 5221 SCC.getOperand(4)); 5222 AddToWorkList(SETCC.getNode()); 5223 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5224 SCC.getOperand(3), SETCC); 5225 } 5226 return SCC; 5227 } 5228 return SDValue(); 5229} 5230 5231/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5232/// are the two values being selected between, see if we can simplify the 5233/// select. Callers of this should assume that TheSelect is deleted if this 5234/// returns true. As such, they should return the appropriate thing (e.g. the 5235/// node) back to the top-level of the DAG combiner loop to avoid it being 5236/// looked at. 5237/// 5238bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5239 SDValue RHS) { 5240 5241 // If this is a select from two identical things, try to pull the operation 5242 // through the select. 5243 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5244 // If this is a load and the token chain is identical, replace the select 5245 // of two loads with a load through a select of the address to load from. 5246 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5247 // constants have been dropped into the constant pool. 5248 if (LHS.getOpcode() == ISD::LOAD && 5249 // Do not let this transformation reduce the number of volatile loads. 5250 !cast<LoadSDNode>(LHS)->isVolatile() && 5251 !cast<LoadSDNode>(RHS)->isVolatile() && 5252 // Token chains must be identical. 5253 LHS.getOperand(0) == RHS.getOperand(0)) { 5254 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5255 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5256 5257 // If this is an EXTLOAD, the VT's must match. 5258 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5259 // FIXME: this conflates two src values, discarding one. This is not 5260 // the right thing to do, but nothing uses srcvalues now. When they do, 5261 // turn SrcValue into a list of locations. 5262 SDValue Addr; 5263 if (TheSelect->getOpcode() == ISD::SELECT) { 5264 // Check that the condition doesn't reach either load. If so, folding 5265 // this will induce a cycle into the DAG. 5266 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5267 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5268 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5269 TheSelect->getOperand(0), LLD->getBasePtr(), 5270 RLD->getBasePtr()); 5271 } 5272 } else { 5273 // Check that the condition doesn't reach either load. If so, folding 5274 // this will induce a cycle into the DAG. 5275 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5276 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5277 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5278 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5279 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5280 TheSelect->getOperand(0), 5281 TheSelect->getOperand(1), 5282 LLD->getBasePtr(), RLD->getBasePtr(), 5283 TheSelect->getOperand(4)); 5284 } 5285 } 5286 5287 if (Addr.getNode()) { 5288 SDValue Load; 5289 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5290 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5291 Addr,LLD->getSrcValue(), 5292 LLD->getSrcValueOffset(), 5293 LLD->isVolatile(), 5294 LLD->getAlignment()); 5295 else { 5296 Load = DAG.getExtLoad(LLD->getExtensionType(), 5297 TheSelect->getValueType(0), 5298 LLD->getChain(), Addr, LLD->getSrcValue(), 5299 LLD->getSrcValueOffset(), 5300 LLD->getMemoryVT(), 5301 LLD->isVolatile(), 5302 LLD->getAlignment()); 5303 } 5304 // Users of the select now use the result of the load. 5305 CombineTo(TheSelect, Load); 5306 5307 // Users of the old loads now use the new load's chain. We know the 5308 // old-load value is dead now. 5309 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5310 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5311 return true; 5312 } 5313 } 5314 } 5315 } 5316 5317 return false; 5318} 5319 5320SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5321 SDValue N2, SDValue N3, 5322 ISD::CondCode CC, bool NotExtCompare) { 5323 5324 MVT VT = N2.getValueType(); 5325 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5326 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5327 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5328 5329 // Determine if the condition we're dealing with is constant 5330 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5331 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5332 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5333 5334 // fold select_cc true, x, y -> x 5335 if (SCCC && !SCCC->isNullValue()) 5336 return N2; 5337 // fold select_cc false, x, y -> y 5338 if (SCCC && SCCC->isNullValue()) 5339 return N3; 5340 5341 // Check to see if we can simplify the select into an fabs node 5342 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5343 // Allow either -0.0 or 0.0 5344 if (CFP->getValueAPF().isZero()) { 5345 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5346 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5347 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5348 N2 == N3.getOperand(0)) 5349 return DAG.getNode(ISD::FABS, VT, N0); 5350 5351 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5352 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5353 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5354 N2.getOperand(0) == N3) 5355 return DAG.getNode(ISD::FABS, VT, N3); 5356 } 5357 } 5358 5359 // Check to see if we can perform the "gzip trick", transforming 5360 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5361 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5362 N0.getValueType().isInteger() && 5363 N2.getValueType().isInteger() && 5364 (N1C->isNullValue() || // (a < 0) ? b : 0 5365 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5366 MVT XType = N0.getValueType(); 5367 MVT AType = N2.getValueType(); 5368 if (XType.bitsGE(AType)) { 5369 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5370 // single-bit constant. 5371 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5372 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5373 ShCtV = XType.getSizeInBits()-ShCtV-1; 5374 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5375 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5376 AddToWorkList(Shift.getNode()); 5377 if (XType.bitsGT(AType)) { 5378 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5379 AddToWorkList(Shift.getNode()); 5380 } 5381 return DAG.getNode(ISD::AND, AType, Shift, N2); 5382 } 5383 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5384 DAG.getConstant(XType.getSizeInBits()-1, 5385 TLI.getShiftAmountTy())); 5386 AddToWorkList(Shift.getNode()); 5387 if (XType.bitsGT(AType)) { 5388 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5389 AddToWorkList(Shift.getNode()); 5390 } 5391 return DAG.getNode(ISD::AND, AType, Shift, N2); 5392 } 5393 } 5394 5395 // fold select C, 16, 0 -> shl C, 4 5396 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5397 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5398 5399 // If the caller doesn't want us to simplify this into a zext of a compare, 5400 // don't do it. 5401 if (NotExtCompare && N2C->getAPIntValue() == 1) 5402 return SDValue(); 5403 5404 // Get a SetCC of the condition 5405 // FIXME: Should probably make sure that setcc is legal if we ever have a 5406 // target where it isn't. 5407 SDValue Temp, SCC; 5408 // cast from setcc result type to select result type 5409 if (AfterLegalize) { 5410 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5411 if (N2.getValueType().bitsLT(SCC.getValueType())) 5412 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5413 else 5414 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5415 } else { 5416 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5417 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5418 } 5419 AddToWorkList(SCC.getNode()); 5420 AddToWorkList(Temp.getNode()); 5421 5422 if (N2C->getAPIntValue() == 1) 5423 return Temp; 5424 // shl setcc result by log2 n2c 5425 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5426 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5427 TLI.getShiftAmountTy())); 5428 } 5429 5430 // Check to see if this is the equivalent of setcc 5431 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5432 // otherwise, go ahead with the folds. 5433 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5434 MVT XType = N0.getValueType(); 5435 if (!AfterLegalize || 5436 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5437 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5438 if (Res.getValueType() != VT) 5439 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5440 return Res; 5441 } 5442 5443 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5444 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5445 (!AfterLegalize || 5446 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5447 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5448 return DAG.getNode(ISD::SRL, XType, Ctlz, 5449 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5450 TLI.getShiftAmountTy())); 5451 } 5452 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5453 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5454 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5455 N0); 5456 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5457 DAG.getConstant(~0ULL, XType)); 5458 return DAG.getNode(ISD::SRL, XType, 5459 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5460 DAG.getConstant(XType.getSizeInBits()-1, 5461 TLI.getShiftAmountTy())); 5462 } 5463 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5464 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5465 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5466 DAG.getConstant(XType.getSizeInBits()-1, 5467 TLI.getShiftAmountTy())); 5468 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5469 } 5470 } 5471 5472 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5473 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5474 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5475 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5476 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5477 MVT XType = N0.getValueType(); 5478 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5479 DAG.getConstant(XType.getSizeInBits()-1, 5480 TLI.getShiftAmountTy())); 5481 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5482 AddToWorkList(Shift.getNode()); 5483 AddToWorkList(Add.getNode()); 5484 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5485 } 5486 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5487 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5488 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5489 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5490 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5491 MVT XType = N0.getValueType(); 5492 if (SubC->isNullValue() && XType.isInteger()) { 5493 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5494 DAG.getConstant(XType.getSizeInBits()-1, 5495 TLI.getShiftAmountTy())); 5496 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5497 AddToWorkList(Shift.getNode()); 5498 AddToWorkList(Add.getNode()); 5499 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5500 } 5501 } 5502 } 5503 5504 return SDValue(); 5505} 5506 5507/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5508SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5509 SDValue N1, ISD::CondCode Cond, 5510 bool foldBooleans) { 5511 TargetLowering::DAGCombinerInfo 5512 DagCombineInfo(DAG, !AfterLegalize, false, this); 5513 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5514} 5515 5516/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5517/// return a DAG expression to select that will generate the same value by 5518/// multiplying by a magic number. See: 5519/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5520SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5521 std::vector<SDNode*> Built; 5522 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5523 5524 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5525 ii != ee; ++ii) 5526 AddToWorkList(*ii); 5527 return S; 5528} 5529 5530/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5531/// return a DAG expression to select that will generate the same value by 5532/// multiplying by a magic number. See: 5533/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5534SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5535 std::vector<SDNode*> Built; 5536 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5537 5538 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5539 ii != ee; ++ii) 5540 AddToWorkList(*ii); 5541 return S; 5542} 5543 5544/// FindBaseOffset - Return true if base is known not to alias with anything 5545/// but itself. Provides base object and offset as results. 5546static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5547 // Assume it is a primitive operation. 5548 Base = Ptr; Offset = 0; 5549 5550 // If it's an adding a simple constant then integrate the offset. 5551 if (Base.getOpcode() == ISD::ADD) { 5552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5553 Base = Base.getOperand(0); 5554 Offset += C->getZExtValue(); 5555 } 5556 } 5557 5558 // If it's any of the following then it can't alias with anything but itself. 5559 return isa<FrameIndexSDNode>(Base) || 5560 isa<ConstantPoolSDNode>(Base) || 5561 isa<GlobalAddressSDNode>(Base); 5562} 5563 5564/// isAlias - Return true if there is any possibility that the two addresses 5565/// overlap. 5566bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5567 const Value *SrcValue1, int SrcValueOffset1, 5568 SDValue Ptr2, int64_t Size2, 5569 const Value *SrcValue2, int SrcValueOffset2) 5570{ 5571 // If they are the same then they must be aliases. 5572 if (Ptr1 == Ptr2) return true; 5573 5574 // Gather base node and offset information. 5575 SDValue Base1, Base2; 5576 int64_t Offset1, Offset2; 5577 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5578 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5579 5580 // If they have a same base address then... 5581 if (Base1 == Base2) { 5582 // Check to see if the addresses overlap. 5583 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5584 } 5585 5586 // If we know both bases then they can't alias. 5587 if (KnownBase1 && KnownBase2) return false; 5588 5589 if (CombinerGlobalAA) { 5590 // Use alias analysis information. 5591 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5592 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5593 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5594 AliasAnalysis::AliasResult AAResult = 5595 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5596 if (AAResult == AliasAnalysis::NoAlias) 5597 return false; 5598 } 5599 5600 // Otherwise we have to assume they alias. 5601 return true; 5602} 5603 5604/// FindAliasInfo - Extracts the relevant alias information from the memory 5605/// node. Returns true if the operand was a load. 5606bool DAGCombiner::FindAliasInfo(SDNode *N, 5607 SDValue &Ptr, int64_t &Size, 5608 const Value *&SrcValue, int &SrcValueOffset) { 5609 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5610 Ptr = LD->getBasePtr(); 5611 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5612 SrcValue = LD->getSrcValue(); 5613 SrcValueOffset = LD->getSrcValueOffset(); 5614 return true; 5615 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5616 Ptr = ST->getBasePtr(); 5617 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5618 SrcValue = ST->getSrcValue(); 5619 SrcValueOffset = ST->getSrcValueOffset(); 5620 } else { 5621 assert(0 && "FindAliasInfo expected a memory operand"); 5622 } 5623 5624 return false; 5625} 5626 5627/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5628/// looking for aliasing nodes and adding them to the Aliases vector. 5629void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5630 SmallVector<SDValue, 8> &Aliases) { 5631 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5632 std::set<SDNode *> Visited; // Visited node set. 5633 5634 // Get alias information for node. 5635 SDValue Ptr; 5636 int64_t Size; 5637 const Value *SrcValue; 5638 int SrcValueOffset; 5639 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5640 5641 // Starting off. 5642 Chains.push_back(OriginalChain); 5643 5644 // Look at each chain and determine if it is an alias. If so, add it to the 5645 // aliases list. If not, then continue up the chain looking for the next 5646 // candidate. 5647 while (!Chains.empty()) { 5648 SDValue Chain = Chains.back(); 5649 Chains.pop_back(); 5650 5651 // Don't bother if we've been before. 5652 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5653 Visited.insert(Chain.getNode()); 5654 5655 switch (Chain.getOpcode()) { 5656 case ISD::EntryToken: 5657 // Entry token is ideal chain operand, but handled in FindBetterChain. 5658 break; 5659 5660 case ISD::LOAD: 5661 case ISD::STORE: { 5662 // Get alias information for Chain. 5663 SDValue OpPtr; 5664 int64_t OpSize; 5665 const Value *OpSrcValue; 5666 int OpSrcValueOffset; 5667 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5668 OpSrcValue, OpSrcValueOffset); 5669 5670 // If chain is alias then stop here. 5671 if (!(IsLoad && IsOpLoad) && 5672 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5673 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5674 Aliases.push_back(Chain); 5675 } else { 5676 // Look further up the chain. 5677 Chains.push_back(Chain.getOperand(0)); 5678 // Clean up old chain. 5679 AddToWorkList(Chain.getNode()); 5680 } 5681 break; 5682 } 5683 5684 case ISD::TokenFactor: 5685 // We have to check each of the operands of the token factor, so we queue 5686 // then up. Adding the operands to the queue (stack) in reverse order 5687 // maintains the original order and increases the likelihood that getNode 5688 // will find a matching token factor (CSE.) 5689 for (unsigned n = Chain.getNumOperands(); n;) 5690 Chains.push_back(Chain.getOperand(--n)); 5691 // Eliminate the token factor if we can. 5692 AddToWorkList(Chain.getNode()); 5693 break; 5694 5695 default: 5696 // For all other instructions we will just have to take what we can get. 5697 Aliases.push_back(Chain); 5698 break; 5699 } 5700 } 5701} 5702 5703/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5704/// for a better chain (aliasing node.) 5705SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5706 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5707 5708 // Accumulate all the aliases to this node. 5709 GatherAllAliases(N, OldChain, Aliases); 5710 5711 if (Aliases.size() == 0) { 5712 // If no operands then chain to entry token. 5713 return DAG.getEntryNode(); 5714 } else if (Aliases.size() == 1) { 5715 // If a single operand then chain to it. We don't need to revisit it. 5716 return Aliases[0]; 5717 } 5718 5719 // Construct a custom tailored token factor. 5720 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5721 &Aliases[0], Aliases.size()); 5722 5723 // Make sure the old chain gets cleaned up. 5724 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5725 5726 return NewChain; 5727} 5728 5729// SelectionDAG::Combine - This is the entry point for the file. 5730// 5731void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5732 bool Fast) { 5733 /// run - This is the main entry point to this class. 5734 /// 5735 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5736} 5737