DAGCombiner.cpp revision f5aeb1a8e4cf272c7348376d185ef8d8267653e0
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 bool AfterLegalize; 54 bool Fast; 55 56 // Worklist of all of the nodes that need to be simplified. 57 std::vector<SDNode*> WorkList; 58 59 // AA - Used for DAG load/store alias analysis. 60 AliasAnalysis &AA; 61 62 /// AddUsersToWorkList - When an instruction is simplified, add all users of 63 /// the instruction to the work lists because they might get more simplified 64 /// now. 65 /// 66 void AddUsersToWorkList(SDNode *N) { 67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 68 UI != UE; ++UI) 69 AddToWorkList(*UI); 70 } 71 72 /// visit - call the node-specific routine that knows how to fold each 73 /// particular type of node. 74 SDValue visit(SDNode *N); 75 76 public: 77 /// AddToWorkList - Add to the work list making sure it's instance is at the 78 /// the back (next to be processed.) 79 void AddToWorkList(SDNode *N) { 80 removeFromWorkList(N); 81 WorkList.push_back(N); 82 } 83 84 /// removeFromWorkList - remove all instances of N from the worklist. 85 /// 86 void removeFromWorkList(SDNode *N) { 87 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 88 WorkList.end()); 89 } 90 91 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 92 bool AddTo = true); 93 94 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 95 return CombineTo(N, &Res, 1, AddTo); 96 } 97 98 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 99 bool AddTo = true) { 100 SDValue To[] = { Res0, Res1 }; 101 return CombineTo(N, To, 2, AddTo); 102 } 103 104 private: 105 106 /// SimplifyDemandedBits - Check the specified integer node value to see if 107 /// it can be simplified or if things it uses can be simplified by bit 108 /// propagation. If so, return true. 109 bool SimplifyDemandedBits(SDValue Op) { 110 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 111 return SimplifyDemandedBits(Op, Demanded); 112 } 113 114 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 115 116 bool CombineToPreIndexedLoadStore(SDNode *N); 117 bool CombineToPostIndexedLoadStore(SDNode *N); 118 119 120 /// combine - call the node-specific routine that knows how to fold each 121 /// particular type of node. If that doesn't do anything, try the 122 /// target-specific DAG combines. 123 SDValue combine(SDNode *N); 124 125 // Visitation implementation - Implement dag node combining for different 126 // node types. The semantics are as follows: 127 // Return Value: 128 // SDValue.getNode() == 0 - No change was made 129 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 130 // otherwise - N should be replaced by the returned Operand. 131 // 132 SDValue visitTokenFactor(SDNode *N); 133 SDValue visitMERGE_VALUES(SDNode *N); 134 SDValue visitADD(SDNode *N); 135 SDValue visitSUB(SDNode *N); 136 SDValue visitADDC(SDNode *N); 137 SDValue visitADDE(SDNode *N); 138 SDValue visitMUL(SDNode *N); 139 SDValue visitSDIV(SDNode *N); 140 SDValue visitUDIV(SDNode *N); 141 SDValue visitSREM(SDNode *N); 142 SDValue visitUREM(SDNode *N); 143 SDValue visitMULHU(SDNode *N); 144 SDValue visitMULHS(SDNode *N); 145 SDValue visitSMUL_LOHI(SDNode *N); 146 SDValue visitUMUL_LOHI(SDNode *N); 147 SDValue visitSDIVREM(SDNode *N); 148 SDValue visitUDIVREM(SDNode *N); 149 SDValue visitAND(SDNode *N); 150 SDValue visitOR(SDNode *N); 151 SDValue visitXOR(SDNode *N); 152 SDValue SimplifyVBinOp(SDNode *N); 153 SDValue visitSHL(SDNode *N); 154 SDValue visitSRA(SDNode *N); 155 SDValue visitSRL(SDNode *N); 156 SDValue visitCTLZ(SDNode *N); 157 SDValue visitCTTZ(SDNode *N); 158 SDValue visitCTPOP(SDNode *N); 159 SDValue visitSELECT(SDNode *N); 160 SDValue visitSELECT_CC(SDNode *N); 161 SDValue visitSETCC(SDNode *N); 162 SDValue visitSIGN_EXTEND(SDNode *N); 163 SDValue visitZERO_EXTEND(SDNode *N); 164 SDValue visitANY_EXTEND(SDNode *N); 165 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 166 SDValue visitTRUNCATE(SDNode *N); 167 SDValue visitBIT_CONVERT(SDNode *N); 168 SDValue visitBUILD_PAIR(SDNode *N); 169 SDValue visitFADD(SDNode *N); 170 SDValue visitFSUB(SDNode *N); 171 SDValue visitFMUL(SDNode *N); 172 SDValue visitFDIV(SDNode *N); 173 SDValue visitFREM(SDNode *N); 174 SDValue visitFCOPYSIGN(SDNode *N); 175 SDValue visitSINT_TO_FP(SDNode *N); 176 SDValue visitUINT_TO_FP(SDNode *N); 177 SDValue visitFP_TO_SINT(SDNode *N); 178 SDValue visitFP_TO_UINT(SDNode *N); 179 SDValue visitFP_ROUND(SDNode *N); 180 SDValue visitFP_ROUND_INREG(SDNode *N); 181 SDValue visitFP_EXTEND(SDNode *N); 182 SDValue visitFNEG(SDNode *N); 183 SDValue visitFABS(SDNode *N); 184 SDValue visitBRCOND(SDNode *N); 185 SDValue visitBR_CC(SDNode *N); 186 SDValue visitLOAD(SDNode *N); 187 SDValue visitSTORE(SDNode *N); 188 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 189 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 190 SDValue visitBUILD_VECTOR(SDNode *N); 191 SDValue visitCONCAT_VECTORS(SDNode *N); 192 SDValue visitVECTOR_SHUFFLE(SDNode *N); 193 194 SDValue XformToShuffleWithZero(SDNode *N); 195 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 196 197 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 198 199 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 200 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 201 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 202 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 203 SDValue N3, ISD::CondCode CC, 204 bool NotExtCompare = false); 205 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, 206 ISD::CondCode Cond, bool foldBooleans = true); 207 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 208 unsigned HiOp); 209 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 210 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 211 SDValue BuildSDIV(SDNode *N); 212 SDValue BuildUDIV(SDNode *N); 213 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 214 SDValue ReduceLoadWidth(SDNode *N); 215 216 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 217 218 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 219 /// looking for aliasing nodes and adding them to the Aliases vector. 220 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 221 SmallVector<SDValue, 8> &Aliases); 222 223 /// isAlias - Return true if there is any possibility that the two addresses 224 /// overlap. 225 bool isAlias(SDValue Ptr1, int64_t Size1, 226 const Value *SrcValue1, int SrcValueOffset1, 227 SDValue Ptr2, int64_t Size2, 228 const Value *SrcValue2, int SrcValueOffset2); 229 230 /// FindAliasInfo - Extracts the relevant alias information from the memory 231 /// node. Returns true if the operand was a load. 232 bool FindAliasInfo(SDNode *N, 233 SDValue &Ptr, int64_t &Size, 234 const Value *&SrcValue, int &SrcValueOffset); 235 236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 237 /// looking for a better chain (aliasing node.) 238 SDValue FindBetterChain(SDNode *N, SDValue Chain); 239 240public: 241 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 242 : DAG(D), 243 TLI(D.getTargetLoweringInfo()), 244 AfterLegalize(false), 245 Fast(fast), 246 AA(A) {} 247 248 /// Run - runs the dag combiner on all nodes in the work list 249 void Run(bool RunningAfterLegalize); 250 }; 251} 252 253 254namespace { 255/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 256/// nodes from the worklist. 257class VISIBILITY_HIDDEN WorkListRemover : 258 public SelectionDAG::DAGUpdateListener { 259 DAGCombiner &DC; 260public: 261 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 262 263 virtual void NodeDeleted(SDNode *N, SDNode *E) { 264 DC.removeFromWorkList(N); 265 } 266 267 virtual void NodeUpdated(SDNode *N) { 268 // Ignore updates. 269 } 270}; 271} 272 273//===----------------------------------------------------------------------===// 274// TargetLowering::DAGCombinerInfo implementation 275//===----------------------------------------------------------------------===// 276 277void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 278 ((DAGCombiner*)DC)->AddToWorkList(N); 279} 280 281SDValue TargetLowering::DAGCombinerInfo:: 282CombineTo(SDNode *N, const std::vector<SDValue> &To) { 283 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 284} 285 286SDValue TargetLowering::DAGCombinerInfo:: 287CombineTo(SDNode *N, SDValue Res) { 288 return ((DAGCombiner*)DC)->CombineTo(N, Res); 289} 290 291 292SDValue TargetLowering::DAGCombinerInfo:: 293CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 294 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 295} 296 297 298//===----------------------------------------------------------------------===// 299// Helper Functions 300//===----------------------------------------------------------------------===// 301 302/// isNegatibleForFree - Return 1 if we can compute the negated form of the 303/// specified expression for the same cost as the expression itself, or 2 if we 304/// can compute the negated form more cheaply than the expression itself. 305static char isNegatibleForFree(SDValue Op, bool AfterLegalize, 306 unsigned Depth = 0) { 307 // No compile time optimizations on this type. 308 if (Op.getValueType() == MVT::ppcf128) 309 return 0; 310 311 // fneg is removable even if it has multiple uses. 312 if (Op.getOpcode() == ISD::FNEG) return 2; 313 314 // Don't allow anything with multiple uses. 315 if (!Op.hasOneUse()) return 0; 316 317 // Don't recurse exponentially. 318 if (Depth > 6) return 0; 319 320 switch (Op.getOpcode()) { 321 default: return false; 322 case ISD::ConstantFP: 323 // Don't invert constant FP values after legalize. The negated constant 324 // isn't necessarily legal. 325 return AfterLegalize ? 0 : 1; 326 case ISD::FADD: 327 // FIXME: determine better conditions for this xform. 328 if (!UnsafeFPMath) return 0; 329 330 // -(A+B) -> -A - B 331 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 332 return V; 333 // -(A+B) -> -B - A 334 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 335 case ISD::FSUB: 336 // We can't turn -(A-B) into B-A when we honor signed zeros. 337 if (!UnsafeFPMath) return 0; 338 339 // -(A-B) -> B-A 340 return 1; 341 342 case ISD::FMUL: 343 case ISD::FDIV: 344 if (HonorSignDependentRoundingFPMath()) return 0; 345 346 // -(X*Y) -> (-X * Y) or (X*-Y) 347 if (char V = isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 348 return V; 349 350 return isNegatibleForFree(Op.getOperand(1), AfterLegalize, Depth+1); 351 352 case ISD::FP_EXTEND: 353 case ISD::FP_ROUND: 354 case ISD::FSIN: 355 return isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1); 356 } 357} 358 359/// GetNegatedExpression - If isNegatibleForFree returns true, this function 360/// returns the newly negated expression. 361static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 362 bool AfterLegalize, unsigned Depth = 0) { 363 // fneg is removable even if it has multiple uses. 364 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 365 366 // Don't allow anything with multiple uses. 367 assert(Op.hasOneUse() && "Unknown reuse!"); 368 369 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 370 switch (Op.getOpcode()) { 371 default: assert(0 && "Unknown code"); 372 case ISD::ConstantFP: { 373 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 374 V.changeSign(); 375 return DAG.getConstantFP(V, Op.getValueType()); 376 } 377 case ISD::FADD: 378 // FIXME: determine better conditions for this xform. 379 assert(UnsafeFPMath); 380 381 // -(A+B) -> -A - B 382 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 383 return DAG.getNode(ISD::FSUB, Op.getValueType(), 384 GetNegatedExpression(Op.getOperand(0), DAG, 385 AfterLegalize, Depth+1), 386 Op.getOperand(1)); 387 // -(A+B) -> -B - A 388 return DAG.getNode(ISD::FSUB, Op.getValueType(), 389 GetNegatedExpression(Op.getOperand(1), DAG, 390 AfterLegalize, Depth+1), 391 Op.getOperand(0)); 392 case ISD::FSUB: 393 // We can't turn -(A-B) into B-A when we honor signed zeros. 394 assert(UnsafeFPMath); 395 396 // -(0-B) -> B 397 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 398 if (N0CFP->getValueAPF().isZero()) 399 return Op.getOperand(1); 400 401 // -(A-B) -> B-A 402 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 403 Op.getOperand(0)); 404 405 case ISD::FMUL: 406 case ISD::FDIV: 407 assert(!HonorSignDependentRoundingFPMath()); 408 409 // -(X*Y) -> -X * Y 410 if (isNegatibleForFree(Op.getOperand(0), AfterLegalize, Depth+1)) 411 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 412 GetNegatedExpression(Op.getOperand(0), DAG, 413 AfterLegalize, Depth+1), 414 Op.getOperand(1)); 415 416 // -(X*Y) -> X * -Y 417 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 418 Op.getOperand(0), 419 GetNegatedExpression(Op.getOperand(1), DAG, 420 AfterLegalize, Depth+1)); 421 422 case ISD::FP_EXTEND: 423 case ISD::FSIN: 424 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, 426 AfterLegalize, Depth+1)); 427 case ISD::FP_ROUND: 428 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 AfterLegalize, Depth+1), 431 Op.getOperand(1)); 432 } 433} 434 435 436// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 437// that selects between the values 1 and 0, making it equivalent to a setcc. 438// Also, set the incoming LHS, RHS, and CC references to the appropriate 439// nodes based on the type of node we are checking. This simplifies life a 440// bit for the callers. 441static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 442 SDValue &CC) { 443 if (N.getOpcode() == ISD::SETCC) { 444 LHS = N.getOperand(0); 445 RHS = N.getOperand(1); 446 CC = N.getOperand(2); 447 return true; 448 } 449 if (N.getOpcode() == ISD::SELECT_CC && 450 N.getOperand(2).getOpcode() == ISD::Constant && 451 N.getOperand(3).getOpcode() == ISD::Constant && 452 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 453 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 454 LHS = N.getOperand(0); 455 RHS = N.getOperand(1); 456 CC = N.getOperand(4); 457 return true; 458 } 459 return false; 460} 461 462// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 463// one use. If this is true, it allows the users to invert the operation for 464// free when it is profitable to do so. 465static bool isOneUseSetCC(SDValue N) { 466 SDValue N0, N1, N2; 467 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 468 return true; 469 return false; 470} 471 472SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 473 MVT VT = N0.getValueType(); 474 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 475 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 476 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 477 if (isa<ConstantSDNode>(N1)) { 478 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 479 AddToWorkList(OpNode.getNode()); 480 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 481 } else if (N0.hasOneUse()) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 485 } 486 } 487 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 488 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 489 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 490 if (isa<ConstantSDNode>(N0)) { 491 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 492 AddToWorkList(OpNode.getNode()); 493 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 494 } else if (N1.hasOneUse()) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 498 } 499 } 500 return SDValue(); 501} 502 503SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 504 bool AddTo) { 505 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 506 ++NodesCombined; 507 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 508 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 509 DOUT << " and " << NumTo-1 << " other values\n"; 510 WorkListRemover DeadNodes(*this); 511 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 512 513 if (AddTo) { 514 // Push the new nodes and any users onto the worklist 515 for (unsigned i = 0, e = NumTo; i != e; ++i) { 516 AddToWorkList(To[i].getNode()); 517 AddUsersToWorkList(To[i].getNode()); 518 } 519 } 520 521 // Nodes can be reintroduced into the worklist. Make sure we do not 522 // process a node that has been replaced. 523 removeFromWorkList(N); 524 525 // Finally, since the node is now dead, remove it from the graph. 526 DAG.DeleteNode(N); 527 return SDValue(N, 0); 528} 529 530/// SimplifyDemandedBits - Check the specified integer node value to see if 531/// it can be simplified or if things it uses can be simplified by bit 532/// propagation. If so, return true. 533bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 534 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 535 APInt KnownZero, KnownOne; 536 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 537 return false; 538 539 // Revisit the node. 540 AddToWorkList(Op.getNode()); 541 542 // Replace the old value with the new one. 543 ++NodesCombined; 544 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 545 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 546 DOUT << '\n'; 547 548 // Replace all uses. If any nodes become isomorphic to other nodes and 549 // are deleted, make sure to remove them from our worklist. 550 WorkListRemover DeadNodes(*this); 551 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 552 553 // Push the new node and any (possibly new) users onto the worklist. 554 AddToWorkList(TLO.New.getNode()); 555 AddUsersToWorkList(TLO.New.getNode()); 556 557 // Finally, if the node is now dead, remove it from the graph. The node 558 // may not be dead if the replacement process recursively simplified to 559 // something else needing this node. 560 if (TLO.Old.getNode()->use_empty()) { 561 removeFromWorkList(TLO.Old.getNode()); 562 563 // If the operands of this node are only used by the node, they will now 564 // be dead. Make sure to visit them first to delete dead nodes early. 565 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 566 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 567 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 568 569 DAG.DeleteNode(TLO.Old.getNode()); 570 } 571 return true; 572} 573 574//===----------------------------------------------------------------------===// 575// Main DAG Combiner implementation 576//===----------------------------------------------------------------------===// 577 578void DAGCombiner::Run(bool RunningAfterLegalize) { 579 // set the instance variable, so that the various visit routines may use it. 580 AfterLegalize = RunningAfterLegalize; 581 582 // Add all the dag nodes to the worklist. 583 WorkList.reserve(DAG.allnodes_size()); 584 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 585 E = DAG.allnodes_end(); I != E; ++I) 586 WorkList.push_back(I); 587 588 // Create a dummy node (which is not added to allnodes), that adds a reference 589 // to the root node, preventing it from being deleted, and tracking any 590 // changes of the root. 591 HandleSDNode Dummy(DAG.getRoot()); 592 593 // The root of the dag may dangle to deleted nodes until the dag combiner is 594 // done. Set it to null to avoid confusion. 595 DAG.setRoot(SDValue()); 596 597 // while the worklist isn't empty, inspect the node on the end of it and 598 // try and combine it. 599 while (!WorkList.empty()) { 600 SDNode *N = WorkList.back(); 601 WorkList.pop_back(); 602 603 // If N has no uses, it is dead. Make sure to revisit all N's operands once 604 // N is deleted from the DAG, since they too may now be dead or may have a 605 // reduced number of uses, allowing other xforms. 606 if (N->use_empty() && N != &Dummy) { 607 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 608 AddToWorkList(N->getOperand(i).getNode()); 609 610 DAG.DeleteNode(N); 611 continue; 612 } 613 614 SDValue RV = combine(N); 615 616 if (RV.getNode() == 0) 617 continue; 618 619 ++NodesCombined; 620 621 // If we get back the same node we passed in, rather than a new node or 622 // zero, we know that the node must have defined multiple values and 623 // CombineTo was used. Since CombineTo takes care of the worklist 624 // mechanics for us, we have no work to do in this case. 625 if (RV.getNode() == N) 626 continue; 627 628 assert(N->getOpcode() != ISD::DELETED_NODE && 629 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 630 "Node was deleted but visit returned new node!"); 631 632 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 633 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 634 DOUT << '\n'; 635 WorkListRemover DeadNodes(*this); 636 if (N->getNumValues() == RV.getNode()->getNumValues()) 637 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 638 else { 639 assert(N->getValueType(0) == RV.getValueType() && 640 N->getNumValues() == 1 && "Type mismatch"); 641 SDValue OpV = RV; 642 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 643 } 644 645 // Push the new node and any users onto the worklist 646 AddToWorkList(RV.getNode()); 647 AddUsersToWorkList(RV.getNode()); 648 649 // Add any uses of the old node to the worklist in case this node is the 650 // last one that uses them. They may become dead after this node is 651 // deleted. 652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 653 AddToWorkList(N->getOperand(i).getNode()); 654 655 // Nodes can be reintroduced into the worklist. Make sure we do not 656 // process a node that has been replaced. 657 removeFromWorkList(N); 658 659 // Finally, since the node is now dead, remove it from the graph. 660 DAG.DeleteNode(N); 661 } 662 663 // If the root changed (e.g. it was a dead load, update the root). 664 DAG.setRoot(Dummy.getValue()); 665} 666 667SDValue DAGCombiner::visit(SDNode *N) { 668 switch(N->getOpcode()) { 669 default: break; 670 case ISD::TokenFactor: return visitTokenFactor(N); 671 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 672 case ISD::ADD: return visitADD(N); 673 case ISD::SUB: return visitSUB(N); 674 case ISD::ADDC: return visitADDC(N); 675 case ISD::ADDE: return visitADDE(N); 676 case ISD::MUL: return visitMUL(N); 677 case ISD::SDIV: return visitSDIV(N); 678 case ISD::UDIV: return visitUDIV(N); 679 case ISD::SREM: return visitSREM(N); 680 case ISD::UREM: return visitUREM(N); 681 case ISD::MULHU: return visitMULHU(N); 682 case ISD::MULHS: return visitMULHS(N); 683 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 684 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 685 case ISD::SDIVREM: return visitSDIVREM(N); 686 case ISD::UDIVREM: return visitUDIVREM(N); 687 case ISD::AND: return visitAND(N); 688 case ISD::OR: return visitOR(N); 689 case ISD::XOR: return visitXOR(N); 690 case ISD::SHL: return visitSHL(N); 691 case ISD::SRA: return visitSRA(N); 692 case ISD::SRL: return visitSRL(N); 693 case ISD::CTLZ: return visitCTLZ(N); 694 case ISD::CTTZ: return visitCTTZ(N); 695 case ISD::CTPOP: return visitCTPOP(N); 696 case ISD::SELECT: return visitSELECT(N); 697 case ISD::SELECT_CC: return visitSELECT_CC(N); 698 case ISD::SETCC: return visitSETCC(N); 699 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 700 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 701 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 702 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 703 case ISD::TRUNCATE: return visitTRUNCATE(N); 704 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 705 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 706 case ISD::FADD: return visitFADD(N); 707 case ISD::FSUB: return visitFSUB(N); 708 case ISD::FMUL: return visitFMUL(N); 709 case ISD::FDIV: return visitFDIV(N); 710 case ISD::FREM: return visitFREM(N); 711 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 712 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 713 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 714 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 715 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 716 case ISD::FP_ROUND: return visitFP_ROUND(N); 717 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 718 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 719 case ISD::FNEG: return visitFNEG(N); 720 case ISD::FABS: return visitFABS(N); 721 case ISD::BRCOND: return visitBRCOND(N); 722 case ISD::BR_CC: return visitBR_CC(N); 723 case ISD::LOAD: return visitLOAD(N); 724 case ISD::STORE: return visitSTORE(N); 725 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 726 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 727 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 728 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 729 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 730 } 731 return SDValue(); 732} 733 734SDValue DAGCombiner::combine(SDNode *N) { 735 736 SDValue RV = visit(N); 737 738 // If nothing happened, try a target-specific DAG combine. 739 if (RV.getNode() == 0) { 740 assert(N->getOpcode() != ISD::DELETED_NODE && 741 "Node was deleted but visit returned NULL!"); 742 743 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 744 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 745 746 // Expose the DAG combiner to the target combiner impls. 747 TargetLowering::DAGCombinerInfo 748 DagCombineInfo(DAG, !AfterLegalize, false, this); 749 750 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 751 } 752 } 753 754 // If N is a commutative binary node, try commuting it to enable more 755 // sdisel CSE. 756 if (RV.getNode() == 0 && 757 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 758 N->getNumValues() == 1) { 759 SDValue N0 = N->getOperand(0); 760 SDValue N1 = N->getOperand(1); 761 // Constant operands are canonicalized to RHS. 762 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 763 SDValue Ops[] = { N1, N0 }; 764 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 765 Ops, 2); 766 if (CSENode) 767 return SDValue(CSENode, 0); 768 } 769 } 770 771 return RV; 772} 773 774/// getInputChainForNode - Given a node, return its input chain if it has one, 775/// otherwise return a null sd operand. 776static SDValue getInputChainForNode(SDNode *N) { 777 if (unsigned NumOps = N->getNumOperands()) { 778 if (N->getOperand(0).getValueType() == MVT::Other) 779 return N->getOperand(0); 780 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 781 return N->getOperand(NumOps-1); 782 for (unsigned i = 1; i < NumOps-1; ++i) 783 if (N->getOperand(i).getValueType() == MVT::Other) 784 return N->getOperand(i); 785 } 786 return SDValue(0, 0); 787} 788 789SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 790 // If N has two operands, where one has an input chain equal to the other, 791 // the 'other' chain is redundant. 792 if (N->getNumOperands() == 2) { 793 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 794 return N->getOperand(0); 795 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 796 return N->getOperand(1); 797 } 798 799 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 800 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 801 SmallPtrSet<SDNode*, 16> SeenOps; 802 bool Changed = false; // If we should replace this token factor. 803 804 // Start out with this token factor. 805 TFs.push_back(N); 806 807 // Iterate through token factors. The TFs grows when new token factors are 808 // encountered. 809 for (unsigned i = 0; i < TFs.size(); ++i) { 810 SDNode *TF = TFs[i]; 811 812 // Check each of the operands. 813 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 814 SDValue Op = TF->getOperand(i); 815 816 switch (Op.getOpcode()) { 817 case ISD::EntryToken: 818 // Entry tokens don't need to be added to the list. They are 819 // rededundant. 820 Changed = true; 821 break; 822 823 case ISD::TokenFactor: 824 if ((CombinerAA || Op.hasOneUse()) && 825 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 826 // Queue up for processing. 827 TFs.push_back(Op.getNode()); 828 // Clean up in case the token factor is removed. 829 AddToWorkList(Op.getNode()); 830 Changed = true; 831 break; 832 } 833 // Fall thru 834 835 default: 836 // Only add if it isn't already in the list. 837 if (SeenOps.insert(Op.getNode())) 838 Ops.push_back(Op); 839 else 840 Changed = true; 841 break; 842 } 843 } 844 } 845 846 SDValue Result; 847 848 // If we've change things around then replace token factor. 849 if (Changed) { 850 if (Ops.empty()) { 851 // The entry token is the only possible outcome. 852 Result = DAG.getEntryNode(); 853 } else { 854 // New and improved token factor. 855 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 856 } 857 858 // Don't add users to work list. 859 return CombineTo(N, Result, false); 860 } 861 862 return Result; 863} 864 865/// MERGE_VALUES can always be eliminated. 866SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 867 WorkListRemover DeadNodes(*this); 868 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 869 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 870 &DeadNodes); 871 removeFromWorkList(N); 872 DAG.DeleteNode(N); 873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 874} 875 876 877static 878SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 879 MVT VT = N0.getValueType(); 880 SDValue N00 = N0.getOperand(0); 881 SDValue N01 = N0.getOperand(1); 882 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 883 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 884 isa<ConstantSDNode>(N00.getOperand(1))) { 885 N0 = DAG.getNode(ISD::ADD, VT, 886 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 887 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 888 return DAG.getNode(ISD::ADD, VT, N0, N1); 889 } 890 return SDValue(); 891} 892 893static 894SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 895 SelectionDAG &DAG) { 896 MVT VT = N->getValueType(0); 897 unsigned Opc = N->getOpcode(); 898 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 899 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 900 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 901 ISD::CondCode CC = ISD::SETCC_INVALID; 902 if (isSlctCC) 903 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 904 else { 905 SDValue CCOp = Slct.getOperand(0); 906 if (CCOp.getOpcode() == ISD::SETCC) 907 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 908 } 909 910 bool DoXform = false; 911 bool InvCC = false; 912 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 913 "Bad input!"); 914 if (LHS.getOpcode() == ISD::Constant && 915 cast<ConstantSDNode>(LHS)->isNullValue()) 916 DoXform = true; 917 else if (CC != ISD::SETCC_INVALID && 918 RHS.getOpcode() == ISD::Constant && 919 cast<ConstantSDNode>(RHS)->isNullValue()) { 920 std::swap(LHS, RHS); 921 SDValue Op0 = Slct.getOperand(0); 922 bool isInt = (isSlctCC ? Op0.getValueType() : 923 Op0.getOperand(0).getValueType()).isInteger(); 924 CC = ISD::getSetCCInverse(CC, isInt); 925 DoXform = true; 926 InvCC = true; 927 } 928 929 if (DoXform) { 930 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 931 if (isSlctCC) 932 return DAG.getSelectCC(OtherOp, Result, 933 Slct.getOperand(0), Slct.getOperand(1), CC); 934 SDValue CCOp = Slct.getOperand(0); 935 if (InvCC) 936 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 937 CCOp.getOperand(1), CC); 938 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 939 } 940 return SDValue(); 941} 942 943SDValue DAGCombiner::visitADD(SDNode *N) { 944 SDValue N0 = N->getOperand(0); 945 SDValue N1 = N->getOperand(1); 946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 948 MVT VT = N0.getValueType(); 949 950 // fold vector ops 951 if (VT.isVector()) { 952 SDValue FoldedVOp = SimplifyVBinOp(N); 953 if (FoldedVOp.getNode()) return FoldedVOp; 954 } 955 956 // fold (add x, undef) -> undef 957 if (N0.getOpcode() == ISD::UNDEF) 958 return N0; 959 if (N1.getOpcode() == ISD::UNDEF) 960 return N1; 961 // fold (add c1, c2) -> c1+c2 962 if (N0C && N1C) 963 return DAG.getConstant(N0C->getAPIntValue() + N1C->getAPIntValue(), VT); 964 // canonicalize constant to RHS 965 if (N0C && !N1C) 966 return DAG.getNode(ISD::ADD, VT, N1, N0); 967 // fold (add x, 0) -> x 968 if (N1C && N1C->isNullValue()) 969 return N0; 970 // fold ((c1-A)+c2) -> (c1+c2)-A 971 if (N1C && N0.getOpcode() == ISD::SUB) 972 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 973 return DAG.getNode(ISD::SUB, VT, 974 DAG.getConstant(N1C->getAPIntValue()+ 975 N0C->getAPIntValue(), VT), 976 N0.getOperand(1)); 977 // reassociate add 978 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 979 if (RADD.getNode() != 0) 980 return RADD; 981 // fold ((0-A) + B) -> B-A 982 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 983 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 984 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 985 // fold (A + (0-B)) -> A-B 986 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 987 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 988 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 989 // fold (A+(B-A)) -> B 990 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 991 return N1.getOperand(0); 992 993 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 994 return SDValue(N, 0); 995 996 // fold (a+b) -> (a|b) iff a and b share no bits. 997 if (VT.isInteger() && !VT.isVector()) { 998 APInt LHSZero, LHSOne; 999 APInt RHSZero, RHSOne; 1000 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1001 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1002 if (LHSZero.getBoolValue()) { 1003 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1004 1005 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1006 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1007 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1008 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1009 return DAG.getNode(ISD::OR, VT, N0, N1); 1010 } 1011 } 1012 1013 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1014 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1015 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1016 if (Result.getNode()) return Result; 1017 } 1018 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1019 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1020 if (Result.getNode()) return Result; 1021 } 1022 1023 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1024 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1025 SDValue Result = combineSelectAndUse(N, N0, N1, DAG); 1026 if (Result.getNode()) return Result; 1027 } 1028 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1029 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1030 if (Result.getNode()) return Result; 1031 } 1032 1033 return SDValue(); 1034} 1035 1036SDValue DAGCombiner::visitADDC(SDNode *N) { 1037 SDValue N0 = N->getOperand(0); 1038 SDValue N1 = N->getOperand(1); 1039 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1040 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1041 MVT VT = N0.getValueType(); 1042 1043 // If the flag result is dead, turn this into an ADD. 1044 if (N->hasNUsesOfValue(0, 1)) 1045 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1046 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1047 1048 // canonicalize constant to RHS. 1049 if (N0C && !N1C) 1050 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1051 1052 // fold (addc x, 0) -> x + no carry out 1053 if (N1C && N1C->isNullValue()) 1054 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1055 1056 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1057 APInt LHSZero, LHSOne; 1058 APInt RHSZero, RHSOne; 1059 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1060 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1061 if (LHSZero.getBoolValue()) { 1062 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1063 1064 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1065 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1066 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1067 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1068 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1069 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1070 } 1071 1072 return SDValue(); 1073} 1074 1075SDValue DAGCombiner::visitADDE(SDNode *N) { 1076 SDValue N0 = N->getOperand(0); 1077 SDValue N1 = N->getOperand(1); 1078 SDValue CarryIn = N->getOperand(2); 1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1081 //MVT VT = N0.getValueType(); 1082 1083 // canonicalize constant to RHS 1084 if (N0C && !N1C) 1085 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1086 1087 // fold (adde x, y, false) -> (addc x, y) 1088 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1089 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1090 1091 return SDValue(); 1092} 1093 1094 1095 1096SDValue DAGCombiner::visitSUB(SDNode *N) { 1097 SDValue N0 = N->getOperand(0); 1098 SDValue N1 = N->getOperand(1); 1099 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1101 MVT VT = N0.getValueType(); 1102 1103 // fold vector ops 1104 if (VT.isVector()) { 1105 SDValue FoldedVOp = SimplifyVBinOp(N); 1106 if (FoldedVOp.getNode()) return FoldedVOp; 1107 } 1108 1109 // fold (sub x, x) -> 0 1110 if (N0 == N1) 1111 return DAG.getConstant(0, N->getValueType(0)); 1112 // fold (sub c1, c2) -> c1-c2 1113 if (N0C && N1C) 1114 return DAG.getNode(ISD::SUB, VT, N0, N1); 1115 // fold (sub x, c) -> (add x, -c) 1116 if (N1C) 1117 return DAG.getNode(ISD::ADD, VT, N0, 1118 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1119 // fold (A+B)-A -> B 1120 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1121 return N0.getOperand(1); 1122 // fold (A+B)-B -> A 1123 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1124 return N0.getOperand(0); 1125 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1126 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1127 SDValue Result = combineSelectAndUse(N, N1, N0, DAG); 1128 if (Result.getNode()) return Result; 1129 } 1130 // If either operand of a sub is undef, the result is undef 1131 if (N0.getOpcode() == ISD::UNDEF) 1132 return N0; 1133 if (N1.getOpcode() == ISD::UNDEF) 1134 return N1; 1135 1136 return SDValue(); 1137} 1138 1139SDValue DAGCombiner::visitMUL(SDNode *N) { 1140 SDValue N0 = N->getOperand(0); 1141 SDValue N1 = N->getOperand(1); 1142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1144 MVT VT = N0.getValueType(); 1145 1146 // fold vector ops 1147 if (VT.isVector()) { 1148 SDValue FoldedVOp = SimplifyVBinOp(N); 1149 if (FoldedVOp.getNode()) return FoldedVOp; 1150 } 1151 1152 // fold (mul x, undef) -> 0 1153 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1154 return DAG.getConstant(0, VT); 1155 // fold (mul c1, c2) -> c1*c2 1156 if (N0C && N1C) 1157 return DAG.getNode(ISD::MUL, VT, N0, N1); 1158 // canonicalize constant to RHS 1159 if (N0C && !N1C) 1160 return DAG.getNode(ISD::MUL, VT, N1, N0); 1161 // fold (mul x, 0) -> 0 1162 if (N1C && N1C->isNullValue()) 1163 return N1; 1164 // fold (mul x, -1) -> 0-x 1165 if (N1C && N1C->isAllOnesValue()) 1166 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1167 // fold (mul x, (1 << c)) -> x << c 1168 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1169 return DAG.getNode(ISD::SHL, VT, N0, 1170 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1171 TLI.getShiftAmountTy())); 1172 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1173 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1174 // FIXME: If the input is something that is easily negated (e.g. a 1175 // single-use add), we should put the negate there. 1176 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1177 DAG.getNode(ISD::SHL, VT, N0, 1178 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1179 TLI.getShiftAmountTy()))); 1180 } 1181 1182 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1183 if (N1C && N0.getOpcode() == ISD::SHL && 1184 isa<ConstantSDNode>(N0.getOperand(1))) { 1185 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1186 AddToWorkList(C3.getNode()); 1187 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1188 } 1189 1190 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1191 // use. 1192 { 1193 SDValue Sh(0,0), Y(0,0); 1194 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1195 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1196 N0.getNode()->hasOneUse()) { 1197 Sh = N0; Y = N1; 1198 } else if (N1.getOpcode() == ISD::SHL && 1199 isa<ConstantSDNode>(N1.getOperand(1)) && 1200 N1.getNode()->hasOneUse()) { 1201 Sh = N1; Y = N0; 1202 } 1203 if (Sh.getNode()) { 1204 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1205 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1206 } 1207 } 1208 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1209 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1210 isa<ConstantSDNode>(N0.getOperand(1))) { 1211 return DAG.getNode(ISD::ADD, VT, 1212 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1213 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1214 } 1215 1216 // reassociate mul 1217 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1218 if (RMUL.getNode() != 0) 1219 return RMUL; 1220 1221 return SDValue(); 1222} 1223 1224SDValue DAGCombiner::visitSDIV(SDNode *N) { 1225 SDValue N0 = N->getOperand(0); 1226 SDValue N1 = N->getOperand(1); 1227 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1228 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1229 MVT VT = N->getValueType(0); 1230 1231 // fold vector ops 1232 if (VT.isVector()) { 1233 SDValue FoldedVOp = SimplifyVBinOp(N); 1234 if (FoldedVOp.getNode()) return FoldedVOp; 1235 } 1236 1237 // fold (sdiv c1, c2) -> c1/c2 1238 if (N0C && N1C && !N1C->isNullValue()) 1239 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1240 // fold (sdiv X, 1) -> X 1241 if (N1C && N1C->getSignExtended() == 1LL) 1242 return N0; 1243 // fold (sdiv X, -1) -> 0-X 1244 if (N1C && N1C->isAllOnesValue()) 1245 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1246 // If we know the sign bits of both operands are zero, strength reduce to a 1247 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1248 if (!VT.isVector()) { 1249 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1250 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1251 } 1252 // fold (sdiv X, pow2) -> simple ops after legalize 1253 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1254 (isPowerOf2_64(N1C->getSignExtended()) || 1255 isPowerOf2_64(-N1C->getSignExtended()))) { 1256 // If dividing by powers of two is cheap, then don't perform the following 1257 // fold. 1258 if (TLI.isPow2DivCheap()) 1259 return SDValue(); 1260 int64_t pow2 = N1C->getSignExtended(); 1261 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1262 unsigned lg2 = Log2_64(abs2); 1263 // Splat the sign bit into the register 1264 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1265 DAG.getConstant(VT.getSizeInBits()-1, 1266 TLI.getShiftAmountTy())); 1267 AddToWorkList(SGN.getNode()); 1268 // Add (N0 < 0) ? abs2 - 1 : 0; 1269 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1270 DAG.getConstant(VT.getSizeInBits()-lg2, 1271 TLI.getShiftAmountTy())); 1272 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1273 AddToWorkList(SRL.getNode()); 1274 AddToWorkList(ADD.getNode()); // Divide by pow2 1275 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1276 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1277 // If we're dividing by a positive value, we're done. Otherwise, we must 1278 // negate the result. 1279 if (pow2 > 0) 1280 return SRA; 1281 AddToWorkList(SRA.getNode()); 1282 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1283 } 1284 // if integer divide is expensive and we satisfy the requirements, emit an 1285 // alternate sequence. 1286 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1287 !TLI.isIntDivCheap()) { 1288 SDValue Op = BuildSDIV(N); 1289 if (Op.getNode()) return Op; 1290 } 1291 1292 // undef / X -> 0 1293 if (N0.getOpcode() == ISD::UNDEF) 1294 return DAG.getConstant(0, VT); 1295 // X / undef -> undef 1296 if (N1.getOpcode() == ISD::UNDEF) 1297 return N1; 1298 1299 return SDValue(); 1300} 1301 1302SDValue DAGCombiner::visitUDIV(SDNode *N) { 1303 SDValue N0 = N->getOperand(0); 1304 SDValue N1 = N->getOperand(1); 1305 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1306 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1307 MVT VT = N->getValueType(0); 1308 1309 // fold vector ops 1310 if (VT.isVector()) { 1311 SDValue FoldedVOp = SimplifyVBinOp(N); 1312 if (FoldedVOp.getNode()) return FoldedVOp; 1313 } 1314 1315 // fold (udiv c1, c2) -> c1/c2 1316 if (N0C && N1C && !N1C->isNullValue()) 1317 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1318 // fold (udiv x, (1 << c)) -> x >>u c 1319 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1320 return DAG.getNode(ISD::SRL, VT, N0, 1321 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1322 TLI.getShiftAmountTy())); 1323 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1324 if (N1.getOpcode() == ISD::SHL) { 1325 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1326 if (SHC->getAPIntValue().isPowerOf2()) { 1327 MVT ADDVT = N1.getOperand(1).getValueType(); 1328 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1329 DAG.getConstant(SHC->getAPIntValue() 1330 .logBase2(), 1331 ADDVT)); 1332 AddToWorkList(Add.getNode()); 1333 return DAG.getNode(ISD::SRL, VT, N0, Add); 1334 } 1335 } 1336 } 1337 // fold (udiv x, c) -> alternate 1338 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1339 SDValue Op = BuildUDIV(N); 1340 if (Op.getNode()) return Op; 1341 } 1342 1343 // undef / X -> 0 1344 if (N0.getOpcode() == ISD::UNDEF) 1345 return DAG.getConstant(0, VT); 1346 // X / undef -> undef 1347 if (N1.getOpcode() == ISD::UNDEF) 1348 return N1; 1349 1350 return SDValue(); 1351} 1352 1353SDValue DAGCombiner::visitSREM(SDNode *N) { 1354 SDValue N0 = N->getOperand(0); 1355 SDValue N1 = N->getOperand(1); 1356 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1357 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1358 MVT VT = N->getValueType(0); 1359 1360 // fold (srem c1, c2) -> c1%c2 1361 if (N0C && N1C && !N1C->isNullValue()) 1362 return DAG.getNode(ISD::SREM, VT, N0, N1); 1363 // If we know the sign bits of both operands are zero, strength reduce to a 1364 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1365 if (!VT.isVector()) { 1366 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1367 return DAG.getNode(ISD::UREM, VT, N0, N1); 1368 } 1369 1370 // If X/C can be simplified by the division-by-constant logic, lower 1371 // X%C to the equivalent of X-X/C*C. 1372 if (N1C && !N1C->isNullValue()) { 1373 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1374 AddToWorkList(Div.getNode()); 1375 SDValue OptimizedDiv = combine(Div.getNode()); 1376 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1377 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1378 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1379 AddToWorkList(Mul.getNode()); 1380 return Sub; 1381 } 1382 } 1383 1384 // undef % X -> 0 1385 if (N0.getOpcode() == ISD::UNDEF) 1386 return DAG.getConstant(0, VT); 1387 // X % undef -> undef 1388 if (N1.getOpcode() == ISD::UNDEF) 1389 return N1; 1390 1391 return SDValue(); 1392} 1393 1394SDValue DAGCombiner::visitUREM(SDNode *N) { 1395 SDValue N0 = N->getOperand(0); 1396 SDValue N1 = N->getOperand(1); 1397 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1398 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1399 MVT VT = N->getValueType(0); 1400 1401 // fold (urem c1, c2) -> c1%c2 1402 if (N0C && N1C && !N1C->isNullValue()) 1403 return DAG.getNode(ISD::UREM, VT, N0, N1); 1404 // fold (urem x, pow2) -> (and x, pow2-1) 1405 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1406 return DAG.getNode(ISD::AND, VT, N0, 1407 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1408 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1409 if (N1.getOpcode() == ISD::SHL) { 1410 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1411 if (SHC->getAPIntValue().isPowerOf2()) { 1412 SDValue Add = 1413 DAG.getNode(ISD::ADD, VT, N1, 1414 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1415 VT)); 1416 AddToWorkList(Add.getNode()); 1417 return DAG.getNode(ISD::AND, VT, N0, Add); 1418 } 1419 } 1420 } 1421 1422 // If X/C can be simplified by the division-by-constant logic, lower 1423 // X%C to the equivalent of X-X/C*C. 1424 if (N1C && !N1C->isNullValue()) { 1425 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1426 AddToWorkList(Div.getNode()); 1427 SDValue OptimizedDiv = combine(Div.getNode()); 1428 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1429 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1430 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1431 AddToWorkList(Mul.getNode()); 1432 return Sub; 1433 } 1434 } 1435 1436 // undef % X -> 0 1437 if (N0.getOpcode() == ISD::UNDEF) 1438 return DAG.getConstant(0, VT); 1439 // X % undef -> undef 1440 if (N1.getOpcode() == ISD::UNDEF) 1441 return N1; 1442 1443 return SDValue(); 1444} 1445 1446SDValue DAGCombiner::visitMULHS(SDNode *N) { 1447 SDValue N0 = N->getOperand(0); 1448 SDValue N1 = N->getOperand(1); 1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1450 MVT VT = N->getValueType(0); 1451 1452 // fold (mulhs x, 0) -> 0 1453 if (N1C && N1C->isNullValue()) 1454 return N1; 1455 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1456 if (N1C && N1C->getAPIntValue() == 1) 1457 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1458 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1459 TLI.getShiftAmountTy())); 1460 // fold (mulhs x, undef) -> 0 1461 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1462 return DAG.getConstant(0, VT); 1463 1464 return SDValue(); 1465} 1466 1467SDValue DAGCombiner::visitMULHU(SDNode *N) { 1468 SDValue N0 = N->getOperand(0); 1469 SDValue N1 = N->getOperand(1); 1470 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1471 MVT VT = N->getValueType(0); 1472 1473 // fold (mulhu x, 0) -> 0 1474 if (N1C && N1C->isNullValue()) 1475 return N1; 1476 // fold (mulhu x, 1) -> 0 1477 if (N1C && N1C->getAPIntValue() == 1) 1478 return DAG.getConstant(0, N0.getValueType()); 1479 // fold (mulhu x, undef) -> 0 1480 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1481 return DAG.getConstant(0, VT); 1482 1483 return SDValue(); 1484} 1485 1486/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1487/// compute two values. LoOp and HiOp give the opcodes for the two computations 1488/// that are being performed. Return true if a simplification was made. 1489/// 1490SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1491 unsigned HiOp) { 1492 // If the high half is not needed, just compute the low half. 1493 bool HiExists = N->hasAnyUseOfValue(1); 1494 if (!HiExists && 1495 (!AfterLegalize || 1496 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1497 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1498 N->getNumOperands()); 1499 return CombineTo(N, Res, Res); 1500 } 1501 1502 // If the low half is not needed, just compute the high half. 1503 bool LoExists = N->hasAnyUseOfValue(0); 1504 if (!LoExists && 1505 (!AfterLegalize || 1506 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1507 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1508 N->getNumOperands()); 1509 return CombineTo(N, Res, Res); 1510 } 1511 1512 // If both halves are used, return as it is. 1513 if (LoExists && HiExists) 1514 return SDValue(); 1515 1516 // If the two computed results can be simplified separately, separate them. 1517 if (LoExists) { 1518 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1519 N->op_begin(), N->getNumOperands()); 1520 AddToWorkList(Lo.getNode()); 1521 SDValue LoOpt = combine(Lo.getNode()); 1522 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1523 (!AfterLegalize || 1524 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1525 return CombineTo(N, LoOpt, LoOpt); 1526 } 1527 1528 if (HiExists) { 1529 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1530 N->op_begin(), N->getNumOperands()); 1531 AddToWorkList(Hi.getNode()); 1532 SDValue HiOpt = combine(Hi.getNode()); 1533 if (HiOpt.getNode() && HiOpt != Hi && 1534 (!AfterLegalize || 1535 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1536 return CombineTo(N, HiOpt, HiOpt); 1537 } 1538 return SDValue(); 1539} 1540 1541SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1542 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1543 if (Res.getNode()) return Res; 1544 1545 return SDValue(); 1546} 1547 1548SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1549 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1550 if (Res.getNode()) return Res; 1551 1552 return SDValue(); 1553} 1554 1555SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1556 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1557 if (Res.getNode()) return Res; 1558 1559 return SDValue(); 1560} 1561 1562SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1563 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1564 if (Res.getNode()) return Res; 1565 1566 return SDValue(); 1567} 1568 1569/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1570/// two operands of the same opcode, try to simplify it. 1571SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1572 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1573 MVT VT = N0.getValueType(); 1574 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1575 1576 // For each of OP in AND/OR/XOR: 1577 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1578 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1579 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1580 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1581 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1582 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1583 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1584 SDValue ORNode = DAG.getNode(N->getOpcode(), 1585 N0.getOperand(0).getValueType(), 1586 N0.getOperand(0), N1.getOperand(0)); 1587 AddToWorkList(ORNode.getNode()); 1588 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1589 } 1590 1591 // For each of OP in SHL/SRL/SRA/AND... 1592 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1593 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1594 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1595 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1596 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1597 N0.getOperand(1) == N1.getOperand(1)) { 1598 SDValue ORNode = DAG.getNode(N->getOpcode(), 1599 N0.getOperand(0).getValueType(), 1600 N0.getOperand(0), N1.getOperand(0)); 1601 AddToWorkList(ORNode.getNode()); 1602 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1603 } 1604 1605 return SDValue(); 1606} 1607 1608SDValue DAGCombiner::visitAND(SDNode *N) { 1609 SDValue N0 = N->getOperand(0); 1610 SDValue N1 = N->getOperand(1); 1611 SDValue LL, LR, RL, RR, CC0, CC1; 1612 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1614 MVT VT = N1.getValueType(); 1615 unsigned BitWidth = VT.getSizeInBits(); 1616 1617 // fold vector ops 1618 if (VT.isVector()) { 1619 SDValue FoldedVOp = SimplifyVBinOp(N); 1620 if (FoldedVOp.getNode()) return FoldedVOp; 1621 } 1622 1623 // fold (and x, undef) -> 0 1624 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1625 return DAG.getConstant(0, VT); 1626 // fold (and c1, c2) -> c1&c2 1627 if (N0C && N1C) 1628 return DAG.getNode(ISD::AND, VT, N0, N1); 1629 // canonicalize constant to RHS 1630 if (N0C && !N1C) 1631 return DAG.getNode(ISD::AND, VT, N1, N0); 1632 // fold (and x, -1) -> x 1633 if (N1C && N1C->isAllOnesValue()) 1634 return N0; 1635 // if (and x, c) is known to be zero, return 0 1636 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1637 APInt::getAllOnesValue(BitWidth))) 1638 return DAG.getConstant(0, VT); 1639 // reassociate and 1640 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1641 if (RAND.getNode() != 0) 1642 return RAND; 1643 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1644 if (N1C && N0.getOpcode() == ISD::OR) 1645 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1646 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1647 return N1; 1648 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1649 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1650 SDValue N0Op0 = N0.getOperand(0); 1651 APInt Mask = ~N1C->getAPIntValue(); 1652 Mask.trunc(N0Op0.getValueSizeInBits()); 1653 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1654 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1655 N0Op0); 1656 1657 // Replace uses of the AND with uses of the Zero extend node. 1658 CombineTo(N, Zext); 1659 1660 // We actually want to replace all uses of the any_extend with the 1661 // zero_extend, to avoid duplicating things. This will later cause this 1662 // AND to be folded. 1663 CombineTo(N0.getNode(), Zext); 1664 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1665 } 1666 } 1667 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1668 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1669 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1670 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1671 1672 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1673 LL.getValueType().isInteger()) { 1674 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1675 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1676 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1677 AddToWorkList(ORNode.getNode()); 1678 return DAG.getSetCC(VT, ORNode, LR, Op1); 1679 } 1680 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1681 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1682 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1683 AddToWorkList(ANDNode.getNode()); 1684 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1685 } 1686 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1687 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1688 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1689 AddToWorkList(ORNode.getNode()); 1690 return DAG.getSetCC(VT, ORNode, LR, Op1); 1691 } 1692 } 1693 // canonicalize equivalent to ll == rl 1694 if (LL == RR && LR == RL) { 1695 Op1 = ISD::getSetCCSwappedOperands(Op1); 1696 std::swap(RL, RR); 1697 } 1698 if (LL == RL && LR == RR) { 1699 bool isInteger = LL.getValueType().isInteger(); 1700 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1701 if (Result != ISD::SETCC_INVALID) 1702 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1703 } 1704 } 1705 1706 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1707 if (N0.getOpcode() == N1.getOpcode()) { 1708 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1709 if (Tmp.getNode()) return Tmp; 1710 } 1711 1712 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1713 // fold (and (sra)) -> (and (srl)) when possible. 1714 if (!VT.isVector() && 1715 SimplifyDemandedBits(SDValue(N, 0))) 1716 return SDValue(N, 0); 1717 // fold (zext_inreg (extload x)) -> (zextload x) 1718 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1719 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1720 MVT EVT = LN0->getMemoryVT(); 1721 // If we zero all the possible extended bits, then we can turn this into 1722 // a zextload if we are running before legalize or the operation is legal. 1723 unsigned BitWidth = N1.getValueSizeInBits(); 1724 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1725 BitWidth - EVT.getSizeInBits())) && 1726 ((!AfterLegalize && !LN0->isVolatile()) || 1727 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1728 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1729 LN0->getBasePtr(), LN0->getSrcValue(), 1730 LN0->getSrcValueOffset(), EVT, 1731 LN0->isVolatile(), 1732 LN0->getAlignment()); 1733 AddToWorkList(N); 1734 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1735 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1736 } 1737 } 1738 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1739 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1740 N0.hasOneUse()) { 1741 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1742 MVT EVT = LN0->getMemoryVT(); 1743 // If we zero all the possible extended bits, then we can turn this into 1744 // a zextload if we are running before legalize or the operation is legal. 1745 unsigned BitWidth = N1.getValueSizeInBits(); 1746 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1747 BitWidth - EVT.getSizeInBits())) && 1748 ((!AfterLegalize && !LN0->isVolatile()) || 1749 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1750 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1751 LN0->getBasePtr(), LN0->getSrcValue(), 1752 LN0->getSrcValueOffset(), EVT, 1753 LN0->isVolatile(), 1754 LN0->getAlignment()); 1755 AddToWorkList(N); 1756 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1757 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1758 } 1759 } 1760 1761 // fold (and (load x), 255) -> (zextload x, i8) 1762 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1763 if (N1C && N0.getOpcode() == ISD::LOAD) { 1764 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1765 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1766 LN0->isUnindexed() && N0.hasOneUse() && 1767 // Do not change the width of a volatile load. 1768 !LN0->isVolatile()) { 1769 MVT EVT = MVT::Other; 1770 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1771 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1772 EVT = MVT::getIntegerVT(ActiveBits); 1773 1774 MVT LoadedVT = LN0->getMemoryVT(); 1775 // Do not generate loads of non-round integer types since these can 1776 // be expensive (and would be wrong if the type is not byte sized). 1777 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1778 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1779 MVT PtrType = N0.getOperand(1).getValueType(); 1780 // For big endian targets, we need to add an offset to the pointer to 1781 // load the correct bytes. For little endian systems, we merely need to 1782 // read fewer bytes from the same pointer. 1783 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1784 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1785 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1786 unsigned Alignment = LN0->getAlignment(); 1787 SDValue NewPtr = LN0->getBasePtr(); 1788 if (TLI.isBigEndian()) { 1789 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1790 DAG.getConstant(PtrOff, PtrType)); 1791 Alignment = MinAlign(Alignment, PtrOff); 1792 } 1793 AddToWorkList(NewPtr.getNode()); 1794 SDValue Load = 1795 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1796 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1797 LN0->isVolatile(), Alignment); 1798 AddToWorkList(N); 1799 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1800 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1801 } 1802 } 1803 } 1804 1805 return SDValue(); 1806} 1807 1808SDValue DAGCombiner::visitOR(SDNode *N) { 1809 SDValue N0 = N->getOperand(0); 1810 SDValue N1 = N->getOperand(1); 1811 SDValue LL, LR, RL, RR, CC0, CC1; 1812 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1813 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1814 MVT VT = N1.getValueType(); 1815 1816 // fold vector ops 1817 if (VT.isVector()) { 1818 SDValue FoldedVOp = SimplifyVBinOp(N); 1819 if (FoldedVOp.getNode()) return FoldedVOp; 1820 } 1821 1822 // fold (or x, undef) -> -1 1823 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1824 return DAG.getConstant(~0ULL, VT); 1825 // fold (or c1, c2) -> c1|c2 1826 if (N0C && N1C) 1827 return DAG.getNode(ISD::OR, VT, N0, N1); 1828 // canonicalize constant to RHS 1829 if (N0C && !N1C) 1830 return DAG.getNode(ISD::OR, VT, N1, N0); 1831 // fold (or x, 0) -> x 1832 if (N1C && N1C->isNullValue()) 1833 return N0; 1834 // fold (or x, -1) -> -1 1835 if (N1C && N1C->isAllOnesValue()) 1836 return N1; 1837 // fold (or x, c) -> c iff (x & ~c) == 0 1838 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1839 return N1; 1840 // reassociate or 1841 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1842 if (ROR.getNode() != 0) 1843 return ROR; 1844 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1845 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1846 isa<ConstantSDNode>(N0.getOperand(1))) { 1847 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1848 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1849 N1), 1850 DAG.getConstant(N1C->getAPIntValue() | 1851 C1->getAPIntValue(), VT)); 1852 } 1853 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1854 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1855 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1856 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1857 1858 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1859 LL.getValueType().isInteger()) { 1860 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1861 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1862 if (cast<ConstantSDNode>(LR)->isNullValue() && 1863 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1864 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1865 AddToWorkList(ORNode.getNode()); 1866 return DAG.getSetCC(VT, ORNode, LR, Op1); 1867 } 1868 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1869 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1870 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1871 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1872 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1873 AddToWorkList(ANDNode.getNode()); 1874 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1875 } 1876 } 1877 // canonicalize equivalent to ll == rl 1878 if (LL == RR && LR == RL) { 1879 Op1 = ISD::getSetCCSwappedOperands(Op1); 1880 std::swap(RL, RR); 1881 } 1882 if (LL == RL && LR == RR) { 1883 bool isInteger = LL.getValueType().isInteger(); 1884 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1885 if (Result != ISD::SETCC_INVALID) 1886 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1887 } 1888 } 1889 1890 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1891 if (N0.getOpcode() == N1.getOpcode()) { 1892 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1893 if (Tmp.getNode()) return Tmp; 1894 } 1895 1896 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1897 if (N0.getOpcode() == ISD::AND && 1898 N1.getOpcode() == ISD::AND && 1899 N0.getOperand(1).getOpcode() == ISD::Constant && 1900 N1.getOperand(1).getOpcode() == ISD::Constant && 1901 // Don't increase # computations. 1902 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1903 // We can only do this xform if we know that bits from X that are set in C2 1904 // but not in C1 are already zero. Likewise for Y. 1905 const APInt &LHSMask = 1906 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1907 const APInt &RHSMask = 1908 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1909 1910 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1911 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1912 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1913 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1914 } 1915 } 1916 1917 1918 // See if this is some rotate idiom. 1919 if (SDNode *Rot = MatchRotate(N0, N1)) 1920 return SDValue(Rot, 0); 1921 1922 return SDValue(); 1923} 1924 1925 1926/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1927static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 1928 if (Op.getOpcode() == ISD::AND) { 1929 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1930 Mask = Op.getOperand(1); 1931 Op = Op.getOperand(0); 1932 } else { 1933 return false; 1934 } 1935 } 1936 1937 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1938 Shift = Op; 1939 return true; 1940 } 1941 return false; 1942} 1943 1944 1945// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1946// idioms for rotate, and if the target supports rotation instructions, generate 1947// a rot[lr]. 1948SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 1949 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 1950 MVT VT = LHS.getValueType(); 1951 if (!TLI.isTypeLegal(VT)) return 0; 1952 1953 // The target must have at least one rotate flavor. 1954 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1955 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1956 if (!HasROTL && !HasROTR) return 0; 1957 1958 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1959 SDValue LHSShift; // The shift. 1960 SDValue LHSMask; // AND value if any. 1961 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1962 return 0; // Not part of a rotate. 1963 1964 SDValue RHSShift; // The shift. 1965 SDValue RHSMask; // AND value if any. 1966 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1967 return 0; // Not part of a rotate. 1968 1969 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1970 return 0; // Not shifting the same value. 1971 1972 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1973 return 0; // Shifts must disagree. 1974 1975 // Canonicalize shl to left side in a shl/srl pair. 1976 if (RHSShift.getOpcode() == ISD::SHL) { 1977 std::swap(LHS, RHS); 1978 std::swap(LHSShift, RHSShift); 1979 std::swap(LHSMask , RHSMask ); 1980 } 1981 1982 unsigned OpSizeInBits = VT.getSizeInBits(); 1983 SDValue LHSShiftArg = LHSShift.getOperand(0); 1984 SDValue LHSShiftAmt = LHSShift.getOperand(1); 1985 SDValue RHSShiftAmt = RHSShift.getOperand(1); 1986 1987 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1988 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1989 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1990 RHSShiftAmt.getOpcode() == ISD::Constant) { 1991 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 1992 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 1993 if ((LShVal + RShVal) != OpSizeInBits) 1994 return 0; 1995 1996 SDValue Rot; 1997 if (HasROTL) 1998 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1999 else 2000 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2001 2002 // If there is an AND of either shifted operand, apply it to the result. 2003 if (LHSMask.getNode() || RHSMask.getNode()) { 2004 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2005 2006 if (LHSMask.getNode()) { 2007 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2008 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2009 } 2010 if (RHSMask.getNode()) { 2011 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2012 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2013 } 2014 2015 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2016 } 2017 2018 return Rot.getNode(); 2019 } 2020 2021 // If there is a mask here, and we have a variable shift, we can't be sure 2022 // that we're masking out the right stuff. 2023 if (LHSMask.getNode() || RHSMask.getNode()) 2024 return 0; 2025 2026 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2027 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2028 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2029 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2030 if (ConstantSDNode *SUBC = 2031 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2032 if (SUBC->getAPIntValue() == OpSizeInBits) { 2033 if (HasROTL) 2034 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2035 else 2036 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2037 } 2038 } 2039 } 2040 2041 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2042 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2043 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2044 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2045 if (ConstantSDNode *SUBC = 2046 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2047 if (SUBC->getAPIntValue() == OpSizeInBits) { 2048 if (HasROTR) 2049 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2050 else 2051 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2052 } 2053 } 2054 } 2055 2056 // Look for sign/zext/any-extended cases: 2057 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2058 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2059 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2060 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2061 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2062 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2063 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2064 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2065 if (RExtOp0.getOpcode() == ISD::SUB && 2066 RExtOp0.getOperand(1) == LExtOp0) { 2067 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2068 // (rotl x, y) 2069 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2070 // (rotr x, (sub 32, y)) 2071 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2072 if (SUBC->getAPIntValue() == OpSizeInBits) { 2073 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2074 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2075 } 2076 } 2077 } else if (LExtOp0.getOpcode() == ISD::SUB && 2078 RExtOp0 == LExtOp0.getOperand(1)) { 2079 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2080 // (rotr x, y) 2081 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2082 // (rotl x, (sub 32, y)) 2083 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2084 if (SUBC->getAPIntValue() == OpSizeInBits) { 2085 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2086 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2087 } 2088 } 2089 } 2090 } 2091 2092 return 0; 2093} 2094 2095 2096SDValue DAGCombiner::visitXOR(SDNode *N) { 2097 SDValue N0 = N->getOperand(0); 2098 SDValue N1 = N->getOperand(1); 2099 SDValue LHS, RHS, CC; 2100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2102 MVT VT = N0.getValueType(); 2103 2104 // fold vector ops 2105 if (VT.isVector()) { 2106 SDValue FoldedVOp = SimplifyVBinOp(N); 2107 if (FoldedVOp.getNode()) return FoldedVOp; 2108 } 2109 2110 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2111 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2112 return DAG.getConstant(0, VT); 2113 // fold (xor x, undef) -> undef 2114 if (N0.getOpcode() == ISD::UNDEF) 2115 return N0; 2116 if (N1.getOpcode() == ISD::UNDEF) 2117 return N1; 2118 // fold (xor c1, c2) -> c1^c2 2119 if (N0C && N1C) 2120 return DAG.getNode(ISD::XOR, VT, N0, N1); 2121 // canonicalize constant to RHS 2122 if (N0C && !N1C) 2123 return DAG.getNode(ISD::XOR, VT, N1, N0); 2124 // fold (xor x, 0) -> x 2125 if (N1C && N1C->isNullValue()) 2126 return N0; 2127 // reassociate xor 2128 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2129 if (RXOR.getNode() != 0) 2130 return RXOR; 2131 // fold !(x cc y) -> (x !cc y) 2132 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2133 bool isInt = LHS.getValueType().isInteger(); 2134 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2135 isInt); 2136 if (N0.getOpcode() == ISD::SETCC) 2137 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2138 if (N0.getOpcode() == ISD::SELECT_CC) 2139 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2140 assert(0 && "Unhandled SetCC Equivalent!"); 2141 abort(); 2142 } 2143 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2144 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2145 N0.getNode()->hasOneUse() && 2146 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2147 SDValue V = N0.getOperand(0); 2148 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2149 DAG.getConstant(1, V.getValueType())); 2150 AddToWorkList(V.getNode()); 2151 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2152 } 2153 2154 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2155 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2156 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2157 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2158 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2159 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2160 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2161 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2162 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2163 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2164 } 2165 } 2166 // fold !(x or y) -> (!x and !y) iff x or y are constants 2167 if (N1C && N1C->isAllOnesValue() && 2168 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2169 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2170 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2171 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2172 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2173 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2174 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2175 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2176 } 2177 } 2178 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2179 if (N1C && N0.getOpcode() == ISD::XOR) { 2180 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2181 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2182 if (N00C) 2183 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2184 DAG.getConstant(N1C->getAPIntValue()^ 2185 N00C->getAPIntValue(), VT)); 2186 if (N01C) 2187 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2188 DAG.getConstant(N1C->getAPIntValue()^ 2189 N01C->getAPIntValue(), VT)); 2190 } 2191 // fold (xor x, x) -> 0 2192 if (N0 == N1) { 2193 if (!VT.isVector()) { 2194 return DAG.getConstant(0, VT); 2195 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2196 // Produce a vector of zeros. 2197 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2198 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2199 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2200 } 2201 } 2202 2203 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2204 if (N0.getOpcode() == N1.getOpcode()) { 2205 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2206 if (Tmp.getNode()) return Tmp; 2207 } 2208 2209 // Simplify the expression using non-local knowledge. 2210 if (!VT.isVector() && 2211 SimplifyDemandedBits(SDValue(N, 0))) 2212 return SDValue(N, 0); 2213 2214 return SDValue(); 2215} 2216 2217/// visitShiftByConstant - Handle transforms common to the three shifts, when 2218/// the shift amount is a constant. 2219SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2220 SDNode *LHS = N->getOperand(0).getNode(); 2221 if (!LHS->hasOneUse()) return SDValue(); 2222 2223 // We want to pull some binops through shifts, so that we have (and (shift)) 2224 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2225 // thing happens with address calculations, so it's important to canonicalize 2226 // it. 2227 bool HighBitSet = false; // Can we transform this if the high bit is set? 2228 2229 switch (LHS->getOpcode()) { 2230 default: return SDValue(); 2231 case ISD::OR: 2232 case ISD::XOR: 2233 HighBitSet = false; // We can only transform sra if the high bit is clear. 2234 break; 2235 case ISD::AND: 2236 HighBitSet = true; // We can only transform sra if the high bit is set. 2237 break; 2238 case ISD::ADD: 2239 if (N->getOpcode() != ISD::SHL) 2240 return SDValue(); // only shl(add) not sr[al](add). 2241 HighBitSet = false; // We can only transform sra if the high bit is clear. 2242 break; 2243 } 2244 2245 // We require the RHS of the binop to be a constant as well. 2246 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2247 if (!BinOpCst) return SDValue(); 2248 2249 2250 // FIXME: disable this for unless the input to the binop is a shift by a 2251 // constant. If it is not a shift, it pessimizes some common cases like: 2252 // 2253 //void foo(int *X, int i) { X[i & 1235] = 1; } 2254 //int bar(int *X, int i) { return X[i & 255]; } 2255 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2256 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2257 BinOpLHSVal->getOpcode() != ISD::SRA && 2258 BinOpLHSVal->getOpcode() != ISD::SRL) || 2259 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2260 return SDValue(); 2261 2262 MVT VT = N->getValueType(0); 2263 2264 // If this is a signed shift right, and the high bit is modified 2265 // by the logical operation, do not perform the transformation. 2266 // The highBitSet boolean indicates the value of the high bit of 2267 // the constant which would cause it to be modified for this 2268 // operation. 2269 if (N->getOpcode() == ISD::SRA) { 2270 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2271 if (BinOpRHSSignSet != HighBitSet) 2272 return SDValue(); 2273 } 2274 2275 // Fold the constants, shifting the binop RHS by the shift amount. 2276 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2277 LHS->getOperand(1), N->getOperand(1)); 2278 2279 // Create the new shift. 2280 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2281 N->getOperand(1)); 2282 2283 // Create the new binop. 2284 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2285} 2286 2287 2288SDValue DAGCombiner::visitSHL(SDNode *N) { 2289 SDValue N0 = N->getOperand(0); 2290 SDValue N1 = N->getOperand(1); 2291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2292 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2293 MVT VT = N0.getValueType(); 2294 unsigned OpSizeInBits = VT.getSizeInBits(); 2295 2296 // fold (shl c1, c2) -> c1<<c2 2297 if (N0C && N1C) 2298 return DAG.getNode(ISD::SHL, VT, N0, N1); 2299 // fold (shl 0, x) -> 0 2300 if (N0C && N0C->isNullValue()) 2301 return N0; 2302 // fold (shl x, c >= size(x)) -> undef 2303 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2304 return DAG.getNode(ISD::UNDEF, VT); 2305 // fold (shl x, 0) -> x 2306 if (N1C && N1C->isNullValue()) 2307 return N0; 2308 // if (shl x, c) is known to be zero, return 0 2309 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2310 APInt::getAllOnesValue(VT.getSizeInBits()))) 2311 return DAG.getConstant(0, VT); 2312 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2313 // iff (trunc c) == c 2314 if (N1.getOpcode() == ISD::TRUNCATE && 2315 N1.getOperand(0).getOpcode() == ISD::AND) { 2316 SDValue N101 = N1.getOperand(0).getOperand(1); 2317 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101); 2318 if (N101C) { 2319 MVT TruncVT = N1.getValueType(); 2320 unsigned TruncBitSize = TruncVT.getSizeInBits(); 2321 APInt ShAmt = N101C->getAPIntValue(); 2322 if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) { 2323 SDValue N100 = N1.getOperand(0).getOperand(0); 2324 return DAG.getNode(ISD::SHL, VT, N0, 2325 DAG.getNode(ISD::AND, TruncVT, 2326 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2327 DAG.getConstant(N101C->getZExtValue(), 2328 TruncVT))); 2329 } 2330 } 2331 } 2332 2333 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2334 return SDValue(N, 0); 2335 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2336 if (N1C && N0.getOpcode() == ISD::SHL && 2337 N0.getOperand(1).getOpcode() == ISD::Constant) { 2338 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2339 uint64_t c2 = N1C->getZExtValue(); 2340 if (c1 + c2 > OpSizeInBits) 2341 return DAG.getConstant(0, VT); 2342 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2343 DAG.getConstant(c1 + c2, N1.getValueType())); 2344 } 2345 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2346 // (srl (and x, -1 << c1), c1-c2) 2347 if (N1C && N0.getOpcode() == ISD::SRL && 2348 N0.getOperand(1).getOpcode() == ISD::Constant) { 2349 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2350 uint64_t c2 = N1C->getZExtValue(); 2351 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2352 DAG.getConstant(~0ULL << c1, VT)); 2353 if (c2 > c1) 2354 return DAG.getNode(ISD::SHL, VT, Mask, 2355 DAG.getConstant(c2-c1, N1.getValueType())); 2356 else 2357 return DAG.getNode(ISD::SRL, VT, Mask, 2358 DAG.getConstant(c1-c2, N1.getValueType())); 2359 } 2360 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2361 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2362 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2363 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2364 2365 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2366} 2367 2368SDValue DAGCombiner::visitSRA(SDNode *N) { 2369 SDValue N0 = N->getOperand(0); 2370 SDValue N1 = N->getOperand(1); 2371 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2372 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2373 MVT VT = N0.getValueType(); 2374 2375 // fold (sra c1, c2) -> c1>>c2 2376 if (N0C && N1C) 2377 return DAG.getNode(ISD::SRA, VT, N0, N1); 2378 // fold (sra 0, x) -> 0 2379 if (N0C && N0C->isNullValue()) 2380 return N0; 2381 // fold (sra -1, x) -> -1 2382 if (N0C && N0C->isAllOnesValue()) 2383 return N0; 2384 // fold (sra x, c >= size(x)) -> undef 2385 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2386 return DAG.getNode(ISD::UNDEF, VT); 2387 // fold (sra x, 0) -> x 2388 if (N1C && N1C->isNullValue()) 2389 return N0; 2390 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2391 // sext_inreg. 2392 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2393 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2394 MVT EVT = MVT::getIntegerVT(LowBits); 2395 if (EVT.isSimple() && // TODO: remove when apint codegen support lands. 2396 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2398 DAG.getValueType(EVT)); 2399 } 2400 2401 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2402 if (N1C && N0.getOpcode() == ISD::SRA) { 2403 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2404 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2405 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2406 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2407 DAG.getConstant(Sum, N1C->getValueType(0))); 2408 } 2409 } 2410 2411 // fold sra (shl X, m), result_size - n 2412 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2413 // result_size - n != m. 2414 // If truncate is free for the target sext(shl) is likely to result in better 2415 // code. 2416 if (N0.getOpcode() == ISD::SHL) { 2417 // Get the two constanst of the shifts, CN0 = m, CN = n. 2418 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2419 if (N01C && N1C) { 2420 // Determine what the truncate's result bitsize and type would be. 2421 unsigned VTValSize = VT.getSizeInBits(); 2422 MVT TruncVT = 2423 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2424 // Determine the residual right-shift amount. 2425 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2426 2427 // If the shift is not a no-op (in which case this should be just a sign 2428 // extend already), the truncated to type is legal, sign_extend is legal 2429 // on that type, and the the truncate to that type is both legal and free, 2430 // perform the transform. 2431 if (ShiftAmt && 2432 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2433 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2434 TLI.isTruncateFree(VT, TruncVT)) { 2435 2436 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2437 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2438 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2439 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2440 } 2441 } 2442 } 2443 2444 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2445 // iff (trunc c) == c 2446 if (N1.getOpcode() == ISD::TRUNCATE && 2447 N1.getOperand(0).getOpcode() == ISD::AND) { 2448 SDValue N101 = N1.getOperand(0).getOperand(1); 2449 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101); 2450 if (N101C) { 2451 MVT TruncVT = N1.getValueType(); 2452 unsigned TruncBitSize = TruncVT.getSizeInBits(); 2453 APInt ShAmt = N101C->getAPIntValue(); 2454 if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) { 2455 SDValue N100 = N1.getOperand(0).getOperand(0); 2456 return DAG.getNode(ISD::SRA, VT, N0, 2457 DAG.getNode(ISD::AND, TruncVT, 2458 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2459 DAG.getConstant(N101C->getZExtValue(), 2460 TruncVT))); 2461 } 2462 } 2463 } 2464 2465 // Simplify, based on bits shifted out of the LHS. 2466 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2467 return SDValue(N, 0); 2468 2469 2470 // If the sign bit is known to be zero, switch this to a SRL. 2471 if (DAG.SignBitIsZero(N0)) 2472 return DAG.getNode(ISD::SRL, VT, N0, N1); 2473 2474 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2475} 2476 2477SDValue DAGCombiner::visitSRL(SDNode *N) { 2478 SDValue N0 = N->getOperand(0); 2479 SDValue N1 = N->getOperand(1); 2480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2482 MVT VT = N0.getValueType(); 2483 unsigned OpSizeInBits = VT.getSizeInBits(); 2484 2485 // fold (srl c1, c2) -> c1 >>u c2 2486 if (N0C && N1C) 2487 return DAG.getNode(ISD::SRL, VT, N0, N1); 2488 // fold (srl 0, x) -> 0 2489 if (N0C && N0C->isNullValue()) 2490 return N0; 2491 // fold (srl x, c >= size(x)) -> undef 2492 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2493 return DAG.getNode(ISD::UNDEF, VT); 2494 // fold (srl x, 0) -> x 2495 if (N1C && N1C->isNullValue()) 2496 return N0; 2497 // if (srl x, c) is known to be zero, return 0 2498 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2499 APInt::getAllOnesValue(OpSizeInBits))) 2500 return DAG.getConstant(0, VT); 2501 2502 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2503 if (N1C && N0.getOpcode() == ISD::SRL && 2504 N0.getOperand(1).getOpcode() == ISD::Constant) { 2505 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2506 uint64_t c2 = N1C->getZExtValue(); 2507 if (c1 + c2 > OpSizeInBits) 2508 return DAG.getConstant(0, VT); 2509 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2510 DAG.getConstant(c1 + c2, N1.getValueType())); 2511 } 2512 2513 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2514 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2515 // Shifting in all undef bits? 2516 MVT SmallVT = N0.getOperand(0).getValueType(); 2517 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2518 return DAG.getNode(ISD::UNDEF, VT); 2519 2520 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2521 AddToWorkList(SmallShift.getNode()); 2522 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2523 } 2524 2525 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2526 // bit, which is unmodified by sra. 2527 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2528 if (N0.getOpcode() == ISD::SRA) 2529 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2530 } 2531 2532 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2533 if (N1C && N0.getOpcode() == ISD::CTLZ && 2534 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2535 APInt KnownZero, KnownOne; 2536 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2537 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2538 2539 // If any of the input bits are KnownOne, then the input couldn't be all 2540 // zeros, thus the result of the srl will always be zero. 2541 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2542 2543 // If all of the bits input the to ctlz node are known to be zero, then 2544 // the result of the ctlz is "32" and the result of the shift is one. 2545 APInt UnknownBits = ~KnownZero & Mask; 2546 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2547 2548 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2549 if ((UnknownBits & (UnknownBits-1)) == 0) { 2550 // Okay, we know that only that the single bit specified by UnknownBits 2551 // could be set on input to the CTLZ node. If this bit is set, the SRL 2552 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2553 // to an SRL,XOR pair, which is likely to simplify more. 2554 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2555 SDValue Op = N0.getOperand(0); 2556 if (ShAmt) { 2557 Op = DAG.getNode(ISD::SRL, VT, Op, 2558 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2559 AddToWorkList(Op.getNode()); 2560 } 2561 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2562 } 2563 } 2564 2565 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2566 // iff (trunc c) == c 2567 if (N1.getOpcode() == ISD::TRUNCATE && 2568 N1.getOperand(0).getOpcode() == ISD::AND) { 2569 SDValue N101 = N1.getOperand(0).getOperand(1); 2570 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101); 2571 if (N101C) { 2572 MVT TruncVT = N1.getValueType(); 2573 unsigned TruncBitSize = TruncVT.getSizeInBits(); 2574 APInt ShAmt = N101C->getAPIntValue(); 2575 if (ShAmt.trunc(TruncBitSize).getZExtValue() == N101C->getZExtValue()) { 2576 SDValue N100 = N1.getOperand(0).getOperand(0); 2577 return DAG.getNode(ISD::SRL, VT, N0, 2578 DAG.getNode(ISD::AND, TruncVT, 2579 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2580 DAG.getConstant(N101C->getZExtValue(), 2581 TruncVT))); 2582 } 2583 } 2584 } 2585 2586 // fold operands of srl based on knowledge that the low bits are not 2587 // demanded. 2588 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2589 return SDValue(N, 0); 2590 2591 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2592} 2593 2594SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2595 SDValue N0 = N->getOperand(0); 2596 MVT VT = N->getValueType(0); 2597 2598 // fold (ctlz c1) -> c2 2599 if (isa<ConstantSDNode>(N0)) 2600 return DAG.getNode(ISD::CTLZ, VT, N0); 2601 return SDValue(); 2602} 2603 2604SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2605 SDValue N0 = N->getOperand(0); 2606 MVT VT = N->getValueType(0); 2607 2608 // fold (cttz c1) -> c2 2609 if (isa<ConstantSDNode>(N0)) 2610 return DAG.getNode(ISD::CTTZ, VT, N0); 2611 return SDValue(); 2612} 2613 2614SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2615 SDValue N0 = N->getOperand(0); 2616 MVT VT = N->getValueType(0); 2617 2618 // fold (ctpop c1) -> c2 2619 if (isa<ConstantSDNode>(N0)) 2620 return DAG.getNode(ISD::CTPOP, VT, N0); 2621 return SDValue(); 2622} 2623 2624SDValue DAGCombiner::visitSELECT(SDNode *N) { 2625 SDValue N0 = N->getOperand(0); 2626 SDValue N1 = N->getOperand(1); 2627 SDValue N2 = N->getOperand(2); 2628 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2629 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2630 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2631 MVT VT = N->getValueType(0); 2632 MVT VT0 = N0.getValueType(); 2633 2634 // fold select C, X, X -> X 2635 if (N1 == N2) 2636 return N1; 2637 // fold select true, X, Y -> X 2638 if (N0C && !N0C->isNullValue()) 2639 return N1; 2640 // fold select false, X, Y -> Y 2641 if (N0C && N0C->isNullValue()) 2642 return N2; 2643 // fold select C, 1, X -> C | X 2644 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2645 return DAG.getNode(ISD::OR, VT, N0, N2); 2646 // fold select C, 0, 1 -> ~C 2647 if (VT.isInteger() && VT0.isInteger() && 2648 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2649 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2650 if (VT == VT0) 2651 return XORNode; 2652 AddToWorkList(XORNode.getNode()); 2653 if (VT.bitsGT(VT0)) 2654 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2655 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2656 } 2657 // fold select C, 0, X -> ~C & X 2658 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2659 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2660 AddToWorkList(XORNode.getNode()); 2661 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2662 } 2663 // fold select C, X, 1 -> ~C | X 2664 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2665 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2666 AddToWorkList(XORNode.getNode()); 2667 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2668 } 2669 // fold select C, X, 0 -> C & X 2670 // FIXME: this should check for C type == X type, not i1? 2671 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2672 return DAG.getNode(ISD::AND, VT, N0, N1); 2673 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2674 if (VT == MVT::i1 && N0 == N1) 2675 return DAG.getNode(ISD::OR, VT, N0, N2); 2676 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2677 if (VT == MVT::i1 && N0 == N2) 2678 return DAG.getNode(ISD::AND, VT, N0, N1); 2679 2680 // If we can fold this based on the true/false value, do so. 2681 if (SimplifySelectOps(N, N1, N2)) 2682 return SDValue(N, 0); // Don't revisit N. 2683 2684 // fold selects based on a setcc into other things, such as min/max/abs 2685 if (N0.getOpcode() == ISD::SETCC) { 2686 // FIXME: 2687 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2688 // having to say they don't support SELECT_CC on every type the DAG knows 2689 // about, since there is no way to mark an opcode illegal at all value types 2690 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2691 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2692 N1, N2, N0.getOperand(2)); 2693 else 2694 return SimplifySelect(N0, N1, N2); 2695 } 2696 return SDValue(); 2697} 2698 2699SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2700 SDValue N0 = N->getOperand(0); 2701 SDValue N1 = N->getOperand(1); 2702 SDValue N2 = N->getOperand(2); 2703 SDValue N3 = N->getOperand(3); 2704 SDValue N4 = N->getOperand(4); 2705 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2706 2707 // fold select_cc lhs, rhs, x, x, cc -> x 2708 if (N2 == N3) 2709 return N2; 2710 2711 // Determine if the condition we're dealing with is constant 2712 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2713 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2714 2715 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2716 if (!SCCC->isNullValue()) 2717 return N2; // cond always true -> true val 2718 else 2719 return N3; // cond always false -> false val 2720 } 2721 2722 // Fold to a simpler select_cc 2723 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2724 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2725 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2726 SCC.getOperand(2)); 2727 2728 // If we can fold this based on the true/false value, do so. 2729 if (SimplifySelectOps(N, N2, N3)) 2730 return SDValue(N, 0); // Don't revisit N. 2731 2732 // fold select_cc into other things, such as min/max/abs 2733 return SimplifySelectCC(N0, N1, N2, N3, CC); 2734} 2735 2736SDValue DAGCombiner::visitSETCC(SDNode *N) { 2737 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2738 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2739} 2740 2741// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2742// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2743// transformation. Returns true if extension are possible and the above 2744// mentioned transformation is profitable. 2745static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2746 unsigned ExtOpc, 2747 SmallVector<SDNode*, 4> &ExtendNodes, 2748 TargetLowering &TLI) { 2749 bool HasCopyToRegUses = false; 2750 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2751 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2752 UE = N0.getNode()->use_end(); 2753 UI != UE; ++UI) { 2754 SDNode *User = *UI; 2755 if (User == N) 2756 continue; 2757 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2758 if (User->getOpcode() == ISD::SETCC) { 2759 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2760 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2761 // Sign bits will be lost after a zext. 2762 return false; 2763 bool Add = false; 2764 for (unsigned i = 0; i != 2; ++i) { 2765 SDValue UseOp = User->getOperand(i); 2766 if (UseOp == N0) 2767 continue; 2768 if (!isa<ConstantSDNode>(UseOp)) 2769 return false; 2770 Add = true; 2771 } 2772 if (Add) 2773 ExtendNodes.push_back(User); 2774 } else { 2775 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2776 SDValue UseOp = User->getOperand(i); 2777 if (UseOp == N0) { 2778 // If truncate from extended type to original load type is free 2779 // on this target, then it's ok to extend a CopyToReg. 2780 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2781 HasCopyToRegUses = true; 2782 else 2783 return false; 2784 } 2785 } 2786 } 2787 } 2788 2789 if (HasCopyToRegUses) { 2790 bool BothLiveOut = false; 2791 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2792 UI != UE; ++UI) { 2793 SDNode *User = *UI; 2794 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2795 SDValue UseOp = User->getOperand(i); 2796 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2797 BothLiveOut = true; 2798 break; 2799 } 2800 } 2801 } 2802 if (BothLiveOut) 2803 // Both unextended and extended values are live out. There had better be 2804 // good a reason for the transformation. 2805 return ExtendNodes.size(); 2806 } 2807 return true; 2808} 2809 2810SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2811 SDValue N0 = N->getOperand(0); 2812 MVT VT = N->getValueType(0); 2813 2814 // fold (sext c1) -> c1 2815 if (isa<ConstantSDNode>(N0)) 2816 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2817 2818 // fold (sext (sext x)) -> (sext x) 2819 // fold (sext (aext x)) -> (sext x) 2820 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2821 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2822 2823 if (N0.getOpcode() == ISD::TRUNCATE) { 2824 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2825 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2826 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2827 if (NarrowLoad.getNode()) { 2828 if (NarrowLoad.getNode() != N0.getNode()) 2829 CombineTo(N0.getNode(), NarrowLoad); 2830 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2831 } 2832 2833 // See if the value being truncated is already sign extended. If so, just 2834 // eliminate the trunc/sext pair. 2835 SDValue Op = N0.getOperand(0); 2836 unsigned OpBits = Op.getValueType().getSizeInBits(); 2837 unsigned MidBits = N0.getValueType().getSizeInBits(); 2838 unsigned DestBits = VT.getSizeInBits(); 2839 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2840 2841 if (OpBits == DestBits) { 2842 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2843 // bits, it is already ready. 2844 if (NumSignBits > DestBits-MidBits) 2845 return Op; 2846 } else if (OpBits < DestBits) { 2847 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2848 // bits, just sext from i32. 2849 if (NumSignBits > OpBits-MidBits) 2850 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2851 } else { 2852 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2853 // bits, just truncate to i32. 2854 if (NumSignBits > OpBits-MidBits) 2855 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2856 } 2857 2858 // fold (sext (truncate x)) -> (sextinreg x). 2859 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2860 N0.getValueType())) { 2861 if (Op.getValueType().bitsLT(VT)) 2862 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2863 else if (Op.getValueType().bitsGT(VT)) 2864 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2865 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2866 DAG.getValueType(N0.getValueType())); 2867 } 2868 } 2869 2870 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2871 if (ISD::isNON_EXTLoad(N0.getNode()) && 2872 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2873 TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2874 bool DoXform = true; 2875 SmallVector<SDNode*, 4> SetCCs; 2876 if (!N0.hasOneUse()) 2877 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2878 if (DoXform) { 2879 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2880 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2881 LN0->getBasePtr(), LN0->getSrcValue(), 2882 LN0->getSrcValueOffset(), 2883 N0.getValueType(), 2884 LN0->isVolatile(), 2885 LN0->getAlignment()); 2886 CombineTo(N, ExtLoad); 2887 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2888 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2889 // Extend SetCC uses if necessary. 2890 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2891 SDNode *SetCC = SetCCs[i]; 2892 SmallVector<SDValue, 4> Ops; 2893 for (unsigned j = 0; j != 2; ++j) { 2894 SDValue SOp = SetCC->getOperand(j); 2895 if (SOp == Trunc) 2896 Ops.push_back(ExtLoad); 2897 else 2898 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2899 } 2900 Ops.push_back(SetCC->getOperand(2)); 2901 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2902 &Ops[0], Ops.size())); 2903 } 2904 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2905 } 2906 } 2907 2908 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2909 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2910 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2911 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2912 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2913 MVT EVT = LN0->getMemoryVT(); 2914 if ((!AfterLegalize && !LN0->isVolatile()) || 2915 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2916 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2917 LN0->getBasePtr(), LN0->getSrcValue(), 2918 LN0->getSrcValueOffset(), EVT, 2919 LN0->isVolatile(), 2920 LN0->getAlignment()); 2921 CombineTo(N, ExtLoad); 2922 CombineTo(N0.getNode(), 2923 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2924 ExtLoad.getValue(1)); 2925 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2926 } 2927 } 2928 2929 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2930 if (N0.getOpcode() == ISD::SETCC) { 2931 SDValue SCC = 2932 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2933 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2934 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2935 if (SCC.getNode()) return SCC; 2936 } 2937 2938 // fold (sext x) -> (zext x) if the sign bit is known zero. 2939 if ((!AfterLegalize || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 2940 DAG.SignBitIsZero(N0)) 2941 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2942 2943 return SDValue(); 2944} 2945 2946SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2947 SDValue N0 = N->getOperand(0); 2948 MVT VT = N->getValueType(0); 2949 2950 // fold (zext c1) -> c1 2951 if (isa<ConstantSDNode>(N0)) 2952 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2953 // fold (zext (zext x)) -> (zext x) 2954 // fold (zext (aext x)) -> (zext x) 2955 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2956 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2957 2958 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2959 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2960 if (N0.getOpcode() == ISD::TRUNCATE) { 2961 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2962 if (NarrowLoad.getNode()) { 2963 if (NarrowLoad.getNode() != N0.getNode()) 2964 CombineTo(N0.getNode(), NarrowLoad); 2965 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2966 } 2967 } 2968 2969 // fold (zext (truncate x)) -> (and x, mask) 2970 if (N0.getOpcode() == ISD::TRUNCATE && 2971 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2972 SDValue Op = N0.getOperand(0); 2973 if (Op.getValueType().bitsLT(VT)) { 2974 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2975 } else if (Op.getValueType().bitsGT(VT)) { 2976 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2977 } 2978 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2979 } 2980 2981 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2982 if (N0.getOpcode() == ISD::AND && 2983 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2984 N0.getOperand(1).getOpcode() == ISD::Constant) { 2985 SDValue X = N0.getOperand(0).getOperand(0); 2986 if (X.getValueType().bitsLT(VT)) { 2987 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2988 } else if (X.getValueType().bitsGT(VT)) { 2989 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2990 } 2991 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2992 Mask.zext(VT.getSizeInBits()); 2993 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2994 } 2995 2996 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2997 if (ISD::isNON_EXTLoad(N0.getNode()) && 2998 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 2999 TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3000 bool DoXform = true; 3001 SmallVector<SDNode*, 4> SetCCs; 3002 if (!N0.hasOneUse()) 3003 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3004 if (DoXform) { 3005 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3006 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3007 LN0->getBasePtr(), LN0->getSrcValue(), 3008 LN0->getSrcValueOffset(), 3009 N0.getValueType(), 3010 LN0->isVolatile(), 3011 LN0->getAlignment()); 3012 CombineTo(N, ExtLoad); 3013 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3014 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3015 // Extend SetCC uses if necessary. 3016 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3017 SDNode *SetCC = SetCCs[i]; 3018 SmallVector<SDValue, 4> Ops; 3019 for (unsigned j = 0; j != 2; ++j) { 3020 SDValue SOp = SetCC->getOperand(j); 3021 if (SOp == Trunc) 3022 Ops.push_back(ExtLoad); 3023 else 3024 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3025 } 3026 Ops.push_back(SetCC->getOperand(2)); 3027 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3028 &Ops[0], Ops.size())); 3029 } 3030 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3031 } 3032 } 3033 3034 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3035 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3036 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3037 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3038 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3039 MVT EVT = LN0->getMemoryVT(); 3040 if ((!AfterLegalize && !LN0->isVolatile()) || 3041 TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT)) { 3042 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3043 LN0->getBasePtr(), LN0->getSrcValue(), 3044 LN0->getSrcValueOffset(), EVT, 3045 LN0->isVolatile(), 3046 LN0->getAlignment()); 3047 CombineTo(N, ExtLoad); 3048 CombineTo(N0.getNode(), 3049 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3050 ExtLoad.getValue(1)); 3051 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3052 } 3053 } 3054 3055 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3056 if (N0.getOpcode() == ISD::SETCC) { 3057 SDValue SCC = 3058 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3059 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3060 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3061 if (SCC.getNode()) return SCC; 3062 } 3063 3064 return SDValue(); 3065} 3066 3067SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3068 SDValue N0 = N->getOperand(0); 3069 MVT VT = N->getValueType(0); 3070 3071 // fold (aext c1) -> c1 3072 if (isa<ConstantSDNode>(N0)) 3073 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3074 // fold (aext (aext x)) -> (aext x) 3075 // fold (aext (zext x)) -> (zext x) 3076 // fold (aext (sext x)) -> (sext x) 3077 if (N0.getOpcode() == ISD::ANY_EXTEND || 3078 N0.getOpcode() == ISD::ZERO_EXTEND || 3079 N0.getOpcode() == ISD::SIGN_EXTEND) 3080 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3081 3082 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3083 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3084 if (N0.getOpcode() == ISD::TRUNCATE) { 3085 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3086 if (NarrowLoad.getNode()) { 3087 if (NarrowLoad.getNode() != N0.getNode()) 3088 CombineTo(N0.getNode(), NarrowLoad); 3089 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3090 } 3091 } 3092 3093 // fold (aext (truncate x)) 3094 if (N0.getOpcode() == ISD::TRUNCATE) { 3095 SDValue TruncOp = N0.getOperand(0); 3096 if (TruncOp.getValueType() == VT) 3097 return TruncOp; // x iff x size == zext size. 3098 if (TruncOp.getValueType().bitsGT(VT)) 3099 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3100 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3101 } 3102 3103 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3104 if (N0.getOpcode() == ISD::AND && 3105 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3106 N0.getOperand(1).getOpcode() == ISD::Constant) { 3107 SDValue X = N0.getOperand(0).getOperand(0); 3108 if (X.getValueType().bitsLT(VT)) { 3109 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3110 } else if (X.getValueType().bitsGT(VT)) { 3111 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3112 } 3113 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3114 Mask.zext(VT.getSizeInBits()); 3115 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3116 } 3117 3118 // fold (aext (load x)) -> (aext (truncate (extload x))) 3119 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3120 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3121 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3122 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3123 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3124 LN0->getBasePtr(), LN0->getSrcValue(), 3125 LN0->getSrcValueOffset(), 3126 N0.getValueType(), 3127 LN0->isVolatile(), 3128 LN0->getAlignment()); 3129 CombineTo(N, ExtLoad); 3130 // Redirect any chain users to the new load. 3131 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3132 SDValue(ExtLoad.getNode(), 1)); 3133 // If any node needs the original loaded value, recompute it. 3134 if (!LN0->use_empty()) 3135 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3136 ExtLoad.getValue(1)); 3137 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3138 } 3139 3140 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3141 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3142 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3143 if (N0.getOpcode() == ISD::LOAD && 3144 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3145 N0.hasOneUse()) { 3146 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3147 MVT EVT = LN0->getMemoryVT(); 3148 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3149 LN0->getChain(), LN0->getBasePtr(), 3150 LN0->getSrcValue(), 3151 LN0->getSrcValueOffset(), EVT, 3152 LN0->isVolatile(), 3153 LN0->getAlignment()); 3154 CombineTo(N, ExtLoad); 3155 CombineTo(N0.getNode(), 3156 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3157 ExtLoad.getValue(1)); 3158 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3159 } 3160 3161 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3162 if (N0.getOpcode() == ISD::SETCC) { 3163 SDValue SCC = 3164 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3165 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3166 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3167 if (SCC.getNode()) 3168 return SCC; 3169 } 3170 3171 return SDValue(); 3172} 3173 3174/// GetDemandedBits - See if the specified operand can be simplified with the 3175/// knowledge that only the bits specified by Mask are used. If so, return the 3176/// simpler operand, otherwise return a null SDValue. 3177SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3178 switch (V.getOpcode()) { 3179 default: break; 3180 case ISD::OR: 3181 case ISD::XOR: 3182 // If the LHS or RHS don't contribute bits to the or, drop them. 3183 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3184 return V.getOperand(1); 3185 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3186 return V.getOperand(0); 3187 break; 3188 case ISD::SRL: 3189 // Only look at single-use SRLs. 3190 if (!V.getNode()->hasOneUse()) 3191 break; 3192 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3193 // See if we can recursively simplify the LHS. 3194 unsigned Amt = RHSC->getZExtValue(); 3195 APInt NewMask = Mask << Amt; 3196 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3197 if (SimplifyLHS.getNode()) { 3198 return DAG.getNode(ISD::SRL, V.getValueType(), 3199 SimplifyLHS, V.getOperand(1)); 3200 } 3201 } 3202 } 3203 return SDValue(); 3204} 3205 3206/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3207/// bits and then truncated to a narrower type and where N is a multiple 3208/// of number of bits of the narrower type, transform it to a narrower load 3209/// from address + N / num of bits of new type. If the result is to be 3210/// extended, also fold the extension to form a extending load. 3211SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3212 unsigned Opc = N->getOpcode(); 3213 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3214 SDValue N0 = N->getOperand(0); 3215 MVT VT = N->getValueType(0); 3216 MVT EVT = N->getValueType(0); 3217 3218 // This transformation isn't valid for vector loads. 3219 if (VT.isVector()) 3220 return SDValue(); 3221 3222 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3223 // extended to VT. 3224 if (Opc == ISD::SIGN_EXTEND_INREG) { 3225 ExtType = ISD::SEXTLOAD; 3226 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3227 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3228 return SDValue(); 3229 } 3230 3231 unsigned EVTBits = EVT.getSizeInBits(); 3232 unsigned ShAmt = 0; 3233 bool CombineSRL = false; 3234 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3235 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3236 ShAmt = N01->getZExtValue(); 3237 // Is the shift amount a multiple of size of VT? 3238 if ((ShAmt & (EVTBits-1)) == 0) { 3239 N0 = N0.getOperand(0); 3240 if (N0.getValueType().getSizeInBits() <= EVTBits) 3241 return SDValue(); 3242 CombineSRL = true; 3243 } 3244 } 3245 } 3246 3247 // Do not generate loads of non-round integer types since these can 3248 // be expensive (and would be wrong if the type is not byte sized). 3249 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3250 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3251 // Do not change the width of a volatile load. 3252 !cast<LoadSDNode>(N0)->isVolatile()) { 3253 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3254 MVT PtrType = N0.getOperand(1).getValueType(); 3255 // For big endian targets, we need to adjust the offset to the pointer to 3256 // load the correct bytes. 3257 if (TLI.isBigEndian()) { 3258 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3259 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3260 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3261 } 3262 uint64_t PtrOff = ShAmt / 8; 3263 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3264 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3265 DAG.getConstant(PtrOff, PtrType)); 3266 AddToWorkList(NewPtr.getNode()); 3267 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3268 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3269 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3270 LN0->isVolatile(), NewAlign) 3271 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3272 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3273 EVT, LN0->isVolatile(), NewAlign); 3274 AddToWorkList(N); 3275 if (CombineSRL) { 3276 WorkListRemover DeadNodes(*this); 3277 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3278 &DeadNodes); 3279 CombineTo(N->getOperand(0).getNode(), Load); 3280 } else 3281 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3282 if (ShAmt) { 3283 if (Opc == ISD::SIGN_EXTEND_INREG) 3284 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3285 else 3286 return DAG.getNode(Opc, VT, Load); 3287 } 3288 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3289 } 3290 3291 return SDValue(); 3292} 3293 3294 3295SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3296 SDValue N0 = N->getOperand(0); 3297 SDValue N1 = N->getOperand(1); 3298 MVT VT = N->getValueType(0); 3299 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3300 unsigned VTBits = VT.getSizeInBits(); 3301 unsigned EVTBits = EVT.getSizeInBits(); 3302 3303 // fold (sext_in_reg c1) -> c1 3304 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3305 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3306 3307 // If the input is already sign extended, just drop the extension. 3308 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3309 return N0; 3310 3311 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3312 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3313 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3314 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3315 } 3316 3317 // fold (sext_in_reg (sext x)) -> (sext x) 3318 // fold (sext_in_reg (aext x)) -> (sext x) 3319 // if x is small enough. 3320 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3321 SDValue N00 = N0.getOperand(0); 3322 if (N00.getValueType().getSizeInBits() < EVTBits) 3323 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3324 } 3325 3326 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3327 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3328 return DAG.getZeroExtendInReg(N0, EVT); 3329 3330 // fold operands of sext_in_reg based on knowledge that the top bits are not 3331 // demanded. 3332 if (SimplifyDemandedBits(SDValue(N, 0))) 3333 return SDValue(N, 0); 3334 3335 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3336 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3337 SDValue NarrowLoad = ReduceLoadWidth(N); 3338 if (NarrowLoad.getNode()) 3339 return NarrowLoad; 3340 3341 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3342 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3343 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3344 if (N0.getOpcode() == ISD::SRL) { 3345 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3346 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3347 // We can turn this into an SRA iff the input to the SRL is already sign 3348 // extended enough. 3349 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3350 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3351 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3352 } 3353 } 3354 3355 // fold (sext_inreg (extload x)) -> (sextload x) 3356 if (ISD::isEXTLoad(N0.getNode()) && 3357 ISD::isUNINDEXEDLoad(N0.getNode()) && 3358 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3359 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3360 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3361 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3362 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3363 LN0->getBasePtr(), LN0->getSrcValue(), 3364 LN0->getSrcValueOffset(), EVT, 3365 LN0->isVolatile(), 3366 LN0->getAlignment()); 3367 CombineTo(N, ExtLoad); 3368 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3369 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3370 } 3371 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3372 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3373 N0.hasOneUse() && 3374 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3375 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 3376 TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3377 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3378 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3379 LN0->getBasePtr(), LN0->getSrcValue(), 3380 LN0->getSrcValueOffset(), EVT, 3381 LN0->isVolatile(), 3382 LN0->getAlignment()); 3383 CombineTo(N, ExtLoad); 3384 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3385 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3386 } 3387 return SDValue(); 3388} 3389 3390SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3391 SDValue N0 = N->getOperand(0); 3392 MVT VT = N->getValueType(0); 3393 3394 // noop truncate 3395 if (N0.getValueType() == N->getValueType(0)) 3396 return N0; 3397 // fold (truncate c1) -> c1 3398 if (isa<ConstantSDNode>(N0)) 3399 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3400 // fold (truncate (truncate x)) -> (truncate x) 3401 if (N0.getOpcode() == ISD::TRUNCATE) 3402 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3403 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3404 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3405 N0.getOpcode() == ISD::ANY_EXTEND) { 3406 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3407 // if the source is smaller than the dest, we still need an extend 3408 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3409 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3410 // if the source is larger than the dest, than we just need the truncate 3411 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3412 else 3413 // if the source and dest are the same type, we can drop both the extend 3414 // and the truncate 3415 return N0.getOperand(0); 3416 } 3417 3418 // See if we can simplify the input to this truncate through knowledge that 3419 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3420 // -> trunc y 3421 SDValue Shorter = 3422 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3423 VT.getSizeInBits())); 3424 if (Shorter.getNode()) 3425 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3426 3427 // fold (truncate (load x)) -> (smaller load x) 3428 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3429 return ReduceLoadWidth(N); 3430} 3431 3432static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3433 SDValue Elt = N->getOperand(i); 3434 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3435 return Elt.getNode(); 3436 return Elt.getOperand(Elt.getResNo()).getNode(); 3437} 3438 3439/// CombineConsecutiveLoads - build_pair (load, load) -> load 3440/// if load locations are consecutive. 3441SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3442 assert(N->getOpcode() == ISD::BUILD_PAIR); 3443 3444 SDNode *LD1 = getBuildPairElt(N, 0); 3445 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3446 return SDValue(); 3447 MVT LD1VT = LD1->getValueType(0); 3448 SDNode *LD2 = getBuildPairElt(N, 1); 3449 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3450 if (ISD::isNON_EXTLoad(LD2) && 3451 LD2->hasOneUse() && 3452 // If both are volatile this would reduce the number of volatile loads. 3453 // If one is volatile it might be ok, but play conservative and bail out. 3454 !cast<LoadSDNode>(LD1)->isVolatile() && 3455 !cast<LoadSDNode>(LD2)->isVolatile() && 3456 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3457 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3458 unsigned Align = LD->getAlignment(); 3459 unsigned NewAlign = TLI.getTargetData()-> 3460 getABITypeAlignment(VT.getTypeForMVT()); 3461 if (NewAlign <= Align && 3462 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) 3463 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3464 LD->getSrcValue(), LD->getSrcValueOffset(), 3465 false, Align); 3466 } 3467 return SDValue(); 3468} 3469 3470SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3471 SDValue N0 = N->getOperand(0); 3472 MVT VT = N->getValueType(0); 3473 3474 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3475 // Only do this before legalize, since afterward the target may be depending 3476 // on the bitconvert. 3477 // First check to see if this is all constant. 3478 if (!AfterLegalize && 3479 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3480 VT.isVector()) { 3481 bool isSimple = true; 3482 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3483 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3484 N0.getOperand(i).getOpcode() != ISD::Constant && 3485 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3486 isSimple = false; 3487 break; 3488 } 3489 3490 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3491 assert(!DestEltVT.isVector() && 3492 "Element type of vector ValueType must not be vector!"); 3493 if (isSimple) { 3494 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3495 } 3496 } 3497 3498 // If the input is a constant, let getNode fold it. 3499 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3500 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3501 if (Res.getNode() != N) return Res; 3502 } 3503 3504 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3505 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3506 3507 // fold (conv (load x)) -> (load (conv*)x) 3508 // If the resultant load doesn't need a higher alignment than the original! 3509 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3510 // Do not change the width of a volatile load. 3511 !cast<LoadSDNode>(N0)->isVolatile() && 3512 (!AfterLegalize || TLI.isOperationLegal(ISD::LOAD, VT))) { 3513 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3514 unsigned Align = TLI.getTargetData()-> 3515 getABITypeAlignment(VT.getTypeForMVT()); 3516 unsigned OrigAlign = LN0->getAlignment(); 3517 if (Align <= OrigAlign) { 3518 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3519 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3520 LN0->isVolatile(), OrigAlign); 3521 AddToWorkList(N); 3522 CombineTo(N0.getNode(), 3523 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3524 Load.getValue(1)); 3525 return Load; 3526 } 3527 } 3528 3529 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3530 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3531 // This often reduces constant pool loads. 3532 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3533 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3534 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3535 AddToWorkList(NewConv.getNode()); 3536 3537 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3538 if (N0.getOpcode() == ISD::FNEG) 3539 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3540 assert(N0.getOpcode() == ISD::FABS); 3541 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3542 } 3543 3544 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3545 // Note that we don't handle copysign(x,cst) because this can always be folded 3546 // to an fneg or fabs. 3547 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3548 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3549 VT.isInteger() && !VT.isVector()) { 3550 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3551 SDValue X = DAG.getNode(ISD::BIT_CONVERT, 3552 MVT::getIntegerVT(OrigXWidth), 3553 N0.getOperand(1)); 3554 AddToWorkList(X.getNode()); 3555 3556 // If X has a different width than the result/lhs, sext it or truncate it. 3557 unsigned VTWidth = VT.getSizeInBits(); 3558 if (OrigXWidth < VTWidth) { 3559 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3560 AddToWorkList(X.getNode()); 3561 } else if (OrigXWidth > VTWidth) { 3562 // To get the sign bit in the right place, we have to shift it right 3563 // before truncating. 3564 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3565 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3566 AddToWorkList(X.getNode()); 3567 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3568 AddToWorkList(X.getNode()); 3569 } 3570 3571 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3572 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3573 AddToWorkList(X.getNode()); 3574 3575 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3576 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3577 AddToWorkList(Cst.getNode()); 3578 3579 return DAG.getNode(ISD::OR, VT, X, Cst); 3580 } 3581 3582 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3583 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3584 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3585 if (CombineLD.getNode()) 3586 return CombineLD; 3587 } 3588 3589 return SDValue(); 3590} 3591 3592SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3593 MVT VT = N->getValueType(0); 3594 return CombineConsecutiveLoads(N, VT); 3595} 3596 3597/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3598/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3599/// destination element value type. 3600SDValue DAGCombiner:: 3601ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3602 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3603 3604 // If this is already the right type, we're done. 3605 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3606 3607 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3608 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3609 3610 // If this is a conversion of N elements of one type to N elements of another 3611 // type, convert each element. This handles FP<->INT cases. 3612 if (SrcBitSize == DstBitSize) { 3613 SmallVector<SDValue, 8> Ops; 3614 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3615 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3616 AddToWorkList(Ops.back().getNode()); 3617 } 3618 MVT VT = MVT::getVectorVT(DstEltVT, 3619 BV->getValueType(0).getVectorNumElements()); 3620 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3621 } 3622 3623 // Otherwise, we're growing or shrinking the elements. To avoid having to 3624 // handle annoying details of growing/shrinking FP values, we convert them to 3625 // int first. 3626 if (SrcEltVT.isFloatingPoint()) { 3627 // Convert the input float vector to a int vector where the elements are the 3628 // same sizes. 3629 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3630 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3631 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3632 SrcEltVT = IntVT; 3633 } 3634 3635 // Now we know the input is an integer vector. If the output is a FP type, 3636 // convert to integer first, then to FP of the right size. 3637 if (DstEltVT.isFloatingPoint()) { 3638 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3639 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3640 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3641 3642 // Next, convert to FP elements of the same size. 3643 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3644 } 3645 3646 // Okay, we know the src/dst types are both integers of differing types. 3647 // Handling growing first. 3648 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3649 if (SrcBitSize < DstBitSize) { 3650 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3651 3652 SmallVector<SDValue, 8> Ops; 3653 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3654 i += NumInputsPerOutput) { 3655 bool isLE = TLI.isLittleEndian(); 3656 APInt NewBits = APInt(DstBitSize, 0); 3657 bool EltIsUndef = true; 3658 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3659 // Shift the previously computed bits over. 3660 NewBits <<= SrcBitSize; 3661 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3662 if (Op.getOpcode() == ISD::UNDEF) continue; 3663 EltIsUndef = false; 3664 3665 NewBits |= 3666 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3667 } 3668 3669 if (EltIsUndef) 3670 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3671 else 3672 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3673 } 3674 3675 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3676 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3677 } 3678 3679 // Finally, this must be the case where we are shrinking elements: each input 3680 // turns into multiple outputs. 3681 bool isS2V = ISD::isScalarToVector(BV); 3682 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3683 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3684 SmallVector<SDValue, 8> Ops; 3685 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3686 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3687 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3688 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3689 continue; 3690 } 3691 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3692 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3693 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3694 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3695 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3696 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3697 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3698 OpVal = OpVal.lshr(DstBitSize); 3699 } 3700 3701 // For big endian targets, swap the order of the pieces of each element. 3702 if (TLI.isBigEndian()) 3703 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3704 } 3705 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3706} 3707 3708 3709 3710SDValue DAGCombiner::visitFADD(SDNode *N) { 3711 SDValue N0 = N->getOperand(0); 3712 SDValue N1 = N->getOperand(1); 3713 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3714 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3715 MVT VT = N->getValueType(0); 3716 3717 // fold vector ops 3718 if (VT.isVector()) { 3719 SDValue FoldedVOp = SimplifyVBinOp(N); 3720 if (FoldedVOp.getNode()) return FoldedVOp; 3721 } 3722 3723 // fold (fadd c1, c2) -> c1+c2 3724 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3725 return DAG.getNode(ISD::FADD, VT, N0, N1); 3726 // canonicalize constant to RHS 3727 if (N0CFP && !N1CFP) 3728 return DAG.getNode(ISD::FADD, VT, N1, N0); 3729 // fold (A + (-B)) -> A-B 3730 if (isNegatibleForFree(N1, AfterLegalize) == 2) 3731 return DAG.getNode(ISD::FSUB, VT, N0, 3732 GetNegatedExpression(N1, DAG, AfterLegalize)); 3733 // fold ((-A) + B) -> B-A 3734 if (isNegatibleForFree(N0, AfterLegalize) == 2) 3735 return DAG.getNode(ISD::FSUB, VT, N1, 3736 GetNegatedExpression(N0, DAG, AfterLegalize)); 3737 3738 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3739 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3740 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3741 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3742 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3743 3744 return SDValue(); 3745} 3746 3747SDValue DAGCombiner::visitFSUB(SDNode *N) { 3748 SDValue N0 = N->getOperand(0); 3749 SDValue N1 = N->getOperand(1); 3750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3752 MVT VT = N->getValueType(0); 3753 3754 // fold vector ops 3755 if (VT.isVector()) { 3756 SDValue FoldedVOp = SimplifyVBinOp(N); 3757 if (FoldedVOp.getNode()) return FoldedVOp; 3758 } 3759 3760 // fold (fsub c1, c2) -> c1-c2 3761 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3762 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3763 // fold (0-B) -> -B 3764 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3765 if (isNegatibleForFree(N1, AfterLegalize)) 3766 return GetNegatedExpression(N1, DAG, AfterLegalize); 3767 return DAG.getNode(ISD::FNEG, VT, N1); 3768 } 3769 // fold (A-(-B)) -> A+B 3770 if (isNegatibleForFree(N1, AfterLegalize)) 3771 return DAG.getNode(ISD::FADD, VT, N0, 3772 GetNegatedExpression(N1, DAG, AfterLegalize)); 3773 3774 return SDValue(); 3775} 3776 3777SDValue DAGCombiner::visitFMUL(SDNode *N) { 3778 SDValue N0 = N->getOperand(0); 3779 SDValue N1 = N->getOperand(1); 3780 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3781 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3782 MVT VT = N->getValueType(0); 3783 3784 // fold vector ops 3785 if (VT.isVector()) { 3786 SDValue FoldedVOp = SimplifyVBinOp(N); 3787 if (FoldedVOp.getNode()) return FoldedVOp; 3788 } 3789 3790 // fold (fmul c1, c2) -> c1*c2 3791 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3792 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3793 // canonicalize constant to RHS 3794 if (N0CFP && !N1CFP) 3795 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3796 // fold (fmul X, 2.0) -> (fadd X, X) 3797 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3798 return DAG.getNode(ISD::FADD, VT, N0, N0); 3799 // fold (fmul X, -1.0) -> (fneg X) 3800 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3801 return DAG.getNode(ISD::FNEG, VT, N0); 3802 3803 // -X * -Y -> X*Y 3804 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3805 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3806 // Both can be negated for free, check to see if at least one is cheaper 3807 // negated. 3808 if (LHSNeg == 2 || RHSNeg == 2) 3809 return DAG.getNode(ISD::FMUL, VT, 3810 GetNegatedExpression(N0, DAG, AfterLegalize), 3811 GetNegatedExpression(N1, DAG, AfterLegalize)); 3812 } 3813 } 3814 3815 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3816 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3817 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3818 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3819 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3820 3821 return SDValue(); 3822} 3823 3824SDValue DAGCombiner::visitFDIV(SDNode *N) { 3825 SDValue N0 = N->getOperand(0); 3826 SDValue N1 = N->getOperand(1); 3827 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3828 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3829 MVT VT = N->getValueType(0); 3830 3831 // fold vector ops 3832 if (VT.isVector()) { 3833 SDValue FoldedVOp = SimplifyVBinOp(N); 3834 if (FoldedVOp.getNode()) return FoldedVOp; 3835 } 3836 3837 // fold (fdiv c1, c2) -> c1/c2 3838 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3839 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3840 3841 3842 // -X / -Y -> X*Y 3843 if (char LHSNeg = isNegatibleForFree(N0, AfterLegalize)) { 3844 if (char RHSNeg = isNegatibleForFree(N1, AfterLegalize)) { 3845 // Both can be negated for free, check to see if at least one is cheaper 3846 // negated. 3847 if (LHSNeg == 2 || RHSNeg == 2) 3848 return DAG.getNode(ISD::FDIV, VT, 3849 GetNegatedExpression(N0, DAG, AfterLegalize), 3850 GetNegatedExpression(N1, DAG, AfterLegalize)); 3851 } 3852 } 3853 3854 return SDValue(); 3855} 3856 3857SDValue DAGCombiner::visitFREM(SDNode *N) { 3858 SDValue N0 = N->getOperand(0); 3859 SDValue N1 = N->getOperand(1); 3860 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3861 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3862 MVT VT = N->getValueType(0); 3863 3864 // fold (frem c1, c2) -> fmod(c1,c2) 3865 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3866 return DAG.getNode(ISD::FREM, VT, N0, N1); 3867 3868 return SDValue(); 3869} 3870 3871SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3872 SDValue N0 = N->getOperand(0); 3873 SDValue N1 = N->getOperand(1); 3874 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3875 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3876 MVT VT = N->getValueType(0); 3877 3878 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3879 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3880 3881 if (N1CFP) { 3882 const APFloat& V = N1CFP->getValueAPF(); 3883 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3884 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3885 if (!V.isNegative()) 3886 return DAG.getNode(ISD::FABS, VT, N0); 3887 else 3888 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3889 } 3890 3891 // copysign(fabs(x), y) -> copysign(x, y) 3892 // copysign(fneg(x), y) -> copysign(x, y) 3893 // copysign(copysign(x,z), y) -> copysign(x, y) 3894 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3895 N0.getOpcode() == ISD::FCOPYSIGN) 3896 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3897 3898 // copysign(x, abs(y)) -> abs(x) 3899 if (N1.getOpcode() == ISD::FABS) 3900 return DAG.getNode(ISD::FABS, VT, N0); 3901 3902 // copysign(x, copysign(y,z)) -> copysign(x, z) 3903 if (N1.getOpcode() == ISD::FCOPYSIGN) 3904 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3905 3906 // copysign(x, fp_extend(y)) -> copysign(x, y) 3907 // copysign(x, fp_round(y)) -> copysign(x, y) 3908 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3909 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3910 3911 return SDValue(); 3912} 3913 3914 3915 3916SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3917 SDValue N0 = N->getOperand(0); 3918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3919 MVT VT = N->getValueType(0); 3920 MVT OpVT = N0.getValueType(); 3921 3922 // fold (sint_to_fp c1) -> c1fp 3923 if (N0C && OpVT != MVT::ppcf128) 3924 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3925 3926 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3927 // but UINT_TO_FP is legal on this target, try to convert. 3928 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3929 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 3930 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 3931 if (DAG.SignBitIsZero(N0)) 3932 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3933 } 3934 3935 3936 return SDValue(); 3937} 3938 3939SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3940 SDValue N0 = N->getOperand(0); 3941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3942 MVT VT = N->getValueType(0); 3943 MVT OpVT = N0.getValueType(); 3944 3945 // fold (uint_to_fp c1) -> c1fp 3946 if (N0C && OpVT != MVT::ppcf128) 3947 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3948 3949 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 3950 // but SINT_TO_FP is legal on this target, try to convert. 3951 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 3952 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 3953 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 3954 if (DAG.SignBitIsZero(N0)) 3955 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3956 } 3957 3958 return SDValue(); 3959} 3960 3961SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3962 SDValue N0 = N->getOperand(0); 3963 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3964 MVT VT = N->getValueType(0); 3965 3966 // fold (fp_to_sint c1fp) -> c1 3967 if (N0CFP) 3968 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3969 return SDValue(); 3970} 3971 3972SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3973 SDValue N0 = N->getOperand(0); 3974 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3975 MVT VT = N->getValueType(0); 3976 3977 // fold (fp_to_uint c1fp) -> c1 3978 if (N0CFP && VT != MVT::ppcf128) 3979 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3980 return SDValue(); 3981} 3982 3983SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 3984 SDValue N0 = N->getOperand(0); 3985 SDValue N1 = N->getOperand(1); 3986 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3987 MVT VT = N->getValueType(0); 3988 3989 // fold (fp_round c1fp) -> c1fp 3990 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3991 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3992 3993 // fold (fp_round (fp_extend x)) -> x 3994 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3995 return N0.getOperand(0); 3996 3997 // fold (fp_round (fp_round x)) -> (fp_round x) 3998 if (N0.getOpcode() == ISD::FP_ROUND) { 3999 // This is a value preserving truncation if both round's are. 4000 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4001 N0.getNode()->getConstantOperandVal(1) == 1; 4002 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4003 DAG.getIntPtrConstant(IsTrunc)); 4004 } 4005 4006 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4007 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4008 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4009 AddToWorkList(Tmp.getNode()); 4010 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4011 } 4012 4013 return SDValue(); 4014} 4015 4016SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4017 SDValue N0 = N->getOperand(0); 4018 MVT VT = N->getValueType(0); 4019 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4020 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4021 4022 // fold (fp_round_inreg c1fp) -> c1fp 4023 if (N0CFP) { 4024 SDValue Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 4025 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4026 } 4027 return SDValue(); 4028} 4029 4030SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4031 SDValue N0 = N->getOperand(0); 4032 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4033 MVT VT = N->getValueType(0); 4034 4035 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4036 if (N->hasOneUse() && 4037 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4038 return SDValue(); 4039 4040 // fold (fp_extend c1fp) -> c1fp 4041 if (N0CFP && VT != MVT::ppcf128) 4042 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4043 4044 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4045 // value of X. 4046 if (N0.getOpcode() == ISD::FP_ROUND 4047 && N0.getNode()->getConstantOperandVal(1) == 1) { 4048 SDValue In = N0.getOperand(0); 4049 if (In.getValueType() == VT) return In; 4050 if (VT.bitsLT(In.getValueType())) 4051 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4052 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4053 } 4054 4055 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4056 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4057 ((!AfterLegalize && !cast<LoadSDNode>(N0)->isVolatile()) || 4058 TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 4059 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4060 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4061 LN0->getBasePtr(), LN0->getSrcValue(), 4062 LN0->getSrcValueOffset(), 4063 N0.getValueType(), 4064 LN0->isVolatile(), 4065 LN0->getAlignment()); 4066 CombineTo(N, ExtLoad); 4067 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4068 ExtLoad, DAG.getIntPtrConstant(1)), 4069 ExtLoad.getValue(1)); 4070 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4071 } 4072 4073 return SDValue(); 4074} 4075 4076SDValue DAGCombiner::visitFNEG(SDNode *N) { 4077 SDValue N0 = N->getOperand(0); 4078 4079 if (isNegatibleForFree(N0, AfterLegalize)) 4080 return GetNegatedExpression(N0, DAG, AfterLegalize); 4081 4082 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4083 // constant pool values. 4084 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4085 N0.getOperand(0).getValueType().isInteger() && 4086 !N0.getOperand(0).getValueType().isVector()) { 4087 SDValue Int = N0.getOperand(0); 4088 MVT IntVT = Int.getValueType(); 4089 if (IntVT.isInteger() && !IntVT.isVector()) { 4090 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4091 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4092 AddToWorkList(Int.getNode()); 4093 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4094 } 4095 } 4096 4097 return SDValue(); 4098} 4099 4100SDValue DAGCombiner::visitFABS(SDNode *N) { 4101 SDValue N0 = N->getOperand(0); 4102 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4103 MVT VT = N->getValueType(0); 4104 4105 // fold (fabs c1) -> fabs(c1) 4106 if (N0CFP && VT != MVT::ppcf128) 4107 return DAG.getNode(ISD::FABS, VT, N0); 4108 // fold (fabs (fabs x)) -> (fabs x) 4109 if (N0.getOpcode() == ISD::FABS) 4110 return N->getOperand(0); 4111 // fold (fabs (fneg x)) -> (fabs x) 4112 // fold (fabs (fcopysign x, y)) -> (fabs x) 4113 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4114 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4115 4116 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4117 // constant pool values. 4118 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4119 N0.getOperand(0).getValueType().isInteger() && 4120 !N0.getOperand(0).getValueType().isVector()) { 4121 SDValue Int = N0.getOperand(0); 4122 MVT IntVT = Int.getValueType(); 4123 if (IntVT.isInteger() && !IntVT.isVector()) { 4124 Int = DAG.getNode(ISD::AND, IntVT, Int, 4125 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4126 AddToWorkList(Int.getNode()); 4127 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4128 } 4129 } 4130 4131 return SDValue(); 4132} 4133 4134SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4135 SDValue Chain = N->getOperand(0); 4136 SDValue N1 = N->getOperand(1); 4137 SDValue N2 = N->getOperand(2); 4138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4139 4140 // never taken branch, fold to chain 4141 if (N1C && N1C->isNullValue()) 4142 return Chain; 4143 // unconditional branch 4144 if (N1C && N1C->getAPIntValue() == 1) 4145 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4146 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4147 // on the target. 4148 if (N1.getOpcode() == ISD::SETCC && 4149 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4150 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4151 N1.getOperand(0), N1.getOperand(1), N2); 4152 } 4153 return SDValue(); 4154} 4155 4156// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4157// 4158SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4159 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4160 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4161 4162 // Use SimplifySetCC to simplify SETCC's. 4163 SDValue Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 4164 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4165 4166 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4167 4168 // fold br_cc true, dest -> br dest (unconditional branch) 4169 if (SCCC && !SCCC->isNullValue()) 4170 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4171 N->getOperand(4)); 4172 // fold br_cc false, dest -> unconditional fall through 4173 if (SCCC && SCCC->isNullValue()) 4174 return N->getOperand(0); 4175 4176 // fold to a simpler setcc 4177 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4178 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4179 Simp.getOperand(2), Simp.getOperand(0), 4180 Simp.getOperand(1), N->getOperand(4)); 4181 return SDValue(); 4182} 4183 4184 4185/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4186/// pre-indexed load / store when the base pointer is an add or subtract 4187/// and it has other uses besides the load / store. After the 4188/// transformation, the new indexed load / store has effectively folded 4189/// the add / subtract in and all of its other uses are redirected to the 4190/// new load / store. 4191bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4192 if (!AfterLegalize) 4193 return false; 4194 4195 bool isLoad = true; 4196 SDValue Ptr; 4197 MVT VT; 4198 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4199 if (LD->isIndexed()) 4200 return false; 4201 VT = LD->getMemoryVT(); 4202 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4203 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4204 return false; 4205 Ptr = LD->getBasePtr(); 4206 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4207 if (ST->isIndexed()) 4208 return false; 4209 VT = ST->getMemoryVT(); 4210 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4211 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4212 return false; 4213 Ptr = ST->getBasePtr(); 4214 isLoad = false; 4215 } else 4216 return false; 4217 4218 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4219 // out. There is no reason to make this a preinc/predec. 4220 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4221 Ptr.getNode()->hasOneUse()) 4222 return false; 4223 4224 // Ask the target to do addressing mode selection. 4225 SDValue BasePtr; 4226 SDValue Offset; 4227 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4228 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4229 return false; 4230 // Don't create a indexed load / store with zero offset. 4231 if (isa<ConstantSDNode>(Offset) && 4232 cast<ConstantSDNode>(Offset)->isNullValue()) 4233 return false; 4234 4235 // Try turning it into a pre-indexed load / store except when: 4236 // 1) The new base ptr is a frame index. 4237 // 2) If N is a store and the new base ptr is either the same as or is a 4238 // predecessor of the value being stored. 4239 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4240 // that would create a cycle. 4241 // 4) All uses are load / store ops that use it as old base ptr. 4242 4243 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4244 // (plus the implicit offset) to a register to preinc anyway. 4245 if (isa<FrameIndexSDNode>(BasePtr)) 4246 return false; 4247 4248 // Check #2. 4249 if (!isLoad) { 4250 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4251 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4252 return false; 4253 } 4254 4255 // Now check for #3 and #4. 4256 bool RealUse = false; 4257 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4258 E = Ptr.getNode()->use_end(); I != E; ++I) { 4259 SDNode *Use = *I; 4260 if (Use == N) 4261 continue; 4262 if (Use->isPredecessorOf(N)) 4263 return false; 4264 4265 if (!((Use->getOpcode() == ISD::LOAD && 4266 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4267 (Use->getOpcode() == ISD::STORE && 4268 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4269 RealUse = true; 4270 } 4271 if (!RealUse) 4272 return false; 4273 4274 SDValue Result; 4275 if (isLoad) 4276 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4277 else 4278 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4279 ++PreIndexedNodes; 4280 ++NodesCombined; 4281 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4282 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4283 DOUT << '\n'; 4284 WorkListRemover DeadNodes(*this); 4285 if (isLoad) { 4286 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4287 &DeadNodes); 4288 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4289 &DeadNodes); 4290 } else { 4291 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4292 &DeadNodes); 4293 } 4294 4295 // Finally, since the node is now dead, remove it from the graph. 4296 DAG.DeleteNode(N); 4297 4298 // Replace the uses of Ptr with uses of the updated base value. 4299 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4300 &DeadNodes); 4301 removeFromWorkList(Ptr.getNode()); 4302 DAG.DeleteNode(Ptr.getNode()); 4303 4304 return true; 4305} 4306 4307/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4308/// add / sub of the base pointer node into a post-indexed load / store. 4309/// The transformation folded the add / subtract into the new indexed 4310/// load / store effectively and all of its uses are redirected to the 4311/// new load / store. 4312bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4313 if (!AfterLegalize) 4314 return false; 4315 4316 bool isLoad = true; 4317 SDValue Ptr; 4318 MVT VT; 4319 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4320 if (LD->isIndexed()) 4321 return false; 4322 VT = LD->getMemoryVT(); 4323 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4324 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4325 return false; 4326 Ptr = LD->getBasePtr(); 4327 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4328 if (ST->isIndexed()) 4329 return false; 4330 VT = ST->getMemoryVT(); 4331 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4332 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4333 return false; 4334 Ptr = ST->getBasePtr(); 4335 isLoad = false; 4336 } else 4337 return false; 4338 4339 if (Ptr.getNode()->hasOneUse()) 4340 return false; 4341 4342 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4343 E = Ptr.getNode()->use_end(); I != E; ++I) { 4344 SDNode *Op = *I; 4345 if (Op == N || 4346 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4347 continue; 4348 4349 SDValue BasePtr; 4350 SDValue Offset; 4351 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4352 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4353 if (Ptr == Offset) 4354 std::swap(BasePtr, Offset); 4355 if (Ptr != BasePtr) 4356 continue; 4357 // Don't create a indexed load / store with zero offset. 4358 if (isa<ConstantSDNode>(Offset) && 4359 cast<ConstantSDNode>(Offset)->isNullValue()) 4360 continue; 4361 4362 // Try turning it into a post-indexed load / store except when 4363 // 1) All uses are load / store ops that use it as base ptr. 4364 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4365 // nor a successor of N. Otherwise, if Op is folded that would 4366 // create a cycle. 4367 4368 // Check for #1. 4369 bool TryNext = false; 4370 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4371 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4372 SDNode *Use = *II; 4373 if (Use == Ptr.getNode()) 4374 continue; 4375 4376 // If all the uses are load / store addresses, then don't do the 4377 // transformation. 4378 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4379 bool RealUse = false; 4380 for (SDNode::use_iterator III = Use->use_begin(), 4381 EEE = Use->use_end(); III != EEE; ++III) { 4382 SDNode *UseUse = *III; 4383 if (!((UseUse->getOpcode() == ISD::LOAD && 4384 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4385 (UseUse->getOpcode() == ISD::STORE && 4386 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4387 RealUse = true; 4388 } 4389 4390 if (!RealUse) { 4391 TryNext = true; 4392 break; 4393 } 4394 } 4395 } 4396 if (TryNext) 4397 continue; 4398 4399 // Check for #2 4400 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4401 SDValue Result = isLoad 4402 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4403 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4404 ++PostIndexedNodes; 4405 ++NodesCombined; 4406 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4407 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4408 DOUT << '\n'; 4409 WorkListRemover DeadNodes(*this); 4410 if (isLoad) { 4411 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4412 &DeadNodes); 4413 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4414 &DeadNodes); 4415 } else { 4416 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4417 &DeadNodes); 4418 } 4419 4420 // Finally, since the node is now dead, remove it from the graph. 4421 DAG.DeleteNode(N); 4422 4423 // Replace the uses of Use with uses of the updated base value. 4424 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4425 Result.getValue(isLoad ? 1 : 0), 4426 &DeadNodes); 4427 removeFromWorkList(Op); 4428 DAG.DeleteNode(Op); 4429 return true; 4430 } 4431 } 4432 } 4433 return false; 4434} 4435 4436/// InferAlignment - If we can infer some alignment information from this 4437/// pointer, return it. 4438static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4439 // If this is a direct reference to a stack slot, use information about the 4440 // stack slot's alignment. 4441 int FrameIdx = 1 << 31; 4442 int64_t FrameOffset = 0; 4443 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4444 FrameIdx = FI->getIndex(); 4445 } else if (Ptr.getOpcode() == ISD::ADD && 4446 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4447 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4448 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4449 FrameOffset = Ptr.getConstantOperandVal(1); 4450 } 4451 4452 if (FrameIdx != (1 << 31)) { 4453 // FIXME: Handle FI+CST. 4454 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4455 if (MFI.isFixedObjectIndex(FrameIdx)) { 4456 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4457 4458 // The alignment of the frame index can be determined from its offset from 4459 // the incoming frame position. If the frame object is at offset 32 and 4460 // the stack is guaranteed to be 16-byte aligned, then we know that the 4461 // object is 16-byte aligned. 4462 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4463 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4464 4465 // Finally, the frame object itself may have a known alignment. Factor 4466 // the alignment + offset into a new alignment. For example, if we know 4467 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4468 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4469 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4470 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4471 FrameOffset); 4472 return std::max(Align, FIInfoAlign); 4473 } 4474 } 4475 4476 return 0; 4477} 4478 4479SDValue DAGCombiner::visitLOAD(SDNode *N) { 4480 LoadSDNode *LD = cast<LoadSDNode>(N); 4481 SDValue Chain = LD->getChain(); 4482 SDValue Ptr = LD->getBasePtr(); 4483 4484 // Try to infer better alignment information than the load already has. 4485 if (!Fast && LD->isUnindexed()) { 4486 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4487 if (Align > LD->getAlignment()) 4488 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4489 Chain, Ptr, LD->getSrcValue(), 4490 LD->getSrcValueOffset(), LD->getMemoryVT(), 4491 LD->isVolatile(), Align); 4492 } 4493 } 4494 4495 4496 // If load is not volatile and there are no uses of the loaded value (and 4497 // the updated indexed value in case of indexed loads), change uses of the 4498 // chain value into uses of the chain input (i.e. delete the dead load). 4499 if (!LD->isVolatile()) { 4500 if (N->getValueType(1) == MVT::Other) { 4501 // Unindexed loads. 4502 if (N->hasNUsesOfValue(0, 0)) { 4503 // It's not safe to use the two value CombineTo variant here. e.g. 4504 // v1, chain2 = load chain1, loc 4505 // v2, chain3 = load chain2, loc 4506 // v3 = add v2, c 4507 // Now we replace use of chain2 with chain1. This makes the second load 4508 // isomorphic to the one we are deleting, and thus makes this load live. 4509 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4510 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4511 DOUT << "\n"; 4512 WorkListRemover DeadNodes(*this); 4513 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4514 if (N->use_empty()) { 4515 removeFromWorkList(N); 4516 DAG.DeleteNode(N); 4517 } 4518 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4519 } 4520 } else { 4521 // Indexed loads. 4522 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4523 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4524 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4525 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4526 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4527 DOUT << " and 2 other values\n"; 4528 WorkListRemover DeadNodes(*this); 4529 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4530 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4531 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4532 &DeadNodes); 4533 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4534 removeFromWorkList(N); 4535 DAG.DeleteNode(N); 4536 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4537 } 4538 } 4539 } 4540 4541 // If this load is directly stored, replace the load value with the stored 4542 // value. 4543 // TODO: Handle store large -> read small portion. 4544 // TODO: Handle TRUNCSTORE/LOADEXT 4545 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4546 !LD->isVolatile()) { 4547 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4548 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4549 if (PrevST->getBasePtr() == Ptr && 4550 PrevST->getValue().getValueType() == N->getValueType(0)) 4551 return CombineTo(N, Chain.getOperand(1), Chain); 4552 } 4553 } 4554 4555 if (CombinerAA) { 4556 // Walk up chain skipping non-aliasing memory nodes. 4557 SDValue BetterChain = FindBetterChain(N, Chain); 4558 4559 // If there is a better chain. 4560 if (Chain != BetterChain) { 4561 SDValue ReplLoad; 4562 4563 // Replace the chain to void dependency. 4564 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4565 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4566 LD->getSrcValue(), LD->getSrcValueOffset(), 4567 LD->isVolatile(), LD->getAlignment()); 4568 } else { 4569 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4570 LD->getValueType(0), 4571 BetterChain, Ptr, LD->getSrcValue(), 4572 LD->getSrcValueOffset(), 4573 LD->getMemoryVT(), 4574 LD->isVolatile(), 4575 LD->getAlignment()); 4576 } 4577 4578 // Create token factor to keep old chain connected. 4579 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4580 Chain, ReplLoad.getValue(1)); 4581 4582 // Replace uses with load result and token factor. Don't add users 4583 // to work list. 4584 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4585 } 4586 } 4587 4588 // Try transforming N to an indexed load. 4589 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4590 return SDValue(N, 0); 4591 4592 return SDValue(); 4593} 4594 4595 4596SDValue DAGCombiner::visitSTORE(SDNode *N) { 4597 StoreSDNode *ST = cast<StoreSDNode>(N); 4598 SDValue Chain = ST->getChain(); 4599 SDValue Value = ST->getValue(); 4600 SDValue Ptr = ST->getBasePtr(); 4601 4602 // Try to infer better alignment information than the store already has. 4603 if (!Fast && ST->isUnindexed()) { 4604 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4605 if (Align > ST->getAlignment()) 4606 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4607 ST->getSrcValueOffset(), ST->getMemoryVT(), 4608 ST->isVolatile(), Align); 4609 } 4610 } 4611 4612 // If this is a store of a bit convert, store the input value if the 4613 // resultant store does not need a higher alignment than the original. 4614 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4615 ST->isUnindexed()) { 4616 unsigned Align = ST->getAlignment(); 4617 MVT SVT = Value.getOperand(0).getValueType(); 4618 unsigned OrigAlign = TLI.getTargetData()-> 4619 getABITypeAlignment(SVT.getTypeForMVT()); 4620 if (Align <= OrigAlign && 4621 ((!AfterLegalize && !ST->isVolatile()) || 4622 TLI.isOperationLegal(ISD::STORE, SVT))) 4623 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4624 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4625 } 4626 4627 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4628 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4629 // NOTE: If the original store is volatile, this transform must not increase 4630 // the number of stores. For example, on x86-32 an f64 can be stored in one 4631 // processor operation but an i64 (which is not legal) requires two. So the 4632 // transform should not be done in this case. 4633 if (Value.getOpcode() != ISD::TargetConstantFP) { 4634 SDValue Tmp; 4635 switch (CFP->getValueType(0).getSimpleVT()) { 4636 default: assert(0 && "Unknown FP type"); 4637 case MVT::f80: // We don't do this for these yet. 4638 case MVT::f128: 4639 case MVT::ppcf128: 4640 break; 4641 case MVT::f32: 4642 if ((!AfterLegalize && !ST->isVolatile()) || 4643 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4644 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4645 convertToAPInt().getZExtValue(), MVT::i32); 4646 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4647 ST->getSrcValueOffset(), ST->isVolatile(), 4648 ST->getAlignment()); 4649 } 4650 break; 4651 case MVT::f64: 4652 if ((!AfterLegalize && !ST->isVolatile()) || 4653 TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4654 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4655 getZExtValue(), MVT::i64); 4656 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4657 ST->getSrcValueOffset(), ST->isVolatile(), 4658 ST->getAlignment()); 4659 } else if (!ST->isVolatile() && 4660 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4661 // Many FP stores are not made apparent until after legalize, e.g. for 4662 // argument passing. Since this is so common, custom legalize the 4663 // 64-bit integer store into two 32-bit stores. 4664 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4665 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4666 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4667 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4668 4669 int SVOffset = ST->getSrcValueOffset(); 4670 unsigned Alignment = ST->getAlignment(); 4671 bool isVolatile = ST->isVolatile(); 4672 4673 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4674 ST->getSrcValueOffset(), 4675 isVolatile, ST->getAlignment()); 4676 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4677 DAG.getConstant(4, Ptr.getValueType())); 4678 SVOffset += 4; 4679 Alignment = MinAlign(Alignment, 4U); 4680 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4681 SVOffset, isVolatile, Alignment); 4682 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4683 } 4684 break; 4685 } 4686 } 4687 } 4688 4689 if (CombinerAA) { 4690 // Walk up chain skipping non-aliasing memory nodes. 4691 SDValue BetterChain = FindBetterChain(N, Chain); 4692 4693 // If there is a better chain. 4694 if (Chain != BetterChain) { 4695 // Replace the chain to avoid dependency. 4696 SDValue ReplStore; 4697 if (ST->isTruncatingStore()) { 4698 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4699 ST->getSrcValue(),ST->getSrcValueOffset(), 4700 ST->getMemoryVT(), 4701 ST->isVolatile(), ST->getAlignment()); 4702 } else { 4703 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4704 ST->getSrcValue(), ST->getSrcValueOffset(), 4705 ST->isVolatile(), ST->getAlignment()); 4706 } 4707 4708 // Create token to keep both nodes around. 4709 SDValue Token = 4710 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4711 4712 // Don't add users to work list. 4713 return CombineTo(N, Token, false); 4714 } 4715 } 4716 4717 // Try transforming N to an indexed store. 4718 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4719 return SDValue(N, 0); 4720 4721 // FIXME: is there such a thing as a truncating indexed store? 4722 if (ST->isTruncatingStore() && ST->isUnindexed() && 4723 Value.getValueType().isInteger()) { 4724 // See if we can simplify the input to this truncstore with knowledge that 4725 // only the low bits are being used. For example: 4726 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4727 SDValue Shorter = 4728 GetDemandedBits(Value, 4729 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4730 ST->getMemoryVT().getSizeInBits())); 4731 AddToWorkList(Value.getNode()); 4732 if (Shorter.getNode()) 4733 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4734 ST->getSrcValueOffset(), ST->getMemoryVT(), 4735 ST->isVolatile(), ST->getAlignment()); 4736 4737 // Otherwise, see if we can simplify the operation with 4738 // SimplifyDemandedBits, which only works if the value has a single use. 4739 if (SimplifyDemandedBits(Value, 4740 APInt::getLowBitsSet( 4741 Value.getValueSizeInBits(), 4742 ST->getMemoryVT().getSizeInBits()))) 4743 return SDValue(N, 0); 4744 } 4745 4746 // If this is a load followed by a store to the same location, then the store 4747 // is dead/noop. 4748 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4749 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4750 ST->isUnindexed() && !ST->isVolatile() && 4751 // There can't be any side effects between the load and store, such as 4752 // a call or store. 4753 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4754 // The store is dead, remove it. 4755 return Chain; 4756 } 4757 } 4758 4759 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4760 // truncating store. We can do this even if this is already a truncstore. 4761 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4762 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4763 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4764 ST->getMemoryVT())) { 4765 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4766 ST->getSrcValueOffset(), ST->getMemoryVT(), 4767 ST->isVolatile(), ST->getAlignment()); 4768 } 4769 4770 return SDValue(); 4771} 4772 4773SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4774 SDValue InVec = N->getOperand(0); 4775 SDValue InVal = N->getOperand(1); 4776 SDValue EltNo = N->getOperand(2); 4777 4778 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4779 // vector with the inserted element. 4780 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4781 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4782 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4783 InVec.getNode()->op_end()); 4784 if (Elt < Ops.size()) 4785 Ops[Elt] = InVal; 4786 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4787 &Ops[0], Ops.size()); 4788 } 4789 4790 return SDValue(); 4791} 4792 4793SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4794 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4795 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4796 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4797 4798 // Perform only after legalization to ensure build_vector / vector_shuffle 4799 // optimizations have already been done. 4800 if (!AfterLegalize) return SDValue(); 4801 4802 SDValue InVec = N->getOperand(0); 4803 SDValue EltNo = N->getOperand(1); 4804 4805 if (isa<ConstantSDNode>(EltNo)) { 4806 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4807 bool NewLoad = false; 4808 MVT VT = InVec.getValueType(); 4809 MVT EVT = VT.getVectorElementType(); 4810 MVT LVT = EVT; 4811 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4812 MVT BCVT = InVec.getOperand(0).getValueType(); 4813 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4814 return SDValue(); 4815 InVec = InVec.getOperand(0); 4816 EVT = BCVT.getVectorElementType(); 4817 NewLoad = true; 4818 } 4819 4820 LoadSDNode *LN0 = NULL; 4821 if (ISD::isNormalLoad(InVec.getNode())) 4822 LN0 = cast<LoadSDNode>(InVec); 4823 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4824 InVec.getOperand(0).getValueType() == EVT && 4825 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4826 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4827 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4828 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4829 // => 4830 // (load $addr+1*size) 4831 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4832 getOperand(Elt))->getZExtValue(); 4833 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4834 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4835 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4836 InVec = InVec.getOperand(0); 4837 if (ISD::isNormalLoad(InVec.getNode())) { 4838 LN0 = cast<LoadSDNode>(InVec); 4839 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4840 } 4841 } 4842 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4843 return SDValue(); 4844 4845 unsigned Align = LN0->getAlignment(); 4846 if (NewLoad) { 4847 // Check the resultant load doesn't need a higher alignment than the 4848 // original load. 4849 unsigned NewAlign = TLI.getTargetData()-> 4850 getABITypeAlignment(LVT.getTypeForMVT()); 4851 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4852 return SDValue(); 4853 Align = NewAlign; 4854 } 4855 4856 SDValue NewPtr = LN0->getBasePtr(); 4857 if (Elt) { 4858 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4859 MVT PtrType = NewPtr.getValueType(); 4860 if (TLI.isBigEndian()) 4861 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4862 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4863 DAG.getConstant(PtrOff, PtrType)); 4864 } 4865 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4866 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4867 LN0->isVolatile(), Align); 4868 } 4869 return SDValue(); 4870} 4871 4872 4873SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4874 unsigned NumInScalars = N->getNumOperands(); 4875 MVT VT = N->getValueType(0); 4876 unsigned NumElts = VT.getVectorNumElements(); 4877 MVT EltType = VT.getVectorElementType(); 4878 4879 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4880 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4881 // at most two distinct vectors, turn this into a shuffle node. 4882 SDValue VecIn1, VecIn2; 4883 for (unsigned i = 0; i != NumInScalars; ++i) { 4884 // Ignore undef inputs. 4885 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4886 4887 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4888 // constant index, bail out. 4889 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4890 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4891 VecIn1 = VecIn2 = SDValue(0, 0); 4892 break; 4893 } 4894 4895 // If the input vector type disagrees with the result of the build_vector, 4896 // we can't make a shuffle. 4897 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4898 if (ExtractedFromVec.getValueType() != VT) { 4899 VecIn1 = VecIn2 = SDValue(0, 0); 4900 break; 4901 } 4902 4903 // Otherwise, remember this. We allow up to two distinct input vectors. 4904 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4905 continue; 4906 4907 if (VecIn1.getNode() == 0) { 4908 VecIn1 = ExtractedFromVec; 4909 } else if (VecIn2.getNode() == 0) { 4910 VecIn2 = ExtractedFromVec; 4911 } else { 4912 // Too many inputs. 4913 VecIn1 = VecIn2 = SDValue(0, 0); 4914 break; 4915 } 4916 } 4917 4918 // If everything is good, we can make a shuffle operation. 4919 if (VecIn1.getNode()) { 4920 SmallVector<SDValue, 8> BuildVecIndices; 4921 for (unsigned i = 0; i != NumInScalars; ++i) { 4922 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4923 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4924 continue; 4925 } 4926 4927 SDValue Extract = N->getOperand(i); 4928 4929 // If extracting from the first vector, just use the index directly. 4930 if (Extract.getOperand(0) == VecIn1) { 4931 BuildVecIndices.push_back(Extract.getOperand(1)); 4932 continue; 4933 } 4934 4935 // Otherwise, use InIdx + VecSize 4936 unsigned Idx = 4937 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 4938 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4939 } 4940 4941 // Add count and size info. 4942 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 4943 4944 // Return the new VECTOR_SHUFFLE node. 4945 SDValue Ops[5]; 4946 Ops[0] = VecIn1; 4947 if (VecIn2.getNode()) { 4948 Ops[1] = VecIn2; 4949 } else { 4950 // Use an undef build_vector as input for the second operand. 4951 std::vector<SDValue> UnOps(NumInScalars, 4952 DAG.getNode(ISD::UNDEF, 4953 EltType)); 4954 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4955 &UnOps[0], UnOps.size()); 4956 AddToWorkList(Ops[1].getNode()); 4957 } 4958 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4959 &BuildVecIndices[0], BuildVecIndices.size()); 4960 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4961 } 4962 4963 return SDValue(); 4964} 4965 4966SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4967 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4968 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4969 // inputs come from at most two distinct vectors, turn this into a shuffle 4970 // node. 4971 4972 // If we only have one input vector, we don't need to do any concatenation. 4973 if (N->getNumOperands() == 1) { 4974 return N->getOperand(0); 4975 } 4976 4977 return SDValue(); 4978} 4979 4980SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4981 SDValue ShufMask = N->getOperand(2); 4982 unsigned NumElts = ShufMask.getNumOperands(); 4983 4984 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4985 bool isIdentity = true; 4986 for (unsigned i = 0; i != NumElts; ++i) { 4987 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4988 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 4989 isIdentity = false; 4990 break; 4991 } 4992 } 4993 if (isIdentity) return N->getOperand(0); 4994 4995 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4996 isIdentity = true; 4997 for (unsigned i = 0; i != NumElts; ++i) { 4998 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4999 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5000 i+NumElts) { 5001 isIdentity = false; 5002 break; 5003 } 5004 } 5005 if (isIdentity) return N->getOperand(1); 5006 5007 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5008 // needed at all. 5009 bool isUnary = true; 5010 bool isSplat = true; 5011 int VecNum = -1; 5012 unsigned BaseIdx = 0; 5013 for (unsigned i = 0; i != NumElts; ++i) 5014 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5015 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5016 int V = (Idx < NumElts) ? 0 : 1; 5017 if (VecNum == -1) { 5018 VecNum = V; 5019 BaseIdx = Idx; 5020 } else { 5021 if (BaseIdx != Idx) 5022 isSplat = false; 5023 if (VecNum != V) { 5024 isUnary = false; 5025 break; 5026 } 5027 } 5028 } 5029 5030 SDValue N0 = N->getOperand(0); 5031 SDValue N1 = N->getOperand(1); 5032 // Normalize unary shuffle so the RHS is undef. 5033 if (isUnary && VecNum == 1) 5034 std::swap(N0, N1); 5035 5036 // If it is a splat, check if the argument vector is a build_vector with 5037 // all scalar elements the same. 5038 if (isSplat) { 5039 SDNode *V = N0.getNode(); 5040 5041 // If this is a bit convert that changes the element type of the vector but 5042 // not the number of vector elements, look through it. Be careful not to 5043 // look though conversions that change things like v4f32 to v2f64. 5044 if (V->getOpcode() == ISD::BIT_CONVERT) { 5045 SDValue ConvInput = V->getOperand(0); 5046 if (ConvInput.getValueType().isVector() && 5047 ConvInput.getValueType().getVectorNumElements() == NumElts) 5048 V = ConvInput.getNode(); 5049 } 5050 5051 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5052 unsigned NumElems = V->getNumOperands(); 5053 if (NumElems > BaseIdx) { 5054 SDValue Base; 5055 bool AllSame = true; 5056 for (unsigned i = 0; i != NumElems; ++i) { 5057 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5058 Base = V->getOperand(i); 5059 break; 5060 } 5061 } 5062 // Splat of <u, u, u, u>, return <u, u, u, u> 5063 if (!Base.getNode()) 5064 return N0; 5065 for (unsigned i = 0; i != NumElems; ++i) { 5066 if (V->getOperand(i) != Base) { 5067 AllSame = false; 5068 break; 5069 } 5070 } 5071 // Splat of <x, x, x, x>, return <x, x, x, x> 5072 if (AllSame) 5073 return N0; 5074 } 5075 } 5076 } 5077 5078 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5079 // into an undef. 5080 if (isUnary || N0 == N1) { 5081 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5082 // first operand. 5083 SmallVector<SDValue, 8> MappedOps; 5084 for (unsigned i = 0; i != NumElts; ++i) { 5085 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5086 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5087 NumElts) { 5088 MappedOps.push_back(ShufMask.getOperand(i)); 5089 } else { 5090 unsigned NewIdx = 5091 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5092 NumElts; 5093 MappedOps.push_back(DAG.getConstant(NewIdx, 5094 ShufMask.getOperand(i).getValueType())); 5095 } 5096 } 5097 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5098 &MappedOps[0], MappedOps.size()); 5099 AddToWorkList(ShufMask.getNode()); 5100 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5101 N0, 5102 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5103 ShufMask); 5104 } 5105 5106 return SDValue(); 5107} 5108 5109/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5110/// an AND to a vector_shuffle with the destination vector and a zero vector. 5111/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5112/// vector_shuffle V, Zero, <0, 4, 2, 4> 5113SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5114 SDValue LHS = N->getOperand(0); 5115 SDValue RHS = N->getOperand(1); 5116 if (N->getOpcode() == ISD::AND) { 5117 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5118 RHS = RHS.getOperand(0); 5119 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5120 std::vector<SDValue> IdxOps; 5121 unsigned NumOps = RHS.getNumOperands(); 5122 unsigned NumElts = NumOps; 5123 MVT EVT = RHS.getValueType().getVectorElementType(); 5124 for (unsigned i = 0; i != NumElts; ++i) { 5125 SDValue Elt = RHS.getOperand(i); 5126 if (!isa<ConstantSDNode>(Elt)) 5127 return SDValue(); 5128 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5129 IdxOps.push_back(DAG.getConstant(i, EVT)); 5130 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5131 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 5132 else 5133 return SDValue(); 5134 } 5135 5136 // Let's see if the target supports this vector_shuffle. 5137 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 5138 return SDValue(); 5139 5140 // Return the new VECTOR_SHUFFLE node. 5141 MVT VT = MVT::getVectorVT(EVT, NumElts); 5142 std::vector<SDValue> Ops; 5143 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5144 Ops.push_back(LHS); 5145 AddToWorkList(LHS.getNode()); 5146 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5147 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5148 &ZeroOps[0], ZeroOps.size())); 5149 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5150 &IdxOps[0], IdxOps.size())); 5151 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5152 &Ops[0], Ops.size()); 5153 if (VT != N->getValueType(0)) 5154 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5155 return Result; 5156 } 5157 } 5158 return SDValue(); 5159} 5160 5161/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5162SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5163 // After legalize, the target may be depending on adds and other 5164 // binary ops to provide legal ways to construct constants or other 5165 // things. Simplifying them may result in a loss of legality. 5166 if (AfterLegalize) return SDValue(); 5167 5168 MVT VT = N->getValueType(0); 5169 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5170 5171 MVT EltType = VT.getVectorElementType(); 5172 SDValue LHS = N->getOperand(0); 5173 SDValue RHS = N->getOperand(1); 5174 SDValue Shuffle = XformToShuffleWithZero(N); 5175 if (Shuffle.getNode()) return Shuffle; 5176 5177 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5178 // this operation. 5179 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5180 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5181 SmallVector<SDValue, 8> Ops; 5182 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5183 SDValue LHSOp = LHS.getOperand(i); 5184 SDValue RHSOp = RHS.getOperand(i); 5185 // If these two elements can't be folded, bail out. 5186 if ((LHSOp.getOpcode() != ISD::UNDEF && 5187 LHSOp.getOpcode() != ISD::Constant && 5188 LHSOp.getOpcode() != ISD::ConstantFP) || 5189 (RHSOp.getOpcode() != ISD::UNDEF && 5190 RHSOp.getOpcode() != ISD::Constant && 5191 RHSOp.getOpcode() != ISD::ConstantFP)) 5192 break; 5193 // Can't fold divide by zero. 5194 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5195 N->getOpcode() == ISD::FDIV) { 5196 if ((RHSOp.getOpcode() == ISD::Constant && 5197 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5198 (RHSOp.getOpcode() == ISD::ConstantFP && 5199 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5200 break; 5201 } 5202 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5203 AddToWorkList(Ops.back().getNode()); 5204 assert((Ops.back().getOpcode() == ISD::UNDEF || 5205 Ops.back().getOpcode() == ISD::Constant || 5206 Ops.back().getOpcode() == ISD::ConstantFP) && 5207 "Scalar binop didn't fold!"); 5208 } 5209 5210 if (Ops.size() == LHS.getNumOperands()) { 5211 MVT VT = LHS.getValueType(); 5212 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5213 } 5214 } 5215 5216 return SDValue(); 5217} 5218 5219SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5220 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5221 5222 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5223 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5224 // If we got a simplified select_cc node back from SimplifySelectCC, then 5225 // break it down into a new SETCC node, and a new SELECT node, and then return 5226 // the SELECT node, since we were called with a SELECT node. 5227 if (SCC.getNode()) { 5228 // Check to see if we got a select_cc back (to turn into setcc/select). 5229 // Otherwise, just return whatever node we got back, like fabs. 5230 if (SCC.getOpcode() == ISD::SELECT_CC) { 5231 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5232 SCC.getOperand(0), SCC.getOperand(1), 5233 SCC.getOperand(4)); 5234 AddToWorkList(SETCC.getNode()); 5235 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5236 SCC.getOperand(3), SETCC); 5237 } 5238 return SCC; 5239 } 5240 return SDValue(); 5241} 5242 5243/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5244/// are the two values being selected between, see if we can simplify the 5245/// select. Callers of this should assume that TheSelect is deleted if this 5246/// returns true. As such, they should return the appropriate thing (e.g. the 5247/// node) back to the top-level of the DAG combiner loop to avoid it being 5248/// looked at. 5249/// 5250bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5251 SDValue RHS) { 5252 5253 // If this is a select from two identical things, try to pull the operation 5254 // through the select. 5255 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5256 // If this is a load and the token chain is identical, replace the select 5257 // of two loads with a load through a select of the address to load from. 5258 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5259 // constants have been dropped into the constant pool. 5260 if (LHS.getOpcode() == ISD::LOAD && 5261 // Do not let this transformation reduce the number of volatile loads. 5262 !cast<LoadSDNode>(LHS)->isVolatile() && 5263 !cast<LoadSDNode>(RHS)->isVolatile() && 5264 // Token chains must be identical. 5265 LHS.getOperand(0) == RHS.getOperand(0)) { 5266 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5267 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5268 5269 // If this is an EXTLOAD, the VT's must match. 5270 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5271 // FIXME: this conflates two src values, discarding one. This is not 5272 // the right thing to do, but nothing uses srcvalues now. When they do, 5273 // turn SrcValue into a list of locations. 5274 SDValue Addr; 5275 if (TheSelect->getOpcode() == ISD::SELECT) { 5276 // Check that the condition doesn't reach either load. If so, folding 5277 // this will induce a cycle into the DAG. 5278 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5279 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5280 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5281 TheSelect->getOperand(0), LLD->getBasePtr(), 5282 RLD->getBasePtr()); 5283 } 5284 } else { 5285 // Check that the condition doesn't reach either load. If so, folding 5286 // this will induce a cycle into the DAG. 5287 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5288 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5289 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5290 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5291 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5292 TheSelect->getOperand(0), 5293 TheSelect->getOperand(1), 5294 LLD->getBasePtr(), RLD->getBasePtr(), 5295 TheSelect->getOperand(4)); 5296 } 5297 } 5298 5299 if (Addr.getNode()) { 5300 SDValue Load; 5301 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5302 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5303 Addr,LLD->getSrcValue(), 5304 LLD->getSrcValueOffset(), 5305 LLD->isVolatile(), 5306 LLD->getAlignment()); 5307 else { 5308 Load = DAG.getExtLoad(LLD->getExtensionType(), 5309 TheSelect->getValueType(0), 5310 LLD->getChain(), Addr, LLD->getSrcValue(), 5311 LLD->getSrcValueOffset(), 5312 LLD->getMemoryVT(), 5313 LLD->isVolatile(), 5314 LLD->getAlignment()); 5315 } 5316 // Users of the select now use the result of the load. 5317 CombineTo(TheSelect, Load); 5318 5319 // Users of the old loads now use the new load's chain. We know the 5320 // old-load value is dead now. 5321 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5322 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5323 return true; 5324 } 5325 } 5326 } 5327 } 5328 5329 return false; 5330} 5331 5332SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5333 SDValue N2, SDValue N3, 5334 ISD::CondCode CC, bool NotExtCompare) { 5335 5336 MVT VT = N2.getValueType(); 5337 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5338 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5339 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5340 5341 // Determine if the condition we're dealing with is constant 5342 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5343 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5344 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5345 5346 // fold select_cc true, x, y -> x 5347 if (SCCC && !SCCC->isNullValue()) 5348 return N2; 5349 // fold select_cc false, x, y -> y 5350 if (SCCC && SCCC->isNullValue()) 5351 return N3; 5352 5353 // Check to see if we can simplify the select into an fabs node 5354 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5355 // Allow either -0.0 or 0.0 5356 if (CFP->getValueAPF().isZero()) { 5357 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5358 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5359 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5360 N2 == N3.getOperand(0)) 5361 return DAG.getNode(ISD::FABS, VT, N0); 5362 5363 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5364 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5365 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5366 N2.getOperand(0) == N3) 5367 return DAG.getNode(ISD::FABS, VT, N3); 5368 } 5369 } 5370 5371 // Check to see if we can perform the "gzip trick", transforming 5372 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5373 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5374 N0.getValueType().isInteger() && 5375 N2.getValueType().isInteger() && 5376 (N1C->isNullValue() || // (a < 0) ? b : 0 5377 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5378 MVT XType = N0.getValueType(); 5379 MVT AType = N2.getValueType(); 5380 if (XType.bitsGE(AType)) { 5381 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5382 // single-bit constant. 5383 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5384 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5385 ShCtV = XType.getSizeInBits()-ShCtV-1; 5386 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5387 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5388 AddToWorkList(Shift.getNode()); 5389 if (XType.bitsGT(AType)) { 5390 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5391 AddToWorkList(Shift.getNode()); 5392 } 5393 return DAG.getNode(ISD::AND, AType, Shift, N2); 5394 } 5395 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5396 DAG.getConstant(XType.getSizeInBits()-1, 5397 TLI.getShiftAmountTy())); 5398 AddToWorkList(Shift.getNode()); 5399 if (XType.bitsGT(AType)) { 5400 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5401 AddToWorkList(Shift.getNode()); 5402 } 5403 return DAG.getNode(ISD::AND, AType, Shift, N2); 5404 } 5405 } 5406 5407 // fold select C, 16, 0 -> shl C, 4 5408 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5409 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5410 5411 // If the caller doesn't want us to simplify this into a zext of a compare, 5412 // don't do it. 5413 if (NotExtCompare && N2C->getAPIntValue() == 1) 5414 return SDValue(); 5415 5416 // Get a SetCC of the condition 5417 // FIXME: Should probably make sure that setcc is legal if we ever have a 5418 // target where it isn't. 5419 SDValue Temp, SCC; 5420 // cast from setcc result type to select result type 5421 if (AfterLegalize) { 5422 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5423 if (N2.getValueType().bitsLT(SCC.getValueType())) 5424 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5425 else 5426 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5427 } else { 5428 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5429 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5430 } 5431 AddToWorkList(SCC.getNode()); 5432 AddToWorkList(Temp.getNode()); 5433 5434 if (N2C->getAPIntValue() == 1) 5435 return Temp; 5436 // shl setcc result by log2 n2c 5437 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5438 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5439 TLI.getShiftAmountTy())); 5440 } 5441 5442 // Check to see if this is the equivalent of setcc 5443 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5444 // otherwise, go ahead with the folds. 5445 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5446 MVT XType = N0.getValueType(); 5447 if (!AfterLegalize || 5448 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5449 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5450 if (Res.getValueType() != VT) 5451 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5452 return Res; 5453 } 5454 5455 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5456 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5457 (!AfterLegalize || 5458 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5459 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5460 return DAG.getNode(ISD::SRL, XType, Ctlz, 5461 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5462 TLI.getShiftAmountTy())); 5463 } 5464 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5465 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5466 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5467 N0); 5468 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5469 DAG.getConstant(~0ULL, XType)); 5470 return DAG.getNode(ISD::SRL, XType, 5471 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5472 DAG.getConstant(XType.getSizeInBits()-1, 5473 TLI.getShiftAmountTy())); 5474 } 5475 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5476 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5477 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5478 DAG.getConstant(XType.getSizeInBits()-1, 5479 TLI.getShiftAmountTy())); 5480 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5481 } 5482 } 5483 5484 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5485 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5486 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5487 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5488 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5489 MVT XType = N0.getValueType(); 5490 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5491 DAG.getConstant(XType.getSizeInBits()-1, 5492 TLI.getShiftAmountTy())); 5493 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5494 AddToWorkList(Shift.getNode()); 5495 AddToWorkList(Add.getNode()); 5496 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5497 } 5498 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5499 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5500 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5501 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5502 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5503 MVT XType = N0.getValueType(); 5504 if (SubC->isNullValue() && XType.isInteger()) { 5505 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5506 DAG.getConstant(XType.getSizeInBits()-1, 5507 TLI.getShiftAmountTy())); 5508 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5509 AddToWorkList(Shift.getNode()); 5510 AddToWorkList(Add.getNode()); 5511 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5512 } 5513 } 5514 } 5515 5516 return SDValue(); 5517} 5518 5519/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5520SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5521 SDValue N1, ISD::CondCode Cond, 5522 bool foldBooleans) { 5523 TargetLowering::DAGCombinerInfo 5524 DagCombineInfo(DAG, !AfterLegalize, false, this); 5525 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5526} 5527 5528/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5529/// return a DAG expression to select that will generate the same value by 5530/// multiplying by a magic number. See: 5531/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5532SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5533 std::vector<SDNode*> Built; 5534 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5535 5536 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5537 ii != ee; ++ii) 5538 AddToWorkList(*ii); 5539 return S; 5540} 5541 5542/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5543/// return a DAG expression to select that will generate the same value by 5544/// multiplying by a magic number. See: 5545/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5546SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5547 std::vector<SDNode*> Built; 5548 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5549 5550 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5551 ii != ee; ++ii) 5552 AddToWorkList(*ii); 5553 return S; 5554} 5555 5556/// FindBaseOffset - Return true if base is known not to alias with anything 5557/// but itself. Provides base object and offset as results. 5558static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5559 // Assume it is a primitive operation. 5560 Base = Ptr; Offset = 0; 5561 5562 // If it's an adding a simple constant then integrate the offset. 5563 if (Base.getOpcode() == ISD::ADD) { 5564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5565 Base = Base.getOperand(0); 5566 Offset += C->getZExtValue(); 5567 } 5568 } 5569 5570 // If it's any of the following then it can't alias with anything but itself. 5571 return isa<FrameIndexSDNode>(Base) || 5572 isa<ConstantPoolSDNode>(Base) || 5573 isa<GlobalAddressSDNode>(Base); 5574} 5575 5576/// isAlias - Return true if there is any possibility that the two addresses 5577/// overlap. 5578bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5579 const Value *SrcValue1, int SrcValueOffset1, 5580 SDValue Ptr2, int64_t Size2, 5581 const Value *SrcValue2, int SrcValueOffset2) 5582{ 5583 // If they are the same then they must be aliases. 5584 if (Ptr1 == Ptr2) return true; 5585 5586 // Gather base node and offset information. 5587 SDValue Base1, Base2; 5588 int64_t Offset1, Offset2; 5589 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5590 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5591 5592 // If they have a same base address then... 5593 if (Base1 == Base2) { 5594 // Check to see if the addresses overlap. 5595 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5596 } 5597 5598 // If we know both bases then they can't alias. 5599 if (KnownBase1 && KnownBase2) return false; 5600 5601 if (CombinerGlobalAA) { 5602 // Use alias analysis information. 5603 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5604 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5605 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5606 AliasAnalysis::AliasResult AAResult = 5607 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5608 if (AAResult == AliasAnalysis::NoAlias) 5609 return false; 5610 } 5611 5612 // Otherwise we have to assume they alias. 5613 return true; 5614} 5615 5616/// FindAliasInfo - Extracts the relevant alias information from the memory 5617/// node. Returns true if the operand was a load. 5618bool DAGCombiner::FindAliasInfo(SDNode *N, 5619 SDValue &Ptr, int64_t &Size, 5620 const Value *&SrcValue, int &SrcValueOffset) { 5621 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5622 Ptr = LD->getBasePtr(); 5623 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5624 SrcValue = LD->getSrcValue(); 5625 SrcValueOffset = LD->getSrcValueOffset(); 5626 return true; 5627 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5628 Ptr = ST->getBasePtr(); 5629 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5630 SrcValue = ST->getSrcValue(); 5631 SrcValueOffset = ST->getSrcValueOffset(); 5632 } else { 5633 assert(0 && "FindAliasInfo expected a memory operand"); 5634 } 5635 5636 return false; 5637} 5638 5639/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5640/// looking for aliasing nodes and adding them to the Aliases vector. 5641void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5642 SmallVector<SDValue, 8> &Aliases) { 5643 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5644 std::set<SDNode *> Visited; // Visited node set. 5645 5646 // Get alias information for node. 5647 SDValue Ptr; 5648 int64_t Size; 5649 const Value *SrcValue; 5650 int SrcValueOffset; 5651 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5652 5653 // Starting off. 5654 Chains.push_back(OriginalChain); 5655 5656 // Look at each chain and determine if it is an alias. If so, add it to the 5657 // aliases list. If not, then continue up the chain looking for the next 5658 // candidate. 5659 while (!Chains.empty()) { 5660 SDValue Chain = Chains.back(); 5661 Chains.pop_back(); 5662 5663 // Don't bother if we've been before. 5664 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5665 Visited.insert(Chain.getNode()); 5666 5667 switch (Chain.getOpcode()) { 5668 case ISD::EntryToken: 5669 // Entry token is ideal chain operand, but handled in FindBetterChain. 5670 break; 5671 5672 case ISD::LOAD: 5673 case ISD::STORE: { 5674 // Get alias information for Chain. 5675 SDValue OpPtr; 5676 int64_t OpSize; 5677 const Value *OpSrcValue; 5678 int OpSrcValueOffset; 5679 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5680 OpSrcValue, OpSrcValueOffset); 5681 5682 // If chain is alias then stop here. 5683 if (!(IsLoad && IsOpLoad) && 5684 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5685 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5686 Aliases.push_back(Chain); 5687 } else { 5688 // Look further up the chain. 5689 Chains.push_back(Chain.getOperand(0)); 5690 // Clean up old chain. 5691 AddToWorkList(Chain.getNode()); 5692 } 5693 break; 5694 } 5695 5696 case ISD::TokenFactor: 5697 // We have to check each of the operands of the token factor, so we queue 5698 // then up. Adding the operands to the queue (stack) in reverse order 5699 // maintains the original order and increases the likelihood that getNode 5700 // will find a matching token factor (CSE.) 5701 for (unsigned n = Chain.getNumOperands(); n;) 5702 Chains.push_back(Chain.getOperand(--n)); 5703 // Eliminate the token factor if we can. 5704 AddToWorkList(Chain.getNode()); 5705 break; 5706 5707 default: 5708 // For all other instructions we will just have to take what we can get. 5709 Aliases.push_back(Chain); 5710 break; 5711 } 5712 } 5713} 5714 5715/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5716/// for a better chain (aliasing node.) 5717SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5718 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5719 5720 // Accumulate all the aliases to this node. 5721 GatherAllAliases(N, OldChain, Aliases); 5722 5723 if (Aliases.size() == 0) { 5724 // If no operands then chain to entry token. 5725 return DAG.getEntryNode(); 5726 } else if (Aliases.size() == 1) { 5727 // If a single operand then chain to it. We don't need to revisit it. 5728 return Aliases[0]; 5729 } 5730 5731 // Construct a custom tailored token factor. 5732 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5733 &Aliases[0], Aliases.size()); 5734 5735 // Make sure the old chain gets cleaned up. 5736 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5737 5738 return NewChain; 5739} 5740 5741// SelectionDAG::Combine - This is the entry point for the file. 5742// 5743void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA, 5744 bool Fast) { 5745 /// run - This is the main entry point to this class. 5746 /// 5747 DAGCombiner(*this, AA, Fast).Run(RunningAfterLegalize); 5748} 5749