TwoAddressInstructionPass.cpp revision 7896c9f436a4eda5ec15e882a7505ba482a2fcd0 
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TwoAddress instruction pass which is used
11// by most register allocators. Two-Address instructions are rewritten
12// from:
13//
14//     A = B op C
15//
16// to:
17//
18//     A = B
19//     A op= C
20//
21// Note that if a register allocator chooses to use this pass, that it
22// has to be capable of handling the non-SSA nature of these rewritten
23// virtual registers.
24//
25// It is also worth noting that the duplicate operand of the two
26// address instruction is removed.
27//
28//===----------------------------------------------------------------------===//
29
30#define DEBUG_TYPE "twoaddrinstr"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/Function.h"
33#include "llvm/CodeGen/LiveVariables.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/Analysis/AliasAnalysis.h"
38#include "llvm/Target/TargetRegisterInfo.h"
39#include "llvm/Target/TargetInstrInfo.h"
40#include "llvm/Target/TargetMachine.h"
41#include "llvm/Target/TargetOptions.h"
42#include "llvm/Support/Debug.h"
43#include "llvm/ADT/BitVector.h"
44#include "llvm/ADT/DenseMap.h"
45#include "llvm/ADT/SmallSet.h"
46#include "llvm/ADT/Statistic.h"
47#include "llvm/ADT/STLExtras.h"
48using namespace llvm;
49
50STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
51STATISTIC(NumCommuted        , "Number of instructions commuted to coalesce");
52STATISTIC(NumAggrCommuted    , "Number of instructions aggressively commuted");
53STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
54STATISTIC(Num3AddrSunk,        "Number of 3-address instructions sunk");
55STATISTIC(NumReMats,           "Number of instructions re-materialized");
56STATISTIC(NumDeletes,          "Number of dead instructions deleted");
57
58namespace {
59  class TwoAddressInstructionPass : public MachineFunctionPass {
60    const TargetInstrInfo *TII;
61    const TargetRegisterInfo *TRI;
62    MachineRegisterInfo *MRI;
63    LiveVariables *LV;
64    AliasAnalysis *AA;
65
66    // DistanceMap - Keep track the distance of a MI from the start of the
67    // current basic block.
68    DenseMap<MachineInstr*, unsigned> DistanceMap;
69
70    // SrcRegMap - A map from virtual registers to physical registers which
71    // are likely targets to be coalesced to due to copies from physical
72    // registers to virtual registers. e.g. v1024 = move r0.
73    DenseMap<unsigned, unsigned> SrcRegMap;
74
75    // DstRegMap - A map from virtual registers to physical registers which
76    // are likely targets to be coalesced to due to copies to physical
77    // registers from virtual registers. e.g. r1 = move v1024.
78    DenseMap<unsigned, unsigned> DstRegMap;
79
80    bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
81                              unsigned Reg,
82                              MachineBasicBlock::iterator OldPos);
83
84    bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
85                             MachineInstr *MI, MachineInstr *DefMI,
86                             MachineBasicBlock *MBB, unsigned Loc);
87
88    bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
89                           unsigned &LastDef);
90
91    MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
92                                   unsigned Dist);
93
94    bool isProfitableToCommute(unsigned regB, unsigned regC,
95                               MachineInstr *MI, MachineBasicBlock *MBB,
96                               unsigned Dist);
97
98    bool CommuteInstruction(MachineBasicBlock::iterator &mi,
99                            MachineFunction::iterator &mbbi,
100                            unsigned RegB, unsigned RegC, unsigned Dist);
101
102    bool isProfitableToConv3Addr(unsigned RegA);
103
104    bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
105                            MachineBasicBlock::iterator &nmi,
106                            MachineFunction::iterator &mbbi,
107                            unsigned RegB, unsigned Dist);
108
109    typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
110    bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
111                               SmallVector<NewKill, 4> &NewKills,
112                               MachineBasicBlock *MBB, unsigned Dist);
113    bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
114                           MachineBasicBlock::iterator &nmi,
115                           MachineFunction::iterator &mbbi, unsigned Dist);
116
117    bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
118                                 MachineBasicBlock::iterator &nmi,
119                                 MachineFunction::iterator &mbbi,
120                                 unsigned SrcIdx, unsigned DstIdx,
121                                 unsigned Dist);
122
123    void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
124                     SmallPtrSet<MachineInstr*, 8> &Processed);
125
126  public:
127    static char ID; // Pass identification, replacement for typeid
128    TwoAddressInstructionPass() : MachineFunctionPass(&ID) {}
129
130    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
131      AU.setPreservesCFG();
132      AU.addRequired<AliasAnalysis>();
133      AU.addPreserved<LiveVariables>();
134      AU.addPreservedID(MachineLoopInfoID);
135      AU.addPreservedID(MachineDominatorsID);
136      if (StrongPHIElim)
137        AU.addPreservedID(StrongPHIEliminationID);
138      else
139        AU.addPreservedID(PHIEliminationID);
140      MachineFunctionPass::getAnalysisUsage(AU);
141    }
142
143    /// runOnMachineFunction - Pass entry point.
144    bool runOnMachineFunction(MachineFunction&);
145  };
146}
147
148char TwoAddressInstructionPass::ID = 0;
149static RegisterPass<TwoAddressInstructionPass>
150X("twoaddressinstruction", "Two-Address instruction pass");
151
152const PassInfo *const llvm::TwoAddressInstructionPassID = &X;
153
154/// Sink3AddrInstruction - A two-address instruction has been converted to a
155/// three-address instruction to avoid clobbering a register. Try to sink it
156/// past the instruction that would kill the above mentioned register to reduce
157/// register pressure.
158bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
159                                           MachineInstr *MI, unsigned SavedReg,
160                                           MachineBasicBlock::iterator OldPos) {
161  // Check if it's safe to move this instruction.
162  bool SeenStore = true; // Be conservative.
163  if (!MI->isSafeToMove(TII, SeenStore, AA))
164    return false;
165
166  unsigned DefReg = 0;
167  SmallSet<unsigned, 4> UseRegs;
168
169  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
170    const MachineOperand &MO = MI->getOperand(i);
171    if (!MO.isReg())
172      continue;
173    unsigned MOReg = MO.getReg();
174    if (!MOReg)
175      continue;
176    if (MO.isUse() && MOReg != SavedReg)
177      UseRegs.insert(MO.getReg());
178    if (!MO.isDef())
179      continue;
180    if (MO.isImplicit())
181      // Don't try to move it if it implicitly defines a register.
182      return false;
183    if (DefReg)
184      // For now, don't move any instructions that define multiple registers.
185      return false;
186    DefReg = MO.getReg();
187  }
188
189  // Find the instruction that kills SavedReg.
190  MachineInstr *KillMI = NULL;
191  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SavedReg),
192         UE = MRI->use_end(); UI != UE; ++UI) {
193    MachineOperand &UseMO = UI.getOperand();
194    if (!UseMO.isKill())
195      continue;
196    KillMI = UseMO.getParent();
197    break;
198  }
199
200  if (!KillMI || KillMI->getParent() != MBB || KillMI == MI)
201    return false;
202
203  // If any of the definitions are used by another instruction between the
204  // position and the kill use, then it's not safe to sink it.
205  //
206  // FIXME: This can be sped up if there is an easy way to query whether an
207  // instruction is before or after another instruction. Then we can use
208  // MachineRegisterInfo def / use instead.
209  MachineOperand *KillMO = NULL;
210  MachineBasicBlock::iterator KillPos = KillMI;
211  ++KillPos;
212
213  unsigned NumVisited = 0;
214  for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
215    MachineInstr *OtherMI = I;
216    if (NumVisited > 30)  // FIXME: Arbitrary limit to reduce compile time cost.
217      return false;
218    ++NumVisited;
219    for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
220      MachineOperand &MO = OtherMI->getOperand(i);
221      if (!MO.isReg())
222        continue;
223      unsigned MOReg = MO.getReg();
224      if (!MOReg)
225        continue;
226      if (DefReg == MOReg)
227        return false;
228
229      if (MO.isKill()) {
230        if (OtherMI == KillMI && MOReg == SavedReg)
231          // Save the operand that kills the register. We want to unset the kill
232          // marker if we can sink MI past it.
233          KillMO = &MO;
234        else if (UseRegs.count(MOReg))
235          // One of the uses is killed before the destination.
236          return false;
237      }
238    }
239  }
240
241  // Update kill and LV information.
242  KillMO->setIsKill(false);
243  KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
244  KillMO->setIsKill(true);
245
246  if (LV)
247    LV->replaceKillInstruction(SavedReg, KillMI, MI);
248
249  // Move instruction to its destination.
250  MBB->remove(MI);
251  MBB->insert(KillPos, MI);
252
253  ++Num3AddrSunk;
254  return true;
255}
256
257/// isTwoAddrUse - Return true if the specified MI is using the specified
258/// register as a two-address operand.
259static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
260  const TargetInstrDesc &TID = UseMI->getDesc();
261  for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
262    MachineOperand &MO = UseMI->getOperand(i);
263    if (MO.isReg() && MO.getReg() == Reg &&
264        (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
265      // Earlier use is a two-address one.
266      return true;
267  }
268  return false;
269}
270
271/// isProfitableToReMat - Return true if the heuristics determines it is likely
272/// to be profitable to re-materialize the definition of Reg rather than copy
273/// the register.
274bool
275TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
276                                         const TargetRegisterClass *RC,
277                                         MachineInstr *MI, MachineInstr *DefMI,
278                                         MachineBasicBlock *MBB, unsigned Loc) {
279  bool OtherUse = false;
280  for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
281         UE = MRI->use_end(); UI != UE; ++UI) {
282    MachineOperand &UseMO = UI.getOperand();
283    MachineInstr *UseMI = UseMO.getParent();
284    MachineBasicBlock *UseMBB = UseMI->getParent();
285    if (UseMBB == MBB) {
286      DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
287      if (DI != DistanceMap.end() && DI->second == Loc)
288        continue;  // Current use.
289      OtherUse = true;
290      // There is at least one other use in the MBB that will clobber the
291      // register.
292      if (isTwoAddrUse(UseMI, Reg))
293        return true;
294    }
295  }
296
297  // If other uses in MBB are not two-address uses, then don't remat.
298  if (OtherUse)
299    return false;
300
301  // No other uses in the same block, remat if it's defined in the same
302  // block so it does not unnecessarily extend the live range.
303  return MBB == DefMI->getParent();
304}
305
306/// NoUseAfterLastDef - Return true if there are no intervening uses between the
307/// last instruction in the MBB that defines the specified register and the
308/// two-address instruction which is being processed. It also returns the last
309/// def location by reference
310bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
311                                           MachineBasicBlock *MBB, unsigned Dist,
312                                           unsigned &LastDef) {
313  LastDef = 0;
314  unsigned LastUse = Dist;
315  for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
316         E = MRI->reg_end(); I != E; ++I) {
317    MachineOperand &MO = I.getOperand();
318    MachineInstr *MI = MO.getParent();
319    if (MI->getParent() != MBB)
320      continue;
321    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
322    if (DI == DistanceMap.end())
323      continue;
324    if (MO.isUse() && DI->second < LastUse)
325      LastUse = DI->second;
326    if (MO.isDef() && DI->second > LastDef)
327      LastDef = DI->second;
328  }
329
330  return !(LastUse > LastDef && LastUse < Dist);
331}
332
333MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
334                                                         MachineBasicBlock *MBB,
335                                                         unsigned Dist) {
336  unsigned LastUseDist = 0;
337  MachineInstr *LastUse = 0;
338  for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
339         E = MRI->reg_end(); I != E; ++I) {
340    MachineOperand &MO = I.getOperand();
341    MachineInstr *MI = MO.getParent();
342    if (MI->getParent() != MBB)
343      continue;
344    DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
345    if (DI == DistanceMap.end())
346      continue;
347    if (DI->second >= Dist)
348      continue;
349
350    if (MO.isUse() && DI->second > LastUseDist) {
351      LastUse = DI->first;
352      LastUseDist = DI->second;
353    }
354  }
355  return LastUse;
356}
357
358/// isCopyToReg - Return true if the specified MI is a copy instruction or
359/// a extract_subreg instruction. It also returns the source and destination
360/// registers and whether they are physical registers by reference.
361static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
362                        unsigned &SrcReg, unsigned &DstReg,
363                        bool &IsSrcPhys, bool &IsDstPhys) {
364  SrcReg = 0;
365  DstReg = 0;
366  unsigned SrcSubIdx, DstSubIdx;
367  if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
368    if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
369      DstReg = MI.getOperand(0).getReg();
370      SrcReg = MI.getOperand(1).getReg();
371    } else if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
372      DstReg = MI.getOperand(0).getReg();
373      SrcReg = MI.getOperand(2).getReg();
374    } else if (MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
375      DstReg = MI.getOperand(0).getReg();
376      SrcReg = MI.getOperand(2).getReg();
377    }
378  }
379
380  if (DstReg) {
381    IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
382    IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
383    return true;
384  }
385  return false;
386}
387
388/// isKilled - Test if the given register value, which is used by the given
389/// instruction, is killed by the given instruction. This looks through
390/// coalescable copies to see if the original value is potentially not killed.
391///
392/// For example, in this code:
393///
394///   %reg1034 = copy %reg1024
395///   %reg1035 = copy %reg1025<kill>
396///   %reg1036 = add %reg1034<kill>, %reg1035<kill>
397///
398/// %reg1034 is not considered to be killed, since it is copied from a
399/// register which is not killed. Treating it as not killed lets the
400/// normal heuristics commute the (two-address) add, which lets
401/// coalescing eliminate the extra copy.
402///
403static bool isKilled(MachineInstr &MI, unsigned Reg,
404                     const MachineRegisterInfo *MRI,
405                     const TargetInstrInfo *TII) {
406  MachineInstr *DefMI = &MI;
407  for (;;) {
408    if (!DefMI->killsRegister(Reg))
409      return false;
410    if (TargetRegisterInfo::isPhysicalRegister(Reg))
411      return true;
412    MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
413    // If there are multiple defs, we can't do a simple analysis, so just
414    // go with what the kill flag says.
415    if (llvm::next(Begin) != MRI->def_end())
416      return true;
417    DefMI = &*Begin;
418    bool IsSrcPhys, IsDstPhys;
419    unsigned SrcReg,  DstReg;
420    // If the def is something other than a copy, then it isn't going to
421    // be coalesced, so follow the kill flag.
422    if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
423      return true;
424    Reg = SrcReg;
425  }
426}
427
428/// isTwoAddrUse - Return true if the specified MI uses the specified register
429/// as a two-address use. If so, return the destination register by reference.
430static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
431  const TargetInstrDesc &TID = MI.getDesc();
432  unsigned NumOps = (MI.getOpcode() == TargetInstrInfo::INLINEASM)
433    ? MI.getNumOperands() : TID.getNumOperands();
434  for (unsigned i = 0; i != NumOps; ++i) {
435    const MachineOperand &MO = MI.getOperand(i);
436    if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
437      continue;
438    unsigned ti;
439    if (MI.isRegTiedToDefOperand(i, &ti)) {
440      DstReg = MI.getOperand(ti).getReg();
441      return true;
442    }
443  }
444  return false;
445}
446
447/// findOnlyInterestingUse - Given a register, if has a single in-basic block
448/// use, return the use instruction if it's a copy or a two-address use.
449static
450MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
451                                     MachineRegisterInfo *MRI,
452                                     const TargetInstrInfo *TII,
453                                     bool &IsCopy,
454                                     unsigned &DstReg, bool &IsDstPhys) {
455  MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg);
456  if (UI == MRI->use_end())
457    return 0;
458  MachineInstr &UseMI = *UI;
459  if (++UI != MRI->use_end())
460    // More than one use.
461    return 0;
462  if (UseMI.getParent() != MBB)
463    return 0;
464  unsigned SrcReg;
465  bool IsSrcPhys;
466  if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
467    IsCopy = true;
468    return &UseMI;
469  }
470  IsDstPhys = false;
471  if (isTwoAddrUse(UseMI, Reg, DstReg)) {
472    IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
473    return &UseMI;
474  }
475  return 0;
476}
477
478/// getMappedReg - Return the physical register the specified virtual register
479/// might be mapped to.
480static unsigned
481getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
482  while (TargetRegisterInfo::isVirtualRegister(Reg))  {
483    DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
484    if (SI == RegMap.end())
485      return 0;
486    Reg = SI->second;
487  }
488  if (TargetRegisterInfo::isPhysicalRegister(Reg))
489    return Reg;
490  return 0;
491}
492
493/// regsAreCompatible - Return true if the two registers are equal or aliased.
494///
495static bool
496regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
497  if (RegA == RegB)
498    return true;
499  if (!RegA || !RegB)
500    return false;
501  return TRI->regsOverlap(RegA, RegB);
502}
503
504
505/// isProfitableToReMat - Return true if it's potentially profitable to commute
506/// the two-address instruction that's being processed.
507bool
508TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
509                                       MachineInstr *MI, MachineBasicBlock *MBB,
510                                       unsigned Dist) {
511  // Determine if it's profitable to commute this two address instruction. In
512  // general, we want no uses between this instruction and the definition of
513  // the two-address register.
514  // e.g.
515  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
516  // %reg1029<def> = MOV8rr %reg1028
517  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
518  // insert => %reg1030<def> = MOV8rr %reg1028
519  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
520  // In this case, it might not be possible to coalesce the second MOV8rr
521  // instruction if the first one is coalesced. So it would be profitable to
522  // commute it:
523  // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
524  // %reg1029<def> = MOV8rr %reg1028
525  // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
526  // insert => %reg1030<def> = MOV8rr %reg1029
527  // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
528
529  if (!MI->killsRegister(regC))
530    return false;
531
532  // Ok, we have something like:
533  // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
534  // let's see if it's worth commuting it.
535
536  // Look for situations like this:
537  // %reg1024<def> = MOV r1
538  // %reg1025<def> = MOV r0
539  // %reg1026<def> = ADD %reg1024, %reg1025
540  // r0            = MOV %reg1026
541  // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
542  unsigned FromRegB = getMappedReg(regB, SrcRegMap);
543  unsigned FromRegC = getMappedReg(regC, SrcRegMap);
544  unsigned ToRegB = getMappedReg(regB, DstRegMap);
545  unsigned ToRegC = getMappedReg(regC, DstRegMap);
546  if (!regsAreCompatible(FromRegB, ToRegB, TRI) &&
547      (regsAreCompatible(FromRegB, ToRegC, TRI) ||
548       regsAreCompatible(FromRegC, ToRegB, TRI)))
549    return true;
550
551  // If there is a use of regC between its last def (could be livein) and this
552  // instruction, then bail.
553  unsigned LastDefC = 0;
554  if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
555    return false;
556
557  // If there is a use of regB between its last def (could be livein) and this
558  // instruction, then go ahead and make this transformation.
559  unsigned LastDefB = 0;
560  if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
561    return true;
562
563  // Since there are no intervening uses for both registers, then commute
564  // if the def of regC is closer. Its live interval is shorter.
565  return LastDefB && LastDefC && LastDefC > LastDefB;
566}
567
568/// CommuteInstruction - Commute a two-address instruction and update the basic
569/// block, distance map, and live variables if needed. Return true if it is
570/// successful.
571bool
572TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
573                               MachineFunction::iterator &mbbi,
574                               unsigned RegB, unsigned RegC, unsigned Dist) {
575  MachineInstr *MI = mi;
576  DEBUG(errs() << "2addr: COMMUTING  : " << *MI);
577  MachineInstr *NewMI = TII->commuteInstruction(MI);
578
579  if (NewMI == 0) {
580    DEBUG(errs() << "2addr: COMMUTING FAILED!\n");
581    return false;
582  }
583
584  DEBUG(errs() << "2addr: COMMUTED TO: " << *NewMI);
585  // If the instruction changed to commute it, update livevar.
586  if (NewMI != MI) {
587    if (LV)
588      // Update live variables
589      LV->replaceKillInstruction(RegC, MI, NewMI);
590
591    mbbi->insert(mi, NewMI);           // Insert the new inst
592    mbbi->erase(mi);                   // Nuke the old inst.
593    mi = NewMI;
594    DistanceMap.insert(std::make_pair(NewMI, Dist));
595  }
596
597  // Update source register map.
598  unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
599  if (FromRegC) {
600    unsigned RegA = MI->getOperand(0).getReg();
601    SrcRegMap[RegA] = FromRegC;
602  }
603
604  return true;
605}
606
607/// isProfitableToConv3Addr - Return true if it is profitable to convert the
608/// given 2-address instruction to a 3-address one.
609bool
610TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
611  // Look for situations like this:
612  // %reg1024<def> = MOV r1
613  // %reg1025<def> = MOV r0
614  // %reg1026<def> = ADD %reg1024, %reg1025
615  // r2            = MOV %reg1026
616  // Turn ADD into a 3-address instruction to avoid a copy.
617  unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
618  unsigned ToRegA = getMappedReg(RegA, DstRegMap);
619  return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
620}
621
622/// ConvertInstTo3Addr - Convert the specified two-address instruction into a
623/// three address one. Return true if this transformation was successful.
624bool
625TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
626                                              MachineBasicBlock::iterator &nmi,
627                                              MachineFunction::iterator &mbbi,
628                                              unsigned RegB, unsigned Dist) {
629  MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
630  if (NewMI) {
631    DEBUG(errs() << "2addr: CONVERTING 2-ADDR: " << *mi);
632    DEBUG(errs() << "2addr:         TO 3-ADDR: " << *NewMI);
633    bool Sunk = false;
634
635    if (NewMI->findRegisterUseOperand(RegB, false, TRI))
636      // FIXME: Temporary workaround. If the new instruction doesn't
637      // uses RegB, convertToThreeAddress must have created more
638      // then one instruction.
639      Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
640
641    mbbi->erase(mi); // Nuke the old inst.
642
643    if (!Sunk) {
644      DistanceMap.insert(std::make_pair(NewMI, Dist));
645      mi = NewMI;
646      nmi = llvm::next(mi);
647    }
648    return true;
649  }
650
651  return false;
652}
653
654/// ProcessCopy - If the specified instruction is not yet processed, process it
655/// if it's a copy. For a copy instruction, we find the physical registers the
656/// source and destination registers might be mapped to. These are kept in
657/// point-to maps used to determine future optimizations. e.g.
658/// v1024 = mov r0
659/// v1025 = mov r1
660/// v1026 = add v1024, v1025
661/// r1    = mov r1026
662/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
663/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
664/// potentially joined with r1 on the output side. It's worthwhile to commute
665/// 'add' to eliminate a copy.
666void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
667                                     MachineBasicBlock *MBB,
668                                     SmallPtrSet<MachineInstr*, 8> &Processed) {
669  if (Processed.count(MI))
670    return;
671
672  bool IsSrcPhys, IsDstPhys;
673  unsigned SrcReg, DstReg;
674  if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
675    return;
676
677  if (IsDstPhys && !IsSrcPhys)
678    DstRegMap.insert(std::make_pair(SrcReg, DstReg));
679  else if (!IsDstPhys && IsSrcPhys) {
680    bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
681    if (!isNew)
682      assert(SrcRegMap[DstReg] == SrcReg &&
683             "Can't map to two src physical registers!");
684
685    SmallVector<unsigned, 4> VirtRegPairs;
686    bool IsCopy = false;
687    unsigned NewReg = 0;
688    while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
689                                                   IsCopy, NewReg, IsDstPhys)) {
690      if (IsCopy) {
691        if (!Processed.insert(UseMI))
692          break;
693      }
694
695      DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
696      if (DI != DistanceMap.end())
697        // Earlier in the same MBB.Reached via a back edge.
698        break;
699
700      if (IsDstPhys) {
701        VirtRegPairs.push_back(NewReg);
702        break;
703      }
704      bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
705      if (!isNew)
706        assert(SrcRegMap[NewReg] == DstReg &&
707               "Can't map to two src physical registers!");
708      VirtRegPairs.push_back(NewReg);
709      DstReg = NewReg;
710    }
711
712    if (!VirtRegPairs.empty()) {
713      unsigned ToReg = VirtRegPairs.back();
714      VirtRegPairs.pop_back();
715      while (!VirtRegPairs.empty()) {
716        unsigned FromReg = VirtRegPairs.back();
717        VirtRegPairs.pop_back();
718        bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
719        if (!isNew)
720          assert(DstRegMap[FromReg] == ToReg &&
721                 "Can't map to two dst physical registers!");
722        ToReg = FromReg;
723      }
724    }
725  }
726
727  Processed.insert(MI);
728}
729
730/// isSafeToDelete - If the specified instruction does not produce any side
731/// effects and all of its defs are dead, then it's safe to delete.
732static bool isSafeToDelete(MachineInstr *MI,
733                           const TargetInstrInfo *TII,
734                           SmallVector<unsigned, 4> &Kills) {
735  const TargetInstrDesc &TID = MI->getDesc();
736  if (TID.mayStore() || TID.isCall())
737    return false;
738  if (TID.isTerminator() || TID.hasUnmodeledSideEffects())
739    return false;
740
741  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
742    MachineOperand &MO = MI->getOperand(i);
743    if (!MO.isReg())
744      continue;
745    if (MO.isDef() && !MO.isDead())
746      return false;
747    if (MO.isUse() && MO.isKill())
748      Kills.push_back(MO.getReg());
749  }
750  return true;
751}
752
753/// canUpdateDeletedKills - Check if all the registers listed in Kills are
754/// killed by instructions in MBB preceding the current instruction at
755/// position Dist.  If so, return true and record information about the
756/// preceding kills in NewKills.
757bool TwoAddressInstructionPass::
758canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
759                      SmallVector<NewKill, 4> &NewKills,
760                      MachineBasicBlock *MBB, unsigned Dist) {
761  while (!Kills.empty()) {
762    unsigned Kill = Kills.back();
763    Kills.pop_back();
764    if (TargetRegisterInfo::isPhysicalRegister(Kill))
765      return false;
766
767    MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
768    if (!LastKill)
769      return false;
770
771    bool isModRef = LastKill->modifiesRegister(Kill);
772    NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
773                                      LastKill));
774  }
775  return true;
776}
777
778/// DeleteUnusedInstr - If an instruction with a tied register operand can
779/// be safely deleted, just delete it.
780bool
781TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
782                                             MachineBasicBlock::iterator &nmi,
783                                             MachineFunction::iterator &mbbi,
784                                             unsigned Dist) {
785  // Check if the instruction has no side effects and if all its defs are dead.
786  SmallVector<unsigned, 4> Kills;
787  if (!isSafeToDelete(mi, TII, Kills))
788    return false;
789
790  // If this instruction kills some virtual registers, we need to
791  // update the kill information. If it's not possible to do so,
792  // then bail out.
793  SmallVector<NewKill, 4> NewKills;
794  if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
795    return false;
796
797  if (LV) {
798    while (!NewKills.empty()) {
799      MachineInstr *NewKill = NewKills.back().second;
800      unsigned Kill = NewKills.back().first.first;
801      bool isDead = NewKills.back().first.second;
802      NewKills.pop_back();
803      if (LV->removeVirtualRegisterKilled(Kill, mi)) {
804        if (isDead)
805          LV->addVirtualRegisterDead(Kill, NewKill);
806        else
807          LV->addVirtualRegisterKilled(Kill, NewKill);
808      }
809    }
810  }
811
812  mbbi->erase(mi); // Nuke the old inst.
813  mi = nmi;
814  return true;
815}
816
817/// TryInstructionTransform - For the case where an instruction has a single
818/// pair of tied register operands, attempt some transformations that may
819/// either eliminate the tied operands or improve the opportunities for
820/// coalescing away the register copy.  Returns true if the tied operands
821/// are eliminated altogether.
822bool TwoAddressInstructionPass::
823TryInstructionTransform(MachineBasicBlock::iterator &mi,
824                        MachineBasicBlock::iterator &nmi,
825                        MachineFunction::iterator &mbbi,
826                        unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
827  const TargetInstrDesc &TID = mi->getDesc();
828  unsigned regA = mi->getOperand(DstIdx).getReg();
829  unsigned regB = mi->getOperand(SrcIdx).getReg();
830
831  assert(TargetRegisterInfo::isVirtualRegister(regB) &&
832         "cannot make instruction into two-address form");
833
834  // If regA is dead and the instruction can be deleted, just delete
835  // it so it doesn't clobber regB.
836  bool regBKilled = isKilled(*mi, regB, MRI, TII);
837  if (!regBKilled && mi->getOperand(DstIdx).isDead() &&
838      DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
839    ++NumDeletes;
840    return true; // Done with this instruction.
841  }
842
843  // Check if it is profitable to commute the operands.
844  unsigned SrcOp1, SrcOp2;
845  unsigned regC = 0;
846  unsigned regCIdx = ~0U;
847  bool TryCommute = false;
848  bool AggressiveCommute = false;
849  if (TID.isCommutable() && mi->getNumOperands() >= 3 &&
850      TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) {
851    if (SrcIdx == SrcOp1)
852      regCIdx = SrcOp2;
853    else if (SrcIdx == SrcOp2)
854      regCIdx = SrcOp1;
855
856    if (regCIdx != ~0U) {
857      regC = mi->getOperand(regCIdx).getReg();
858      if (!regBKilled && isKilled(*mi, regC, MRI, TII))
859        // If C dies but B does not, swap the B and C operands.
860        // This makes the live ranges of A and C joinable.
861        TryCommute = true;
862      else if (isProfitableToCommute(regB, regC, mi, mbbi, Dist)) {
863        TryCommute = true;
864        AggressiveCommute = true;
865      }
866    }
867  }
868
869  // If it's profitable to commute, try to do so.
870  if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
871    ++NumCommuted;
872    if (AggressiveCommute)
873      ++NumAggrCommuted;
874    return false;
875  }
876
877  if (TID.isConvertibleTo3Addr()) {
878    // This instruction is potentially convertible to a true
879    // three-address instruction.  Check if it is profitable.
880    if (!regBKilled || isProfitableToConv3Addr(regA)) {
881      // Try to convert it.
882      if (ConvertInstTo3Addr(mi, nmi, mbbi, regB, Dist)) {
883        ++NumConvertedTo3Addr;
884        return true; // Done with this instruction.
885      }
886    }
887  }
888  return false;
889}
890
891/// runOnMachineFunction - Reduce two-address instructions to two operands.
892///
893bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
894  DEBUG(errs() << "Machine Function\n");
895  const TargetMachine &TM = MF.getTarget();
896  MRI = &MF.getRegInfo();
897  TII = TM.getInstrInfo();
898  TRI = TM.getRegisterInfo();
899  LV = getAnalysisIfAvailable<LiveVariables>();
900  AA = &getAnalysis<AliasAnalysis>();
901
902  bool MadeChange = false;
903
904  DEBUG(errs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
905  DEBUG(errs() << "********** Function: "
906        << MF.getFunction()->getName() << '\n');
907
908  // ReMatRegs - Keep track of the registers whose def's are remat'ed.
909  BitVector ReMatRegs;
910  ReMatRegs.resize(MRI->getLastVirtReg()+1);
911
912  typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
913    TiedOperandMap;
914  TiedOperandMap TiedOperands(4);
915
916  SmallPtrSet<MachineInstr*, 8> Processed;
917  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
918       mbbi != mbbe; ++mbbi) {
919    unsigned Dist = 0;
920    DistanceMap.clear();
921    SrcRegMap.clear();
922    DstRegMap.clear();
923    Processed.clear();
924    for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
925         mi != me; ) {
926      MachineBasicBlock::iterator nmi = llvm::next(mi);
927      const TargetInstrDesc &TID = mi->getDesc();
928      bool FirstTied = true;
929
930      DistanceMap.insert(std::make_pair(mi, ++Dist));
931
932      ProcessCopy(&*mi, &*mbbi, Processed);
933
934      // First scan through all the tied register uses in this instruction
935      // and record a list of pairs of tied operands for each register.
936      unsigned NumOps = (mi->getOpcode() == TargetInstrInfo::INLINEASM)
937        ? mi->getNumOperands() : TID.getNumOperands();
938      for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
939        unsigned DstIdx = 0;
940        if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
941          continue;
942
943        if (FirstTied) {
944          FirstTied = false;
945          ++NumTwoAddressInstrs;
946          DEBUG(errs() << '\t' << *mi);
947        }
948
949        assert(mi->getOperand(SrcIdx).isReg() &&
950               mi->getOperand(SrcIdx).getReg() &&
951               mi->getOperand(SrcIdx).isUse() &&
952               "two address instruction invalid");
953
954        unsigned regB = mi->getOperand(SrcIdx).getReg();
955        TiedOperandMap::iterator OI = TiedOperands.find(regB);
956        if (OI == TiedOperands.end()) {
957          SmallVector<std::pair<unsigned, unsigned>, 4> TiedPair;
958          OI = TiedOperands.insert(std::make_pair(regB, TiedPair)).first;
959        }
960        OI->second.push_back(std::make_pair(SrcIdx, DstIdx));
961      }
962
963      // Now iterate over the information collected above.
964      for (TiedOperandMap::iterator OI = TiedOperands.begin(),
965             OE = TiedOperands.end(); OI != OE; ++OI) {
966        SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
967
968        // If the instruction has a single pair of tied operands, try some
969        // transformations that may either eliminate the tied operands or
970        // improve the opportunities for coalescing away the register copy.
971        if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
972          unsigned SrcIdx = TiedPairs[0].first;
973          unsigned DstIdx = TiedPairs[0].second;
974
975          // If the registers are already equal, nothing needs to be done.
976          if (mi->getOperand(SrcIdx).getReg() ==
977              mi->getOperand(DstIdx).getReg())
978            break; // Done with this instruction.
979
980          if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
981            break; // The tied operands have been eliminated.
982        }
983
984        bool RemovedKillFlag = false;
985        bool AllUsesCopied = true;
986        unsigned LastCopiedReg = 0;
987        unsigned regB = OI->first;
988        for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
989          unsigned SrcIdx = TiedPairs[tpi].first;
990          unsigned DstIdx = TiedPairs[tpi].second;
991          unsigned regA = mi->getOperand(DstIdx).getReg();
992          // Grab regB from the instruction because it may have changed if the
993          // instruction was commuted.
994          regB = mi->getOperand(SrcIdx).getReg();
995
996          if (regA == regB) {
997            // The register is tied to multiple destinations (or else we would
998            // not have continued this far), but this use of the register
999            // already matches the tied destination.  Leave it.
1000            AllUsesCopied = false;
1001            continue;
1002          }
1003          LastCopiedReg = regA;
1004
1005          assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1006                 "cannot make instruction into two-address form");
1007
1008#ifndef NDEBUG
1009          // First, verify that we don't have a use of "a" in the instruction
1010          // (a = b + a for example) because our transformation will not
1011          // work. This should never occur because we are in SSA form.
1012          for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1013            assert(i == DstIdx ||
1014                   !mi->getOperand(i).isReg() ||
1015                   mi->getOperand(i).getReg() != regA);
1016#endif
1017
1018          // Emit a copy or rematerialize the definition.
1019          const TargetRegisterClass *rc = MRI->getRegClass(regB);
1020          MachineInstr *DefMI = MRI->getVRegDef(regB);
1021          // If it's safe and profitable, remat the definition instead of
1022          // copying it.
1023          if (DefMI &&
1024              DefMI->getDesc().isAsCheapAsAMove() &&
1025              DefMI->isSafeToReMat(TII, regB, AA) &&
1026              isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1027            DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
1028            unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1029            TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI);
1030            ReMatRegs.set(regB);
1031            ++NumReMats;
1032          } else {
1033            bool Emitted = TII->copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
1034            (void)Emitted;
1035            assert(Emitted && "Unable to issue a copy instruction!\n");
1036          }
1037
1038          MachineBasicBlock::iterator prevMI = prior(mi);
1039          // Update DistanceMap.
1040          DistanceMap.insert(std::make_pair(prevMI, Dist));
1041          DistanceMap[mi] = ++Dist;
1042
1043          DEBUG(errs() << "\t\tprepend:\t" << *prevMI);
1044
1045          MachineOperand &MO = mi->getOperand(SrcIdx);
1046          assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1047                 "inconsistent operand info for 2-reg pass");
1048          if (MO.isKill()) {
1049            MO.setIsKill(false);
1050            RemovedKillFlag = true;
1051          }
1052          MO.setReg(regA);
1053        }
1054
1055        if (AllUsesCopied) {
1056          // Replace other (un-tied) uses of regB with LastCopiedReg.
1057          for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1058            MachineOperand &MO = mi->getOperand(i);
1059            if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1060              if (MO.isKill()) {
1061                MO.setIsKill(false);
1062                RemovedKillFlag = true;
1063              }
1064              MO.setReg(LastCopiedReg);
1065            }
1066          }
1067
1068          // Update live variables for regB.
1069          if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1070            LV->addVirtualRegisterKilled(regB, prior(mi));
1071
1072        } else if (RemovedKillFlag) {
1073          // Some tied uses of regB matched their destination registers, so
1074          // regB is still used in this instruction, but a kill flag was
1075          // removed from a different tied use of regB, so now we need to add
1076          // a kill flag to one of the remaining uses of regB.
1077          for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1078            MachineOperand &MO = mi->getOperand(i);
1079            if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1080              MO.setIsKill(true);
1081              break;
1082            }
1083          }
1084        }
1085
1086        MadeChange = true;
1087
1088        DEBUG(errs() << "\t\trewrite to:\t" << *mi);
1089      }
1090
1091      // Clear TiedOperands here instead of at the top of the loop
1092      // since most instructions do not have tied operands.
1093      TiedOperands.clear();
1094      mi = nmi;
1095    }
1096  }
1097
1098  // Some remat'ed instructions are dead.
1099  int VReg = ReMatRegs.find_first();
1100  while (VReg != -1) {
1101    if (MRI->use_empty(VReg)) {
1102      MachineInstr *DefMI = MRI->getVRegDef(VReg);
1103      DefMI->eraseFromParent();
1104    }
1105    VReg = ReMatRegs.find_next(VReg);
1106  }
1107
1108  return MadeChange;
1109}
1110