TwoAddressInstructionPass.cpp revision be766c72464116a445a02b542a450c4274bab5d0 
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TwoAddress instruction pass which is used
11// by most register allocators. Two-Address instructions are rewritten
12// from:
13//
14//     A = B op C
15//
16// to:
17//
18//     A = B
19//     A op= C
20//
21// Note that if a register allocator chooses to use this pass, that it
22// has to be capable of handling the non-SSA nature of these rewritten
23// virtual registers.
24//
25// It is also worth noting that the duplicate operand of the two
26// address instruction is removed.
27//
28//===----------------------------------------------------------------------===//
29
30#define DEBUG_TYPE "twoaddrinstr"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/CodeGen/LiveVariables.h"
33#include "llvm/CodeGen/MachineFunctionPass.h"
34#include "llvm/CodeGen/MachineInstr.h"
35#include "llvm/CodeGen/SSARegMap.h"
36#include "llvm/Target/MRegisterInfo.h"
37#include "llvm/Target/TargetInstrInfo.h"
38#include "llvm/Target/TargetMachine.h"
39#include "Support/Debug.h"
40#include "Support/Statistic.h"
41#include <iostream>
42using namespace llvm;
43
44namespace {
45    Statistic<> numTwoAddressInstrs("twoaddressinstruction",
46                                    "Number of two-address instructions");
47    Statistic<> numInstrsAdded("twoaddressinstruction",
48                               "Number of instructions added");
49
50    struct TwoAddressInstructionPass : public MachineFunctionPass
51    {
52        virtual void getAnalysisUsage(AnalysisUsage &AU) const;
53
54        /// runOnMachineFunction - pass entry point
55        bool runOnMachineFunction(MachineFunction&);
56    };
57
58    RegisterPass<TwoAddressInstructionPass> X(
59        "twoaddressinstruction", "Two-Address instruction pass");
60};
61
62const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
63
64void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const
65{
66    AU.addPreserved<LiveVariables>();
67    AU.addRequired<LiveVariables>();
68    AU.addPreservedID(PHIEliminationID);
69    AU.addRequiredID(PHIEliminationID);
70    MachineFunctionPass::getAnalysisUsage(AU);
71}
72
73/// runOnMachineFunction - Reduce two-address instructions to two
74/// operands.
75///
76bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
77    DEBUG(std::cerr << "Machine Function\n");
78    const TargetMachine &TM = MF.getTarget();
79    const MRegisterInfo &MRI = *TM.getRegisterInfo();
80    const TargetInstrInfo &TII = TM.getInstrInfo();
81    LiveVariables &LV = getAnalysis<LiveVariables>();
82
83    bool MadeChange = false;
84
85    for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
86         mbbi != mbbe; ++mbbi) {
87        for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
88             mi != me; ++mi) {
89            unsigned opcode = mi->getOpcode();
90
91            // ignore if it is not a two-address instruction
92            if (!TII.isTwoAddrInstr(opcode))
93                continue;
94
95            ++numTwoAddressInstrs;
96
97            DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
98
99            assert(mi->getOperand(1).isRegister() &&
100                   mi->getOperand(1).getReg() &&
101                   mi->getOperand(1).isUse() &&
102                   "two address instruction invalid");
103
104            // if the two operands are the same we just remove the use
105            // and mark the def as def&use
106            if (mi->getOperand(0).getReg() ==
107                mi->getOperand(1).getReg()) {
108            }
109            else {
110                MadeChange = true;
111
112                // rewrite:
113                //     a = b op c
114                // to:
115                //     a = b
116                //     a = a op c
117                unsigned regA = mi->getOperand(0).getReg();
118                unsigned regB = mi->getOperand(1).getReg();
119
120                assert(MRegisterInfo::isVirtualRegister(regA) &&
121                       MRegisterInfo::isVirtualRegister(regB) &&
122                       "cannot update physical register live information");
123
124                // first make sure we do not have a use of a in the
125                // instruction (a = b + a for example) because our
126                // transformation will not work. This should never occur
127                // because we are in SSA form.
128                for (unsigned i = 1; i != mi->getNumOperands(); ++i)
129                    assert(!mi->getOperand(i).isRegister() ||
130                           mi->getOperand(i).getReg() != regA);
131
132                const TargetRegisterClass* rc =
133                    MF.getSSARegMap()->getRegClass(regA);
134                unsigned Added = MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
135                numInstrsAdded += Added;
136
137                MachineBasicBlock::iterator prevMi = mi;
138                --prevMi;
139                DEBUG(std::cerr << "\t\tadded instruction: ";
140                      prevMi->print(std::cerr, TM));
141
142                // update live variables for regA
143                assert(Added == 1 &&
144                       "Cannot handle multi-instruction copies yet!");
145                LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
146                varInfo.DefInst = prevMi;
147
148                // update live variables for regB
149                if (LV.removeVirtualRegisterKilled(regB, &*mbbi, mi))
150                    LV.addVirtualRegisterKilled(regB, &*mbbi, prevMi);
151
152                if (LV.removeVirtualRegisterDead(regB, &*mbbi, mi))
153                    LV.addVirtualRegisterDead(regB, &*mbbi, prevMi);
154
155                // replace all occurences of regB with regA
156                for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
157                    if (mi->getOperand(i).isRegister() &&
158                        mi->getOperand(i).getReg() == regB)
159                        mi->SetMachineOperandReg(i, regA);
160                }
161            }
162
163            assert(mi->getOperand(0).isDef());
164            mi->getOperand(0).setUse();
165            mi->RemoveOperand(1);
166
167            DEBUG(std::cerr << "\t\tmodified original to: ";
168                  mi->print(std::cerr, TM));
169        }
170    }
171
172    return MadeChange;
173}
174