TwoAddressInstructionPass.cpp revision d74ea2bbd8bb630331f35ead42d385249bd42af8 
1//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TwoAddress instruction pass which is used
11// by most register allocators. Two-Address instructions are rewritten
12// from:
13//
14//     A = B op C
15//
16// to:
17//
18//     A = B
19//     A op= C
20//
21// Note that if a register allocator chooses to use this pass, that it
22// has to be capable of handling the non-SSA nature of these rewritten
23// virtual registers.
24//
25// It is also worth noting that the duplicate operand of the two
26// address instruction is removed.
27//
28//===----------------------------------------------------------------------===//
29
30#define DEBUG_TYPE "twoaddrinstr"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/Function.h"
33#include "llvm/CodeGen/LiveVariables.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/SSARegMap.h"
37#include "llvm/Target/MRegisterInfo.h"
38#include "llvm/Target/TargetInstrInfo.h"
39#include "llvm/Target/TargetMachine.h"
40#include "llvm/Support/Debug.h"
41#include "llvm/ADT/Statistic.h"
42#include "llvm/ADT/STLExtras.h"
43#include <iostream>
44using namespace llvm;
45
46namespace {
47  Statistic<> NumTwoAddressInstrs("twoaddressinstruction",
48                                  "Number of two-address instructions");
49  Statistic<> NumCommuted("twoaddressinstruction",
50                          "Number of instructions commuted to coalesce");
51  Statistic<> NumConvertedTo3Addr("twoaddressinstruction",
52                                "Number of instructions promoted to 3-address");
53
54  struct TwoAddressInstructionPass : public MachineFunctionPass {
55    virtual void getAnalysisUsage(AnalysisUsage &AU) const;
56
57    /// runOnMachineFunction - pass entry point
58    bool runOnMachineFunction(MachineFunction&);
59  };
60
61  RegisterPass<TwoAddressInstructionPass>
62  X("twoaddressinstruction", "Two-Address instruction pass");
63}
64
65const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
66
67void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
68  AU.addRequired<LiveVariables>();
69  AU.addPreserved<LiveVariables>();
70  AU.addPreservedID(PHIEliminationID);
71  MachineFunctionPass::getAnalysisUsage(AU);
72}
73
74/// runOnMachineFunction - Reduce two-address instructions to two
75/// operands.
76///
77bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
78  DEBUG(std::cerr << "Machine Function\n");
79  const TargetMachine &TM = MF.getTarget();
80  const MRegisterInfo &MRI = *TM.getRegisterInfo();
81  const TargetInstrInfo &TII = *TM.getInstrInfo();
82  LiveVariables &LV = getAnalysis<LiveVariables>();
83
84  bool MadeChange = false;
85
86  DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
87  DEBUG(std::cerr << "********** Function: "
88                  << MF.getFunction()->getName() << '\n');
89
90  for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
91       mbbi != mbbe; ++mbbi) {
92    for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
93         mi != me; ++mi) {
94      unsigned opcode = mi->getOpcode();
95
96      // ignore if it is not a two-address instruction
97      if (!TII.isTwoAddrInstr(opcode))
98        continue;
99
100      ++NumTwoAddressInstrs;
101      DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
102      assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
103             mi->getOperand(1).isUse() && "two address instruction invalid");
104
105      // if the two operands are the same we just remove the use
106      // and mark the def as def&use, otherwise we have to insert a copy.
107      if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
108        // rewrite:
109        //     a = b op c
110        // to:
111        //     a = b
112        //     a = a op c
113        unsigned regA = mi->getOperand(0).getReg();
114        unsigned regB = mi->getOperand(1).getReg();
115
116        assert(MRegisterInfo::isVirtualRegister(regA) &&
117               MRegisterInfo::isVirtualRegister(regB) &&
118               "cannot update physical register live information");
119
120#ifndef NDEBUG
121        // First, verify that we do not have a use of a in the instruction (a =
122        // b + a for example) because our transformation will not work. This
123        // should never occur because we are in SSA form.
124        for (unsigned i = 1; i != mi->getNumOperands(); ++i)
125          assert(!mi->getOperand(i).isRegister() ||
126                 mi->getOperand(i).getReg() != regA);
127#endif
128
129        // If this instruction is not the killing user of B, see if we can
130        // rearrange the code to make it so.  Making it the killing user will
131        // allow us to coalesce A and B together, eliminating the copy we are
132        // about to insert.
133        if (!LV.KillsRegister(mi, regB)) {
134          const TargetInstrDescriptor &TID = TII.get(opcode);
135
136          // If this instruction is commutative, check to see if C dies.  If so,
137          // swap the B and C operands.  This makes the live ranges of A and C
138          // joinable.
139          if (TID.Flags & M_COMMUTABLE) {
140            assert(mi->getOperand(2).isRegister() &&
141                   "Not a proper commutative instruction!");
142            unsigned regC = mi->getOperand(2).getReg();
143            if (LV.KillsRegister(mi, regC)) {
144              DEBUG(std::cerr << "2addr: COMMUTING  : " << *mi);
145              MachineInstr *NewMI = TII.commuteInstruction(mi);
146              if (NewMI == 0) {
147                DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
148              } else {
149                DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
150                // If the instruction changed to commute it, update livevar.
151                if (NewMI != mi) {
152                  LV.instructionChanged(mi, NewMI);  // Update live variables
153                  mbbi->insert(mi, NewMI);           // Insert the new inst
154                  mbbi->erase(mi);                   // Nuke the old inst.
155                  mi = NewMI;
156                }
157
158                ++NumCommuted;
159                regB = regC;
160                goto InstructionRearranged;
161              }
162            }
163          }
164          // If this instruction is potentially convertible to a true
165          // three-address instruction,
166          if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
167            if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
168              DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
169              DEBUG(std::cerr << "2addr:         TO 3-ADDR: " << *New);
170              LV.instructionChanged(mi, New);  // Update live variables
171              mbbi->insert(mi, New);           // Insert the new inst
172              mbbi->erase(mi);                 // Nuke the old inst.
173              mi = New;
174              ++NumConvertedTo3Addr;
175              assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
176                     "convertToThreeAddress returned a 2-addr instruction??");
177              // Done with this instruction.
178              continue;
179            }
180        }
181      InstructionRearranged:
182        const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
183        MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
184
185        MachineBasicBlock::iterator prevMi = prior(mi);
186        DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
187
188        // Update live variables for regA
189        LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
190        varInfo.DefInst = prevMi;
191
192        // update live variables for regB
193        if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
194          LV.addVirtualRegisterKilled(regB, prevMi);
195
196        if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
197          LV.addVirtualRegisterDead(regB, prevMi);
198
199        // replace all occurences of regB with regA
200        for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
201          if (mi->getOperand(i).isRegister() &&
202              mi->getOperand(i).getReg() == regB)
203            mi->getOperand(i).setReg(regA);
204        }
205      }
206
207      assert(mi->getOperand(0).isDef());
208      mi->getOperand(0).setUse();
209      mi->RemoveOperand(1);
210      MadeChange = true;
211
212      DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
213    }
214  }
215
216  return MadeChange;
217}
218