1//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the ARM implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMFrameLowering.h" 15#include "ARMBaseInstrInfo.h" 16#include "ARMBaseRegisterInfo.h" 17#include "ARMMachineFunctionInfo.h" 18#include "MCTargetDesc/ARMAddressingModes.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/RegisterScavenging.h" 24#include "llvm/Target/TargetOptions.h" 25 26using namespace llvm; 27 28/// hasFP - Return true if the specified function should have a dedicated frame 29/// pointer register. This is true if the function has variable sized allocas 30/// or if frame pointer elimination is disabled. 31bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { 32 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 33 34 // Mac OS X requires FP not to be clobbered for backtracing purpose. 35 if (STI.isTargetDarwin()) 36 return true; 37 38 const MachineFrameInfo *MFI = MF.getFrameInfo(); 39 // Always eliminate non-leaf frame pointers. 40 return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || 41 RegInfo->needsStackRealignment(MF) || 42 MFI->hasVarSizedObjects() || 43 MFI->isFrameAddressTaken()); 44} 45 46/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is 47/// not required, we reserve argument space for call sites in the function 48/// immediately on entry to the current function. This eliminates the need for 49/// add/sub sp brackets around call sites. Returns true if the call frame is 50/// included as part of the stack frame. 51bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 52 const MachineFrameInfo *FFI = MF.getFrameInfo(); 53 unsigned CFSize = FFI->getMaxCallFrameSize(); 54 // It's not always a good idea to include the call frame as part of the 55 // stack frame. ARM (especially Thumb) has small immediate offset to 56 // address the stack frame. So a large call frame can cause poor codegen 57 // and may even makes it impossible to scavenge a register. 58 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 59 return false; 60 61 return !MF.getFrameInfo()->hasVarSizedObjects(); 62} 63 64/// canSimplifyCallFramePseudos - If there is a reserved call frame, the 65/// call frame pseudos can be simplified. Unlike most targets, having a FP 66/// is not sufficient here since we still may reference some objects via SP 67/// even when FP is available in Thumb2 mode. 68bool 69ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { 70 return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); 71} 72 73static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { 74 for (unsigned i = 0; CSRegs[i]; ++i) 75 if (Reg == CSRegs[i]) 76 return true; 77 return false; 78} 79 80static bool isCSRestore(MachineInstr *MI, 81 const ARMBaseInstrInfo &TII, 82 const unsigned *CSRegs) { 83 // Integer spill area is handled with "pop". 84 if (MI->getOpcode() == ARM::LDMIA_RET || 85 MI->getOpcode() == ARM::t2LDMIA_RET || 86 MI->getOpcode() == ARM::LDMIA_UPD || 87 MI->getOpcode() == ARM::t2LDMIA_UPD || 88 MI->getOpcode() == ARM::VLDMDIA_UPD) { 89 // The first two operands are predicates. The last two are 90 // imp-def and imp-use of SP. Check everything in between. 91 for (int i = 5, e = MI->getNumOperands(); i != e; ++i) 92 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) 93 return false; 94 return true; 95 } 96 if ((MI->getOpcode() == ARM::LDR_POST_IMM || 97 MI->getOpcode() == ARM::LDR_POST_REG || 98 MI->getOpcode() == ARM::t2LDR_POST) && 99 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && 100 MI->getOperand(1).getReg() == ARM::SP) 101 return true; 102 103 return false; 104} 105 106static void 107emitSPUpdate(bool isARM, 108 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 109 DebugLoc dl, const ARMBaseInstrInfo &TII, 110 int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) { 111 if (isARM) 112 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 113 ARMCC::AL, 0, TII, MIFlags); 114 else 115 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 116 ARMCC::AL, 0, TII, MIFlags); 117} 118 119void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { 120 MachineBasicBlock &MBB = MF.front(); 121 MachineBasicBlock::iterator MBBI = MBB.begin(); 122 MachineFrameInfo *MFI = MF.getFrameInfo(); 123 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 124 const ARMBaseRegisterInfo *RegInfo = 125 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 126 const ARMBaseInstrInfo &TII = 127 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 128 assert(!AFI->isThumb1OnlyFunction() && 129 "This emitPrologue does not support Thumb1!"); 130 bool isARM = !AFI->isThumbFunction(); 131 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 132 unsigned NumBytes = MFI->getStackSize(); 133 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 134 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 135 unsigned FramePtr = RegInfo->getFrameRegister(MF); 136 137 // Determine the sizes of each callee-save spill areas and record which frame 138 // belongs to which callee-save spill areas. 139 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; 140 int FramePtrSpillFI = 0; 141 142 // Allocate the vararg register save area. This is not counted in NumBytes. 143 if (VARegSaveSize) 144 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize, 145 MachineInstr::FrameSetup); 146 147 if (!AFI->hasStackFrame()) { 148 if (NumBytes != 0) 149 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 150 MachineInstr::FrameSetup); 151 return; 152 } 153 154 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 155 unsigned Reg = CSI[i].getReg(); 156 int FI = CSI[i].getFrameIdx(); 157 switch (Reg) { 158 case ARM::R4: 159 case ARM::R5: 160 case ARM::R6: 161 case ARM::R7: 162 case ARM::LR: 163 if (Reg == FramePtr) 164 FramePtrSpillFI = FI; 165 AFI->addGPRCalleeSavedArea1Frame(FI); 166 GPRCS1Size += 4; 167 break; 168 case ARM::R8: 169 case ARM::R9: 170 case ARM::R10: 171 case ARM::R11: 172 if (Reg == FramePtr) 173 FramePtrSpillFI = FI; 174 if (STI.isTargetDarwin()) { 175 AFI->addGPRCalleeSavedArea2Frame(FI); 176 GPRCS2Size += 4; 177 } else { 178 AFI->addGPRCalleeSavedArea1Frame(FI); 179 GPRCS1Size += 4; 180 } 181 break; 182 default: 183 AFI->addDPRCalleeSavedAreaFrame(FI); 184 DPRCSSize += 8; 185 } 186 } 187 188 // Move past area 1. 189 if (GPRCS1Size > 0) MBBI++; 190 191 // Set FP to point to the stack slot that contains the previous FP. 192 // For Darwin, FP is R7, which has now been stored in spill area 1. 193 // Otherwise, if this is not Darwin, all the callee-saved registers go 194 // into spill area 1, including the FP in R11. In either case, it is 195 // now safe to emit this assignment. 196 bool HasFP = hasFP(MF); 197 if (HasFP) { 198 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; 199 MachineInstrBuilder MIB = 200 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) 201 .addFrameIndex(FramePtrSpillFI).addImm(0) 202 .setMIFlag(MachineInstr::FrameSetup); 203 AddDefaultCC(AddDefaultPred(MIB)); 204 } 205 206 // Move past area 2. 207 if (GPRCS2Size > 0) MBBI++; 208 209 // Determine starting offsets of spill areas. 210 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); 211 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; 212 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; 213 if (HasFP) 214 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + 215 NumBytes); 216 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); 217 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); 218 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); 219 220 // Move past area 3. 221 if (DPRCSSize > 0) { 222 MBBI++; 223 // Since vpush register list cannot have gaps, there may be multiple vpush 224 // instructions in the prologue. 225 while (MBBI->getOpcode() == ARM::VSTMDDB_UPD) 226 MBBI++; 227 } 228 229 NumBytes = DPRCSOffset; 230 if (NumBytes) { 231 // Adjust SP after all the callee-save spills. 232 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes, 233 MachineInstr::FrameSetup); 234 if (HasFP && isARM) 235 // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 236 // Note it's not safe to do this in Thumb2 mode because it would have 237 // taken two instructions: 238 // mov sp, r7 239 // sub sp, #24 240 // If an interrupt is taken between the two instructions, then sp is in 241 // an inconsistent state (pointing to the middle of callee-saved area). 242 // The interrupt handler can end up clobbering the registers. 243 AFI->setShouldRestoreSPFromFP(true); 244 } 245 246 if (STI.isTargetELF() && hasFP(MF)) 247 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - 248 AFI->getFramePtrSpillOffset()); 249 250 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); 251 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); 252 AFI->setDPRCalleeSavedAreaSize(DPRCSSize); 253 254 // If we need dynamic stack realignment, do it here. Be paranoid and make 255 // sure if we also have VLAs, we have a base pointer for frame access. 256 if (RegInfo->needsStackRealignment(MF)) { 257 unsigned MaxAlign = MFI->getMaxAlignment(); 258 assert (!AFI->isThumb1OnlyFunction()); 259 if (!AFI->isThumbFunction()) { 260 // Emit bic sp, sp, MaxAlign 261 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 262 TII.get(ARM::BICri), ARM::SP) 263 .addReg(ARM::SP, RegState::Kill) 264 .addImm(MaxAlign-1))); 265 } else { 266 // We cannot use sp as source/dest register here, thus we're emitting the 267 // following sequence: 268 // mov r4, sp 269 // bic r4, r4, MaxAlign 270 // mov sp, r4 271 // FIXME: It will be better just to find spare register here. 272 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4) 273 .addReg(ARM::SP, RegState::Kill)); 274 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, 275 TII.get(ARM::t2BICri), ARM::R4) 276 .addReg(ARM::R4, RegState::Kill) 277 .addImm(MaxAlign-1))); 278 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP) 279 .addReg(ARM::R4, RegState::Kill)); 280 } 281 282 AFI->setShouldRestoreSPFromFP(true); 283 } 284 285 // If we need a base pointer, set it up here. It's whatever the value 286 // of the stack pointer is at this point. Any variable size objects 287 // will be allocated after this, so we can still use the base pointer 288 // to reference locals. 289 // FIXME: Clarify FrameSetup flags here. 290 if (RegInfo->hasBasePointer(MF)) { 291 if (isARM) 292 BuildMI(MBB, MBBI, dl, 293 TII.get(ARM::MOVr), RegInfo->getBaseRegister()) 294 .addReg(ARM::SP) 295 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 296 else 297 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 298 RegInfo->getBaseRegister()) 299 .addReg(ARM::SP)); 300 } 301 302 // If the frame has variable sized objects then the epilogue must restore 303 // the sp from fp. We can assume there's an FP here since hasFP already 304 // checks for hasVarSizedObjects. 305 if (MFI->hasVarSizedObjects()) 306 AFI->setShouldRestoreSPFromFP(true); 307} 308 309void ARMFrameLowering::emitEpilogue(MachineFunction &MF, 310 MachineBasicBlock &MBB) const { 311 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 312 assert(MBBI->getDesc().isReturn() && 313 "Can only insert epilog into returning blocks"); 314 unsigned RetOpcode = MBBI->getOpcode(); 315 DebugLoc dl = MBBI->getDebugLoc(); 316 MachineFrameInfo *MFI = MF.getFrameInfo(); 317 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 318 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 319 const ARMBaseInstrInfo &TII = 320 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 321 assert(!AFI->isThumb1OnlyFunction() && 322 "This emitEpilogue does not support Thumb1!"); 323 bool isARM = !AFI->isThumbFunction(); 324 325 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); 326 int NumBytes = (int)MFI->getStackSize(); 327 unsigned FramePtr = RegInfo->getFrameRegister(MF); 328 329 if (!AFI->hasStackFrame()) { 330 if (NumBytes != 0) 331 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 332 } else { 333 // Unwind MBBI to point to first LDR / VLDRD. 334 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 335 if (MBBI != MBB.begin()) { 336 do 337 --MBBI; 338 while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); 339 if (!isCSRestore(MBBI, TII, CSRegs)) 340 ++MBBI; 341 } 342 343 // Move SP to start of FP callee save spill area. 344 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + 345 AFI->getGPRCalleeSavedArea2Size() + 346 AFI->getDPRCalleeSavedAreaSize()); 347 348 // Reset SP based on frame pointer only if the stack frame extends beyond 349 // frame pointer stack slot or target is ELF and the function has FP. 350 if (AFI->shouldRestoreSPFromFP()) { 351 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; 352 if (NumBytes) { 353 if (isARM) 354 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, 355 ARMCC::AL, 0, TII); 356 else { 357 // It's not possible to restore SP from FP in a single instruction. 358 // For Darwin, this looks like: 359 // mov sp, r7 360 // sub sp, #24 361 // This is bad, if an interrupt is taken after the mov, sp is in an 362 // inconsistent state. 363 // Use the first callee-saved register as a scratch register. 364 assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && 365 "No scratch register to restore SP from FP!"); 366 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, 367 ARMCC::AL, 0, TII); 368 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 369 ARM::SP) 370 .addReg(ARM::R4)); 371 } 372 } else { 373 // Thumb2 or ARM. 374 if (isARM) 375 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) 376 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 377 else 378 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), 379 ARM::SP) 380 .addReg(FramePtr)); 381 } 382 } else if (NumBytes) 383 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); 384 385 // Increment past our save areas. 386 if (AFI->getDPRCalleeSavedAreaSize()) { 387 MBBI++; 388 // Since vpop register list cannot have gaps, there may be multiple vpop 389 // instructions in the epilogue. 390 while (MBBI->getOpcode() == ARM::VLDMDIA_UPD) 391 MBBI++; 392 } 393 if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; 394 if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; 395 } 396 397 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || 398 RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { 399 // Tail call return: adjust the stack pointer and jump to callee. 400 MBBI = MBB.getLastNonDebugInstr(); 401 MachineOperand &JumpTarget = MBBI->getOperand(0); 402 403 // Jump to label or value in register. 404 if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) { 405 unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi) 406 ? (STI.isThumb() ? ARM::tTAILJMPd : ARM::TAILJMPd) 407 : (STI.isThumb() ? ARM::tTAILJMPdND : ARM::TAILJMPdND); 408 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 409 if (JumpTarget.isGlobal()) 410 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 411 JumpTarget.getTargetFlags()); 412 else { 413 assert(JumpTarget.isSymbol()); 414 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 415 JumpTarget.getTargetFlags()); 416 } 417 418 // Add the default predicate in Thumb mode. 419 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0); 420 } else if (RetOpcode == ARM::TCRETURNri) { 421 BuildMI(MBB, MBBI, dl, 422 TII.get(STI.isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr)). 423 addReg(JumpTarget.getReg(), RegState::Kill); 424 } else if (RetOpcode == ARM::TCRETURNriND) { 425 BuildMI(MBB, MBBI, dl, 426 TII.get(STI.isThumb() ? ARM::tTAILJMPrND : ARM::TAILJMPrND)). 427 addReg(JumpTarget.getReg(), RegState::Kill); 428 } 429 430 MachineInstr *NewMI = prior(MBBI); 431 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) 432 NewMI->addOperand(MBBI->getOperand(i)); 433 434 // Delete the pseudo instruction TCRETURN. 435 MBB.erase(MBBI); 436 MBBI = NewMI; 437 } 438 439 if (VARegSaveSize) 440 emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); 441} 442 443/// getFrameIndexReference - Provide a base+offset reference to an FI slot for 444/// debug info. It's the same as what we use for resolving the code-gen 445/// references for now. FIXME: This can go wrong when references are 446/// SP-relative and simple call frames aren't used. 447int 448ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, 449 unsigned &FrameReg) const { 450 return ResolveFrameIndexReference(MF, FI, FrameReg, 0); 451} 452 453int 454ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, 455 int FI, unsigned &FrameReg, 456 int SPAdj) const { 457 const MachineFrameInfo *MFI = MF.getFrameInfo(); 458 const ARMBaseRegisterInfo *RegInfo = 459 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 460 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 461 int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); 462 int FPOffset = Offset - AFI->getFramePtrSpillOffset(); 463 bool isFixed = MFI->isFixedObjectIndex(FI); 464 465 FrameReg = ARM::SP; 466 Offset += SPAdj; 467 if (AFI->isGPRCalleeSavedArea1Frame(FI)) 468 return Offset - AFI->getGPRCalleeSavedArea1Offset(); 469 else if (AFI->isGPRCalleeSavedArea2Frame(FI)) 470 return Offset - AFI->getGPRCalleeSavedArea2Offset(); 471 else if (AFI->isDPRCalleeSavedAreaFrame(FI)) 472 return Offset - AFI->getDPRCalleeSavedAreaOffset(); 473 474 // When dynamically realigning the stack, use the frame pointer for 475 // parameters, and the stack/base pointer for locals. 476 if (RegInfo->needsStackRealignment(MF)) { 477 assert (hasFP(MF) && "dynamic stack realignment without a FP!"); 478 if (isFixed) { 479 FrameReg = RegInfo->getFrameRegister(MF); 480 Offset = FPOffset; 481 } else if (MFI->hasVarSizedObjects()) { 482 assert(RegInfo->hasBasePointer(MF) && 483 "VLAs and dynamic stack alignment, but missing base pointer!"); 484 FrameReg = RegInfo->getBaseRegister(); 485 } 486 return Offset; 487 } 488 489 // If there is a frame pointer, use it when we can. 490 if (hasFP(MF) && AFI->hasStackFrame()) { 491 // Use frame pointer to reference fixed objects. Use it for locals if 492 // there are VLAs (and thus the SP isn't reliable as a base). 493 if (isFixed || (MFI->hasVarSizedObjects() && 494 !RegInfo->hasBasePointer(MF))) { 495 FrameReg = RegInfo->getFrameRegister(MF); 496 return FPOffset; 497 } else if (MFI->hasVarSizedObjects()) { 498 assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); 499 if (AFI->isThumb2Function()) { 500 // Try to use the frame pointer if we can, else use the base pointer 501 // since it's available. This is handy for the emergency spill slot, in 502 // particular. 503 if (FPOffset >= -255 && FPOffset < 0) { 504 FrameReg = RegInfo->getFrameRegister(MF); 505 return FPOffset; 506 } 507 } 508 } else if (AFI->isThumb2Function()) { 509 // Use add <rd>, sp, #<imm8> 510 // ldr <rd>, [sp, #<imm8>] 511 // if at all possible to save space. 512 if (Offset >= 0 && (Offset & 3) == 0 && Offset <= 1020) 513 return Offset; 514 // In Thumb2 mode, the negative offset is very limited. Try to avoid 515 // out of range references. ldr <rt>,[<rn>, #-<imm8>] 516 if (FPOffset >= -255 && FPOffset < 0) { 517 FrameReg = RegInfo->getFrameRegister(MF); 518 return FPOffset; 519 } 520 } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { 521 // Otherwise, use SP or FP, whichever is closer to the stack slot. 522 FrameReg = RegInfo->getFrameRegister(MF); 523 return FPOffset; 524 } 525 } 526 // Use the base pointer if we have one. 527 if (RegInfo->hasBasePointer(MF)) 528 FrameReg = RegInfo->getBaseRegister(); 529 return Offset; 530} 531 532int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, 533 int FI) const { 534 unsigned FrameReg; 535 return getFrameIndexReference(MF, FI, FrameReg); 536} 537 538void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, 539 MachineBasicBlock::iterator MI, 540 const std::vector<CalleeSavedInfo> &CSI, 541 unsigned StmOpc, unsigned StrOpc, 542 bool NoGap, 543 bool(*Func)(unsigned, bool), 544 unsigned MIFlags) const { 545 MachineFunction &MF = *MBB.getParent(); 546 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 547 548 DebugLoc DL; 549 if (MI != MBB.end()) DL = MI->getDebugLoc(); 550 551 SmallVector<std::pair<unsigned,bool>, 4> Regs; 552 unsigned i = CSI.size(); 553 while (i != 0) { 554 unsigned LastReg = 0; 555 for (; i != 0; --i) { 556 unsigned Reg = CSI[i-1].getReg(); 557 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 558 559 // Add the callee-saved register as live-in unless it's LR and 560 // @llvm.returnaddress is called. If LR is returned for 561 // @llvm.returnaddress then it's already added to the function and 562 // entry block live-in sets. 563 bool isKill = true; 564 if (Reg == ARM::LR) { 565 if (MF.getFrameInfo()->isReturnAddressTaken() && 566 MF.getRegInfo().isLiveIn(Reg)) 567 isKill = false; 568 } 569 570 if (isKill) 571 MBB.addLiveIn(Reg); 572 573 // If NoGap is true, push consecutive registers and then leave the rest 574 // for other instructions. e.g. 575 // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} 576 if (NoGap && LastReg && LastReg != Reg-1) 577 break; 578 LastReg = Reg; 579 Regs.push_back(std::make_pair(Reg, isKill)); 580 } 581 582 if (Regs.empty()) 583 continue; 584 if (Regs.size() > 1 || StrOpc== 0) { 585 MachineInstrBuilder MIB = 586 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) 587 .addReg(ARM::SP).setMIFlags(MIFlags)); 588 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 589 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); 590 } else if (Regs.size() == 1) { 591 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 592 ARM::SP) 593 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) 594 .addReg(ARM::SP).setMIFlags(MIFlags) 595 .addImm(-4); 596 AddDefaultPred(MIB); 597 } 598 Regs.clear(); 599 } 600} 601 602void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, 603 MachineBasicBlock::iterator MI, 604 const std::vector<CalleeSavedInfo> &CSI, 605 unsigned LdmOpc, unsigned LdrOpc, 606 bool isVarArg, bool NoGap, 607 bool(*Func)(unsigned, bool)) const { 608 MachineFunction &MF = *MBB.getParent(); 609 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 610 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 611 DebugLoc DL = MI->getDebugLoc(); 612 unsigned RetOpcode = MI->getOpcode(); 613 bool isTailCall = (RetOpcode == ARM::TCRETURNdi || 614 RetOpcode == ARM::TCRETURNdiND || 615 RetOpcode == ARM::TCRETURNri || 616 RetOpcode == ARM::TCRETURNriND); 617 618 SmallVector<unsigned, 4> Regs; 619 unsigned i = CSI.size(); 620 while (i != 0) { 621 unsigned LastReg = 0; 622 bool DeleteRet = false; 623 for (; i != 0; --i) { 624 unsigned Reg = CSI[i-1].getReg(); 625 if (!(Func)(Reg, STI.isTargetDarwin())) continue; 626 627 if (Reg == ARM::LR && !isTailCall && !isVarArg && STI.hasV5TOps()) { 628 Reg = ARM::PC; 629 LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; 630 // Fold the return instruction into the LDM. 631 DeleteRet = true; 632 } 633 634 // If NoGap is true, pop consecutive registers and then leave the rest 635 // for other instructions. e.g. 636 // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} 637 if (NoGap && LastReg && LastReg != Reg-1) 638 break; 639 640 LastReg = Reg; 641 Regs.push_back(Reg); 642 } 643 644 if (Regs.empty()) 645 continue; 646 if (Regs.size() > 1 || LdrOpc == 0) { 647 MachineInstrBuilder MIB = 648 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) 649 .addReg(ARM::SP)); 650 for (unsigned i = 0, e = Regs.size(); i < e; ++i) 651 MIB.addReg(Regs[i], getDefRegState(true)); 652 if (DeleteRet) { 653 MIB->copyImplicitOps(&*MI); 654 MI->eraseFromParent(); 655 } 656 MI = MIB; 657 } else if (Regs.size() == 1) { 658 // If we adjusted the reg to PC from LR above, switch it back here. We 659 // only do that for LDM. 660 if (Regs[0] == ARM::PC) 661 Regs[0] = ARM::LR; 662 MachineInstrBuilder MIB = 663 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) 664 .addReg(ARM::SP, RegState::Define) 665 .addReg(ARM::SP); 666 // ARM mode needs an extra reg0 here due to addrmode2. Will go away once 667 // that refactoring is complete (eventually). 668 if (LdrOpc == ARM::LDR_POST_REG || LdrOpc == ARM::LDR_POST_IMM) { 669 MIB.addReg(0); 670 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); 671 } else 672 MIB.addImm(4); 673 AddDefaultPred(MIB); 674 } 675 Regs.clear(); 676 } 677} 678 679bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 680 MachineBasicBlock::iterator MI, 681 const std::vector<CalleeSavedInfo> &CSI, 682 const TargetRegisterInfo *TRI) const { 683 if (CSI.empty()) 684 return false; 685 686 MachineFunction &MF = *MBB.getParent(); 687 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 688 689 unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; 690 unsigned PushOneOpc = AFI->isThumbFunction() ? 691 ARM::t2STR_PRE : ARM::STR_PRE_IMM; 692 unsigned FltOpc = ARM::VSTMDDB_UPD; 693 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 694 MachineInstr::FrameSetup); 695 emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 696 MachineInstr::FrameSetup); 697 emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register, 698 MachineInstr::FrameSetup); 699 700 return true; 701} 702 703bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 704 MachineBasicBlock::iterator MI, 705 const std::vector<CalleeSavedInfo> &CSI, 706 const TargetRegisterInfo *TRI) const { 707 if (CSI.empty()) 708 return false; 709 710 MachineFunction &MF = *MBB.getParent(); 711 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 712 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; 713 714 unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; 715 unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST :ARM::LDR_POST_IMM; 716 unsigned FltOpc = ARM::VLDMDIA_UPD; 717 emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register); 718 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 719 &isARMArea2Register); 720 emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, 721 &isARMArea1Register); 722 723 return true; 724} 725 726// FIXME: Make generic? 727static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, 728 const ARMBaseInstrInfo &TII) { 729 unsigned FnSize = 0; 730 for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); 731 MBBI != E; ++MBBI) { 732 const MachineBasicBlock &MBB = *MBBI; 733 for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); 734 I != E; ++I) 735 FnSize += TII.GetInstSizeInBytes(I); 736 } 737 return FnSize; 738} 739 740/// estimateStackSize - Estimate and return the size of the frame. 741/// FIXME: Make generic? 742static unsigned estimateStackSize(MachineFunction &MF) { 743 const MachineFrameInfo *MFI = MF.getFrameInfo(); 744 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 745 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 746 unsigned MaxAlign = MFI->getMaxAlignment(); 747 int Offset = 0; 748 749 // This code is very, very similar to PEI::calculateFrameObjectOffsets(). 750 // It really should be refactored to share code. Until then, changes 751 // should keep in mind that there's tight coupling between the two. 752 753 for (int i = MFI->getObjectIndexBegin(); i != 0; ++i) { 754 int FixedOff = -MFI->getObjectOffset(i); 755 if (FixedOff > Offset) Offset = FixedOff; 756 } 757 for (unsigned i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { 758 if (MFI->isDeadObjectIndex(i)) 759 continue; 760 Offset += MFI->getObjectSize(i); 761 unsigned Align = MFI->getObjectAlignment(i); 762 // Adjust to alignment boundary 763 Offset = (Offset+Align-1)/Align*Align; 764 765 MaxAlign = std::max(Align, MaxAlign); 766 } 767 768 if (MFI->adjustsStack() && TFI->hasReservedCallFrame(MF)) 769 Offset += MFI->getMaxCallFrameSize(); 770 771 // Round up the size to a multiple of the alignment. If the function has 772 // any calls or alloca's, align to the target's StackAlignment value to 773 // ensure that the callee's frame or the alloca data is suitably aligned; 774 // otherwise, for leaf functions, align to the TransientStackAlignment 775 // value. 776 unsigned StackAlign; 777 if (MFI->adjustsStack() || MFI->hasVarSizedObjects() || 778 (RegInfo->needsStackRealignment(MF) && MFI->getObjectIndexEnd() != 0)) 779 StackAlign = TFI->getStackAlignment(); 780 else 781 StackAlign = TFI->getTransientStackAlignment(); 782 783 // If the frame pointer is eliminated, all frame offsets will be relative to 784 // SP not FP. Align to MaxAlign so this works. 785 StackAlign = std::max(StackAlign, MaxAlign); 786 unsigned AlignMask = StackAlign - 1; 787 Offset = (Offset + AlignMask) & ~uint64_t(AlignMask); 788 789 return (unsigned)Offset; 790} 791 792/// estimateRSStackSizeLimit - Look at each instruction that references stack 793/// frames and return the stack size limit beyond which some of these 794/// instructions will require a scratch register during their expansion later. 795// FIXME: Move to TII? 796static unsigned estimateRSStackSizeLimit(MachineFunction &MF, 797 const TargetFrameLowering *TFI) { 798 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 799 unsigned Limit = (1 << 12) - 1; 800 for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { 801 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); 802 I != E; ++I) { 803 for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { 804 if (!I->getOperand(i).isFI()) continue; 805 806 // When using ADDri to get the address of a stack object, 255 is the 807 // largest offset guaranteed to fit in the immediate offset. 808 if (I->getOpcode() == ARM::ADDri) { 809 Limit = std::min(Limit, (1U << 8) - 1); 810 break; 811 } 812 813 // Otherwise check the addressing mode. 814 switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { 815 case ARMII::AddrMode3: 816 case ARMII::AddrModeT2_i8: 817 Limit = std::min(Limit, (1U << 8) - 1); 818 break; 819 case ARMII::AddrMode5: 820 case ARMII::AddrModeT2_i8s4: 821 Limit = std::min(Limit, ((1U << 8) - 1) * 4); 822 break; 823 case ARMII::AddrModeT2_i12: 824 // i12 supports only positive offset so these will be converted to 825 // i8 opcodes. See llvm::rewriteT2FrameIndex. 826 if (TFI->hasFP(MF) && AFI->hasStackFrame()) 827 Limit = std::min(Limit, (1U << 8) - 1); 828 break; 829 case ARMII::AddrMode4: 830 case ARMII::AddrMode6: 831 // Addressing modes 4 & 6 (load/store) instructions can't encode an 832 // immediate offset for stack references. 833 return 0; 834 default: 835 break; 836 } 837 break; // At most one FI per instruction 838 } 839 } 840 } 841 842 return Limit; 843} 844 845void 846ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 847 RegScavenger *RS) const { 848 // This tells PEI to spill the FP as if it is any other callee-save register 849 // to take advantage the eliminateFrameIndex machinery. This also ensures it 850 // is spilled in the order specified by getCalleeSavedRegs() to make it easier 851 // to combine multiple loads / stores. 852 bool CanEliminateFrame = true; 853 bool CS1Spilled = false; 854 bool LRSpilled = false; 855 unsigned NumGPRSpills = 0; 856 SmallVector<unsigned, 4> UnspilledCS1GPRs; 857 SmallVector<unsigned, 4> UnspilledCS2GPRs; 858 const ARMBaseRegisterInfo *RegInfo = 859 static_cast<const ARMBaseRegisterInfo*>(MF.getTarget().getRegisterInfo()); 860 const ARMBaseInstrInfo &TII = 861 *static_cast<const ARMBaseInstrInfo*>(MF.getTarget().getInstrInfo()); 862 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 863 MachineFrameInfo *MFI = MF.getFrameInfo(); 864 unsigned FramePtr = RegInfo->getFrameRegister(MF); 865 866 // Spill R4 if Thumb2 function requires stack realignment - it will be used as 867 // scratch register. Also spill R4 if Thumb2 function has varsized objects, 868 // since it's not always possible to restore sp from fp in a single 869 // instruction. 870 // FIXME: It will be better just to find spare register here. 871 if (AFI->isThumb2Function() && 872 (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) 873 MF.getRegInfo().setPhysRegUsed(ARM::R4); 874 875 if (AFI->isThumb1OnlyFunction()) { 876 // Spill LR if Thumb1 function uses variable length argument lists. 877 if (AFI->getVarArgsRegSaveSize() > 0) 878 MF.getRegInfo().setPhysRegUsed(ARM::LR); 879 880 // Spill R4 if Thumb1 epilogue has to restore SP from FP. We don't know 881 // for sure what the stack size will be, but for this, an estimate is good 882 // enough. If there anything changes it, it'll be a spill, which implies 883 // we've used all the registers and so R4 is already used, so not marking 884 // it here will be OK. Also spill R4 if Thumb1 function requires stack 885 // realignment. 886 // FIXME: It will be better just to find spare register here. 887 unsigned StackSize = estimateStackSize(MF); 888 if (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF) || 889 StackSize > 508) 890 MF.getRegInfo().setPhysRegUsed(ARM::R4); 891 } 892 893 // Spill the BasePtr if it's used. 894 if (RegInfo->hasBasePointer(MF)) 895 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); 896 897 // Don't spill FP if the frame can be eliminated. This is determined 898 // by scanning the callee-save registers to see if any is used. 899 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); 900 for (unsigned i = 0; CSRegs[i]; ++i) { 901 unsigned Reg = CSRegs[i]; 902 bool Spilled = false; 903 if (MF.getRegInfo().isPhysRegUsed(Reg)) { 904 Spilled = true; 905 CanEliminateFrame = false; 906 } else { 907 // Check alias registers too. 908 for (const unsigned *Aliases = 909 RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) { 910 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { 911 Spilled = true; 912 CanEliminateFrame = false; 913 } 914 } 915 } 916 917 if (!ARM::GPRRegisterClass->contains(Reg)) 918 continue; 919 920 if (Spilled) { 921 NumGPRSpills++; 922 923 if (!STI.isTargetDarwin()) { 924 if (Reg == ARM::LR) 925 LRSpilled = true; 926 CS1Spilled = true; 927 continue; 928 } 929 930 // Keep track if LR and any of R4, R5, R6, and R7 is spilled. 931 switch (Reg) { 932 case ARM::LR: 933 LRSpilled = true; 934 // Fallthrough 935 case ARM::R4: case ARM::R5: 936 case ARM::R6: case ARM::R7: 937 CS1Spilled = true; 938 break; 939 default: 940 break; 941 } 942 } else { 943 if (!STI.isTargetDarwin()) { 944 UnspilledCS1GPRs.push_back(Reg); 945 continue; 946 } 947 948 switch (Reg) { 949 case ARM::R4: case ARM::R5: 950 case ARM::R6: case ARM::R7: 951 case ARM::LR: 952 UnspilledCS1GPRs.push_back(Reg); 953 break; 954 default: 955 UnspilledCS2GPRs.push_back(Reg); 956 break; 957 } 958 } 959 } 960 961 bool ForceLRSpill = false; 962 if (!LRSpilled && AFI->isThumb1OnlyFunction()) { 963 unsigned FnSize = GetFunctionSizeInBytes(MF, TII); 964 // Force LR to be spilled if the Thumb function size is > 2048. This enables 965 // use of BL to implement far jump. If it turns out that it's not needed 966 // then the branch fix up path will undo it. 967 if (FnSize >= (1 << 11)) { 968 CanEliminateFrame = false; 969 ForceLRSpill = true; 970 } 971 } 972 973 // If any of the stack slot references may be out of range of an immediate 974 // offset, make sure a register (or a spill slot) is available for the 975 // register scavenger. Note that if we're indexing off the frame pointer, the 976 // effective stack size is 4 bytes larger since the FP points to the stack 977 // slot of the previous FP. Also, if we have variable sized objects in the 978 // function, stack slot references will often be negative, and some of 979 // our instructions are positive-offset only, so conservatively consider 980 // that case to want a spill slot (or register) as well. Similarly, if 981 // the function adjusts the stack pointer during execution and the 982 // adjustments aren't already part of our stack size estimate, our offset 983 // calculations may be off, so be conservative. 984 // FIXME: We could add logic to be more precise about negative offsets 985 // and which instructions will need a scratch register for them. Is it 986 // worth the effort and added fragility? 987 bool BigStack = 988 (RS && 989 (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= 990 estimateRSStackSizeLimit(MF, this))) 991 || MFI->hasVarSizedObjects() 992 || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); 993 994 bool ExtraCSSpill = false; 995 if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { 996 AFI->setHasStackFrame(true); 997 998 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. 999 // Spill LR as well so we can fold BX_RET to the registers restore (LDM). 1000 if (!LRSpilled && CS1Spilled) { 1001 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1002 NumGPRSpills++; 1003 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), 1004 UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); 1005 ForceLRSpill = false; 1006 ExtraCSSpill = true; 1007 } 1008 1009 if (hasFP(MF)) { 1010 MF.getRegInfo().setPhysRegUsed(FramePtr); 1011 NumGPRSpills++; 1012 } 1013 1014 // If stack and double are 8-byte aligned and we are spilling an odd number 1015 // of GPRs, spill one extra callee save GPR so we won't have to pad between 1016 // the integer and double callee save areas. 1017 unsigned TargetAlign = getStackAlignment(); 1018 if (TargetAlign == 8 && (NumGPRSpills & 1)) { 1019 if (CS1Spilled && !UnspilledCS1GPRs.empty()) { 1020 for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { 1021 unsigned Reg = UnspilledCS1GPRs[i]; 1022 // Don't spill high register if the function is thumb1 1023 if (!AFI->isThumb1OnlyFunction() || 1024 isARMLowRegister(Reg) || Reg == ARM::LR) { 1025 MF.getRegInfo().setPhysRegUsed(Reg); 1026 if (!RegInfo->isReservedReg(MF, Reg)) 1027 ExtraCSSpill = true; 1028 break; 1029 } 1030 } 1031 } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { 1032 unsigned Reg = UnspilledCS2GPRs.front(); 1033 MF.getRegInfo().setPhysRegUsed(Reg); 1034 if (!RegInfo->isReservedReg(MF, Reg)) 1035 ExtraCSSpill = true; 1036 } 1037 } 1038 1039 // Estimate if we might need to scavenge a register at some point in order 1040 // to materialize a stack offset. If so, either spill one additional 1041 // callee-saved register or reserve a special spill slot to facilitate 1042 // register scavenging. Thumb1 needs a spill slot for stack pointer 1043 // adjustments also, even when the frame itself is small. 1044 if (BigStack && !ExtraCSSpill) { 1045 // If any non-reserved CS register isn't spilled, just spill one or two 1046 // extra. That should take care of it! 1047 unsigned NumExtras = TargetAlign / 4; 1048 SmallVector<unsigned, 2> Extras; 1049 while (NumExtras && !UnspilledCS1GPRs.empty()) { 1050 unsigned Reg = UnspilledCS1GPRs.back(); 1051 UnspilledCS1GPRs.pop_back(); 1052 if (!RegInfo->isReservedReg(MF, Reg) && 1053 (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || 1054 Reg == ARM::LR)) { 1055 Extras.push_back(Reg); 1056 NumExtras--; 1057 } 1058 } 1059 // For non-Thumb1 functions, also check for hi-reg CS registers 1060 if (!AFI->isThumb1OnlyFunction()) { 1061 while (NumExtras && !UnspilledCS2GPRs.empty()) { 1062 unsigned Reg = UnspilledCS2GPRs.back(); 1063 UnspilledCS2GPRs.pop_back(); 1064 if (!RegInfo->isReservedReg(MF, Reg)) { 1065 Extras.push_back(Reg); 1066 NumExtras--; 1067 } 1068 } 1069 } 1070 if (Extras.size() && NumExtras == 0) { 1071 for (unsigned i = 0, e = Extras.size(); i != e; ++i) { 1072 MF.getRegInfo().setPhysRegUsed(Extras[i]); 1073 } 1074 } else if (!AFI->isThumb1OnlyFunction()) { 1075 // note: Thumb1 functions spill to R12, not the stack. Reserve a slot 1076 // closest to SP or frame pointer. 1077 const TargetRegisterClass *RC = ARM::GPRRegisterClass; 1078 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1079 RC->getAlignment(), 1080 false)); 1081 } 1082 } 1083 } 1084 1085 if (ForceLRSpill) { 1086 MF.getRegInfo().setPhysRegUsed(ARM::LR); 1087 AFI->setLRIsSpilledForFarJump(true); 1088 } 1089} 1090