ARMISelLowering.h revision 5657c01949dca6c012ac60d242d1a8d2ffdf5603
1a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file defines the interfaces that ARM uses to lower LLVM code into a 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// selection DAG. 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef ARMISELLOWERING_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define ARMISELLOWERING_H 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 18f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola#include "ARMSubtarget.h" 19a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Target/TargetLowering.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/CodeGen/SelectionDAG.h" 211f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson#include "llvm/CodeGen/CallingConvLower.h" 22a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <vector> 23a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 24a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMConstantPoolValue; 26a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 27a8e2989ece6dc46df59b0768184028257f913843Evan Cheng namespace ARMISD { 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ARM Specific DAG Nodes 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum NodeType { 306aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach // Start the numbering where the builtin ops and target ops leave off. 310ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bddDan Gohman FIRST_NUMBER = ISD::BUILTIN_OP_END, 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // TargetExternalSymbol, and TargetGlobalAddress. 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 366aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL, // Function call. 38277f0741c5ea123b30360c382a153df238c31caeEvan Cheng CALL_PRED, // Function call that's predicable. 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL_NOLINK, // Function call with branch not branch-and-link. 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng tCALL, // Thumb function call. 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BRCOND, // Conditional branch. 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BR_JT, // Jumptable branch. 435657c01949dca6c012ac60d242d1a8d2ffdf5603Evan Cheng BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RET_FLAG, // Return with a flag operand. 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PIC_ADD, // Add with a PC operand and a PIC label. 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMP, // ARM compare instructions. 49c0309b48b560f119982c02a81416c8c1fd208648David Goodwin CMPZ, // ARM compare that sets only Z flag. 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFP, // ARM VFP compare instruction, sets FPSCR. 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FMSTAT, // ARM fmstat instruction. 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMOV, // ARM conditional move instructions. 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CNEG, // ARM conditional negate instructions. 556aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FTOSI, // FP to sint within a FP register. 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FTOUI, // FP to uint within a FP register. 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SITOF, // sint to FP within a FP register. 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UITOF, // uint to FP within a FP register. 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 646aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FMRRD, // double to two gprs. 66261f2a2337990bc7cc3d9e20d3338de54b26c74cBob Wilson FMDRR, // Two gprs to double. 6764f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio 68f95701286664df01a5683a71c9a02c056fed0aa7Jim Grosbach EH_SJLJ_SETJMP, // SjLj exception handling setjmp 69f95701286664df01a5683a71c9a02c056fed0aa7Jim Grosbach EH_SJLJ_LONGJMP, // SjLj exception handling longjmp 700e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach 715bafff36c798608a189c517d37527e4a38863071Bob Wilson THREAD_POINTER, 725bafff36c798608a189c517d37527e4a38863071Bob Wilson 735bafff36c798608a189c517d37527e4a38863071Bob Wilson VCEQ, // Vector compare equal. 745bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGE, // Vector compare greater than or equal. 755bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGEU, // Vector compare unsigned greater than or equal. 765bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGT, // Vector compare greater than. 775bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGTU, // Vector compare unsigned greater than. 785bafff36c798608a189c517d37527e4a38863071Bob Wilson VTST, // Vector test bits. 795bafff36c798608a189c517d37527e4a38863071Bob Wilson 805bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift by immediate: 815bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHL, // ...left 825bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRs, // ...right (signed) 835bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRu, // ...right (unsigned) 845bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLs, // ...left long (signed) 855bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLu, // ...left long (unsigned) 865bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLi, // ...left long (with maximum shift count) 875bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRN, // ...right narrow 885bafff36c798608a189c517d37527e4a38863071Bob Wilson 895bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector rounding shift by immediate: 905bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRs, // ...right (signed) 915bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRu, // ...right (unsigned) 925bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRN, // ...right narrow 935bafff36c798608a189c517d37527e4a38863071Bob Wilson 945bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating shift by immediate: 955bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLs, // ...left (signed) 965bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLu, // ...left (unsigned) 975bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLsu, // ...left (signed to unsigned) 985bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNs, // ...right narrow (signed) 995bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNu, // ...right narrow (unsigned) 1005bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNsu, // ...right narrow (signed to unsigned) 1015bafff36c798608a189c517d37527e4a38863071Bob Wilson 1025bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating rounding shift by immediate: 1035bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNs, // ...right narrow (signed) 1045bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNu, // ...right narrow (unsigned) 1055bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNsu, // ...right narrow (signed to unsigned) 1065bafff36c798608a189c517d37527e4a38863071Bob Wilson 1075bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift and insert: 1085bafff36c798608a189c517d37527e4a38863071Bob Wilson VSLI, // ...left 1095bafff36c798608a189c517d37527e4a38863071Bob Wilson VSRI, // ...right 1105bafff36c798608a189c517d37527e4a38863071Bob Wilson 1115bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector get lane (VMOV scalar to ARM core register) 1125bafff36c798608a189c517d37527e4a38863071Bob Wilson // (These are used for 8- and 16-bit element types only.) 1135bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEu, // zero-extend vector extract element 1145bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEs, // sign-extend vector extract element 1155bafff36c798608a189c517d37527e4a38863071Bob Wilson 1165bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector duplicate lane (128-bit result only; 64-bit is a shuffle) 1175bafff36c798608a189c517d37527e4a38863071Bob Wilson VDUPLANEQ // splat a lane from a 64-bit vector to a 128-bit vector 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1215bafff36c798608a189c517d37527e4a38863071Bob Wilson /// Define some predicates that are used for node matching. 1225bafff36c798608a189c517d37527e4a38863071Bob Wilson namespace ARM { 1235bafff36c798608a189c517d37527e4a38863071Bob Wilson /// getVMOVImm - If this is a build_vector of constants which can be 1245bafff36c798608a189c517d37527e4a38863071Bob Wilson /// formed by using a VMOV instruction of the specified element size, 1255bafff36c798608a189c517d37527e4a38863071Bob Wilson /// return the constant being splatted. The ByteSize field indicates the 1265bafff36c798608a189c517d37527e4a38863071Bob Wilson /// number of bytes of each element [1248]. 1275bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 1288bb9e48752b4a88e512ceb8fb802e2cdf8150e7bBob Wilson 1298bb9e48752b4a88e512ceb8fb802e2cdf8150e7bBob Wilson /// isVREVMask - Check if a vector shuffle corresponds to a VREV 1308bb9e48752b4a88e512ceb8fb802e2cdf8150e7bBob Wilson /// instruction with the specified blocksize. (The order of the elements 1318bb9e48752b4a88e512ceb8fb802e2cdf8150e7bBob Wilson /// within each block of the vector is reversed.) 1328bb9e48752b4a88e512ceb8fb802e2cdf8150e7bBob Wilson bool isVREVMask(ShuffleVectorSDNode *N, unsigned blocksize); 1335bafff36c798608a189c517d37527e4a38863071Bob Wilson } 1345bafff36c798608a189c517d37527e4a38863071Bob Wilson 135261f2a2337990bc7cc3d9e20d3338de54b26c74cBob Wilson //===--------------------------------------------------------------------===// 13680dae195c75a3ef38854645ae3cf41f8ae835644Dale Johannesen // ARMTargetLowering - ARM Implementation of the TargetLowering interface 1376aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 138a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMTargetLowering : public TargetLowering { 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int VarArgsFrameIndex; // FrameIndex for start of varargs area. 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng public: 14161e729e2e9517ab2d8887bab86fb377900fa1081Dan Gohman explicit ARMTargetLowering(TargetMachine &TM); 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 143475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1441607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 1451607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// ReplaceNodeResults - Replace the results of node with an illegal result 1461607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// type with new values built out of custom code. 1471607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// 1481607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 1491607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands SelectionDAG &DAG); 1501607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 151475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1526aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual const char *getTargetNodeName(unsigned Opcode) const; 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 155ff9b373e8f5006c629af81e2619778b4c4f5249eEvan Cheng virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 1561fdbc1dd4e9cb42c79a30e8dc308c322e923cc52Dan Gohman MachineBasicBlock *MBB) const; 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 158c9addb74883fef318140272768422656a694341fChris Lattner /// isLegalAddressingMode - Return true if the addressing mode represented 159c9addb74883fef318140272768422656a694341fChris Lattner /// by AM is legal for this target, for a load/store of the specified type. 160c9addb74883fef318140272768422656a694341fChris Lattner virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 1616aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPreIndexedAddressParts - returns true by value, base pointer and 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if the node's address 164a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// can be legally represented as pre-indexed load / store address. 165475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 166475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Offset, 167a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 16873e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 169a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 170a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPostIndexedAddressParts - returns true by value, base pointer and 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if this node can be 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// combined with a load / store to form a post-indexed load / store. 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 174475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Base, SDValue &Offset, 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 17673e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 178475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual void computeMaskedBitsForTargetNode(const SDValue Op, 179977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3Dan Gohman const APInt &Mask, 1806aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach APInt &KnownZero, 181fd29e0eb060ea8b4d490860329234d2ae5f5952eDan Gohman APInt &KnownOne, 182ea859be53ca13a1547c4675549946b74dc3c6f41Dan Gohman const SelectionDAG &DAG, 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Depth) const; 1844234f57fa02b1f04a9f52a7b3c2aa22d32ac521cChris Lattner ConstraintType getConstraintType(const std::string &Constraint) const; 1856aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach std::pair<unsigned, const TargetRegisterClass*> 186a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegForInlineAsmConstraint(const std::string &Constraint, 18783ec4b6711980242ef3c55a4fa36b2d7a39c1bfbDuncan Sands MVT VT) const; 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::vector<unsigned> 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegClassForInlineAsmConstraint(const std::string &Constraint, 19083ec4b6711980242ef3c55a4fa36b2d7a39c1bfbDuncan Sands MVT VT) const; 191f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 192bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 193bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 194bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// true it means one of the asm constraint of the inline asm instruction 195bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// being processed is 'm'. 196bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson virtual void LowerAsmOperandForConstraint(SDValue Op, 197bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson char ConstraintLetter, 198bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson bool hasMemory, 199bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson std::vector<SDValue> &Ops, 200bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson SelectionDAG &DAG) const; 2016aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 202707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman virtual const ARMSubtarget* getSubtarget() { 203707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman return Subtarget; 204f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola } 205f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 206b4202b84d7e54efe5e144885c7da63e6cc465f80Bill Wendling /// getFunctionAlignment - Return the Log2 alignment of this function. 20720c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling virtual unsigned getFunctionAlignment(const Function *F) const; 20820c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng private: 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// make the right decision when generating code for different targets. 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget *Subtarget; 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 214d2559bf3f30cc7400483825414489ec0fb36481aBob Wilson /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ARMPCLabelIndex; 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 2185bafff36c798608a189c517d37527e4a38863071Bob Wilson void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 2195bafff36c798608a189c517d37527e4a38863071Bob Wilson void addDRTypeForNEON(MVT VT); 2205bafff36c798608a189c517d37527e4a38863071Bob Wilson void addQRTypeForNEON(MVT VT); 2215bafff36c798608a189c517d37527e4a38863071Bob Wilson 2225bafff36c798608a189c517d37527e4a38863071Bob Wilson typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 2235bafff36c798608a189c517d37527e4a38863071Bob Wilson void PassF64ArgInRegs(CallSDNode *TheCall, SelectionDAG &DAG, 2245bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue Chain, SDValue &Arg, 2255bafff36c798608a189c517d37527e4a38863071Bob Wilson RegsToPassVector &RegsToPass, 2265bafff36c798608a189c517d37527e4a38863071Bob Wilson CCValAssign &VA, CCValAssign &NextVA, 2275bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &StackPtr, 2285bafff36c798608a189c517d37527e4a38863071Bob Wilson SmallVector<SDValue, 8> &MemOpChains, 2295bafff36c798608a189c517d37527e4a38863071Bob Wilson ISD::ArgFlagsTy Flags); 2305bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2315bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &Root, SelectionDAG &DAG, DebugLoc dl); 2325bafff36c798608a189c517d37527e4a38863071Bob Wilson 233385f5a99ecc7fee48a7539bc63d3e1d3b5089c0dAnton Korobeynikov CCAssignFn *CCAssignFnForNode(unsigned CC, bool Return) const; 2341f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 2351f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson const SDValue &StackPtr, const CCValAssign &VA, 236dee46d7f6d61ca628725b54c2d24154ebe70ed96Bob Wilson SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags); 237dee46d7f6d61ca628725b54c2d24154ebe70ed96Bob Wilson SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 2381f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson unsigned CallingConv, SelectionDAG &DAG); 239475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerCALL(SDValue Op, SelectionDAG &DAG); 2400e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 2411f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson SDValue LowerRET(SDValue Op, SelectionDAG &DAG); 242475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); 243475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); 244475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 245475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 24664f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio SelectionDAG &DAG); 247475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 2484102eb57bbeecbbf5b5b5122ed1ecd4cd5487878Evan Cheng SelectionDAG &DAG); 249475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); 250475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG); 251475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); 2520e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 253475871a144eb604ddaf37503397ba0941442e5fbDan Gohman 2540f502f6f44f2756f5cb7b17d8f1d8eae000d51b4Dale Johannesen SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 255475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Chain, 256475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Dst, SDValue Src, 257475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Size, unsigned Align, 258707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman bool AlwaysInline, 2591f13c686df75ddbbe15b208606ece4846d7479a8Dan Gohman const Value *DstSV, uint64_t DstSVOff, 2601f13c686df75ddbbe15b208606ece4846d7479a8Dan Gohman const Value *SrcSV, uint64_t SrcSVOff); 261a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 262a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 263a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 264a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif // ARMISELLOWERING_H 265