ARMAddressingModes.h revision ac79e4c82f201c30a06c2cd05baebd20f5b49888
1a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file contains the ARM addressing mode implementation stuff. 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/CodeGen/SelectionDAGNodes.h" 18a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Support/MathExtras.h" 19a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <cassert> 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 21a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 22764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 23a8e2989ece6dc46df59b0768184028257f913843Evan Cheng/// ARM_AM - ARM Addressing Mode Stuff 24a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace ARM_AM { 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum ShiftOpc { 26a8e2989ece6dc46df59b0768184028257f913843Evan Cheng no_shift = 0, 27a8e2989ece6dc46df59b0768184028257f913843Evan Cheng asr, 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng lsl, 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng lsr, 30a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ror, 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng rrx 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 33764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum AddrOpc { 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng add = '+', sub = '-' 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 37764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 389e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen static inline const char *getAddrOpcStr(AddrOpc Op) { 399e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen return Op == sub ? "-" : ""; 409e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen } 419e08876a2ae329feb7a76dbfe33666cb58033c00Johnny Chen 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline const char *getShiftOpcStr(ShiftOpc Op) { 43a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Op) { 448514e21deb12714d84038e6afa1b755a9d335098Chris Lattner default: assert(0 && "Unknown shift opc!"); 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::asr: return "asr"; 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::lsl: return "lsl"; 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::lsr: return "lsr"; 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ror: return "ror"; 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::rrx: return "rrx"; 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 52764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 5342fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { 5442fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach switch (Op) { 5542fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach default: assert(0 && "Unknown shift opc!"); 5642fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::asr: return 2; 5742fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::lsl: return 0; 5842fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::lsr: return 1; 5942fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach case ARM_AM::ror: return 3; 6042fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach } 6142fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach } 6242fac8ee3bc02e18a5887800e812af762b45b9ebJim Grosbach 63475871a144eb604ddaf37503397ba0941442e5fbDan Gohman static inline ShiftOpc getShiftOpcForNode(SDValue N) { 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (N.getOpcode()) { 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng default: return ARM_AM::no_shift; 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ISD::SHL: return ARM_AM::lsl; 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ISD::SRL: return ARM_AM::lsr; 68a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ISD::SRA: return ARM_AM::asr; 69a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ISD::ROTR: return ARM_AM::ror; 70a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //case ISD::ROTL: // Only if imm -> turn into ROTR. 71a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Can't handle RRX here, because it would require folding a flag into 72a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // the addressing mode. :( This causes us to miss certain things. 73a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //case ARMISD::RRX: return ARM_AM::rrx; 74a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 75a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 76a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum AMSubMode { 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bad_am_submode = 0, 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ia, 80a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ib, 81a8e2989ece6dc46df59b0768184028257f913843Evan Cheng da, 82a8e2989ece6dc46df59b0768184028257f913843Evan Cheng db 83a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 84a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 85a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline const char *getAMSubModeStr(AMSubMode Mode) { 86a8e2989ece6dc46df59b0768184028257f913843Evan Cheng switch (Mode) { 878514e21deb12714d84038e6afa1b755a9d335098Chris Lattner default: assert(0 && "Unknown addressing sub-mode!"); 88a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ia: return "ia"; 89a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::ib: return "ib"; 90a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::da: return "da"; 91a8e2989ece6dc46df59b0768184028257f913843Evan Cheng case ARM_AM::db: return "db"; 92a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 93a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 94a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 95a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. 96a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 97a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned rotr32(unsigned Val, unsigned Amt) { 98a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Amt < 32 && "Invalid rotate amount"); 99a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Val >> Amt) | (Val << ((32-Amt)&31)); 100a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 101764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 102a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. 103a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 104a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned rotl32(unsigned Val, unsigned Amt) { 105a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Amt < 32 && "Invalid rotate amount"); 106a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Val << Amt) | (Val >> ((32-Amt)&31)); 107a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 108764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 109a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 110a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #1: shift_operand with registers 111a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 112a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 113a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This 'addressing mode' is used for arithmetic instructions. It can 114a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // represent things like: 115a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg 116a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg [asr|lsl|lsr|ror|rrx] reg 117a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg [asr|lsl|lsr|ror|rrx] imm 118a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 119a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is stored three operands [rega, regb, opc]. The first is the base 120a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg, the second is the shift amount (or reg0 if not present or imm). The 121a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // third operand encodes the shift opcode and the imm if a reg isn't present. 122a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 123a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 124a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ShOp | (Imm << 3); 125a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 126a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSORegOffset(unsigned Op) { 127a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return Op >> 3; 128a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 129a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline ShiftOpc getSORegShOp(unsigned Op) { 130a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (ShiftOpc)(Op & 7); 131a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 132a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 133a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 134a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// the 8-bit imm value. 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValImm(unsigned Imm) { 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return Imm & 0xFF; 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 138d83712ad678ae453f3342762c78142f851d3a2d3Bob Wilson /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return 139a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// the rotate amount. 140a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValRot(unsigned Imm) { 141a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (Imm >> 8) * 2; 142a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 143764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 144a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 145a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// computing the rotate amount to use. If this immediate value cannot be 146a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// handled with a single shifter-op, determine a good rotate amount that will 147a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// take a maximal chunk of bits out of the immediate. 148a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmValRotate(unsigned Imm) { 149a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially shifter_operands with a rotate 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Imm & ~255U) == 0) return 0; 152764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 153a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use CTZ to compute the rotate amount. 154a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned TZ = CountTrailingZeros_32(Imm); 155764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 156a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // not 9. 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned RotAmt = TZ & ~1; 159764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 160a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If we can handle this spread, return it. 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((rotr32(Imm, RotAmt) & ~255U) == 0) 162a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (32-RotAmt)&31; // HW rotates right, not left. 163a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1648a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen // For values like 0xF000000F, we should ignore the low 6 bits, then 165a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // retry the hunt. 1668a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen if (Imm & 63U) { 1678a87ffb9252d6d66093dcd96f3b9a496dae4a439Johnny Chen unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U); 168b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson unsigned RotAmt2 = TZ2 & ~1; 169b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson if ((rotr32(Imm, RotAmt2) & ~255U) == 0) 170b123b8bee0b2c3f5e296ef7ca067e20982a7dbc8Bob Wilson return (32-RotAmt2)&31; // HW rotates right, not left. 171a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 172764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Otherwise, we have no way to cover this span of bits with a single 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // shifter_op immediate. Return a chunk of bits that will be useful to 175a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // handle. 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (32-RotAmt)&31; // HW rotates right, not left. 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 178a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 179a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit 180a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// into an shifter_operand immediate operand, return the 12-bit encoding for 181a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// it. If not, return -1. 182a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline int getSOImmVal(unsigned Arg) { 183a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially shifter_operands with a rotate 184a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 185a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Arg & ~255U) == 0) return Arg; 186764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 187e6f83878bc7cc26ae2fcf3112e6a9fe687e8eba6Johnny Chen unsigned RotAmt = getSOImmValRotate(Arg); 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 189a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this cannot be handled with a single shifter_op, bail out. 190a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (rotr32(~255U, RotAmt) & Arg) 191a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return -1; 192764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 193a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Encode this correctly. 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 196764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 197a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isSOImmTwoPartVal - Return true if the specified value can be obtained by 198a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// or'ing together two SOImmVal's. 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline bool isSOImmTwoPartVal(unsigned V) { 200a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this can be handled with a single shifter_op, bail out. 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if (V == 0) 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return false; 204764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this can be handled with two shifter_op's, accept. 206a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V == 0; 208a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 209764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// return the first chunk of it. 212a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmTwoPartFirst(unsigned V) { 213a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return rotr32(255U, getSOImmValRotate(V)) & V; 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// return the second chunk of it. 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getSOImmTwoPartSecond(unsigned V) { 219764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // Mask out the first hunk. 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = rotr32(~255U, getSOImmValRotate(V)) & V; 221764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Take what's left. 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V; 225a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 226764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 227a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// by a left shift. Returns the shift amount to use. 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getThumbImmValShift(unsigned Imm) { 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 8-bit (or less) immediates are trivially immediate operand with a shift 231a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // of zero. 232a8e2989ece6dc46df59b0768184028257f913843Evan Cheng if ((Imm & ~255U) == 0) return 0; 233a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 234a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Use CTZ to compute the shift amount. 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return CountTrailingZeros_32(Imm); 236a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isThumbImmShiftedVal - Return true if the specified value can be obtained 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// by left shifting a 8-bit immediate. 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline bool isThumbImmShiftedVal(unsigned V) { 241764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // If this can be handled with 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng V = (~255U << getThumbImmValShift(V)) & V; 243a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V == 0; 244a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 245a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 246f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed 247f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// by a left shift. Returns the shift amount to use. 248f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline unsigned getThumbImm16ValShift(unsigned Imm) { 249f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // 16-bit (or less) immediates are trivially immediate operand with a shift 250f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // of zero. 251f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if ((Imm & ~65535U) == 0) return 0; 252f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 253f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Use CTZ to compute the shift amount. 254f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return CountTrailingZeros_32(Imm); 255f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 256f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 257764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach /// isThumbImm16ShiftedVal - Return true if the specified value can be 258f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// obtained by left shifting a 16-bit immediate. 259f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline bool isThumbImm16ShiftedVal(unsigned V) { 260764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // If this can be handled with 261f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng V = (~65535U << getThumbImm16ValShift(V)) & V; 262f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return V == 0; 263f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 264f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 265a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getThumbImmNonShiftedVal - If V is a value that satisfies 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// isThumbImmShiftedVal, return the non-shiftd value. 267a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getThumbImmNonShiftedVal(unsigned V) { 268a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return V >> getThumbImmValShift(V); 269a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 270a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 2716495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng 272f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getT2SOImmValSplat - Return the 12-bit encoded representation 273f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// if the specified value can be obtained by splatting the low 8 bits 274f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// into every other byte or every byte of a 32-bit value. i.e., 275f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// 00000000 00000000 00000000 abcdefgh control = 0 276f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// 00000000 abcdefgh 00000000 abcdefgh control = 1 277f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// abcdefgh 00000000 abcdefgh 00000000 control = 2 278f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 279f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// Return -1 if none of the above apply. 280f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 2816495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng static inline int getT2SOImmValSplatVal(unsigned V) { 282f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng unsigned u, Vs, Imm; 283f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 0 284764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach if ((V & 0xffffff00) == 0) 285f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return V; 286764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 287f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If the value is zeroes in the first byte, just shift those off 288f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng Vs = ((V & 0xff) == 0) ? V >> 8 : V; 289f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Any passing value only has 8 bits of payload, splatted across the word 290f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng Imm = Vs & 0xff; 291f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // Likewise, any passing values have the payload splatted into the 3rd byte 292f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng u = Imm | (Imm << 16); 293f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 294f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 1 or 2 295f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Vs == u) 296f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (((Vs == V) ? 1 : 2) << 8) | Imm; 297f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 298f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // control = 3 299f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Vs == (u | (u << 8))) 300f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (3 << 8) | Imm; 301f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 302f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 303f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 304f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 3056495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng /// getT2SOImmValRotateVal - Return the 12-bit encoded representation if the 306f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// specified value is a rotated 8-bit value. Return -1 if no rotation 307f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// encoding is possible. 308f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 3096495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng static inline int getT2SOImmValRotateVal(unsigned V) { 310f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng unsigned RotAmt = CountLeadingZeros_32(V); 311f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (RotAmt >= 24) 312f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 313f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 314f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' can be handled with a single shifter_op return the value. 315f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if ((rotr32(0xff000000U, RotAmt) & V) == V) 316f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); 317f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 318f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 319f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 320f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 321f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit 322764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit 323f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// encoding for it. If not, return -1. 324f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng /// See ARM Reference Manual A6.3.2. 325f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng static inline int getT2SOImmVal(unsigned Arg) { 326f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' is an 8-bit splat, then get the encoded value. 3276495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int Splat = getT2SOImmValSplatVal(Arg); 328f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Splat != -1) 329f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return Splat; 330764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 331f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng // If 'Arg' can be handled with a single shifter_op return the value. 3326495f63945e8dbde81f03a1dc2ab421993b9a495Evan Cheng int Rot = getT2SOImmValRotateVal(Arg); 333f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng if (Rot != -1) 334f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return Rot; 335f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 336f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng return -1; 337f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng } 338764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 33965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmValRotate(unsigned V) { 34065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if ((V & ~255U) == 0) return 0; 34165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Use CTZ to compute the rotate amount. 34265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned RotAmt = CountTrailingZeros_32(V); 34365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return (32 - RotAmt) & 31; 34465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 34565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 34665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline bool isT2SOImmTwoPartVal (unsigned Imm) { 34765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned V = Imm; 34865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Passing values can be any combination of splat values and shifter 34965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // values. If this can be handled with a single shifter or splat, bail 35065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // out. Those should be handled directly, not with a two-part val. 35165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(V) != -1) 35265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 35365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V = rotr32 (~255U, getT2SOImmValRotate(V)) & V; 35465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (V == 0) 35565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 35665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 35765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If this can be handled as an immediate, accept. 35865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return true; 35965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 36065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Likewise, try masking out a splat value first. 36165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V = Imm; 36265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1) 36365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V &= ~0xff00ff00U; 36465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1) 36565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach V &= ~0x00ff00ffU; 36665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If what's left can be handled as an immediate, accept. 36765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return true; 36865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 36965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Otherwise, do not accept. 37065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return false; 37165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 37265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 37365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) { 37465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (isT2SOImmTwoPartVal(Imm) && 37565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach "Immedate cannot be encoded as two part immediate!"); 37665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Try a shifter operand as one part 37765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm; 37865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // If the rest is encodable as an immediate, then return it. 37965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmVal(V) != -1) return V; 38065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 38165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Try masking out a splat value first. 38265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1) 38365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm & 0xff00ff00U; 38465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 38565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // The other splat is all that's left as an option. 38665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1); 38765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm & 0x00ff00ffU; 38865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 38965b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 39065b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) { 39165b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Mask out the first hunk 39265b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach Imm ^= getT2SOImmTwoPartFirst(Imm); 39365b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach // Return what's left 39465b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach assert (getT2SOImmVal(Imm) != -1 && 39565b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach "Unable to encode second part of T2 two part SO immediate"); 39665b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach return Imm; 39765b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach } 39865b7f3af76d0ba5bce49b56ab3e18f970b95f9d1Jim Grosbach 399f49810c7e60807c43a68ab02c936a4ee77a4d2cfEvan Cheng 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 401a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #2 402a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 403a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 404a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for most simple load/store instructions. 405a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 406a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode2 := reg +/- reg shop imm 407a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode2 := reg +/- imm12 408a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 409a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The first operand is always a Reg. The second operand is a reg if in 410a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg/reg form, otherwise it's reg#0. The third field encodes the operation 411ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The 412ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // fourth operand 16-17 encodes the index mode. 413a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 414a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // If this addressing mode is a frame index (before prolog/epilog insertion 415a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // and code rewriting), this operand will have the form: FI#, reg0, <offs> 416a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // with no shift amount for the frame offset. 417764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach // 418ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, 419ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes unsigned IdxMode = 0) { 420a8e2989ece6dc46df59b0768184028257f913843Evan Cheng assert(Imm12 < (1 << 12) && "Imm too large!"); 421a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 422ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ; 423a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 424a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getAM2Offset(unsigned AM2Opc) { 425a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM2Opc & ((1 << 12)-1); 426a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 427a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM2Op(unsigned AM2Opc) { 428a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM2Opc >> 12) & 1) ? sub : add; 429a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 430a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { 431ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return (ShiftOpc)((AM2Opc >> 13) & 7); 432ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes } 433ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes static inline unsigned getAM2IdxMode(unsigned AM2Opc) { 434ae0855401b8c80f96904b6808b0bc4c89216aecdBruno Cardoso Lopes return (AM2Opc >> 16); 435a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 436764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 437764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 438a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 439a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #3 440a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 441a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 442a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for sign-extending loads, and load/store-pair instructions. 443a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 444a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode3 := reg +/- reg 445a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode3 := reg +/- imm8 446a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 447a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The first operand is always a Reg. The second operand is a reg if in 448a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // reg/reg form, otherwise it's reg#0. The third field encodes the operation 449ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the 450ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes // index mode. 451764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 452a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getAM3Opc - This function encodes the addrmode3 opc field. 453ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, 454ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes unsigned IdxMode = 0) { 455a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 456ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return ((int)isSub << 8) | Offset | (IdxMode << 9); 457a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 458a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned char getAM3Offset(unsigned AM3Opc) { 459a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM3Opc & 0xFF; 460a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 461a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM3Op(unsigned AM3Opc) { 462a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM3Opc >> 8) & 1) ? sub : add; 463a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 464ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes static inline unsigned getAM3IdxMode(unsigned AM3Opc) { 465ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes return (AM3Opc >> 9); 466ac79e4c82f201c30a06c2cd05baebd20f5b49888Bruno Cardoso Lopes } 467764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 468a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 469a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #4 470a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 471a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 472a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for load / store multiple instructions. 473a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 474a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode4 := reg, <mode> 475a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 476a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // The four modes are: 477a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // IA - Increment after 478a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // IB - Increment before 479a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // DA - Decrement after 480a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // DB - Decrement before 481d4bfd54ec2947e73ab152c3c548e4dd4beb700baBob Wilson // For VFP instructions, only the IA and DB modes are valid. 482a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 483a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AMSubMode getAM4SubMode(unsigned Mode) { 484a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return (AMSubMode)(Mode & 0x7); 485a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 486a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 487ab3460519e8013cdba33a416cefd55dfb418999cBob Wilson static inline unsigned getAM4ModeImm(AMSubMode SubMode) { 488ab3460519e8013cdba33a416cefd55dfb418999cBob Wilson return (int)SubMode; 489a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 490a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 491a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 492a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // Addressing Mode #5 493a8e2989ece6dc46df59b0768184028257f913843Evan Cheng //===--------------------------------------------------------------------===// 494a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 495a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // This is used for coprocessor instructions, such as FP load/stores. 496a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 497a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // addrmode5 := reg +/- imm8*4 498a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // 499d4d826e17081808fea81509a959a983ed5df1d36Bob Wilson // The first operand is always a Reg. The second operand encodes the 500d4d826e17081808fea81509a959a983ed5df1d36Bob Wilson // operation in bit 8 and the immediate in bits 0-7. 501764ab52dd80310a205c9888bf166d09dab858f90Jim Grosbach 502a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getAM5Opc - This function encodes the addrmode5 opc field. 503a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { 504a8e2989ece6dc46df59b0768184028257f913843Evan Cheng bool isSub = Opc == sub; 505a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((int)isSub << 8) | Offset; 506a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 507a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline unsigned char getAM5Offset(unsigned AM5Opc) { 508a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return AM5Opc & 0xFF; 509a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 510a8e2989ece6dc46df59b0768184028257f913843Evan Cheng static inline AddrOpc getAM5Op(unsigned AM5Opc) { 511a8e2989ece6dc46df59b0768184028257f913843Evan Cheng return ((AM5Opc >> 8) & 1) ? sub : add; 512a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 513a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 5148b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson //===--------------------------------------------------------------------===// 5158b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // Addressing Mode #6 5168b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson //===--------------------------------------------------------------------===// 5178b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 5188b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // This is used for NEON load / store instructions. 5198b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 520226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // addrmode6 := reg with optional alignment 5218b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson // 522226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // This is stored in two operands [regaddr, align]. The first is the 523226036ee731a2041f37f28f958d2b6a50373f4f4Bob Wilson // address register. The second operand is the value of the alignment 524273ff31e134d48c8247e981d30e214e82568ff86Bob Wilson // specifier in bytes or zero if no explicit alignment. 525273ff31e134d48c8247e981d30e214e82568ff86Bob Wilson // Valid alignments depend on the specific instruction. 5268b024a5eb5b64b482f7d92aad7a3f0e6cac93f12Bob Wilson 5276dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson //===--------------------------------------------------------------------===// 5286dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // NEON Modified Immediates 5296dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson //===--------------------------------------------------------------------===// 5306dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 5316dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // Several NEON instructions (e.g., VMOV) take a "modified immediate" 5326dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // vector operand, where a small immediate encoded in the instruction 5336dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // specifies a full NEON vector value. These modified immediates are 5346dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // represented here as encoded integers. The low 8 bits hold the immediate 5356dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // value; bit 12 holds the "Op" field of the instruction, and bits 11-8 hold 5366dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // the "Cmode" field of the instruction. The interfaces below treat the 5376dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // Op and Cmode values as a single 5-bit value. 5386dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5396dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned createNEONModImm(unsigned OpCmode, unsigned Val) { 5406dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return (OpCmode << 8) | Val; 5416dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5426dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned getNEONModImmOpCmode(unsigned ModImm) { 5436dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return (ModImm >> 8) & 0x1f; 5446dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5456dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline unsigned getNEONModImmVal(unsigned ModImm) { 5466dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return ModImm & 0xff; 5476dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5486dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5496dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// decodeNEONModImm - Decode a NEON modified immediate value into the 5506dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// element value and the element size in bits. (If the element size is 5516dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson /// smaller than the vector, it is splatted into all the elements.) 5526dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson static inline uint64_t decodeNEONModImm(unsigned ModImm, unsigned &EltBits) { 5536dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned OpCmode = getNEONModImmOpCmode(ModImm); 5546dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned Imm8 = getNEONModImmVal(ModImm); 5556dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson uint64_t Val = 0; 5566dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5576dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson if (OpCmode == 0xe) { 5586dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 8-bit vector elements 5596dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8; 5606dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 8; 5616dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0xc) == 0x8) { 5626dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 16-bit vector elements 5636dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = (OpCmode & 0x6) >> 1; 5646dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8 << (8 * ByteNum); 5656dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 16; 5666dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0x8) == 0) { 5676dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 32-bit vector elements, zero with one byte set 5686dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = (OpCmode & 0x6) >> 1; 5696dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = Imm8 << (8 * ByteNum); 5706dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 32; 5716dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if ((OpCmode & 0xe) == 0xc) { 5726dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 32-bit vector elements, one byte with low bits set 5736dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson unsigned ByteNum = 1 + (OpCmode & 0x1); 5746dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum))); 5756dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 32; 5766dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else if (OpCmode == 0x1e) { 5776dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson // 64-bit vector elements 5786dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson for (unsigned ByteNum = 0; ByteNum < 8; ++ByteNum) { 5796dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson if ((ModImm >> ByteNum) & 1) 5806dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson Val |= (uint64_t)0xff << (8 * ByteNum); 5816dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5826dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson EltBits = 64; 5836dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } else { 5846dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson assert(false && "Unsupported NEON immediate"); 5856dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5866dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson return Val; 5876dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson } 5886dce00ced45b5bd1b7f34fe6f2d70c50fc090664Bob Wilson 5892567eec4233d58a2a0cbdcafca9420452689b395Bill Wendling AMSubMode getLoadStoreMultipleSubMode(int Opcode); 5902567eec4233d58a2a0cbdcafca9420452689b395Bill Wendling 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} // end namespace ARM_AM 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} // end namespace llvm 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 594a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif 595a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 596