ARMAddressingModes.h revision f49810c7e60807c43a68ab02c936a4ee77a4d2cf
1//===- ARMAddressingModes.h - ARM Addressing Modes --------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the ARM addressing mode implementation stuff. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 15#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H 16 17#include "llvm/CodeGen/SelectionDAGNodes.h" 18#include "llvm/Support/MathExtras.h" 19#include <cassert> 20 21namespace llvm { 22 23/// ARM_AM - ARM Addressing Mode Stuff 24namespace ARM_AM { 25 enum ShiftOpc { 26 no_shift = 0, 27 asr, 28 lsl, 29 lsr, 30 ror, 31 rrx 32 }; 33 34 enum AddrOpc { 35 add = '+', sub = '-' 36 }; 37 38 static inline const char *getShiftOpcStr(ShiftOpc Op) { 39 switch (Op) { 40 default: assert(0 && "Unknown shift opc!"); 41 case ARM_AM::asr: return "asr"; 42 case ARM_AM::lsl: return "lsl"; 43 case ARM_AM::lsr: return "lsr"; 44 case ARM_AM::ror: return "ror"; 45 case ARM_AM::rrx: return "rrx"; 46 } 47 } 48 49 static inline ShiftOpc getShiftOpcForNode(SDValue N) { 50 switch (N.getOpcode()) { 51 default: return ARM_AM::no_shift; 52 case ISD::SHL: return ARM_AM::lsl; 53 case ISD::SRL: return ARM_AM::lsr; 54 case ISD::SRA: return ARM_AM::asr; 55 case ISD::ROTR: return ARM_AM::ror; 56 //case ISD::ROTL: // Only if imm -> turn into ROTR. 57 // Can't handle RRX here, because it would require folding a flag into 58 // the addressing mode. :( This causes us to miss certain things. 59 //case ARMISD::RRX: return ARM_AM::rrx; 60 } 61 } 62 63 enum AMSubMode { 64 bad_am_submode = 0, 65 ia, 66 ib, 67 da, 68 db 69 }; 70 71 static inline const char *getAMSubModeStr(AMSubMode Mode) { 72 switch (Mode) { 73 default: assert(0 && "Unknown addressing sub-mode!"); 74 case ARM_AM::ia: return "ia"; 75 case ARM_AM::ib: return "ib"; 76 case ARM_AM::da: return "da"; 77 case ARM_AM::db: return "db"; 78 } 79 } 80 81 static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) { 82 switch (Mode) { 83 default: assert(0 && "Unknown addressing sub-mode!"); 84 case ARM_AM::ia: return isLD ? "fd" : "ea"; 85 case ARM_AM::ib: return isLD ? "ed" : "fa"; 86 case ARM_AM::da: return isLD ? "fa" : "ed"; 87 case ARM_AM::db: return isLD ? "ea" : "fd"; 88 } 89 } 90 91 /// rotr32 - Rotate a 32-bit unsigned value right by a specified # bits. 92 /// 93 static inline unsigned rotr32(unsigned Val, unsigned Amt) { 94 assert(Amt < 32 && "Invalid rotate amount"); 95 return (Val >> Amt) | (Val << ((32-Amt)&31)); 96 } 97 98 /// rotl32 - Rotate a 32-bit unsigned value left by a specified # bits. 99 /// 100 static inline unsigned rotl32(unsigned Val, unsigned Amt) { 101 assert(Amt < 32 && "Invalid rotate amount"); 102 return (Val << Amt) | (Val >> ((32-Amt)&31)); 103 } 104 105 //===--------------------------------------------------------------------===// 106 // Addressing Mode #1: shift_operand with registers 107 //===--------------------------------------------------------------------===// 108 // 109 // This 'addressing mode' is used for arithmetic instructions. It can 110 // represent things like: 111 // reg 112 // reg [asr|lsl|lsr|ror|rrx] reg 113 // reg [asr|lsl|lsr|ror|rrx] imm 114 // 115 // This is stored three operands [rega, regb, opc]. The first is the base 116 // reg, the second is the shift amount (or reg0 if not present or imm). The 117 // third operand encodes the shift opcode and the imm if a reg isn't present. 118 // 119 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { 120 return ShOp | (Imm << 3); 121 } 122 static inline unsigned getSORegOffset(unsigned Op) { 123 return Op >> 3; 124 } 125 static inline ShiftOpc getSORegShOp(unsigned Op) { 126 return (ShiftOpc)(Op & 7); 127 } 128 129 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return 130 /// the 8-bit imm value. 131 static inline unsigned getSOImmValImm(unsigned Imm) { 132 return Imm & 0xFF; 133 } 134 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return 135 /// the rotate amount. 136 static inline unsigned getSOImmValRot(unsigned Imm) { 137 return (Imm >> 8) * 2; 138 } 139 140 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand, 141 /// computing the rotate amount to use. If this immediate value cannot be 142 /// handled with a single shifter-op, determine a good rotate amount that will 143 /// take a maximal chunk of bits out of the immediate. 144 static inline unsigned getSOImmValRotate(unsigned Imm) { 145 // 8-bit (or less) immediates are trivially shifter_operands with a rotate 146 // of zero. 147 if ((Imm & ~255U) == 0) return 0; 148 149 // Use CTZ to compute the rotate amount. 150 unsigned TZ = CountTrailingZeros_32(Imm); 151 152 // Rotate amount must be even. Something like 0x200 must be rotated 8 bits, 153 // not 9. 154 unsigned RotAmt = TZ & ~1; 155 156 // If we can handle this spread, return it. 157 if ((rotr32(Imm, RotAmt) & ~255U) == 0) 158 return (32-RotAmt)&31; // HW rotates right, not left. 159 160 // For values like 0xF000000F, we should skip the first run of ones, then 161 // retry the hunt. 162 if (Imm & 1) { 163 unsigned TrailingOnes = CountTrailingZeros_32(~Imm); 164 if (TrailingOnes != 32) { // Avoid overflow on 0xFFFFFFFF 165 // Restart the search for a high-order bit after the initial seconds of 166 // ones. 167 unsigned TZ2 = CountTrailingZeros_32(Imm & ~((1 << TrailingOnes)-1)); 168 169 // Rotate amount must be even. 170 unsigned RotAmt2 = TZ2 & ~1; 171 172 // If this fits, use it. 173 if (RotAmt2 != 32 && (rotr32(Imm, RotAmt2) & ~255U) == 0) 174 return (32-RotAmt2)&31; // HW rotates right, not left. 175 } 176 } 177 178 // Otherwise, we have no way to cover this span of bits with a single 179 // shifter_op immediate. Return a chunk of bits that will be useful to 180 // handle. 181 return (32-RotAmt)&31; // HW rotates right, not left. 182 } 183 184 /// getSOImmVal - Given a 32-bit immediate, if it is something that can fit 185 /// into an shifter_operand immediate operand, return the 12-bit encoding for 186 /// it. If not, return -1. 187 static inline int getSOImmVal(unsigned Arg) { 188 // 8-bit (or less) immediates are trivially shifter_operands with a rotate 189 // of zero. 190 if ((Arg & ~255U) == 0) return Arg; 191 192 unsigned RotAmt = getSOImmValRotate(Arg); 193 194 // If this cannot be handled with a single shifter_op, bail out. 195 if (rotr32(~255U, RotAmt) & Arg) 196 return -1; 197 198 // Encode this correctly. 199 return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8); 200 } 201 202 /// isSOImmTwoPartVal - Return true if the specified value can be obtained by 203 /// or'ing together two SOImmVal's. 204 static inline bool isSOImmTwoPartVal(unsigned V) { 205 // If this can be handled with a single shifter_op, bail out. 206 V = rotr32(~255U, getSOImmValRotate(V)) & V; 207 if (V == 0) 208 return false; 209 210 // If this can be handled with two shifter_op's, accept. 211 V = rotr32(~255U, getSOImmValRotate(V)) & V; 212 return V == 0; 213 } 214 215 /// getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, 216 /// return the first chunk of it. 217 static inline unsigned getSOImmTwoPartFirst(unsigned V) { 218 return rotr32(255U, getSOImmValRotate(V)) & V; 219 } 220 221 /// getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, 222 /// return the second chunk of it. 223 static inline unsigned getSOImmTwoPartSecond(unsigned V) { 224 // Mask out the first hunk. 225 V = rotr32(~255U, getSOImmValRotate(V)) & V; 226 227 // Take what's left. 228 assert(V == (rotr32(255U, getSOImmValRotate(V)) & V)); 229 return V; 230 } 231 232 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed 233 /// by a left shift. Returns the shift amount to use. 234 static inline unsigned getThumbImmValShift(unsigned Imm) { 235 // 8-bit (or less) immediates are trivially immediate operand with a shift 236 // of zero. 237 if ((Imm & ~255U) == 0) return 0; 238 239 // Use CTZ to compute the shift amount. 240 return CountTrailingZeros_32(Imm); 241 } 242 243 /// isThumbImmShiftedVal - Return true if the specified value can be obtained 244 /// by left shifting a 8-bit immediate. 245 static inline bool isThumbImmShiftedVal(unsigned V) { 246 // If this can be handled with 247 V = (~255U << getThumbImmValShift(V)) & V; 248 return V == 0; 249 } 250 251 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed 252 /// by a left shift. Returns the shift amount to use. 253 static inline unsigned getThumbImm16ValShift(unsigned Imm) { 254 // 16-bit (or less) immediates are trivially immediate operand with a shift 255 // of zero. 256 if ((Imm & ~65535U) == 0) return 0; 257 258 // Use CTZ to compute the shift amount. 259 return CountTrailingZeros_32(Imm); 260 } 261 262 /// isThumbImm16ShiftedVal - Return true if the specified value can be 263 /// obtained by left shifting a 16-bit immediate. 264 static inline bool isThumbImm16ShiftedVal(unsigned V) { 265 // If this can be handled with 266 V = (~65535U << getThumbImm16ValShift(V)) & V; 267 return V == 0; 268 } 269 270 /// getThumbImmNonShiftedVal - If V is a value that satisfies 271 /// isThumbImmShiftedVal, return the non-shiftd value. 272 static inline unsigned getThumbImmNonShiftedVal(unsigned V) { 273 return V >> getThumbImmValShift(V); 274 } 275 276 /// getT2SOImmValDecode - Given a 12-bit encoded Thumb-2 modified immediate, 277 /// return the corresponding 32-bit immediate value. 278 /// See ARM Reference Manual A6.3.2. 279 static inline unsigned getT2SOImmValDecode(unsigned Imm) { 280 unsigned Base = Imm & 0xff; 281 switch ((Imm >> 8) & 0xf) { 282 case 0: 283 return Base; 284 case 1: 285 return Base | (Base << 16); 286 case 2: 287 return (Base << 8) | (Base << 24); 288 case 3: 289 return Base | (Base << 8) | (Base << 16) | (Base << 24); 290 default: 291 break; 292 } 293 294 // shifted immediate 295 unsigned RotAmount = ((Imm >> 7) & 0x1f) - 8; 296 return (Base | 0x80) << (24 - RotAmount); 297 } 298 299 /// getT2SOImmValSplat - Return the 12-bit encoded representation 300 /// if the specified value can be obtained by splatting the low 8 bits 301 /// into every other byte or every byte of a 32-bit value. i.e., 302 /// 00000000 00000000 00000000 abcdefgh control = 0 303 /// 00000000 abcdefgh 00000000 abcdefgh control = 1 304 /// abcdefgh 00000000 abcdefgh 00000000 control = 2 305 /// abcdefgh abcdefgh abcdefgh abcdefgh control = 3 306 /// Return -1 if none of the above apply. 307 /// See ARM Reference Manual A6.3.2. 308 static inline int getT2SOImmValSplat (unsigned V) { 309 unsigned u, Vs, Imm; 310 // control = 0 311 if ((V & 0xffffff00) == 0) 312 return V; 313 314 // If the value is zeroes in the first byte, just shift those off 315 Vs = ((V & 0xff) == 0) ? V >> 8 : V; 316 // Any passing value only has 8 bits of payload, splatted across the word 317 Imm = Vs & 0xff; 318 // Likewise, any passing values have the payload splatted into the 3rd byte 319 u = Imm | (Imm << 16); 320 321 // control = 1 or 2 322 if (Vs == u) 323 return (((Vs == V) ? 1 : 2) << 8) | Imm; 324 325 // control = 3 326 if (Vs == (u | (u << 8))) 327 return (3 << 8) | Imm; 328 329 return -1; 330 } 331 332 /// getT2SOImmValRotate - Return the 12-bit encoded representation if the 333 /// specified value is a rotated 8-bit value. Return -1 if no rotation 334 /// encoding is possible. 335 /// See ARM Reference Manual A6.3.2. 336 static inline int getT2SOImmValRotate (unsigned V) { 337 unsigned RotAmt = CountLeadingZeros_32(V); 338 if (RotAmt >= 24) 339 return -1; 340 341 // If 'Arg' can be handled with a single shifter_op return the value. 342 if ((rotr32(0xff000000U, RotAmt) & V) == V) 343 return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7); 344 345 return -1; 346 } 347 348 /// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit 349 /// into a Thumb-2 shifter_operand immediate operand, return the 12-bit 350 /// encoding for it. If not, return -1. 351 /// See ARM Reference Manual A6.3.2. 352 static inline int getT2SOImmVal(unsigned Arg) { 353 // If 'Arg' is an 8-bit splat, then get the encoded value. 354 int Splat = getT2SOImmValSplat(Arg); 355 if (Splat != -1) 356 return Splat; 357 358 // If 'Arg' can be handled with a single shifter_op return the value. 359 int Rot = getT2SOImmValRotate(Arg); 360 if (Rot != -1) 361 return Rot; 362 363 return -1; 364 } 365 366 367 //===--------------------------------------------------------------------===// 368 // Addressing Mode #2 369 //===--------------------------------------------------------------------===// 370 // 371 // This is used for most simple load/store instructions. 372 // 373 // addrmode2 := reg +/- reg shop imm 374 // addrmode2 := reg +/- imm12 375 // 376 // The first operand is always a Reg. The second operand is a reg if in 377 // reg/reg form, otherwise it's reg#0. The third field encodes the operation 378 // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. 379 // 380 // If this addressing mode is a frame index (before prolog/epilog insertion 381 // and code rewriting), this operand will have the form: FI#, reg0, <offs> 382 // with no shift amount for the frame offset. 383 // 384 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO) { 385 assert(Imm12 < (1 << 12) && "Imm too large!"); 386 bool isSub = Opc == sub; 387 return Imm12 | ((int)isSub << 12) | (SO << 13); 388 } 389 static inline unsigned getAM2Offset(unsigned AM2Opc) { 390 return AM2Opc & ((1 << 12)-1); 391 } 392 static inline AddrOpc getAM2Op(unsigned AM2Opc) { 393 return ((AM2Opc >> 12) & 1) ? sub : add; 394 } 395 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { 396 return (ShiftOpc)(AM2Opc >> 13); 397 } 398 399 400 //===--------------------------------------------------------------------===// 401 // Addressing Mode #3 402 //===--------------------------------------------------------------------===// 403 // 404 // This is used for sign-extending loads, and load/store-pair instructions. 405 // 406 // addrmode3 := reg +/- reg 407 // addrmode3 := reg +/- imm8 408 // 409 // The first operand is always a Reg. The second operand is a reg if in 410 // reg/reg form, otherwise it's reg#0. The third field encodes the operation 411 // in bit 8, the immediate in bits 0-7. 412 413 /// getAM3Opc - This function encodes the addrmode3 opc field. 414 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) { 415 bool isSub = Opc == sub; 416 return ((int)isSub << 8) | Offset; 417 } 418 static inline unsigned char getAM3Offset(unsigned AM3Opc) { 419 return AM3Opc & 0xFF; 420 } 421 static inline AddrOpc getAM3Op(unsigned AM3Opc) { 422 return ((AM3Opc >> 8) & 1) ? sub : add; 423 } 424 425 //===--------------------------------------------------------------------===// 426 // Addressing Mode #4 427 //===--------------------------------------------------------------------===// 428 // 429 // This is used for load / store multiple instructions. 430 // 431 // addrmode4 := reg, <mode> 432 // 433 // The four modes are: 434 // IA - Increment after 435 // IB - Increment before 436 // DA - Decrement after 437 // DB - Decrement before 438 // 439 // If the 4th bit (writeback)is set, then the base register is updated after 440 // the memory transfer. 441 442 static inline AMSubMode getAM4SubMode(unsigned Mode) { 443 return (AMSubMode)(Mode & 0x7); 444 } 445 446 static inline unsigned getAM4ModeImm(AMSubMode SubMode, bool WB = false) { 447 return (int)SubMode | ((int)WB << 3); 448 } 449 450 static inline bool getAM4WBFlag(unsigned Mode) { 451 return (Mode >> 3) & 1; 452 } 453 454 //===--------------------------------------------------------------------===// 455 // Addressing Mode #5 456 //===--------------------------------------------------------------------===// 457 // 458 // This is used for coprocessor instructions, such as FP load/stores. 459 // 460 // addrmode5 := reg +/- imm8*4 461 // 462 // The first operand is always a Reg. The third field encodes the operation 463 // in bit 8, the immediate in bits 0-7. 464 // 465 // This can also be used for FP load/store multiple ops. The third field encodes 466 // writeback mode in bit 8, the number of registers (or 2 times the number of 467 // registers for DPR ops) in bits 0-7. In addition, bit 9-11 encodes one of the 468 // following two sub-modes: 469 // 470 // IA - Increment after 471 // DB - Decrement before 472 473 /// getAM5Opc - This function encodes the addrmode5 opc field. 474 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { 475 bool isSub = Opc == sub; 476 return ((int)isSub << 8) | Offset; 477 } 478 static inline unsigned char getAM5Offset(unsigned AM5Opc) { 479 return AM5Opc & 0xFF; 480 } 481 static inline AddrOpc getAM5Op(unsigned AM5Opc) { 482 return ((AM5Opc >> 8) & 1) ? sub : add; 483 } 484 485 /// getAM5Opc - This function encodes the addrmode5 opc field for FLDM and 486 /// FSTM instructions. 487 static inline unsigned getAM5Opc(AMSubMode SubMode, bool WB, 488 unsigned char Offset) { 489 assert((SubMode == ia || SubMode == db) && 490 "Illegal addressing mode 5 sub-mode!"); 491 return ((int)SubMode << 9) | ((int)WB << 8) | Offset; 492 } 493 static inline AMSubMode getAM5SubMode(unsigned AM5Opc) { 494 return (AMSubMode)((AM5Opc >> 9) & 0x7); 495 } 496 static inline bool getAM5WBFlag(unsigned AM5Opc) { 497 return ((AM5Opc >> 8) & 1); 498 } 499 500} // end namespace ARM_AM 501} // end namespace llvm 502 503#endif 504 505