1//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the X86 machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "x86-emitter" 16#include "X86InstrInfo.h" 17#include "X86JITInfo.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "X86Relocations.h" 21#include "X86.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/PassManager.h" 24#include "llvm/CodeGen/JITCodeEmitter.h" 25#include "llvm/CodeGen/MachineFunctionPass.h" 26#include "llvm/CodeGen/MachineInstr.h" 27#include "llvm/CodeGen/MachineModuleInfo.h" 28#include "llvm/CodeGen/Passes.h" 29#include "llvm/Function.h" 30#include "llvm/ADT/Statistic.h" 31#include "llvm/MC/MCCodeEmitter.h" 32#include "llvm/MC/MCExpr.h" 33#include "llvm/MC/MCInst.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#include "llvm/Target/TargetOptions.h" 38using namespace llvm; 39 40STATISTIC(NumEmitted, "Number of machine instructions emitted"); 41 42namespace { 43 template<class CodeEmitter> 44 class Emitter : public MachineFunctionPass { 45 const X86InstrInfo *II; 46 const TargetData *TD; 47 X86TargetMachine &TM; 48 CodeEmitter &MCE; 49 MachineModuleInfo *MMI; 50 intptr_t PICBaseOffset; 51 bool Is64BitMode; 52 bool IsPIC; 53 public: 54 static char ID; 55 explicit Emitter(X86TargetMachine &tm, CodeEmitter &mce) 56 : MachineFunctionPass(ID), II(0), TD(0), TM(tm), 57 MCE(mce), PICBaseOffset(0), Is64BitMode(false), 58 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 59 Emitter(X86TargetMachine &tm, CodeEmitter &mce, 60 const X86InstrInfo &ii, const TargetData &td, bool is64) 61 : MachineFunctionPass(ID), II(&ii), TD(&td), TM(tm), 62 MCE(mce), PICBaseOffset(0), Is64BitMode(is64), 63 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 64 65 bool runOnMachineFunction(MachineFunction &MF); 66 67 virtual const char *getPassName() const { 68 return "X86 Machine Code Emitter"; 69 } 70 71 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); 72 73 void getAnalysisUsage(AnalysisUsage &AU) const { 74 AU.setPreservesAll(); 75 AU.addRequired<MachineModuleInfo>(); 76 MachineFunctionPass::getAnalysisUsage(AU); 77 } 78 79 private: 80 void emitPCRelativeBlockAddress(MachineBasicBlock *MBB); 81 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 82 intptr_t Disp = 0, intptr_t PCAdj = 0, 83 bool Indirect = false); 84 void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 85 void emitConstPoolAddress(unsigned CPI, unsigned Reloc, intptr_t Disp = 0, 86 intptr_t PCAdj = 0); 87 void emitJumpTableAddress(unsigned JTI, unsigned Reloc, 88 intptr_t PCAdj = 0); 89 90 void emitDisplacementField(const MachineOperand *RelocOp, int DispVal, 91 intptr_t Adj = 0, bool IsPCRel = true); 92 93 void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField); 94 void emitRegModRMByte(unsigned RegOpcodeField); 95 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base); 96 void emitConstant(uint64_t Val, unsigned Size); 97 98 void emitMemModRMByte(const MachineInstr &MI, 99 unsigned Op, unsigned RegOpcodeField, 100 intptr_t PCAdj = 0); 101 }; 102 103template<class CodeEmitter> 104 char Emitter<CodeEmitter>::ID = 0; 105} // end anonymous namespace. 106 107/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code 108/// to the specified templated MachineCodeEmitter object. 109FunctionPass *llvm::createX86JITCodeEmitterPass(X86TargetMachine &TM, 110 JITCodeEmitter &JCE) { 111 return new Emitter<JITCodeEmitter>(TM, JCE); 112} 113 114template<class CodeEmitter> 115bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 116 MMI = &getAnalysis<MachineModuleInfo>(); 117 MCE.setModuleInfo(MMI); 118 119 II = TM.getInstrInfo(); 120 TD = TM.getTargetData(); 121 Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit(); 122 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 123 124 do { 125 DEBUG(dbgs() << "JITTing function '" 126 << MF.getFunction()->getName() << "'\n"); 127 MCE.startFunction(MF); 128 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 129 MBB != E; ++MBB) { 130 MCE.StartMachineBasicBlock(MBB); 131 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 132 I != E; ++I) { 133 const MCInstrDesc &Desc = I->getDesc(); 134 emitInstruction(*I, &Desc); 135 // MOVPC32r is basically a call plus a pop instruction. 136 if (Desc.getOpcode() == X86::MOVPC32r) 137 emitInstruction(*I, &II->get(X86::POP32r)); 138 ++NumEmitted; // Keep track of the # of mi's emitted 139 } 140 } 141 } while (MCE.finishFunction(MF)); 142 143 return false; 144} 145 146/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 147/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 148/// size, and 3) use of X86-64 extended registers. 149static unsigned determineREX(const MachineInstr &MI) { 150 unsigned REX = 0; 151 const MCInstrDesc &Desc = MI.getDesc(); 152 153 // Pseudo instructions do not need REX prefix byte. 154 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 155 return 0; 156 if (Desc.TSFlags & X86II::REX_W) 157 REX |= 1 << 3; 158 159 unsigned NumOps = Desc.getNumOperands(); 160 if (NumOps) { 161 bool isTwoAddr = NumOps > 1 && 162 Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; 163 164 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 165 unsigned i = isTwoAddr ? 1 : 0; 166 for (unsigned e = NumOps; i != e; ++i) { 167 const MachineOperand& MO = MI.getOperand(i); 168 if (MO.isReg()) { 169 unsigned Reg = MO.getReg(); 170 if (X86II::isX86_64NonExtLowByteReg(Reg)) 171 REX |= 0x40; 172 } 173 } 174 175 switch (Desc.TSFlags & X86II::FormMask) { 176 case X86II::MRMInitReg: 177 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 178 REX |= (1 << 0) | (1 << 2); 179 break; 180 case X86II::MRMSrcReg: { 181 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 182 REX |= 1 << 2; 183 i = isTwoAddr ? 2 : 1; 184 for (unsigned e = NumOps; i != e; ++i) { 185 const MachineOperand& MO = MI.getOperand(i); 186 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 187 REX |= 1 << 0; 188 } 189 break; 190 } 191 case X86II::MRMSrcMem: { 192 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 193 REX |= 1 << 2; 194 unsigned Bit = 0; 195 i = isTwoAddr ? 2 : 1; 196 for (; i != NumOps; ++i) { 197 const MachineOperand& MO = MI.getOperand(i); 198 if (MO.isReg()) { 199 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 200 REX |= 1 << Bit; 201 Bit++; 202 } 203 } 204 break; 205 } 206 case X86II::MRM0m: case X86II::MRM1m: 207 case X86II::MRM2m: case X86II::MRM3m: 208 case X86II::MRM4m: case X86II::MRM5m: 209 case X86II::MRM6m: case X86II::MRM7m: 210 case X86II::MRMDestMem: { 211 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands); 212 i = isTwoAddr ? 1 : 0; 213 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e))) 214 REX |= 1 << 2; 215 unsigned Bit = 0; 216 for (; i != e; ++i) { 217 const MachineOperand& MO = MI.getOperand(i); 218 if (MO.isReg()) { 219 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 220 REX |= 1 << Bit; 221 Bit++; 222 } 223 } 224 break; 225 } 226 default: { 227 if (X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0))) 228 REX |= 1 << 0; 229 i = isTwoAddr ? 2 : 1; 230 for (unsigned e = NumOps; i != e; ++i) { 231 const MachineOperand& MO = MI.getOperand(i); 232 if (X86InstrInfo::isX86_64ExtendedReg(MO)) 233 REX |= 1 << 2; 234 } 235 break; 236 } 237 } 238 } 239 return REX; 240} 241 242 243/// emitPCRelativeBlockAddress - This method keeps track of the information 244/// necessary to resolve the address of this block later and emits a dummy 245/// value. 246/// 247template<class CodeEmitter> 248void Emitter<CodeEmitter>::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) { 249 // Remember where this reference was and where it is to so we can 250 // deal with it later. 251 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 252 X86::reloc_pcrel_word, MBB)); 253 MCE.emitWordLE(0); 254} 255 256/// emitGlobalAddress - Emit the specified address to the code stream assuming 257/// this is part of a "take the address of a global" instruction. 258/// 259template<class CodeEmitter> 260void Emitter<CodeEmitter>::emitGlobalAddress(const GlobalValue *GV, 261 unsigned Reloc, 262 intptr_t Disp /* = 0 */, 263 intptr_t PCAdj /* = 0 */, 264 bool Indirect /* = false */) { 265 intptr_t RelocCST = Disp; 266 if (Reloc == X86::reloc_picrel_word) 267 RelocCST = PICBaseOffset; 268 else if (Reloc == X86::reloc_pcrel_word) 269 RelocCST = PCAdj; 270 MachineRelocation MR = Indirect 271 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 272 const_cast<GlobalValue *>(GV), 273 RelocCST, false) 274 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 275 const_cast<GlobalValue *>(GV), RelocCST, false); 276 MCE.addRelocation(MR); 277 // The relocated value will be added to the displacement 278 if (Reloc == X86::reloc_absolute_dword) 279 MCE.emitDWordLE(Disp); 280 else 281 MCE.emitWordLE((int32_t)Disp); 282} 283 284/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 285/// be emitted to the current location in the function, and allow it to be PC 286/// relative. 287template<class CodeEmitter> 288void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 289 unsigned Reloc) { 290 intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0; 291 292 // X86 never needs stubs because instruction selection will always pick 293 // an instruction sequence that is large enough to hold any address 294 // to a symbol. 295 // (see X86ISelLowering.cpp, near 2039: X86TargetLowering::LowerCall) 296 bool NeedStub = false; 297 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 298 Reloc, ES, RelocCST, 299 0, NeedStub)); 300 if (Reloc == X86::reloc_absolute_dword) 301 MCE.emitDWordLE(0); 302 else 303 MCE.emitWordLE(0); 304} 305 306/// emitConstPoolAddress - Arrange for the address of an constant pool 307/// to be emitted to the current location in the function, and allow it to be PC 308/// relative. 309template<class CodeEmitter> 310void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, unsigned Reloc, 311 intptr_t Disp /* = 0 */, 312 intptr_t PCAdj /* = 0 */) { 313 intptr_t RelocCST = 0; 314 if (Reloc == X86::reloc_picrel_word) 315 RelocCST = PICBaseOffset; 316 else if (Reloc == X86::reloc_pcrel_word) 317 RelocCST = PCAdj; 318 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 319 Reloc, CPI, RelocCST)); 320 // The relocated value will be added to the displacement 321 if (Reloc == X86::reloc_absolute_dword) 322 MCE.emitDWordLE(Disp); 323 else 324 MCE.emitWordLE((int32_t)Disp); 325} 326 327/// emitJumpTableAddress - Arrange for the address of a jump table to 328/// be emitted to the current location in the function, and allow it to be PC 329/// relative. 330template<class CodeEmitter> 331void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTI, unsigned Reloc, 332 intptr_t PCAdj /* = 0 */) { 333 intptr_t RelocCST = 0; 334 if (Reloc == X86::reloc_picrel_word) 335 RelocCST = PICBaseOffset; 336 else if (Reloc == X86::reloc_pcrel_word) 337 RelocCST = PCAdj; 338 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 339 Reloc, JTI, RelocCST)); 340 // The relocated value will be added to the displacement 341 if (Reloc == X86::reloc_absolute_dword) 342 MCE.emitDWordLE(0); 343 else 344 MCE.emitWordLE(0); 345} 346 347inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode, 348 unsigned RM) { 349 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 350 return RM | (RegOpcode << 3) | (Mod << 6); 351} 352 353template<class CodeEmitter> 354void Emitter<CodeEmitter>::emitRegModRMByte(unsigned ModRMReg, 355 unsigned RegOpcodeFld){ 356 MCE.emitByte(ModRMByte(3, RegOpcodeFld, X86_MC::getX86RegNum(ModRMReg))); 357} 358 359template<class CodeEmitter> 360void Emitter<CodeEmitter>::emitRegModRMByte(unsigned RegOpcodeFld) { 361 MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0)); 362} 363 364template<class CodeEmitter> 365void Emitter<CodeEmitter>::emitSIBByte(unsigned SS, 366 unsigned Index, 367 unsigned Base) { 368 // SIB byte is in the same format as the ModRMByte... 369 MCE.emitByte(ModRMByte(SS, Index, Base)); 370} 371 372template<class CodeEmitter> 373void Emitter<CodeEmitter>::emitConstant(uint64_t Val, unsigned Size) { 374 // Output the constant in little endian byte order... 375 for (unsigned i = 0; i != Size; ++i) { 376 MCE.emitByte(Val & 255); 377 Val >>= 8; 378 } 379} 380 381/// isDisp8 - Return true if this signed displacement fits in a 8-bit 382/// sign-extended field. 383static bool isDisp8(int Value) { 384 return Value == (signed char)Value; 385} 386 387static bool gvNeedsNonLazyPtr(const MachineOperand &GVOp, 388 const TargetMachine &TM) { 389 // For Darwin-64, simulate the linktime GOT by using the same non-lazy-pointer 390 // mechanism as 32-bit mode. 391 if (TM.getSubtarget<X86Subtarget>().is64Bit() && 392 !TM.getSubtarget<X86Subtarget>().isTargetDarwin()) 393 return false; 394 395 // Return true if this is a reference to a stub containing the address of the 396 // global, not the global itself. 397 return isGlobalStubReference(GVOp.getTargetFlags()); 398} 399 400template<class CodeEmitter> 401void Emitter<CodeEmitter>::emitDisplacementField(const MachineOperand *RelocOp, 402 int DispVal, 403 intptr_t Adj /* = 0 */, 404 bool IsPCRel /* = true */) { 405 // If this is a simple integer displacement that doesn't require a relocation, 406 // emit it now. 407 if (!RelocOp) { 408 emitConstant(DispVal, 4); 409 return; 410 } 411 412 // Otherwise, this is something that requires a relocation. Emit it as such 413 // now. 414 unsigned RelocType = Is64BitMode ? 415 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext) 416 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 417 if (RelocOp->isGlobal()) { 418 // In 64-bit static small code model, we could potentially emit absolute. 419 // But it's probably not beneficial. If the MCE supports using RIP directly 420 // do it, otherwise fallback to absolute (this is determined by IsPCRel). 421 // 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative 422 // 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute 423 bool Indirect = gvNeedsNonLazyPtr(*RelocOp, TM); 424 emitGlobalAddress(RelocOp->getGlobal(), RelocType, RelocOp->getOffset(), 425 Adj, Indirect); 426 } else if (RelocOp->isSymbol()) { 427 emitExternalSymbolAddress(RelocOp->getSymbolName(), RelocType); 428 } else if (RelocOp->isCPI()) { 429 emitConstPoolAddress(RelocOp->getIndex(), RelocType, 430 RelocOp->getOffset(), Adj); 431 } else { 432 assert(RelocOp->isJTI() && "Unexpected machine operand!"); 433 emitJumpTableAddress(RelocOp->getIndex(), RelocType, Adj); 434 } 435} 436 437template<class CodeEmitter> 438void Emitter<CodeEmitter>::emitMemModRMByte(const MachineInstr &MI, 439 unsigned Op,unsigned RegOpcodeField, 440 intptr_t PCAdj) { 441 const MachineOperand &Op3 = MI.getOperand(Op+3); 442 int DispVal = 0; 443 const MachineOperand *DispForReloc = 0; 444 445 // Figure out what sort of displacement we have to handle here. 446 if (Op3.isGlobal()) { 447 DispForReloc = &Op3; 448 } else if (Op3.isSymbol()) { 449 DispForReloc = &Op3; 450 } else if (Op3.isCPI()) { 451 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 452 DispForReloc = &Op3; 453 } else { 454 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); 455 DispVal += Op3.getOffset(); 456 } 457 } else if (Op3.isJTI()) { 458 if (!MCE.earlyResolveAddresses() || Is64BitMode || IsPIC) { 459 DispForReloc = &Op3; 460 } else { 461 DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex()); 462 } 463 } else { 464 DispVal = Op3.getImm(); 465 } 466 467 const MachineOperand &Base = MI.getOperand(Op); 468 const MachineOperand &Scale = MI.getOperand(Op+1); 469 const MachineOperand &IndexReg = MI.getOperand(Op+2); 470 471 unsigned BaseReg = Base.getReg(); 472 473 // Handle %rip relative addressing. 474 if (BaseReg == X86::RIP || 475 (Is64BitMode && DispForReloc)) { // [disp32+RIP] in X86-64 mode 476 assert(IndexReg.getReg() == 0 && Is64BitMode && 477 "Invalid rip-relative address"); 478 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 479 emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 480 return; 481 } 482 483 // Indicate that the displacement will use an pcrel or absolute reference 484 // by default. MCEs able to resolve addresses on-the-fly use pcrel by default 485 // while others, unless explicit asked to use RIP, use absolute references. 486 bool IsPCRel = MCE.earlyResolveAddresses() ? true : false; 487 488 // Is a SIB byte needed? 489 // If no BaseReg, issue a RIP relative instruction only if the MCE can 490 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 491 // 2-7) and absolute references. 492 unsigned BaseRegNo = -1U; 493 if (BaseReg != 0 && BaseReg != X86::RIP) 494 BaseRegNo = X86_MC::getX86RegNum(BaseReg); 495 496 if (// The SIB byte must be used if there is an index register. 497 IndexReg.getReg() == 0 && 498 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 499 // encode to an R/M value of 4, which indicates that a SIB byte is 500 // present. 501 BaseRegNo != N86::ESP && 502 // If there is no base register and we're in 64-bit mode, we need a SIB 503 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 504 (!Is64BitMode || BaseReg != 0)) { 505 if (BaseReg == 0 || // [disp32] in X86-32 mode 506 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode 507 MCE.emitByte(ModRMByte(0, RegOpcodeField, 5)); 508 emitDisplacementField(DispForReloc, DispVal, PCAdj, true); 509 return; 510 } 511 512 // If the base is not EBP/ESP and there is no displacement, use simple 513 // indirect register encoding, this handles addresses like [EAX]. The 514 // encoding for [EBP] with no displacement means [disp32] so we handle it 515 // by emitting a displacement of 0 below. 516 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 517 MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo)); 518 return; 519 } 520 521 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 522 if (!DispForReloc && isDisp8(DispVal)) { 523 MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo)); 524 emitConstant(DispVal, 1); 525 return; 526 } 527 528 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 529 MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo)); 530 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 531 return; 532 } 533 534 // Otherwise we need a SIB byte, so start by outputting the ModR/M byte first. 535 assert(IndexReg.getReg() != X86::ESP && 536 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 537 538 bool ForceDisp32 = false; 539 bool ForceDisp8 = false; 540 if (BaseReg == 0) { 541 // If there is no base register, we emit the special case SIB byte with 542 // MOD=0, BASE=4, to JUST get the index, scale, and displacement. 543 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 544 ForceDisp32 = true; 545 } else if (DispForReloc) { 546 // Emit the normal disp32 encoding. 547 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 548 ForceDisp32 = true; 549 } else if (DispVal == 0 && BaseRegNo != N86::EBP) { 550 // Emit no displacement ModR/M byte 551 MCE.emitByte(ModRMByte(0, RegOpcodeField, 4)); 552 } else if (isDisp8(DispVal)) { 553 // Emit the disp8 encoding... 554 MCE.emitByte(ModRMByte(1, RegOpcodeField, 4)); 555 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 556 } else { 557 // Emit the normal disp32 encoding... 558 MCE.emitByte(ModRMByte(2, RegOpcodeField, 4)); 559 } 560 561 // Calculate what the SS field value should be... 562 static const unsigned SSTable[] = { ~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3 }; 563 unsigned SS = SSTable[Scale.getImm()]; 564 565 if (BaseReg == 0) { 566 // Handle the SIB byte for the case where there is no base, see Intel 567 // Manual 2A, table 2-7. The displacement has already been output. 568 unsigned IndexRegNo; 569 if (IndexReg.getReg()) 570 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 571 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 572 IndexRegNo = 4; 573 emitSIBByte(SS, IndexRegNo, 5); 574 } else { 575 unsigned BaseRegNo = X86_MC::getX86RegNum(BaseReg); 576 unsigned IndexRegNo; 577 if (IndexReg.getReg()) 578 IndexRegNo = X86_MC::getX86RegNum(IndexReg.getReg()); 579 else 580 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 581 emitSIBByte(SS, IndexRegNo, BaseRegNo); 582 } 583 584 // Do we need to output a displacement? 585 if (ForceDisp8) { 586 emitConstant(DispVal, 1); 587 } else if (DispVal != 0 || ForceDisp32) { 588 emitDisplacementField(DispForReloc, DispVal, PCAdj, IsPCRel); 589 } 590} 591 592template<class CodeEmitter> 593void Emitter<CodeEmitter>::emitInstruction(MachineInstr &MI, 594 const MCInstrDesc *Desc) { 595 DEBUG(dbgs() << MI); 596 597 // If this is a pseudo instruction, lower it. 598 switch (Desc->getOpcode()) { 599 case X86::ADD16rr_DB: Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break; 600 case X86::ADD32rr_DB: Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break; 601 case X86::ADD64rr_DB: Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break; 602 case X86::ADD16ri_DB: Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break; 603 case X86::ADD32ri_DB: Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break; 604 case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break; 605 case X86::ADD16ri8_DB: Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break; 606 case X86::ADD32ri8_DB: Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break; 607 case X86::ADD64ri8_DB: Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break; 608 } 609 610 611 MCE.processDebugLoc(MI.getDebugLoc(), true); 612 613 unsigned Opcode = Desc->Opcode; 614 615 // Emit the lock opcode prefix as needed. 616 if (Desc->TSFlags & X86II::LOCK) 617 MCE.emitByte(0xF0); 618 619 // Emit segment override opcode prefix as needed. 620 switch (Desc->TSFlags & X86II::SegOvrMask) { 621 case X86II::FS: 622 MCE.emitByte(0x64); 623 break; 624 case X86II::GS: 625 MCE.emitByte(0x65); 626 break; 627 default: llvm_unreachable("Invalid segment!"); 628 case 0: break; // No segment override! 629 } 630 631 // Emit the repeat opcode prefix as needed. 632 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) 633 MCE.emitByte(0xF3); 634 635 // Emit the operand size opcode prefix as needed. 636 if (Desc->TSFlags & X86II::OpSize) 637 MCE.emitByte(0x66); 638 639 // Emit the address size opcode prefix as needed. 640 if (Desc->TSFlags & X86II::AdSize) 641 MCE.emitByte(0x67); 642 643 bool Need0FPrefix = false; 644 switch (Desc->TSFlags & X86II::Op0Mask) { 645 case X86II::TB: // Two-byte opcode prefix 646 case X86II::T8: // 0F 38 647 case X86II::TA: // 0F 3A 648 case X86II::A6: // 0F A6 649 case X86II::A7: // 0F A7 650 Need0FPrefix = true; 651 break; 652 case X86II::REP: break; // already handled. 653 case X86II::T8XS: // F3 0F 38 654 case X86II::XS: // F3 0F 655 MCE.emitByte(0xF3); 656 Need0FPrefix = true; 657 break; 658 case X86II::T8XD: // F2 0F 38 659 case X86II::XD: // F2 0F 660 MCE.emitByte(0xF2); 661 Need0FPrefix = true; 662 break; 663 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 664 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 665 MCE.emitByte(0xD8+ 666 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8) 667 >> X86II::Op0Shift)); 668 break; // Two-byte opcode prefix 669 default: llvm_unreachable("Invalid prefix!"); 670 case 0: break; // No prefix! 671 } 672 673 // Handle REX prefix. 674 if (Is64BitMode) { 675 if (unsigned REX = determineREX(MI)) 676 MCE.emitByte(0x40 | REX); 677 } 678 679 // 0x0F escape code must be emitted just before the opcode. 680 if (Need0FPrefix) 681 MCE.emitByte(0x0F); 682 683 switch (Desc->TSFlags & X86II::Op0Mask) { 684 case X86II::T8XD: // F2 0F 38 685 case X86II::T8XS: // F3 0F 38 686 case X86II::T8: // 0F 38 687 MCE.emitByte(0x38); 688 break; 689 case X86II::TA: // 0F 3A 690 MCE.emitByte(0x3A); 691 break; 692 case X86II::A6: // 0F A6 693 MCE.emitByte(0xA6); 694 break; 695 case X86II::A7: // 0F A7 696 MCE.emitByte(0xA7); 697 break; 698 } 699 700 // If this is a two-address instruction, skip one of the register operands. 701 unsigned NumOps = Desc->getNumOperands(); 702 unsigned CurOp = 0; 703 if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1) 704 ++CurOp; 705 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0) 706 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 707 --NumOps; 708 709 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(Desc->TSFlags); 710 switch (Desc->TSFlags & X86II::FormMask) { 711 default: 712 llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 713 case X86II::Pseudo: 714 // Remember the current PC offset, this is the PIC relocation 715 // base address. 716 switch (Opcode) { 717 default: 718 llvm_unreachable("pseudo instructions should be removed before code" 719 " emission"); 720 break; 721 // Do nothing for Int_MemBarrier - it's just a comment. Add a debug 722 // to make it slightly easier to see. 723 case X86::Int_MemBarrier: 724 DEBUG(dbgs() << "#MEMBARRIER\n"); 725 break; 726 727 case TargetOpcode::INLINEASM: 728 // We allow inline assembler nodes with empty bodies - they can 729 // implicitly define registers, which is ok for JIT. 730 if (MI.getOperand(0).getSymbolName()[0]) 731 report_fatal_error("JIT does not support inline asm!"); 732 break; 733 case TargetOpcode::PROLOG_LABEL: 734 case TargetOpcode::GC_LABEL: 735 case TargetOpcode::EH_LABEL: 736 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 737 break; 738 739 case TargetOpcode::IMPLICIT_DEF: 740 case TargetOpcode::KILL: 741 break; 742 case X86::MOVPC32r: { 743 // This emits the "call" portion of this pseudo instruction. 744 MCE.emitByte(BaseOpcode); 745 emitConstant(0, X86II::getSizeOfImm(Desc->TSFlags)); 746 // Remember PIC base. 747 PICBaseOffset = (intptr_t) MCE.getCurrentPCOffset(); 748 X86JITInfo *JTI = TM.getJITInfo(); 749 JTI->setPICBase(MCE.getCurrentPCValue()); 750 break; 751 } 752 } 753 CurOp = NumOps; 754 break; 755 case X86II::RawFrm: { 756 MCE.emitByte(BaseOpcode); 757 758 if (CurOp == NumOps) 759 break; 760 761 const MachineOperand &MO = MI.getOperand(CurOp++); 762 763 DEBUG(dbgs() << "RawFrm CurOp " << CurOp << "\n"); 764 DEBUG(dbgs() << "isMBB " << MO.isMBB() << "\n"); 765 DEBUG(dbgs() << "isGlobal " << MO.isGlobal() << "\n"); 766 DEBUG(dbgs() << "isSymbol " << MO.isSymbol() << "\n"); 767 DEBUG(dbgs() << "isImm " << MO.isImm() << "\n"); 768 769 if (MO.isMBB()) { 770 emitPCRelativeBlockAddress(MO.getMBB()); 771 break; 772 } 773 774 if (MO.isGlobal()) { 775 emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word, 776 MO.getOffset(), 0); 777 break; 778 } 779 780 if (MO.isSymbol()) { 781 emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word); 782 break; 783 } 784 785 // FIXME: Only used by hackish MCCodeEmitter, remove when dead. 786 if (MO.isJTI()) { 787 emitJumpTableAddress(MO.getIndex(), X86::reloc_pcrel_word); 788 break; 789 } 790 791 assert(MO.isImm() && "Unknown RawFrm operand!"); 792 if (Opcode == X86::CALLpcrel32 || Opcode == X86::CALL64pcrel32 || 793 Opcode == X86::WINCALL64pcrel32) { 794 // Fix up immediate operand for pc relative calls. 795 intptr_t Imm = (intptr_t)MO.getImm(); 796 Imm = Imm - MCE.getCurrentPCValue() - 4; 797 emitConstant(Imm, X86II::getSizeOfImm(Desc->TSFlags)); 798 } else 799 emitConstant(MO.getImm(), X86II::getSizeOfImm(Desc->TSFlags)); 800 break; 801 } 802 803 case X86II::AddRegFrm: { 804 MCE.emitByte(BaseOpcode + 805 X86_MC::getX86RegNum(MI.getOperand(CurOp++).getReg())); 806 807 if (CurOp == NumOps) 808 break; 809 810 const MachineOperand &MO1 = MI.getOperand(CurOp++); 811 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 812 if (MO1.isImm()) { 813 emitConstant(MO1.getImm(), Size); 814 break; 815 } 816 817 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 818 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 819 if (Opcode == X86::MOV64ri64i32) 820 rt = X86::reloc_absolute_word; // FIXME: add X86II flag? 821 // This should not occur on Darwin for relocatable objects. 822 if (Opcode == X86::MOV64ri) 823 rt = X86::reloc_absolute_dword; // FIXME: add X86II flag? 824 if (MO1.isGlobal()) { 825 bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 826 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 827 Indirect); 828 } else if (MO1.isSymbol()) 829 emitExternalSymbolAddress(MO1.getSymbolName(), rt); 830 else if (MO1.isCPI()) 831 emitConstPoolAddress(MO1.getIndex(), rt); 832 else if (MO1.isJTI()) 833 emitJumpTableAddress(MO1.getIndex(), rt); 834 break; 835 } 836 837 case X86II::MRMDestReg: { 838 MCE.emitByte(BaseOpcode); 839 emitRegModRMByte(MI.getOperand(CurOp).getReg(), 840 X86_MC::getX86RegNum(MI.getOperand(CurOp+1).getReg())); 841 CurOp += 2; 842 if (CurOp != NumOps) 843 emitConstant(MI.getOperand(CurOp++).getImm(), 844 X86II::getSizeOfImm(Desc->TSFlags)); 845 break; 846 } 847 case X86II::MRMDestMem: { 848 MCE.emitByte(BaseOpcode); 849 emitMemModRMByte(MI, CurOp, 850 X86_MC::getX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands) 851 .getReg())); 852 CurOp += X86::AddrNumOperands + 1; 853 if (CurOp != NumOps) 854 emitConstant(MI.getOperand(CurOp++).getImm(), 855 X86II::getSizeOfImm(Desc->TSFlags)); 856 break; 857 } 858 859 case X86II::MRMSrcReg: 860 MCE.emitByte(BaseOpcode); 861 emitRegModRMByte(MI.getOperand(CurOp+1).getReg(), 862 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 863 CurOp += 2; 864 if (CurOp != NumOps) 865 emitConstant(MI.getOperand(CurOp++).getImm(), 866 X86II::getSizeOfImm(Desc->TSFlags)); 867 break; 868 869 case X86II::MRMSrcMem: { 870 int AddrOperands = X86::AddrNumOperands; 871 872 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ? 873 X86II::getSizeOfImm(Desc->TSFlags) : 0; 874 875 MCE.emitByte(BaseOpcode); 876 emitMemModRMByte(MI, CurOp+1, 877 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg()),PCAdj); 878 CurOp += AddrOperands + 1; 879 if (CurOp != NumOps) 880 emitConstant(MI.getOperand(CurOp++).getImm(), 881 X86II::getSizeOfImm(Desc->TSFlags)); 882 break; 883 } 884 885 case X86II::MRM0r: case X86II::MRM1r: 886 case X86II::MRM2r: case X86II::MRM3r: 887 case X86II::MRM4r: case X86II::MRM5r: 888 case X86II::MRM6r: case X86II::MRM7r: { 889 MCE.emitByte(BaseOpcode); 890 emitRegModRMByte(MI.getOperand(CurOp++).getReg(), 891 (Desc->TSFlags & X86II::FormMask)-X86II::MRM0r); 892 893 if (CurOp == NumOps) 894 break; 895 896 const MachineOperand &MO1 = MI.getOperand(CurOp++); 897 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 898 if (MO1.isImm()) { 899 emitConstant(MO1.getImm(), Size); 900 break; 901 } 902 903 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 904 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 905 if (Opcode == X86::MOV64ri32) 906 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 907 if (MO1.isGlobal()) { 908 bool Indirect = gvNeedsNonLazyPtr(MO1, TM); 909 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0, 910 Indirect); 911 } else if (MO1.isSymbol()) 912 emitExternalSymbolAddress(MO1.getSymbolName(), rt); 913 else if (MO1.isCPI()) 914 emitConstPoolAddress(MO1.getIndex(), rt); 915 else if (MO1.isJTI()) 916 emitJumpTableAddress(MO1.getIndex(), rt); 917 break; 918 } 919 920 case X86II::MRM0m: case X86II::MRM1m: 921 case X86II::MRM2m: case X86II::MRM3m: 922 case X86II::MRM4m: case X86II::MRM5m: 923 case X86II::MRM6m: case X86II::MRM7m: { 924 intptr_t PCAdj = (CurOp + X86::AddrNumOperands != NumOps) ? 925 (MI.getOperand(CurOp+X86::AddrNumOperands).isImm() ? 926 X86II::getSizeOfImm(Desc->TSFlags) : 4) : 0; 927 928 MCE.emitByte(BaseOpcode); 929 emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m, 930 PCAdj); 931 CurOp += X86::AddrNumOperands; 932 933 if (CurOp == NumOps) 934 break; 935 936 const MachineOperand &MO = MI.getOperand(CurOp++); 937 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 938 if (MO.isImm()) { 939 emitConstant(MO.getImm(), Size); 940 break; 941 } 942 943 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word 944 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word); 945 if (Opcode == X86::MOV64mi32) 946 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag? 947 if (MO.isGlobal()) { 948 bool Indirect = gvNeedsNonLazyPtr(MO, TM); 949 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0, 950 Indirect); 951 } else if (MO.isSymbol()) 952 emitExternalSymbolAddress(MO.getSymbolName(), rt); 953 else if (MO.isCPI()) 954 emitConstPoolAddress(MO.getIndex(), rt); 955 else if (MO.isJTI()) 956 emitJumpTableAddress(MO.getIndex(), rt); 957 break; 958 } 959 960 case X86II::MRMInitReg: 961 MCE.emitByte(BaseOpcode); 962 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 963 emitRegModRMByte(MI.getOperand(CurOp).getReg(), 964 X86_MC::getX86RegNum(MI.getOperand(CurOp).getReg())); 965 ++CurOp; 966 break; 967 968 case X86II::MRM_C1: 969 MCE.emitByte(BaseOpcode); 970 MCE.emitByte(0xC1); 971 break; 972 case X86II::MRM_C8: 973 MCE.emitByte(BaseOpcode); 974 MCE.emitByte(0xC8); 975 break; 976 case X86II::MRM_C9: 977 MCE.emitByte(BaseOpcode); 978 MCE.emitByte(0xC9); 979 break; 980 case X86II::MRM_E8: 981 MCE.emitByte(BaseOpcode); 982 MCE.emitByte(0xE8); 983 break; 984 case X86II::MRM_F0: 985 MCE.emitByte(BaseOpcode); 986 MCE.emitByte(0xF0); 987 break; 988 } 989 990 if (!Desc->isVariadic() && CurOp != NumOps) { 991#ifndef NDEBUG 992 dbgs() << "Cannot encode all operands of: " << MI << "\n"; 993#endif 994 llvm_unreachable(0); 995 } 996 997 MCE.processDebugLoc(MI.getDebugLoc(), false); 998} 999