EDEmitter.cpp revision ddcdcc88631c6bd4ad43d9198b98bc9a829be036 
1//===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of each
11// instruction in a format that the enhanced disassembler can use to tokenize
12// and parse instructions.
13//
14//===----------------------------------------------------------------------===//
15
16#include "EDEmitter.h"
17
18#include "AsmWriterInst.h"
19#include "CodeGenTarget.h"
20#include "Record.h"
21
22#include "llvm/MC/EDInstInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/Format.h"
25#include "llvm/Support/raw_ostream.h"
26
27#include <string>
28#include <vector>
29
30using namespace llvm;
31
32///////////////////////////////////////////////////////////
33// Support classes for emitting nested C data structures //
34///////////////////////////////////////////////////////////
35
36namespace {
37
38  class EnumEmitter {
39  private:
40    std::string Name;
41    std::vector<std::string> Entries;
42  public:
43    EnumEmitter(const char *N) : Name(N) {
44    }
45    int addEntry(const char *e) {
46      Entries.push_back(std::string(e));
47      return Entries.size() - 1;
48    }
49    void emit(raw_ostream &o, unsigned int &i) {
50      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
51      i += 2;
52
53      unsigned int index = 0;
54      unsigned int numEntries = Entries.size();
55      for (index = 0; index < numEntries; ++index) {
56        o.indent(i) << Entries[index];
57        if (index < (numEntries - 1))
58          o << ",";
59        o << "\n";
60      }
61
62      i -= 2;
63      o.indent(i) << "};" << "\n";
64    }
65
66    void emitAsFlags(raw_ostream &o, unsigned int &i) {
67      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
68      i += 2;
69
70      unsigned int index = 0;
71      unsigned int numEntries = Entries.size();
72      unsigned int flag = 1;
73      for (index = 0; index < numEntries; ++index) {
74        o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75        if (index < (numEntries - 1))
76          o << ",";
77        o << "\n";
78        flag <<= 1;
79      }
80
81      i -= 2;
82      o.indent(i) << "};" << "\n";
83    }
84  };
85
86  class ConstantEmitter {
87  public:
88    virtual ~ConstantEmitter() { }
89    virtual void emit(raw_ostream &o, unsigned int &i) = 0;
90  };
91
92  class LiteralConstantEmitter : public ConstantEmitter {
93  private:
94    bool IsNumber;
95    union {
96      int Number;
97      const char* String;
98    };
99  public:
100    LiteralConstantEmitter(int number = 0) :
101      IsNumber(true),
102      Number(number) {
103    }
104    void set(const char *string) {
105      IsNumber = false;
106      Number = 0;
107      String = string;
108    }
109    bool is(const char *string) {
110      return !strcmp(String, string);
111    }
112    void emit(raw_ostream &o, unsigned int &i) {
113      if (IsNumber)
114        o << Number;
115      else
116        o << String;
117    }
118  };
119
120  class CompoundConstantEmitter : public ConstantEmitter {
121  private:
122    unsigned int Padding;
123    std::vector<ConstantEmitter *> Entries;
124  public:
125    CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
126    }
127    CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128      Entries.push_back(e);
129
130      return *this;
131    }
132    ~CompoundConstantEmitter() {
133      while (Entries.size()) {
134        ConstantEmitter *entry = Entries.back();
135        Entries.pop_back();
136        delete entry;
137      }
138    }
139    void emit(raw_ostream &o, unsigned int &i) {
140      o << "{" << "\n";
141      i += 2;
142
143      unsigned int index;
144      unsigned int numEntries = Entries.size();
145
146      unsigned int numToPrint;
147
148      if (Padding) {
149        if (numEntries > Padding) {
150          fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151          llvm_unreachable("More entries than padding");
152        }
153        numToPrint = Padding;
154      } else {
155        numToPrint = numEntries;
156      }
157
158      for (index = 0; index < numToPrint; ++index) {
159        o.indent(i);
160        if (index < numEntries)
161          Entries[index]->emit(o, i);
162        else
163          o << "-1";
164
165        if (index < (numToPrint - 1))
166          o << ",";
167        o << "\n";
168      }
169
170      i -= 2;
171      o.indent(i) << "}";
172    }
173  };
174
175  class FlagsConstantEmitter : public ConstantEmitter {
176  private:
177    std::vector<std::string> Flags;
178  public:
179    FlagsConstantEmitter() {
180    }
181    FlagsConstantEmitter &addEntry(const char *f) {
182      Flags.push_back(std::string(f));
183      return *this;
184    }
185    void emit(raw_ostream &o, unsigned int &i) {
186      unsigned int index;
187      unsigned int numFlags = Flags.size();
188      if (numFlags == 0)
189        o << "0";
190
191      for (index = 0; index < numFlags; ++index) {
192        o << Flags[index].c_str();
193        if (index < (numFlags - 1))
194          o << " | ";
195      }
196    }
197  };
198}
199
200EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
201}
202
203/// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204///   AsmWriterInst for the desired assembly syntax, giving an ordered list of
205///   operands in the order they appear in the printed instruction.  Then, for
206///   each entry in that list, determines the index of the same operand in the
207///   CodeGenInstruction, and emits the resulting mapping into an array, filling
208///   in unused slots with -1.
209///
210/// @arg operandOrder - The array that will be populated with the operand
211///                     mapping.  Each entry will contain -1 (invalid index
212///                     into the operands present in the AsmString) or a number
213///                     representing an index in the operand descriptor array.
214/// @arg inst         - The instruction to use when looking up the operands
215/// @arg syntax       - The syntax to use, according to LLVM's enumeration
216void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217                          const CodeGenInstruction &inst,
218                          unsigned syntax) {
219  unsigned int numArgs = 0;
220
221  AsmWriterInst awInst(inst, syntax, -1, -1);
222
223  std::vector<AsmWriterOperand>::iterator operandIterator;
224
225  for (operandIterator = awInst.Operands.begin();
226       operandIterator != awInst.Operands.end();
227       ++operandIterator) {
228    if (operandIterator->OperandType ==
229        AsmWriterOperand::isMachineInstrOperand) {
230      operandOrder->addEntry(
231        new LiteralConstantEmitter(operandIterator->CGIOpNo));
232      numArgs++;
233    }
234  }
235}
236
237/////////////////////////////////////////////////////
238// Support functions for handling X86 instructions //
239/////////////////////////////////////////////////////
240
241#define SET(flag) { type->set(flag); return 0; }
242
243#define REG(str) if (name == str) SET("kOperandTypeRegister");
244#define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245#define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247#define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
248
249/// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250///   actually its type) and translates it into an operand type
251///
252/// @arg flags    - The type object to set
253/// @arg name     - The name of the operand
254static int X86TypeFromOpName(LiteralConstantEmitter *type,
255                             const std::string &name) {
256  REG("GR8");
257  REG("GR8_NOREX");
258  REG("GR16");
259  REG("GR32");
260  REG("GR32_NOREX");
261  REG("GR32_TC");
262  REG("FR32");
263  REG("RFP32");
264  REG("GR64");
265  REG("GR64_TC");
266  REG("FR64");
267  REG("VR64");
268  REG("RFP64");
269  REG("RFP80");
270  REG("VR128");
271  REG("VR256");
272  REG("RST");
273  REG("SEGMENT_REG");
274  REG("DEBUG_REG");
275  REG("CONTROL_REG");
276
277  IMM("i8imm");
278  IMM("i16imm");
279  IMM("i16i8imm");
280  IMM("i32imm");
281  IMM("i32i8imm");
282  IMM("i64imm");
283  IMM("i64i8imm");
284  IMM("i64i32imm");
285  IMM("SSECC");
286
287  // all R, I, R, I, R
288  MEM("i8mem");
289  MEM("i8mem_NOREX");
290  MEM("i16mem");
291  MEM("i32mem");
292  MEM("i32mem_TC");
293  MEM("f32mem");
294  MEM("ssmem");
295  MEM("opaque32mem");
296  MEM("opaque48mem");
297  MEM("i64mem");
298  MEM("i64mem_TC");
299  MEM("f64mem");
300  MEM("sdmem");
301  MEM("f80mem");
302  MEM("opaque80mem");
303  MEM("i128mem");
304  MEM("i256mem");
305  MEM("f128mem");
306  MEM("f256mem");
307  MEM("opaque512mem");
308
309  // all R, I, R, I
310  LEA("lea32mem");
311  LEA("lea64_32mem");
312  LEA("lea64mem");
313
314  // all I
315  PCR("i16imm_pcrel");
316  PCR("i32imm_pcrel");
317  PCR("i64i32imm_pcrel");
318  PCR("brtarget8");
319  PCR("offset8");
320  PCR("offset16");
321  PCR("offset32");
322  PCR("offset64");
323  PCR("brtarget");
324  PCR("uncondbrtarget");
325  PCR("bltarget");
326
327  // all I, ARM mode only, conditional/unconditional
328  PCR("br_target");
329  PCR("bl_target");
330  return 1;
331}
332
333#undef REG
334#undef MEM
335#undef LEA
336#undef IMM
337#undef PCR
338
339#undef SET
340
341/// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
342///   the appropriate flags to their descriptors
343///
344/// @operandFlags - A reference the array of operand flag objects
345/// @inst         - The instruction to use as a source of information
346static void X86PopulateOperands(
347  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
348  const CodeGenInstruction &inst) {
349  if (!inst.TheDef->isSubClassOf("X86Inst"))
350    return;
351
352  unsigned int index;
353  unsigned int numOperands = inst.Operands.size();
354
355  for (index = 0; index < numOperands; ++index) {
356    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
357    Record &rec = *operandInfo.Rec;
358
359    if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
360        !rec.isSubClassOf("PointerLikeRegClass")) {
361      errs() << "Operand type: " << rec.getName().c_str() << "\n";
362      errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
363      errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
364      llvm_unreachable("Unhandled type");
365    }
366  }
367}
368
369/// decorate1 - Decorates a named operand with a new flag
370///
371/// @operandFlags - The array of operand flag objects, which don't have names
372/// @inst         - The CodeGenInstruction, which provides a way to translate
373///                 between names and operand indices
374/// @opName       - The name of the operand
375/// @flag         - The name of the flag to add
376static inline void decorate1(
377  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
378  const CodeGenInstruction &inst,
379  const char *opName,
380  const char *opFlag) {
381  unsigned opIndex;
382
383  opIndex = inst.Operands.getOperandNamed(std::string(opName));
384
385  operandFlags[opIndex]->addEntry(opFlag);
386}
387
388#define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
389
390#define MOV(source, target) {               \
391  instType.set("kInstructionTypeMove");     \
392  DECORATE1(source, "kOperandFlagSource");  \
393  DECORATE1(target, "kOperandFlagTarget");  \
394}
395
396#define BRANCH(target) {                    \
397  instType.set("kInstructionTypeBranch");   \
398  DECORATE1(target, "kOperandFlagTarget");  \
399}
400
401#define PUSH(source) {                      \
402  instType.set("kInstructionTypePush");     \
403  DECORATE1(source, "kOperandFlagSource");  \
404}
405
406#define POP(target) {                       \
407  instType.set("kInstructionTypePop");      \
408  DECORATE1(target, "kOperandFlagTarget");  \
409}
410
411#define CALL(target) {                      \
412  instType.set("kInstructionTypeCall");     \
413  DECORATE1(target, "kOperandFlagTarget");  \
414}
415
416#define RETURN() {                          \
417  instType.set("kInstructionTypeReturn");   \
418}
419
420/// X86ExtractSemantics - Performs various checks on the name of an X86
421///   instruction to determine what sort of an instruction it is and then adds
422///   the appropriate flags to the instruction and its operands
423///
424/// @arg instType     - A reference to the type for the instruction as a whole
425/// @arg operandFlags - A reference to the array of operand flag object pointers
426/// @arg inst         - A reference to the original instruction
427static void X86ExtractSemantics(
428  LiteralConstantEmitter &instType,
429  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
430  const CodeGenInstruction &inst) {
431  const std::string &name = inst.TheDef->getName();
432
433  if (name.find("MOV") != name.npos) {
434    if (name.find("MOV_V") != name.npos) {
435      // ignore (this is a pseudoinstruction)
436    } else if (name.find("MASK") != name.npos) {
437      // ignore (this is a masking move)
438    } else if (name.find("r0") != name.npos) {
439      // ignore (this is a pseudoinstruction)
440    } else if (name.find("PS") != name.npos ||
441             name.find("PD") != name.npos) {
442      // ignore (this is a shuffling move)
443    } else if (name.find("MOVS") != name.npos) {
444      // ignore (this is a string move)
445    } else if (name.find("_F") != name.npos) {
446      // TODO handle _F moves to ST(0)
447    } else if (name.find("a") != name.npos) {
448      // TODO handle moves to/from %ax
449    } else if (name.find("CMOV") != name.npos) {
450      MOV("src2", "dst");
451    } else if (name.find("PC") != name.npos) {
452      MOV("label", "reg")
453    } else {
454      MOV("src", "dst");
455    }
456  }
457
458  if (name.find("JMP") != name.npos ||
459      name.find("J") == 0) {
460    if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
461      BRANCH("off");
462    } else {
463      BRANCH("dst");
464    }
465  }
466
467  if (name.find("PUSH") != name.npos) {
468    if (name.find("CS") != name.npos ||
469        name.find("DS") != name.npos ||
470        name.find("ES") != name.npos ||
471        name.find("FS") != name.npos ||
472        name.find("GS") != name.npos ||
473        name.find("SS") != name.npos) {
474      instType.set("kInstructionTypePush");
475      // TODO add support for fixed operands
476    } else if (name.find("F") != name.npos) {
477      // ignore (this pushes onto the FP stack)
478    } else if (name.find("A") != name.npos) {
479      // ignore (pushes all GP registoers onto the stack)
480    } else if (name[name.length() - 1] == 'm') {
481      PUSH("src");
482    } else if (name.find("i") != name.npos) {
483      PUSH("imm");
484    } else {
485      PUSH("reg");
486    }
487  }
488
489  if (name.find("POP") != name.npos) {
490    if (name.find("POPCNT") != name.npos) {
491      // ignore (not a real pop)
492    } else if (name.find("CS") != name.npos ||
493               name.find("DS") != name.npos ||
494               name.find("ES") != name.npos ||
495               name.find("FS") != name.npos ||
496               name.find("GS") != name.npos ||
497               name.find("SS") != name.npos) {
498      instType.set("kInstructionTypePop");
499      // TODO add support for fixed operands
500    } else if (name.find("F") != name.npos) {
501      // ignore (this pops from the FP stack)
502    } else if (name.find("A") != name.npos) {
503      // ignore (pushes all GP registoers onto the stack)
504    } else if (name[name.length() - 1] == 'm') {
505      POP("dst");
506    } else {
507      POP("reg");
508    }
509  }
510
511  if (name.find("CALL") != name.npos) {
512    if (name.find("ADJ") != name.npos) {
513      // ignore (not a call)
514    } else if (name.find("SYSCALL") != name.npos) {
515      // ignore (doesn't go anywhere we know about)
516    } else if (name.find("VMCALL") != name.npos) {
517      // ignore (rather different semantics than a regular call)
518    } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
519      CALL("off");
520    } else {
521      CALL("dst");
522    }
523  }
524
525  if (name.find("RET") != name.npos) {
526    RETURN();
527  }
528}
529
530#undef MOV
531#undef BRANCH
532#undef PUSH
533#undef POP
534#undef CALL
535#undef RETURN
536
537/////////////////////////////////////////////////////
538// Support functions for handling ARM instructions //
539/////////////////////////////////////////////////////
540
541#define SET(flag) { type->set(flag); return 0; }
542
543#define REG(str)    if (name == str) SET("kOperandTypeRegister");
544#define IMM(str)    if (name == str) SET("kOperandTypeImmediate");
545
546#define MISC(str, type)   if (name == str) SET(type);
547
548/// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
549///   actually its type) and translates it into an operand type
550///
551/// @arg type     - The type object to set
552/// @arg name     - The name of the operand
553static int ARMFlagFromOpName(LiteralConstantEmitter *type,
554                             const std::string &name) {
555  REG("GPR");
556  REG("rGPR");
557  REG("tcGPR");
558  REG("cc_out");
559  REG("s_cc_out");
560  REG("tGPR");
561  REG("DPR");
562  REG("DPR_VFP2");
563  REG("DPR_8");
564  REG("SPR");
565  REG("QPR");
566  REG("QQPR");
567  REG("QQQQPR");
568
569  IMM("i32imm");
570  IMM("i32imm_hilo16");
571  IMM("bf_inv_mask_imm");
572  IMM("lsb_pos_imm");
573  IMM("width_imm");
574  IMM("jtblock_operand");
575  IMM("nohash_imm");
576  IMM("p_imm");
577  IMM("c_imm");
578  IMM("imod_op");
579  IMM("iflags_op");
580  IMM("cpinst_operand");
581  IMM("setend_op");
582  IMM("cps_opt");
583  IMM("vfp_f64imm");
584  IMM("vfp_f32imm");
585  IMM("memb_opt");
586  IMM("msr_mask");
587  IMM("neg_zero");
588  IMM("imm0_31");
589  IMM("imm0_31_m1");
590  IMM("nModImm");
591  IMM("imm0_4095");
592  IMM("jt2block_operand");
593  IMM("t_imm_s4");
594  IMM("pclabel");
595  IMM("adrlabel");
596  IMM("t_adrlabel");
597  IMM("t2adrlabel");
598  IMM("shift_imm");
599  IMM("neon_vcvt_imm32");
600  IMM("shr_imm8");
601  IMM("shr_imm16");
602  IMM("shr_imm32");
603  IMM("shr_imm64");
604  IMM("t2ldrlabel");
605
606  MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
607  MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
608  MISC("t_brtarget", "kOperandTypeARMBranchTarget");              // ?
609  MISC("t_bcctarget", "kOperandTypeARMBranchTarget");             // ?
610  MISC("t_cbtarget", "kOperandTypeARMBranchTarget");              // ?
611  MISC("bltarget", "kOperandTypeARMBranchTarget");                // ?
612
613  MISC("br_target", "kOperandTypeARMBranchTarget");                // ?
614  MISC("bl_target", "kOperandTypeARMBranchTarget");                // ?
615
616  MISC("t_bltarget", "kOperandTypeARMBranchTarget");              // ?
617  MISC("t_blxtarget", "kOperandTypeARMBranchTarget");             // ?
618  MISC("so_reg", "kOperandTypeARMSoReg");                         // R, R, I
619  MISC("shift_so_reg", "kOperandTypeARMSoReg");                   // R, R, I
620  MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I
621  MISC("so_imm", "kOperandTypeARMSoImm");                         // I
622  MISC("rot_imm", "kOperandTypeARMRotImm");                       // I
623  MISC("t2_so_imm", "kOperandTypeThumb2SoImm");                   // I
624  MISC("so_imm2part", "kOperandTypeARMSoImm2Part");               // I
625  MISC("pred", "kOperandTypeARMPredicate");                       // I, R
626  MISC("it_pred", "kOperandTypeARMPredicate");                    // I
627  MISC("addrmode_imm12", "kOperandTypeAddrModeImm12");            // R, I
628  MISC("ldst_so_reg", "kOperandTypeLdStSOReg");                   // R, R, I
629  MISC("addrmode2", "kOperandTypeARMAddrMode2");                  // R, R, I
630  MISC("am2offset", "kOperandTypeARMAddrMode2Offset");            // R, I
631  MISC("addrmode3", "kOperandTypeARMAddrMode3");                  // R, R, I
632  MISC("am3offset", "kOperandTypeARMAddrMode3Offset");            // R, I
633  MISC("ldstm_mode", "kOperandTypeARMLdStmMode");                 // I
634  MISC("addrmode5", "kOperandTypeARMAddrMode5");                  // R, I
635  MISC("addrmode6", "kOperandTypeARMAddrMode6");                  // R, R, I, I
636  MISC("am6offset", "kOperandTypeARMAddrMode6Offset");            // R, I, I
637  MISC("addrmode6dup", "kOperandTypeARMAddrMode6");               // R, R, I, I
638  MISC("addrmodepc", "kOperandTypeARMAddrModePC");                // R, I
639  MISC("addrmode7", "kOperandTypeARMAddrMode7");                  // R
640  MISC("reglist", "kOperandTypeARMRegisterList");                 // I, R, ...
641  MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList");          // I, R, ...
642  MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
643  MISC("it_mask", "kOperandTypeThumbITMask");                     // I
644  MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
645  MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
646  MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
647  MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
648  MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
649  MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
650  MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
651                                                                  // R, I
652  MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
653  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS");       // R, R
654  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS");       // R, R
655  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS");       // R, R
656  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS");        // R, I
657  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS");        // R, I
658  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS");        // R, I
659  MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
660  MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
661  MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
662
663  return 1;
664}
665
666#undef SOREG
667#undef SOIMM
668#undef PRED
669#undef REG
670#undef MEM
671#undef LEA
672#undef IMM
673#undef PCR
674
675#undef SET
676
677/// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
678///   the appropriate flags to their descriptors
679///
680/// @operandFlags - A reference the array of operand flag objects
681/// @inst         - The instruction to use as a source of information
682static void ARMPopulateOperands(
683  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
684  const CodeGenInstruction &inst) {
685  if (!inst.TheDef->isSubClassOf("InstARM") &&
686      !inst.TheDef->isSubClassOf("InstThumb"))
687    return;
688
689  unsigned int index;
690  unsigned int numOperands = inst.Operands.size();
691
692  if (numOperands > EDIS_MAX_OPERANDS) {
693    errs() << "numOperands == " << numOperands << " > " <<
694      EDIS_MAX_OPERANDS << '\n';
695    llvm_unreachable("Too many operands");
696  }
697
698  for (index = 0; index < numOperands; ++index) {
699    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
700    Record &rec = *operandInfo.Rec;
701
702    if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
703      errs() << "Operand type: " << rec.getName() << '\n';
704      errs() << "Operand name: " << operandInfo.Name << '\n';
705      errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
706      llvm_unreachable("Unhandled type");
707    }
708  }
709}
710
711#define BRANCH(target) {                    \
712  instType.set("kInstructionTypeBranch");   \
713  DECORATE1(target, "kOperandFlagTarget");  \
714}
715
716/// ARMExtractSemantics - Performs various checks on the name of an ARM
717///   instruction to determine what sort of an instruction it is and then adds
718///   the appropriate flags to the instruction and its operands
719///
720/// @arg instType     - A reference to the type for the instruction as a whole
721/// @arg operandTypes - A reference to the array of operand type object pointers
722/// @arg operandFlags - A reference to the array of operand flag object pointers
723/// @arg inst         - A reference to the original instruction
724static void ARMExtractSemantics(
725  LiteralConstantEmitter &instType,
726  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
727  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
728  const CodeGenInstruction &inst) {
729  const std::string &name = inst.TheDef->getName();
730
731  if (name == "tBcc"   ||
732      name == "tB"     ||
733      name == "t2Bcc"  ||
734      name == "Bcc"    ||
735      name == "tCBZ"   ||
736      name == "tCBNZ") {
737    BRANCH("target");
738  }
739
740  if (name == "tBLr9"      ||
741      name == "BLr9_pred"  ||
742      name == "tBLXi_r9"   ||
743      name == "tBLXr_r9"   ||
744      name == "BLXr9"      ||
745      name == "t2BXJ"      ||
746      name == "BXJ") {
747    BRANCH("func");
748
749    unsigned opIndex;
750    opIndex = inst.Operands.getOperandNamed("func");
751    if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
752      operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
753  }
754}
755
756#undef BRANCH
757
758/// populateInstInfo - Fills an array of InstInfos with information about each
759///   instruction in a target
760///
761/// @arg infoArray  - The array of InstInfo objects to populate
762/// @arg target     - The CodeGenTarget to use as a source of instructions
763static void populateInstInfo(CompoundConstantEmitter &infoArray,
764                             CodeGenTarget &target) {
765  const std::vector<const CodeGenInstruction*> &numberedInstructions =
766    target.getInstructionsByEnumValue();
767
768  unsigned int index;
769  unsigned int numInstructions = numberedInstructions.size();
770
771  for (index = 0; index < numInstructions; ++index) {
772    const CodeGenInstruction& inst = *numberedInstructions[index];
773
774    CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
775    infoArray.addEntry(infoStruct);
776
777    LiteralConstantEmitter *instType = new LiteralConstantEmitter;
778    infoStruct->addEntry(instType);
779
780    LiteralConstantEmitter *numOperandsEmitter =
781      new LiteralConstantEmitter(inst.Operands.size());
782    infoStruct->addEntry(numOperandsEmitter);
783
784    CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
785    infoStruct->addEntry(operandTypeArray);
786
787    LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
788
789    CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
790    infoStruct->addEntry(operandFlagArray);
791
792    FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
793
794    for (unsigned operandIndex = 0;
795         operandIndex < EDIS_MAX_OPERANDS;
796         ++operandIndex) {
797      operandTypes[operandIndex] = new LiteralConstantEmitter;
798      operandTypeArray->addEntry(operandTypes[operandIndex]);
799
800      operandFlags[operandIndex] = new FlagsConstantEmitter;
801      operandFlagArray->addEntry(operandFlags[operandIndex]);
802    }
803
804    unsigned numSyntaxes = 0;
805
806    if (target.getName() == "X86") {
807      X86PopulateOperands(operandTypes, inst);
808      X86ExtractSemantics(*instType, operandFlags, inst);
809      numSyntaxes = 2;
810    }
811    else if (target.getName() == "ARM") {
812      ARMPopulateOperands(operandTypes, inst);
813      ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
814      numSyntaxes = 1;
815    }
816
817    CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
818
819    infoStruct->addEntry(operandOrderArray);
820
821    for (unsigned syntaxIndex = 0;
822         syntaxIndex < EDIS_MAX_SYNTAXES;
823         ++syntaxIndex) {
824      CompoundConstantEmitter *operandOrder =
825        new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
826
827      operandOrderArray->addEntry(operandOrder);
828
829      if (syntaxIndex < numSyntaxes) {
830        populateOperandOrder(operandOrder, inst, syntaxIndex);
831      }
832    }
833
834    infoStruct = NULL;
835  }
836}
837
838static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
839  EnumEmitter operandTypes("OperandTypes");
840  operandTypes.addEntry("kOperandTypeNone");
841  operandTypes.addEntry("kOperandTypeImmediate");
842  operandTypes.addEntry("kOperandTypeRegister");
843  operandTypes.addEntry("kOperandTypeX86Memory");
844  operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
845  operandTypes.addEntry("kOperandTypeX86PCRelative");
846  operandTypes.addEntry("kOperandTypeARMBranchTarget");
847  operandTypes.addEntry("kOperandTypeARMSoReg");
848  operandTypes.addEntry("kOperandTypeARMSoImm");
849  operandTypes.addEntry("kOperandTypeARMRotImm");
850  operandTypes.addEntry("kOperandTypeARMSoImm2Part");
851  operandTypes.addEntry("kOperandTypeARMPredicate");
852  operandTypes.addEntry("kOperandTypeAddrModeImm12");
853  operandTypes.addEntry("kOperandTypeLdStSOReg");
854  operandTypes.addEntry("kOperandTypeARMAddrMode2");
855  operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
856  operandTypes.addEntry("kOperandTypeARMAddrMode3");
857  operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
858  operandTypes.addEntry("kOperandTypeARMLdStmMode");
859  operandTypes.addEntry("kOperandTypeARMAddrMode5");
860  operandTypes.addEntry("kOperandTypeARMAddrMode6");
861  operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
862  operandTypes.addEntry("kOperandTypeARMAddrMode7");
863  operandTypes.addEntry("kOperandTypeARMAddrModePC");
864  operandTypes.addEntry("kOperandTypeARMRegisterList");
865  operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
866  operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
867  operandTypes.addEntry("kOperandTypeARMTBAddrMode");
868  operandTypes.addEntry("kOperandTypeThumbITMask");
869  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS");
870  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS");
871  operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
872  operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
873  operandTypes.addEntry("kOperandTypeThumbAddrModePC");
874  operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
875  operandTypes.addEntry("kOperandTypeThumb2SoReg");
876  operandTypes.addEntry("kOperandTypeThumb2SoImm");
877  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
878  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
879  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
880  operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
881  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
882  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
883  operandTypes.emit(o, i);
884
885  o << "\n";
886
887  EnumEmitter operandFlags("OperandFlags");
888  operandFlags.addEntry("kOperandFlagSource");
889  operandFlags.addEntry("kOperandFlagTarget");
890  operandFlags.emitAsFlags(o, i);
891
892  o << "\n";
893
894  EnumEmitter instructionTypes("InstructionTypes");
895  instructionTypes.addEntry("kInstructionTypeNone");
896  instructionTypes.addEntry("kInstructionTypeMove");
897  instructionTypes.addEntry("kInstructionTypeBranch");
898  instructionTypes.addEntry("kInstructionTypePush");
899  instructionTypes.addEntry("kInstructionTypePop");
900  instructionTypes.addEntry("kInstructionTypeCall");
901  instructionTypes.addEntry("kInstructionTypeReturn");
902  instructionTypes.emit(o, i);
903
904  o << "\n";
905}
906
907void EDEmitter::run(raw_ostream &o) {
908  unsigned int i = 0;
909
910  CompoundConstantEmitter infoArray;
911  CodeGenTarget target(Records);
912
913  populateInstInfo(infoArray, target);
914
915  emitCommonEnums(o, i);
916
917  o << "namespace {\n";
918
919  o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
920  infoArray.emit(o, i);
921  o << ";" << "\n";
922
923  o << "}\n";
924}
925