EDEmitter.cpp revision f0eee6eca8c39b11b6a41d9b04eba8985655df77 
1//===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of each
11// instruction in a format that the enhanced disassembler can use to tokenize
12// and parse instructions.
13//
14//===----------------------------------------------------------------------===//
15
16#include "EDEmitter.h"
17
18#include "AsmWriterInst.h"
19#include "CodeGenTarget.h"
20#include "Record.h"
21
22#include "llvm/MC/EDInstInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/Format.h"
25#include "llvm/Support/raw_ostream.h"
26
27#include <string>
28#include <vector>
29
30using namespace llvm;
31
32///////////////////////////////////////////////////////////
33// Support classes for emitting nested C data structures //
34///////////////////////////////////////////////////////////
35
36namespace {
37
38  class EnumEmitter {
39  private:
40    std::string Name;
41    std::vector<std::string> Entries;
42  public:
43    EnumEmitter(const char *N) : Name(N) {
44    }
45    int addEntry(const char *e) {
46      Entries.push_back(std::string(e));
47      return Entries.size() - 1;
48    }
49    void emit(raw_ostream &o, unsigned int &i) {
50      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
51      i += 2;
52
53      unsigned int index = 0;
54      unsigned int numEntries = Entries.size();
55      for (index = 0; index < numEntries; ++index) {
56        o.indent(i) << Entries[index];
57        if (index < (numEntries - 1))
58          o << ",";
59        o << "\n";
60      }
61
62      i -= 2;
63      o.indent(i) << "};" << "\n";
64    }
65
66    void emitAsFlags(raw_ostream &o, unsigned int &i) {
67      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
68      i += 2;
69
70      unsigned int index = 0;
71      unsigned int numEntries = Entries.size();
72      unsigned int flag = 1;
73      for (index = 0; index < numEntries; ++index) {
74        o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75        if (index < (numEntries - 1))
76          o << ",";
77        o << "\n";
78        flag <<= 1;
79      }
80
81      i -= 2;
82      o.indent(i) << "};" << "\n";
83    }
84  };
85
86  class ConstantEmitter {
87  public:
88    virtual ~ConstantEmitter() { }
89    virtual void emit(raw_ostream &o, unsigned int &i) = 0;
90  };
91
92  class LiteralConstantEmitter : public ConstantEmitter {
93  private:
94    bool IsNumber;
95    union {
96      int Number;
97      const char* String;
98    };
99  public:
100    LiteralConstantEmitter(int number = 0) :
101      IsNumber(true),
102      Number(number) {
103    }
104    void set(const char *string) {
105      IsNumber = false;
106      Number = 0;
107      String = string;
108    }
109    bool is(const char *string) {
110      return !strcmp(String, string);
111    }
112    void emit(raw_ostream &o, unsigned int &i) {
113      if (IsNumber)
114        o << Number;
115      else
116        o << String;
117    }
118  };
119
120  class CompoundConstantEmitter : public ConstantEmitter {
121  private:
122    unsigned int Padding;
123    std::vector<ConstantEmitter *> Entries;
124  public:
125    CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
126    }
127    CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128      Entries.push_back(e);
129
130      return *this;
131    }
132    ~CompoundConstantEmitter() {
133      while (Entries.size()) {
134        ConstantEmitter *entry = Entries.back();
135        Entries.pop_back();
136        delete entry;
137      }
138    }
139    void emit(raw_ostream &o, unsigned int &i) {
140      o << "{" << "\n";
141      i += 2;
142
143      unsigned int index;
144      unsigned int numEntries = Entries.size();
145
146      unsigned int numToPrint;
147
148      if (Padding) {
149        if (numEntries > Padding) {
150          fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151          llvm_unreachable("More entries than padding");
152        }
153        numToPrint = Padding;
154      } else {
155        numToPrint = numEntries;
156      }
157
158      for (index = 0; index < numToPrint; ++index) {
159        o.indent(i);
160        if (index < numEntries)
161          Entries[index]->emit(o, i);
162        else
163          o << "-1";
164
165        if (index < (numToPrint - 1))
166          o << ",";
167        o << "\n";
168      }
169
170      i -= 2;
171      o.indent(i) << "}";
172    }
173  };
174
175  class FlagsConstantEmitter : public ConstantEmitter {
176  private:
177    std::vector<std::string> Flags;
178  public:
179    FlagsConstantEmitter() {
180    }
181    FlagsConstantEmitter &addEntry(const char *f) {
182      Flags.push_back(std::string(f));
183      return *this;
184    }
185    void emit(raw_ostream &o, unsigned int &i) {
186      unsigned int index;
187      unsigned int numFlags = Flags.size();
188      if (numFlags == 0)
189        o << "0";
190
191      for (index = 0; index < numFlags; ++index) {
192        o << Flags[index].c_str();
193        if (index < (numFlags - 1))
194          o << " | ";
195      }
196    }
197  };
198}
199
200EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
201}
202
203/// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204///   AsmWriterInst for the desired assembly syntax, giving an ordered list of
205///   operands in the order they appear in the printed instruction.  Then, for
206///   each entry in that list, determines the index of the same operand in the
207///   CodeGenInstruction, and emits the resulting mapping into an array, filling
208///   in unused slots with -1.
209///
210/// @arg operandOrder - The array that will be populated with the operand
211///                     mapping.  Each entry will contain -1 (invalid index
212///                     into the operands present in the AsmString) or a number
213///                     representing an index in the operand descriptor array.
214/// @arg inst         - The instruction to use when looking up the operands
215/// @arg syntax       - The syntax to use, according to LLVM's enumeration
216void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217                          const CodeGenInstruction &inst,
218                          unsigned syntax) {
219  unsigned int numArgs = 0;
220
221  AsmWriterInst awInst(inst, syntax, -1, -1);
222
223  std::vector<AsmWriterOperand>::iterator operandIterator;
224
225  for (operandIterator = awInst.Operands.begin();
226       operandIterator != awInst.Operands.end();
227       ++operandIterator) {
228    if (operandIterator->OperandType ==
229        AsmWriterOperand::isMachineInstrOperand) {
230      operandOrder->addEntry(
231        new LiteralConstantEmitter(operandIterator->CGIOpNo));
232      numArgs++;
233    }
234  }
235}
236
237/////////////////////////////////////////////////////
238// Support functions for handling X86 instructions //
239/////////////////////////////////////////////////////
240
241#define SET(flag) { type->set(flag); return 0; }
242
243#define REG(str) if (name == str) SET("kOperandTypeRegister");
244#define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245#define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247#define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
248
249/// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250///   actually its type) and translates it into an operand type
251///
252/// @arg flags    - The type object to set
253/// @arg name     - The name of the operand
254static int X86TypeFromOpName(LiteralConstantEmitter *type,
255                             const std::string &name) {
256  REG("GR8");
257  REG("GR8_NOREX");
258  REG("GR16");
259  REG("GR32");
260  REG("GR32_NOREX");
261  REG("GR32_TC");
262  REG("FR32");
263  REG("RFP32");
264  REG("GR64");
265  REG("GR64_TC");
266  REG("FR64");
267  REG("VR64");
268  REG("RFP64");
269  REG("RFP80");
270  REG("VR128");
271  REG("VR256");
272  REG("RST");
273  REG("SEGMENT_REG");
274  REG("DEBUG_REG");
275  REG("CONTROL_REG");
276
277  IMM("i8imm");
278  IMM("i16imm");
279  IMM("i16i8imm");
280  IMM("i32imm");
281  IMM("i32i8imm");
282  IMM("u32u8imm");
283  IMM("i64imm");
284  IMM("i64i8imm");
285  IMM("i64i32imm");
286  IMM("SSECC");
287
288  // all R, I, R, I, R
289  MEM("i8mem");
290  MEM("i8mem_NOREX");
291  MEM("i16mem");
292  MEM("i32mem");
293  MEM("i32mem_TC");
294  MEM("f32mem");
295  MEM("ssmem");
296  MEM("opaque32mem");
297  MEM("opaque48mem");
298  MEM("i64mem");
299  MEM("i64mem_TC");
300  MEM("f64mem");
301  MEM("sdmem");
302  MEM("f80mem");
303  MEM("opaque80mem");
304  MEM("i128mem");
305  MEM("i256mem");
306  MEM("f128mem");
307  MEM("f256mem");
308  MEM("opaque512mem");
309
310  // all R, I, R, I
311  LEA("lea32mem");
312  LEA("lea64_32mem");
313  LEA("lea64mem");
314
315  // all I
316  PCR("i16imm_pcrel");
317  PCR("i32imm_pcrel");
318  PCR("i64i32imm_pcrel");
319  PCR("brtarget8");
320  PCR("offset8");
321  PCR("offset16");
322  PCR("offset32");
323  PCR("offset64");
324  PCR("brtarget");
325  PCR("uncondbrtarget");
326  PCR("bltarget");
327
328  // all I, ARM mode only, conditional/unconditional
329  PCR("br_target");
330  PCR("bl_target");
331  return 1;
332}
333
334#undef REG
335#undef MEM
336#undef LEA
337#undef IMM
338#undef PCR
339
340#undef SET
341
342/// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
343///   the appropriate flags to their descriptors
344///
345/// @operandFlags - A reference the array of operand flag objects
346/// @inst         - The instruction to use as a source of information
347static void X86PopulateOperands(
348  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
349  const CodeGenInstruction &inst) {
350  if (!inst.TheDef->isSubClassOf("X86Inst"))
351    return;
352
353  unsigned int index;
354  unsigned int numOperands = inst.Operands.size();
355
356  for (index = 0; index < numOperands; ++index) {
357    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
358    Record &rec = *operandInfo.Rec;
359
360    if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
361        !rec.isSubClassOf("PointerLikeRegClass")) {
362      errs() << "Operand type: " << rec.getName().c_str() << "\n";
363      errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
364      errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
365      llvm_unreachable("Unhandled type");
366    }
367  }
368}
369
370/// decorate1 - Decorates a named operand with a new flag
371///
372/// @operandFlags - The array of operand flag objects, which don't have names
373/// @inst         - The CodeGenInstruction, which provides a way to translate
374///                 between names and operand indices
375/// @opName       - The name of the operand
376/// @flag         - The name of the flag to add
377static inline void decorate1(
378  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
379  const CodeGenInstruction &inst,
380  const char *opName,
381  const char *opFlag) {
382  unsigned opIndex;
383
384  opIndex = inst.Operands.getOperandNamed(std::string(opName));
385
386  operandFlags[opIndex]->addEntry(opFlag);
387}
388
389#define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
390
391#define MOV(source, target) {               \
392  instType.set("kInstructionTypeMove");     \
393  DECORATE1(source, "kOperandFlagSource");  \
394  DECORATE1(target, "kOperandFlagTarget");  \
395}
396
397#define BRANCH(target) {                    \
398  instType.set("kInstructionTypeBranch");   \
399  DECORATE1(target, "kOperandFlagTarget");  \
400}
401
402#define PUSH(source) {                      \
403  instType.set("kInstructionTypePush");     \
404  DECORATE1(source, "kOperandFlagSource");  \
405}
406
407#define POP(target) {                       \
408  instType.set("kInstructionTypePop");      \
409  DECORATE1(target, "kOperandFlagTarget");  \
410}
411
412#define CALL(target) {                      \
413  instType.set("kInstructionTypeCall");     \
414  DECORATE1(target, "kOperandFlagTarget");  \
415}
416
417#define RETURN() {                          \
418  instType.set("kInstructionTypeReturn");   \
419}
420
421/// X86ExtractSemantics - Performs various checks on the name of an X86
422///   instruction to determine what sort of an instruction it is and then adds
423///   the appropriate flags to the instruction and its operands
424///
425/// @arg instType     - A reference to the type for the instruction as a whole
426/// @arg operandFlags - A reference to the array of operand flag object pointers
427/// @arg inst         - A reference to the original instruction
428static void X86ExtractSemantics(
429  LiteralConstantEmitter &instType,
430  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
431  const CodeGenInstruction &inst) {
432  const std::string &name = inst.TheDef->getName();
433
434  if (name.find("MOV") != name.npos) {
435    if (name.find("MOV_V") != name.npos) {
436      // ignore (this is a pseudoinstruction)
437    } else if (name.find("MASK") != name.npos) {
438      // ignore (this is a masking move)
439    } else if (name.find("r0") != name.npos) {
440      // ignore (this is a pseudoinstruction)
441    } else if (name.find("PS") != name.npos ||
442             name.find("PD") != name.npos) {
443      // ignore (this is a shuffling move)
444    } else if (name.find("MOVS") != name.npos) {
445      // ignore (this is a string move)
446    } else if (name.find("_F") != name.npos) {
447      // TODO handle _F moves to ST(0)
448    } else if (name.find("a") != name.npos) {
449      // TODO handle moves to/from %ax
450    } else if (name.find("CMOV") != name.npos) {
451      MOV("src2", "dst");
452    } else if (name.find("PC") != name.npos) {
453      MOV("label", "reg")
454    } else {
455      MOV("src", "dst");
456    }
457  }
458
459  if (name.find("JMP") != name.npos ||
460      name.find("J") == 0) {
461    if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
462      BRANCH("off");
463    } else {
464      BRANCH("dst");
465    }
466  }
467
468  if (name.find("PUSH") != name.npos) {
469    if (name.find("CS") != name.npos ||
470        name.find("DS") != name.npos ||
471        name.find("ES") != name.npos ||
472        name.find("FS") != name.npos ||
473        name.find("GS") != name.npos ||
474        name.find("SS") != name.npos) {
475      instType.set("kInstructionTypePush");
476      // TODO add support for fixed operands
477    } else if (name.find("F") != name.npos) {
478      // ignore (this pushes onto the FP stack)
479    } else if (name.find("A") != name.npos) {
480      // ignore (pushes all GP registoers onto the stack)
481    } else if (name[name.length() - 1] == 'm') {
482      PUSH("src");
483    } else if (name.find("i") != name.npos) {
484      PUSH("imm");
485    } else {
486      PUSH("reg");
487    }
488  }
489
490  if (name.find("POP") != name.npos) {
491    if (name.find("POPCNT") != name.npos) {
492      // ignore (not a real pop)
493    } else if (name.find("CS") != name.npos ||
494               name.find("DS") != name.npos ||
495               name.find("ES") != name.npos ||
496               name.find("FS") != name.npos ||
497               name.find("GS") != name.npos ||
498               name.find("SS") != name.npos) {
499      instType.set("kInstructionTypePop");
500      // TODO add support for fixed operands
501    } else if (name.find("F") != name.npos) {
502      // ignore (this pops from the FP stack)
503    } else if (name.find("A") != name.npos) {
504      // ignore (pushes all GP registoers onto the stack)
505    } else if (name[name.length() - 1] == 'm') {
506      POP("dst");
507    } else {
508      POP("reg");
509    }
510  }
511
512  if (name.find("CALL") != name.npos) {
513    if (name.find("ADJ") != name.npos) {
514      // ignore (not a call)
515    } else if (name.find("SYSCALL") != name.npos) {
516      // ignore (doesn't go anywhere we know about)
517    } else if (name.find("VMCALL") != name.npos) {
518      // ignore (rather different semantics than a regular call)
519    } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
520      CALL("off");
521    } else {
522      CALL("dst");
523    }
524  }
525
526  if (name.find("RET") != name.npos) {
527    RETURN();
528  }
529}
530
531#undef MOV
532#undef BRANCH
533#undef PUSH
534#undef POP
535#undef CALL
536#undef RETURN
537
538/////////////////////////////////////////////////////
539// Support functions for handling ARM instructions //
540/////////////////////////////////////////////////////
541
542#define SET(flag) { type->set(flag); return 0; }
543
544#define REG(str)    if (name == str) SET("kOperandTypeRegister");
545#define IMM(str)    if (name == str) SET("kOperandTypeImmediate");
546
547#define MISC(str, type)   if (name == str) SET(type);
548
549/// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
550///   actually its type) and translates it into an operand type
551///
552/// @arg type     - The type object to set
553/// @arg name     - The name of the operand
554static int ARMFlagFromOpName(LiteralConstantEmitter *type,
555                             const std::string &name) {
556  REG("GPR");
557  REG("rGPR");
558  REG("GPRnopc");
559  REG("GPRsp");
560  REG("tcGPR");
561  REG("cc_out");
562  REG("s_cc_out");
563  REG("tGPR");
564  REG("DPR");
565  REG("DPR_VFP2");
566  REG("DPR_8");
567  REG("SPR");
568  REG("QPR");
569  REG("QQPR");
570  REG("QQQQPR");
571
572  IMM("i32imm");
573  IMM("i32imm_hilo16");
574  IMM("bf_inv_mask_imm");
575  IMM("lsb_pos_imm");
576  IMM("width_imm");
577  IMM("jtblock_operand");
578  IMM("nohash_imm");
579  IMM("p_imm");
580  IMM("c_imm");
581  IMM("imod_op");
582  IMM("iflags_op");
583  IMM("cpinst_operand");
584  IMM("setend_op");
585  IMM("cps_opt");
586  IMM("vfp_f64imm");
587  IMM("vfp_f32imm");
588  IMM("memb_opt");
589  IMM("msr_mask");
590  IMM("neg_zero");
591  IMM("imm0_31");
592  IMM("imm0_31_m1");
593  IMM("imm1_16");
594  IMM("imm1_32");
595  IMM("nModImm");
596  IMM("imm0_7");
597  IMM("imm0_15");
598  IMM("imm0_255");
599  IMM("imm0_4095");
600  IMM("imm0_65535");
601  IMM("imm0_65535_expr");
602  IMM("imm24b");
603  IMM("pkh_lsl_amt");
604  IMM("pkh_asr_amt");
605  IMM("jt2block_operand");
606  IMM("t_imm0_1020s4");
607  IMM("t_imm0_508s4");
608  IMM("pclabel");
609  IMM("adrlabel");
610  IMM("t_adrlabel");
611  IMM("t2adrlabel");
612  IMM("shift_imm");
613  IMM("neon_vcvt_imm32");
614  IMM("shr_imm8");
615  IMM("shr_imm16");
616  IMM("shr_imm32");
617  IMM("shr_imm64");
618  IMM("t2ldrlabel");
619  IMM("postidx_imm8");
620  IMM("postidx_imm8s4");
621  IMM("imm_sr");
622  IMM("imm1_31");
623
624  MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
625  MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
626  MISC("t_brtarget", "kOperandTypeARMBranchTarget");              // ?
627  MISC("t_bcctarget", "kOperandTypeARMBranchTarget");             // ?
628  MISC("t_cbtarget", "kOperandTypeARMBranchTarget");              // ?
629  MISC("bltarget", "kOperandTypeARMBranchTarget");                // ?
630
631  MISC("br_target", "kOperandTypeARMBranchTarget");                // ?
632  MISC("bl_target", "kOperandTypeARMBranchTarget");                // ?
633  MISC("blx_target", "kOperandTypeARMBranchTarget");                // ?
634
635  MISC("t_bltarget", "kOperandTypeARMBranchTarget");              // ?
636  MISC("t_blxtarget", "kOperandTypeARMBranchTarget");             // ?
637  MISC("so_reg_imm", "kOperandTypeARMSoRegReg");                         // R, R, I
638  MISC("so_reg_reg", "kOperandTypeARMSoRegImm");                         // R, R, I
639  MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg");                   // R, R, I
640  MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm");                   // R, R, I
641  MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I
642  MISC("so_imm", "kOperandTypeARMSoImm");                         // I
643  MISC("rot_imm", "kOperandTypeARMRotImm");                       // I
644  MISC("t2_so_imm", "kOperandTypeThumb2SoImm");                   // I
645  MISC("so_imm2part", "kOperandTypeARMSoImm2Part");               // I
646  MISC("pred", "kOperandTypeARMPredicate");                       // I, R
647  MISC("it_pred", "kOperandTypeARMPredicate");                    // I
648  MISC("addrmode_imm12", "kOperandTypeAddrModeImm12");            // R, I
649  MISC("ldst_so_reg", "kOperandTypeLdStSOReg");                   // R, R, I
650  MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset");          // R, I
651  MISC("addrmode2", "kOperandTypeARMAddrMode2");                  // R, R, I
652  MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset");        // R, I
653  MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset");        // R, I
654  MISC("addrmode3", "kOperandTypeARMAddrMode3");                  // R, R, I
655  MISC("am3offset", "kOperandTypeARMAddrMode3Offset");            // R, I
656  MISC("ldstm_mode", "kOperandTypeARMLdStmMode");                 // I
657  MISC("addrmode5", "kOperandTypeARMAddrMode5");                  // R, I
658  MISC("addrmode6", "kOperandTypeARMAddrMode6");                  // R, R, I, I
659  MISC("am6offset", "kOperandTypeARMAddrMode6Offset");            // R, I, I
660  MISC("addrmode6dup", "kOperandTypeARMAddrMode6");               // R, R, I, I
661  MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6");            // R, R, I, I
662  MISC("addrmodepc", "kOperandTypeARMAddrModePC");                // R, I
663  MISC("addr_offset_none", "kOperandTypeARMAddrMode7");           // R
664  MISC("reglist", "kOperandTypeARMRegisterList");                 // I, R, ...
665  MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList");          // I, R, ...
666  MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
667  MISC("it_mask", "kOperandTypeThumbITMask");                     // I
668  MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
669  MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
670  MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
671  MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
672  MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
673  MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
674  MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
675  MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
676  MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
677                                                                  // R, I
678  MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
679  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1");      // R, R
680  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2");      // R, R
681  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4");      // R, R
682  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1");       // R, I
683  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2");       // R, I
684  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4");       // R, I
685  MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
686  MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
687  MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
688
689  return 1;
690}
691
692#undef REG
693#undef MEM
694#undef MISC
695
696#undef SET
697
698/// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
699///   the appropriate flags to their descriptors
700///
701/// @operandFlags - A reference the array of operand flag objects
702/// @inst         - The instruction to use as a source of information
703static void ARMPopulateOperands(
704  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
705  const CodeGenInstruction &inst) {
706  if (!inst.TheDef->isSubClassOf("InstARM") &&
707      !inst.TheDef->isSubClassOf("InstThumb"))
708    return;
709
710  unsigned int index;
711  unsigned int numOperands = inst.Operands.size();
712
713  if (numOperands > EDIS_MAX_OPERANDS) {
714    errs() << "numOperands == " << numOperands << " > " <<
715      EDIS_MAX_OPERANDS << '\n';
716    llvm_unreachable("Too many operands");
717  }
718
719  for (index = 0; index < numOperands; ++index) {
720    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
721    Record &rec = *operandInfo.Rec;
722
723    if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
724      errs() << "Operand type: " << rec.getName() << '\n';
725      errs() << "Operand name: " << operandInfo.Name << '\n';
726      errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
727      llvm_unreachable("Unhandled type");
728    }
729  }
730}
731
732#define BRANCH(target) {                    \
733  instType.set("kInstructionTypeBranch");   \
734  DECORATE1(target, "kOperandFlagTarget");  \
735}
736
737/// ARMExtractSemantics - Performs various checks on the name of an ARM
738///   instruction to determine what sort of an instruction it is and then adds
739///   the appropriate flags to the instruction and its operands
740///
741/// @arg instType     - A reference to the type for the instruction as a whole
742/// @arg operandTypes - A reference to the array of operand type object pointers
743/// @arg operandFlags - A reference to the array of operand flag object pointers
744/// @arg inst         - A reference to the original instruction
745static void ARMExtractSemantics(
746  LiteralConstantEmitter &instType,
747  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
748  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
749  const CodeGenInstruction &inst) {
750  const std::string &name = inst.TheDef->getName();
751
752  if (name == "tBcc"   ||
753      name == "tB"     ||
754      name == "t2Bcc"  ||
755      name == "Bcc"    ||
756      name == "tCBZ"   ||
757      name == "tCBNZ") {
758    BRANCH("target");
759  }
760
761  if (name == "tBLr9"      ||
762      name == "BLr9_pred"  ||
763      name == "tBLXi_r9"   ||
764      name == "tBLXr_r9"   ||
765      name == "BLXr9"      ||
766      name == "t2BXJ"      ||
767      name == "BXJ") {
768    BRANCH("func");
769
770    unsigned opIndex;
771    opIndex = inst.Operands.getOperandNamed("func");
772    if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
773      operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
774  }
775}
776
777#undef BRANCH
778
779/// populateInstInfo - Fills an array of InstInfos with information about each
780///   instruction in a target
781///
782/// @arg infoArray  - The array of InstInfo objects to populate
783/// @arg target     - The CodeGenTarget to use as a source of instructions
784static void populateInstInfo(CompoundConstantEmitter &infoArray,
785                             CodeGenTarget &target) {
786  const std::vector<const CodeGenInstruction*> &numberedInstructions =
787    target.getInstructionsByEnumValue();
788
789  unsigned int index;
790  unsigned int numInstructions = numberedInstructions.size();
791
792  for (index = 0; index < numInstructions; ++index) {
793    const CodeGenInstruction& inst = *numberedInstructions[index];
794
795    // We don't need to do anything for pseudo-instructions, as we'll never
796    // see them here. We'll only see real instructions.
797    if (inst.isPseudo)
798      continue;
799
800    CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
801    infoArray.addEntry(infoStruct);
802
803    LiteralConstantEmitter *instType = new LiteralConstantEmitter;
804    infoStruct->addEntry(instType);
805
806    LiteralConstantEmitter *numOperandsEmitter =
807      new LiteralConstantEmitter(inst.Operands.size());
808    infoStruct->addEntry(numOperandsEmitter);
809
810    CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
811    infoStruct->addEntry(operandTypeArray);
812
813    LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
814
815    CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
816    infoStruct->addEntry(operandFlagArray);
817
818    FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
819
820    for (unsigned operandIndex = 0;
821         operandIndex < EDIS_MAX_OPERANDS;
822         ++operandIndex) {
823      operandTypes[operandIndex] = new LiteralConstantEmitter;
824      operandTypeArray->addEntry(operandTypes[operandIndex]);
825
826      operandFlags[operandIndex] = new FlagsConstantEmitter;
827      operandFlagArray->addEntry(operandFlags[operandIndex]);
828    }
829
830    unsigned numSyntaxes = 0;
831
832    if (target.getName() == "X86") {
833      X86PopulateOperands(operandTypes, inst);
834      X86ExtractSemantics(*instType, operandFlags, inst);
835      numSyntaxes = 2;
836    }
837    else if (target.getName() == "ARM") {
838      ARMPopulateOperands(operandTypes, inst);
839      ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
840      numSyntaxes = 1;
841    }
842
843    CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
844
845    infoStruct->addEntry(operandOrderArray);
846
847    for (unsigned syntaxIndex = 0;
848         syntaxIndex < EDIS_MAX_SYNTAXES;
849         ++syntaxIndex) {
850      CompoundConstantEmitter *operandOrder =
851        new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
852
853      operandOrderArray->addEntry(operandOrder);
854
855      if (syntaxIndex < numSyntaxes) {
856        populateOperandOrder(operandOrder, inst, syntaxIndex);
857      }
858    }
859
860    infoStruct = NULL;
861  }
862}
863
864static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
865  EnumEmitter operandTypes("OperandTypes");
866  operandTypes.addEntry("kOperandTypeNone");
867  operandTypes.addEntry("kOperandTypeImmediate");
868  operandTypes.addEntry("kOperandTypeRegister");
869  operandTypes.addEntry("kOperandTypeX86Memory");
870  operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
871  operandTypes.addEntry("kOperandTypeX86PCRelative");
872  operandTypes.addEntry("kOperandTypeARMBranchTarget");
873  operandTypes.addEntry("kOperandTypeARMSoRegReg");
874  operandTypes.addEntry("kOperandTypeARMSoRegImm");
875  operandTypes.addEntry("kOperandTypeARMSoImm");
876  operandTypes.addEntry("kOperandTypeARMRotImm");
877  operandTypes.addEntry("kOperandTypeARMSoImm2Part");
878  operandTypes.addEntry("kOperandTypeARMPredicate");
879  operandTypes.addEntry("kOperandTypeAddrModeImm12");
880  operandTypes.addEntry("kOperandTypeLdStSOReg");
881  operandTypes.addEntry("kOperandTypeARMAddrMode2");
882  operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
883  operandTypes.addEntry("kOperandTypeARMAddrMode3");
884  operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
885  operandTypes.addEntry("kOperandTypeARMLdStmMode");
886  operandTypes.addEntry("kOperandTypeARMAddrMode5");
887  operandTypes.addEntry("kOperandTypeARMAddrMode6");
888  operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
889  operandTypes.addEntry("kOperandTypeARMAddrMode7");
890  operandTypes.addEntry("kOperandTypeARMAddrModePC");
891  operandTypes.addEntry("kOperandTypeARMRegisterList");
892  operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
893  operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
894  operandTypes.addEntry("kOperandTypeARMTBAddrMode");
895  operandTypes.addEntry("kOperandTypeThumbITMask");
896  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
897  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
898  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
899  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
900  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
901  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
902  operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
903  operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
904  operandTypes.addEntry("kOperandTypeThumbAddrModePC");
905  operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
906  operandTypes.addEntry("kOperandTypeThumb2SoReg");
907  operandTypes.addEntry("kOperandTypeThumb2SoImm");
908  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
909  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
910  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
911  operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
912  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
913  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
914  operandTypes.emit(o, i);
915
916  o << "\n";
917
918  EnumEmitter operandFlags("OperandFlags");
919  operandFlags.addEntry("kOperandFlagSource");
920  operandFlags.addEntry("kOperandFlagTarget");
921  operandFlags.emitAsFlags(o, i);
922
923  o << "\n";
924
925  EnumEmitter instructionTypes("InstructionTypes");
926  instructionTypes.addEntry("kInstructionTypeNone");
927  instructionTypes.addEntry("kInstructionTypeMove");
928  instructionTypes.addEntry("kInstructionTypeBranch");
929  instructionTypes.addEntry("kInstructionTypePush");
930  instructionTypes.addEntry("kInstructionTypePop");
931  instructionTypes.addEntry("kInstructionTypeCall");
932  instructionTypes.addEntry("kInstructionTypeReturn");
933  instructionTypes.emit(o, i);
934
935  o << "\n";
936}
937
938void EDEmitter::run(raw_ostream &o) {
939  unsigned int i = 0;
940
941  CompoundConstantEmitter infoArray;
942  CodeGenTarget target(Records);
943
944  populateInstInfo(infoArray, target);
945
946  emitCommonEnums(o, i);
947
948  o << "namespace {\n";
949
950  o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
951  infoArray.emit(o, i);
952  o << ";" << "\n";
953
954  o << "}\n";
955}
956