opd_ibs_macro.h revision 5a4eb4eb367eccd4b976d1feae96cea96d2c50f2
1/** 2 * @file daemon/opd_ibs_macro.h 3 * AMD Family10h Instruction Based Sampling (IBS) related macro. 4 * 5 * @remark Copyright 2008 OProfile authors 6 * @remark Read the file COPYING 7 * 8 * @author Jason Yeh <jason.yeh@amd.com> 9 * @author Paul Drongowski <paul.drongowski@amd.com> 10 * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> 11 * Copyright (c) 2008 Advanced Micro Devices, Inc. 12 */ 13 14#ifndef OPD_IBS_MACRO_H 15#define OPD_IBS_MACRO_H 16 17/** 18 * The following defines are bit masks that are used to select 19 * IBS fetch event flags and values at the MSR level. 20 */ 21#define FETCH_MASK_LATENCY 0x0000ffff 22#define FETCH_MASK_COMPLETE 0x00040000 23#define FETCH_MASK_IC_MISS 0x00080000 24#define FETCH_MASK_PHY_ADDR 0x00100000 25#define FETCH_MASK_PG_SIZE 0x00600000 26#define FETCH_MASK_L1_MISS 0x00800000 27#define FETCH_MASK_L2_MISS 0x01000000 28#define FETCH_MASK_KILLED \ 29 (FETCH_MASK_L1_MISS|FETCH_MASK_L2_MISS|FETCH_MASK_PHY_ADDR|\ 30 FETCH_MASK_COMPLETE|FETCH_MASK_IC_MISS) 31 32 33/** 34 * The following defines are bit masks that are used to select 35 * IBS op event flags and values at the MSR level. 36 */ 37#define BR_MASK_RETIRE 0x0000ffff 38#define BR_MASK_BRN_RET 0x00000020 39#define BR_MASK_BRN_MISP 0x00000010 40#define BR_MASK_BRN_TAKEN 0x00000008 41#define BR_MASK_RETURN 0x00000004 42#define BR_MASK_MISP_RETURN 0x00000002 43#define BR_MASK_BRN_RESYNC 0x00000001 44 45#define NB_MASK_L3_STATE 0x00000020 46#define NB_MASK_REQ_DST_PROC 0x00000010 47#define NB_MASK_REQ_DATA_SRC 0x00000007 48 49#define DC_MASK_L2_HIT_1G 0x00080000 50#define DC_MASK_PHY_ADDR_VALID 0x00040000 51#define DC_MASK_LIN_ADDR_VALID 0x00020000 52#define DC_MASK_MAB_HIT 0x00010000 53#define DC_MASK_LOCKED_OP 0x00008000 54#define DC_MASK_WC_MEM_ACCESS 0x00004000 55#define DC_MASK_UC_MEM_ACCESS 0x00002000 56#define DC_MASK_ST_TO_LD_CANCEL 0x00001000 57#define DC_MASK_ST_TO_LD_FOR 0x00000800 58#define DC_MASK_ST_BANK_CONFLICT 0x00000400 59#define DC_MASK_LD_BANK_CONFLICT 0x00000200 60#define DC_MASK_MISALIGN_ACCESS 0x00000100 61#define DC_MASK_DC_MISS 0x00000080 62#define DC_MASK_L2_HIT_2M 0x00000040 63#define DC_MASK_L1_HIT_1G 0x00000020 64#define DC_MASK_L1_HIT_2M 0x00000010 65#define DC_MASK_L2_TLB_MISS 0x00000008 66#define DC_MASK_L1_TLB_MISS 0x00000004 67#define DC_MASK_STORE_OP 0x00000002 68#define DC_MASK_LOAD_OP 0x00000001 69 70 71/** 72 * IBS derived events: 73 * 74 * IBS derived events are identified by event select values which are 75 * similar to the event select values that identify performance monitoring 76 * counter (PMC) events. Event select values for IBS derived events begin 77 * at 0xf000. 78 * 79 * The definitions in this file *must* match definitions 80 * of IBS derived events in gh-events.xml and in the 81 * oprofile AMD Family 10h events file. More information 82 * about IBS derived events is given in the Software Oprimization 83 * Guide for AMD Family 10h Processors. 84 */ 85 86/** 87 * The following defines associate a 16-bit select value with an IBS 88 * derived fetch event. 89 */ 90#define DE_IBS_FETCH_ALL 0xf000 91#define DE_IBS_FETCH_KILLED 0xf001 92#define DE_IBS_FETCH_ATTEMPTED 0xf002 93#define DE_IBS_FETCH_COMPLETED 0xf003 94#define DE_IBS_FETCH_ABORTED 0xf004 95#define DE_IBS_L1_ITLB_HIT 0xf005 96#define DE_IBS_ITLB_L1M_L2H 0xf006 97#define DE_IBS_ITLB_L1M_L2M 0xf007 98#define DE_IBS_IC_MISS 0xf008 99#define DE_IBS_IC_HIT 0xf009 100#define DE_IBS_FETCH_4K_PAGE 0xf00a 101#define DE_IBS_FETCH_2M_PAGE 0xf00b 102#define DE_IBS_FETCH_1G_PAGE 0xf00c 103#define DE_IBS_FETCH_XX_PAGE 0xf00d 104#define DE_IBS_FETCH_LATENCY 0xf00e 105 106#define IBS_FETCH_BASE 0xf000 107#define IBS_FETCH_END 0xf00e 108#define IBS_FETCH_MAX (IBS_FETCH_END - IBS_FETCH_BASE + 1) 109#define IS_IBS_FETCH(x) (IBS_FETCH_BASE <= x && x <= IBS_FETCH_END) 110#define IBS_FETCH_OFFSET(x) (x - IBS_FETCH_BASE) 111 112/** 113 * The following defines associate a 16-bit select value with an IBS 114 * derived branch/return macro-op event. 115 */ 116#define DE_IBS_OP_ALL 0xf100 117#define DE_IBS_OP_TAG_TO_RETIRE 0xf101 118#define DE_IBS_OP_COMP_TO_RETIRE 0xf102 119#define DE_IBS_BRANCH_RETIRED 0xf103 120#define DE_IBS_BRANCH_MISP 0xf104 121#define DE_IBS_BRANCH_TAKEN 0xf105 122#define DE_IBS_BRANCH_MISP_TAKEN 0xf106 123#define DE_IBS_RETURN 0xf107 124#define DE_IBS_RETURN_MISP 0xf108 125#define DE_IBS_RESYNC 0xf109 126 127#define IBS_OP_BASE 0xf100 128#define IBS_OP_END 0xf109 129#define IBS_OP_MAX (IBS_OP_END - IBS_OP_BASE + 1) 130#define IS_IBS_OP(x) (IBS_OP_BASE <= x && x <= IBS_OP_END) 131#define IBS_OP_OFFSET(x) (x - IBS_OP_BASE) 132 133/** 134 * The following defines associate a 16-bit select value with an IBS 135 * derived load/store event. 136 */ 137#define DE_IBS_LS_ALL_OP 0xf200 138#define DE_IBS_LS_LOAD_OP 0xf201 139#define DE_IBS_LS_STORE_OP 0xf202 140#define DE_IBS_LS_DTLB_L1H 0xf203 141#define DE_IBS_LS_DTLB_L1M_L2H 0xf204 142#define DE_IBS_LS_DTLB_L1M_L2M 0xf205 143#define DE_IBS_LS_DC_MISS 0xf206 144#define DE_IBS_LS_DC_HIT 0xf207 145#define DE_IBS_LS_MISALIGNED 0xf208 146#define DE_IBS_LS_BNK_CONF_LOAD 0xf209 147#define DE_IBS_LS_BNK_CONF_STORE 0xf20a 148#define DE_IBS_LS_STL_FORWARDED 0xf20b 149#define DE_IBS_LS_STL_CANCELLED 0xf20c 150#define DE_IBS_LS_UC_MEM_ACCESS 0xf20d 151#define DE_IBS_LS_WC_MEM_ACCESS 0xf20e 152#define DE_IBS_LS_LOCKED_OP 0xf20f 153#define DE_IBS_LS_MAB_HIT 0xf210 154#define DE_IBS_LS_L1_DTLB_4K 0xf211 155#define DE_IBS_LS_L1_DTLB_2M 0xf212 156#define DE_IBS_LS_L1_DTLB_1G 0xf213 157#define DE_IBS_LS_L1_DTLB_RES 0xf214 158#define DE_IBS_LS_L2_DTLB_4K 0xf215 159#define DE_IBS_LS_L2_DTLB_2M 0xf216 160#define DE_IBS_LS_L2_DTLB_1G 0xf217 161#define DE_IBS_LS_L2_DTLB_RES2 0xf218 162#define DE_IBS_LS_DC_LOAD_LAT 0xf219 163 164#define IBS_OP_LS_BASE 0xf200 165#define IBS_OP_LS_END 0xf219 166#define IBS_OP_LS_MAX (IBS_OP_LS_END - IBS_OP_LS_BASE + 1) 167#define IS_IBS_OP_LS(x) (IBS_OP_LS_BASE <= x && x <= IBS_OP_LS_END) 168#define IBS_OP_LS_OFFSET(x) (x - IBS_OP_LS_BASE) 169 170 171/** 172 * The following defines associate a 16-bit select value with an IBS 173 * derived Northbridge (NB) event. 174 */ 175#define DE_IBS_NB_LOCAL 0xf240 176#define DE_IBS_NB_REMOTE 0xf241 177#define DE_IBS_NB_LOCAL_L3 0xf242 178#define DE_IBS_NB_LOCAL_CACHE 0xf243 179#define DE_IBS_NB_REMOTE_CACHE 0xf244 180#define DE_IBS_NB_LOCAL_DRAM 0xf245 181#define DE_IBS_NB_REMOTE_DRAM 0xf246 182#define DE_IBS_NB_LOCAL_OTHER 0xf247 183#define DE_IBS_NB_REMOTE_OTHER 0xf248 184#define DE_IBS_NB_CACHE_STATE_M 0xf249 185#define DE_IBS_NB_CACHE_STATE_O 0xf24a 186#define DE_IBS_NB_LOCAL_LATENCY 0xf24b 187#define DE_IBS_NB_REMOTE_LATENCY 0xf24c 188 189#define IBS_OP_NB_BASE 0xf240 190#define IBS_OP_NB_END 0xf24c 191#define IBS_OP_NB_MAX (IBS_OP_NB_END - IBS_OP_NB_BASE + 1) 192#define IS_IBS_OP_NB(x) (IBS_OP_NB_BASE <= x && x <= IBS_OP_NB_END) 193#define IBS_OP_NB_OFFSET(x) (x - IBS_OP_NB_BASE) 194 195 196#define OP_MAX_IBS_COUNTERS (IBS_FETCH_MAX + IBS_OP_MAX + IBS_OP_LS_MAX + IBS_OP_NB_MAX) 197 198 199/** 200 * These macro decodes IBS hardware-level event flags and fields. 201 * Translation results are either zero (false) or non-zero (true), except 202 * the fetch latency, which is a 16-bit cycle count, and the fetch page size 203 * field, which is a 2-bit unsigned integer. 204 */ 205 206/** Bits 47:32 IbsFetchLat: instruction fetch latency */ 207#define IBS_FETCH_FETCH_LATENCY(x) ((unsigned short)(x->ibs_fetch_ctl_high & FETCH_MASK_LATENCY)) 208 209/** Bit 50 IbsFetchComp: instruction fetch complete. */ 210#define IBS_FETCH_FETCH_COMPLETION(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_COMPLETE) != 0) 211 212/** Bit 51 IbsIcMiss: instruction cache miss. */ 213#define IBS_FETCH_INST_CACHE_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_IC_MISS) != 0) 214 215/** Bit 52 IbsPhyAddrValid: instruction fetch physical address valid. */ 216#define IBS_FETCH_PHYS_ADDR_VALID(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_PHY_ADDR) != 0) 217 218/** Bits 54:53 IbsL1TlbPgSz: instruction cache L1TLB page size. */ 219#define IBS_FETCH_TLB_PAGE_SIZE(x) ((unsigned short)((x->ibs_fetch_ctl_high >> 21) & 0x3)) 220 221/** Bit 55 IbsL1TlbMiss: instruction cache L1TLB miss. */ 222#define IBS_FETCH_M_L1_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L1_MISS) != 0) 223 224/** Bit 56 IbsL2TlbMiss: instruction cache L2TLB miss. */ 225#define IBS_FETCH_L2_TLB_MISS(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_L2_MISS) != 0) 226 227/** A fetch is a killed fetch if all the masked bits are clear */ 228#define IBS_FETCH_KILLED(x) ((x->ibs_fetch_ctl_high & FETCH_MASK_KILLED) == 0) 229 230#define IBS_FETCH_INST_CACHE_HIT(x) (IBS_FETCH_FETCH_COMPLETION(x) && !IBS_FETCH_INST_CACHE_MISS(x)) 231 232#define IBS_FETCH_L1_TLB_HIT(x) (!IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_PHYS_ADDR_VALID(x)) 233 234#define IBS_FETCH_ITLB_L1M_L2H(x) (IBS_FETCH_M_L1_TLB_MISS(x) && !IBS_FETCH_L2_TLB_MISS(x)) 235 236#define IBS_FETCH_ITLB_L1M_L2M(x) (IBS_FETCH_M_L1_TLB_MISS(x) && IBS_FETCH_L2_TLB_MISS(x)) 237 238 239/** 240 * These macros translates IBS op event data from its hardware-level 241 * representation .It hides the MSR layout of IBS op data. 242 */ 243 244/** 245 * MSRC001_1035 IBS OP Data Register (IbsOpData) 246 * 247 * 15:0 IbsCompToRetCtr: macro-op completion to retire count 248 */ 249#define IBS_OP_COM_TO_RETIRE_CYCLES(x) ((unsigned short)(x->ibs_op_data1_low & BR_MASK_RETIRE)) 250 251/** 31:16 tag_to_retire_cycles : macro-op tag to retire count. */ 252#define IBS_OP_TAG_TO_RETIRE_CYCLES(x) ((unsigned short)((x->ibs_op_data1_low >> 16) & BR_MASK_RETIRE)) 253 254/** 32 op_branch_resync : resync macro-op. */ 255#define IBS_OP_OP_BRANCH_RESYNC(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RESYNC) != 0) 256 257/** 33 op_mispredict_return : mispredicted return macro-op. */ 258#define IBS_OP_OP_MISPREDICT_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_MISP_RETURN) != 0) 259 260/** 34 IbsOpReturn: return macro-op. */ 261#define IBS_OP_OP_RETURN(x) ((x->ibs_op_data1_high & BR_MASK_RETURN) != 0) 262 263/** 35 IbsOpBrnTaken: taken branch macro-op. */ 264#define IBS_OP_OP_BRANCH_TAKEN(x) ((x->ibs_op_data1_high & BR_MASK_BRN_TAKEN) != 0) 265 266/** 36 IbsOpBrnMisp: mispredicted branch macro-op. */ 267#define IBS_OP_OP_BRANCH_MISPREDICT(x) ((x->ibs_op_data1_high & BR_MASK_BRN_MISP) != 0) 268 269/** 37 IbsOpBrnRet: branch macro-op retired. */ 270#define IBS_OP_OP_BRANCH_RETIRED(x) ((x->ibs_op_data1_high & BR_MASK_BRN_RET) != 0) 271 272/** 273 * MSRC001_1036 IBS Op Data 2 Register (IbsOpData2) 274 * 275 * 5 NbIbsReqCacheHitSt: IBS L3 cache state 276 */ 277#define IBS_OP_NB_IBS_CACHE_HIT_ST(x) ((x->ibs_op_data2_low & NB_MASK_L3_STATE) != 0) 278 279/** 4 NbIbsReqDstProc: IBS request destination processor */ 280#define IBS_OP_NB_IBS_REQ_DST_PROC(x) ((x->ibs_op_data2_low & NB_MASK_REQ_DST_PROC) != 0) 281 282/** 2:0 NbIbsReqSrc: Northbridge IBS request data source */ 283#define IBS_OP_NB_IBS_REQ_SRC(x) ((unsigned char)(x->ibs_op_data2_low & NB_MASK_REQ_DATA_SRC)) 284 285/** 286 * MSRC001_1037 IBS Op Data3 Register 287 * 288 * Bits 48:32 IbsDcMissLat 289 */ 290#define IBS_OP_DC_MISS_LATENCY(x) ((unsigned short)(x->ibs_op_data3_high & 0xffff)) 291 292/** 0 IbsLdOp: Load op */ 293#define IBS_OP_IBS_LD_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOAD_OP) != 0) 294 295/** 1 IbsStOp: Store op */ 296#define IBS_OP_IBS_ST_OP(x) ((x->ibs_op_data3_low & DC_MASK_STORE_OP) != 0) 297 298/** 2 ibs_dc_l1_tlb_miss: Data cache L1TLB miss */ 299#define IBS_OP_IBS_DC_L1_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L1_TLB_MISS) != 0) 300 301/** 3 ibs_dc_l2_tlb_miss: Data cache L2TLB miss */ 302#define IBS_OP_IBS_DC_L2_TLB_MISS(x) ((x->ibs_op_data3_low & DC_MASK_L2_TLB_MISS) != 0) 303 304/** 4 IbsDcL1tlbHit2M: Data cache L1TLB hit in 2M page */ 305#define IBS_OP_IBS_DC_L1_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_2M) != 0) 306 307/** 5 ibs_dc_l1_tlb_hit_1gb: Data cache L1TLB hit in 1G page */ 308#define IBS_OP_IBS_DC_L1_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L1_HIT_1G) != 0) 309 310/** 6 ibs_dc_l2_tlb_hit_2mb: Data cache L2TLB hit in 2M page */ 311#define IBS_OP_IBS_DC_L2_TLB_HIT_2MB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_2M) != 0) 312 313/** 7 ibs_dc_miss: Data cache miss */ 314#define IBS_OP_IBS_DC_MISS(x) ((x->ibs_op_data3_low & DC_MASK_DC_MISS) != 0) 315 316/** 8 ibs_dc_miss_acc: Misaligned access */ 317#define IBS_OP_IBS_DC_MISS_ACC(x) ((x->ibs_op_data3_low & DC_MASK_MISALIGN_ACCESS) != 0) 318 319/** 9 ibs_dc_ld_bnk_con: Bank conflict on load operation */ 320#define IBS_OP_IBS_DC_LD_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_LD_BANK_CONFLICT) != 0) 321 322/** 10 ibs_dc_st_bnk_con: Bank conflict on store operation */ 323#define IBS_OP_IBS_DC_ST_BNK_CON(x) ((x->ibs_op_data3_low & DC_MASK_ST_BANK_CONFLICT) != 0) 324 325/** 11 ibs_dc_st_to_ld_fwd : Data forwarded from store to load operation */ 326#define IBS_OP_IBS_DC_ST_TO_LD_FWD(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_FOR) != 0) 327 328/** 12 ibs_dc_st_to_ld_can: Data forwarding from store to load operation cancelled */ 329#define IBS_OP_IBS_DC_ST_TO_LD_CAN(x) ((x->ibs_op_data3_low & DC_MASK_ST_TO_LD_CANCEL) != 0) 330 331/** 13 ibs_dc_uc_mem_acc: UC memory access */ 332#define IBS_OP_IBS_DC_UC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_UC_MEM_ACCESS) != 0) 333 334/** 14 ibs_dc_wc_mem_acc : WC memory access */ 335#define IBS_OP_IBS_DC_WC_MEM_ACC(x) ((x->ibs_op_data3_low & DC_MASK_WC_MEM_ACCESS) != 0) 336 337/** 15 ibs_locked_op: Locked operation */ 338#define IBS_OP_IBS_LOCKED_OP(x) ((x->ibs_op_data3_low & DC_MASK_LOCKED_OP) != 0) 339 340/** 16 ibs_dc_mab_hit : MAB hit */ 341#define IBS_OP_IBS_DC_MAB_HIT(x) ((x->ibs_op_data3_low & DC_MASK_MAB_HIT) != 0) 342 343/** 17 IbsDcLinAddrValid: Data cache linear address valid */ 344#define IBS_OP_IBS_DC_LIN_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_LIN_ADDR_VALID) != 0) 345 346/** 18 ibs_dc_phy_addr_valid: Data cache physical address valid */ 347#define IBS_OP_IBS_DC_PHY_ADDR_VALID(x) ((x->ibs_op_data3_low & DC_MASK_PHY_ADDR_VALID) != 0) 348 349/** 19 ibs_dc_l2_tlb_hit_1gb: Data cache L2TLB hit in 1G page */ 350#define IBS_OP_IBS_DC_L2_TLB_HIT_1GB(x) ((x->ibs_op_data3_low & DC_MASK_L2_HIT_1G) != 0) 351 352 353/** 354 * Aggregate the IBS derived event. Increase the 355 * derived event count by one. 356 */ 357#define AGG_IBS_EVENT(EV) opd_log_ibs_event(EV, trans) 358 359/** 360 * Aggregate the IBS latency/cycle counts. Increase the 361 * derived event count by the specified count value. 362 */ 363#define AGG_IBS_COUNT(EV, COUNT) opd_log_ibs_count(EV, trans, COUNT) 364 365 366#endif /*OPD_IBS_MACRO_H*/ 367