events revision 7a33c86eb98056ef0570c99e713214f8dc56b6ef 
1# ARM V7 events
2# From ARM ARM
3#
4event:0x00 counters:1,2,3,4,5,6 um:zero minimum:500 name:PMNC_SW_INCR : Software increment of PMNC registers
5event:0x01 counters:1,2,3,4,5,6 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
6event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
7event:0x03 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_REFILL : Data R/W operation that causes a refill from cache or normal cacheable memory
8event:0x04 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_ACCESS : Data R/W from cache
9event:0x05 counters:1,2,3,4,5,6 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill
10event:0x06 counters:1,2,3,4,5,6 um:zero minimum:500 name:DREAD : Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)
11event:0x07 counters:1,2,3,4,5,6 um:zero minimum:500 name:DWRITE : Data write architecturally executed
12event:0x08 counters:1,2,3,4,5,6 um:zero minimum:500 name:INSTR_EXECUTED : All executed instructions
13event:0x09 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_TAKEN : Exception taken
14event:0x0A counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_EXECUTED : Exception return architecturally executed
15event:0x0B counters:1,2,3,4,5,6 um:zero minimum:500 name:CID_WRITE : Instruction that writes to the Context ID Register architecturally executed
16event:0x0C counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_WRITE : SW change of PC, architecturally executed (not by exceptions)
17event:0x0D counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_IMM_BRANCH : Immediate branch instruction executed (taken or not)
18event:0x0E counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_PROC_RETURN : Procedure return architecturally executed (not by exceptions)
19event:0x0F counters:1,2,3,4,5,6 um:zero minimum:500 name:UNALIGNED_ACCESS : Unaligned access architecturally executed
20event:0x10 counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_BRANCH_MIS_PRED : Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction
21event:0x12 counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_BRANCH_MIS_USED : Branch or change in program flow that could have been predicted
22event:0xFF counters:0 um:zero minimum:500 name:CPU_CYCLES : Number of CPU cycles
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