unit_masks revision cc2ee177dbb3befca43e36cfc56778b006c3d050
1# Pentium IV possible unit masks 2# 3name:branch_retired type:bitmask default:0x0c 4 0x01 branch not-taken predicted 5 0x02 branch not-taken mispredicted 6 0x04 branch taken predicted 7 0x08 branch taken mispredicted 8name:mispred_branch_retired type:bitmask default:0x01 9 0x01 retired instruction is non-bogus 10# FIXME: 0 count nothing, 0xff count more than 0x01, docs says it's a bitmask: 11# something wrong in documentation ? 12name:bpu_fetch_request type:bitmask default:0x01 13 0x01 trace cache lookup miss 14name:itlb_reference type:bitmask default:0x07 15 0x01 ITLB hit 16 0x02 ITLB miss 17 0x04 uncacheable ITLB hit 18name:memory_cancel type:bitmask default:0x08 19 0x04 replayed because no store request buffer available 20 0x08 conflicts due to 64k aliasing 21name:memory_complete type:bitmask default:0x03 22 0x01 load split completed, excluding UC/WC loads 23 0x02 any split stores completed 24 0x04 uncacheable load split completed 25 0x08 uncacheable store split complete 26name:load_port_replay type:mandatory default:0x02 27 0x02 split load 28name:store_port_replay type:mandatory default:0x02 29 0x02 split store 30name:mob_load_replay type:bitmask default:0x3a 31 0x02 replay cause: unknown store address 32 0x08 replay cause: unknown store data 33 0x10 replay cause: partial overlap between load and store 34 0x20 replay cause: mismatched low 4 bits between load and store addr 35name:bsq_cache_reference type:bitmask default:0x073f 36 0x01 read 2nd level cache hit shared 37 0x02 read 2nd level cache hit exclusive 38 0x04 read 2nd level cache hit modified 39 0x08 read 3rd level cache hit shared 40 0x10 read 3rd level cache hit exclusive 41 0x20 read 3rd level cache hit modified 42 0x100 read 2nd level cache miss 43 0x200 read 3rd level cache miss 44 0x400 writeback lookup from DAC misses 2nd level cache 45name:ioq type:bitmask default:0xefe1 46 0x01 bus request type bit 0 47 0x02 bus request type bit 1 48 0x04 bus request type bit 2 49 0x08 bus request type bit 3 50 0x10 bus request type bit 4 51 0x20 count read entries 52 0x40 count write entries 53 0x80 count UC memory access entries 54 0x100 count WC memory access entries 55 0x200 count write-through memory access entries 56 0x400 count write-protected memory access entries 57 0x800 count WB memory access entries 58 0x2000 count own store requests 59 0x4000 count other / DMA store requests 60 0x8000 count HW/SW prefetch requests 61name:bsq type:bitmask default:0x21 62 0x01 (r)eq (t)ype (e)ncoding, bit 0: see next bit 63 0x02 rte bit 1: 00=read, 01=read invalidate, 10=write, 11=writeback 64 0x04 req len bit 0 65 0x08 req len bit 1 66 0x20 request type is input (0=output) 67 0x40 request type is bus lock 68 0x80 request type is cacheable 69 0x100 request type is 8-byte chunk split across 8-byte boundary 70 0x200 request type is demand (0=prefetch) 71 0x400 request type is ordered 72 0x800 (m)emory (t)ype (e)ncoding, bit 0: see next bits 73 0x1000 mte bit 1: see next bits 74 0x2000 mte bit 2: 000=UC, 001=USWC, 100=WT, 101=WP, 110=WB 75name:x87_assist type:bitmask default:0x1f 76 0x01 handle FP stack underflow 77 0x02 handle FP stack overflow 78 0x04 handle x87 output overflow 79 0x08 handle x87 output underflow 80 0x10 handle x87 input assist 81name:machine_clear type:bitmask default:0x01 82 0x01 count a portion of cycles the machine is cleared for any cause 83 0x04 count each time the machine is cleared due to memory ordering issues 84 0x40 count each time the machine is cleared due to self modifying code 85name:global_power_events type:mandatory default:0x01 86 0x01 mandatory 87name:tc_ms_xfer type:mandatory default:0x01 88 0x01 count TC to MS transfers 89name:uop_queue_writes type:bitmask default:0x07 90 0x01 count uops written to queue from TC build mode 91 0x02 count uops written to queue from TC deliver mode 92 0x04 count uops written to queue from microcode ROM 93name:instr_retired type:bitmask default:0x01 94 0x01 count non-bogus instructions which are not tagged 95 0x02 count non-bogus instructions which are tagged 96 0x04 count bogus instructions which are not tagged 97 0x08 count bogus instructions which are tagged 98name:uops_retired type:bitmask default:0x01 99 0x01 count marked uops which are non-bogus 100 0x02 count marked uops which are bogus 101name:uop_type type:bitmask default:0x02 102 0x02 count uops which are load operations 103 0x04 count uops which are store operations 104name:branch_type type:bitmask default:0x1f 105 0x01 count unconditional jumps 106 0x02 count conditional jumps 107 0x04 count call branches 108 0x08 count return branches 109 0x10 count indirect jumps 110name:tc_deliver_mode type:bitmask default:0x04 111 0x04 processor is in deliver mode 112 0x20 processor is in build mode 113name:page_walk_type type:bitmask default:0x01 114 0x01 page walk for data TLB miss 115 0x02 page walk for instruction TLB miss 116name:fsb_data_activity type:bitmask default:0x3f 117 0x01 count when this processor drives data onto bus 118 0x02 count when this processor reads data from bus 119 0x04 count when data is on bus but not sampled by this processor 120 0x08 count when this processor reserves bus for driving 121 0x10 count when other reserves bus and this processor will sample 122 0x20 count when other reserves bus and this processor will not sample 123name:flame_uop type:mandatory default:0x8000 124 0x8000 count all uops of this type 125name:x87_simd_moves_uop type:bitmask default:0x18 126 0x08 count all x87 SIMD store/move uops 127 0x10 count all x87 SIMD load uops 128